SelectionDAGISel.h revision 286033
150479Speter//===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===// 25266Sgclarkii// 3107543Sscottl// The LLVM Compiler Infrastructure 475286Sru// 519393Swosch// This file is distributed under the University of Illinois Open Source 65266Sgclarkii// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAGISel class, which is used as the common 11// base class for SelectionDAG-based instruction selectors. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H 16#define LLVM_CODEGEN_SELECTIONDAGISEL_H 17 18#include "llvm/CodeGen/MachineFunctionPass.h" 19#include "llvm/CodeGen/SelectionDAG.h" 20#include "llvm/IR/BasicBlock.h" 21#include "llvm/Pass.h" 22 23namespace llvm { 24 class FastISel; 25 class SelectionDAGBuilder; 26 class SDValue; 27 class MachineRegisterInfo; 28 class MachineBasicBlock; 29 class MachineFunction; 30 class MachineInstr; 31 class TargetLowering; 32 class TargetLibraryInfo; 33 class TargetTransformInfo; 34 class FunctionLoweringInfo; 35 class ScheduleHazardRecognizer; 36 class GCFunctionInfo; 37 class ScheduleDAGSDNodes; 38 class LoadInst; 39 40/// SelectionDAGISel - This is the common base class used for SelectionDAG-based 41/// pattern-matching instruction selectors. 42class SelectionDAGISel : public MachineFunctionPass { 43public: 44 TargetMachine &TM; 45 const TargetLibraryInfo *LibInfo; 46 const TargetTransformInfo *TTI; 47 FunctionLoweringInfo *FuncInfo; 48 MachineFunction *MF; 49 MachineRegisterInfo *RegInfo; 50 SelectionDAG *CurDAG; 51 SelectionDAGBuilder *SDB; 52 AliasAnalysis *AA; 53 GCFunctionInfo *GFI; 54 CodeGenOpt::Level OptLevel; 55 static char ID; 56 57 explicit SelectionDAGISel(TargetMachine &tm, 58 CodeGenOpt::Level OL = CodeGenOpt::Default); 59 virtual ~SelectionDAGISel(); 60 61 const TargetLowering *getTargetLowering() const { 62 return TM.getTargetLowering(); 63 } 64 65 virtual void getAnalysisUsage(AnalysisUsage &AU) const; 66 67 virtual bool runOnMachineFunction(MachineFunction &MF); 68 69 virtual void EmitFunctionEntryCode() {} 70 71 /// PreprocessISelDAG - This hook allows targets to hack on the graph before 72 /// instruction selection starts. 73 virtual void PreprocessISelDAG() {} 74 75 /// PostprocessISelDAG() - This hook allows the target to hack on the graph 76 /// right after selection. 77 virtual void PostprocessISelDAG() {} 78 79 /// Select - Main hook targets implement to select a node. 80 virtual SDNode *Select(SDNode *N) = 0; 81 82 /// SelectInlineAsmMemoryOperand - Select the specified address as a target 83 /// addressing mode, according to the specified constraint code. If this does 84 /// not match or is not implemented, return true. The resultant operands 85 /// (which will appear in the machine instruction) should be added to the 86 /// OutOps vector. 87 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 88 char ConstraintCode, 89 std::vector<SDValue> &OutOps) { 90 return true; 91 } 92 93 /// IsProfitableToFold - Returns true if it's profitable to fold the specific 94 /// operand node N of U during instruction selection that starts at Root. 95 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const; 96 97 /// IsLegalToFold - Returns true if the specific operand node N of 98 /// U can be folded during instruction selection that starts at Root. 99 /// FIXME: This is a static member function because the MSP430/X86 100 /// targets, which uses it during isel. This could become a proper member. 101 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 102 CodeGenOpt::Level OptLevel, 103 bool IgnoreChains = false); 104 105 // Opcodes used by the DAG state machine: 106 enum BuiltinOpcodes { 107 OPC_Scope, 108 OPC_RecordNode, 109 OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3, 110 OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7, 111 OPC_RecordMemRef, 112 OPC_CaptureGlueInput, 113 OPC_MoveChild, 114 OPC_MoveParent, 115 OPC_CheckSame, 116 OPC_CheckChild0Same, OPC_CheckChild1Same, 117 OPC_CheckChild2Same, OPC_CheckChild3Same, 118 OPC_CheckPatternPredicate, 119 OPC_CheckPredicate, 120 OPC_CheckOpcode, 121 OPC_SwitchOpcode, 122 OPC_CheckType, 123 OPC_SwitchType, 124 OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type, 125 OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type, 126 OPC_CheckChild6Type, OPC_CheckChild7Type, 127 OPC_CheckInteger, 128 OPC_CheckCondCode, 129 OPC_CheckValueType, 130 OPC_CheckComplexPat, 131 OPC_CheckAndImm, OPC_CheckOrImm, 132 OPC_CheckFoldableChainNode, 133 134 OPC_EmitInteger, 135 OPC_EmitRegister, 136 OPC_EmitRegister2, 137 OPC_EmitConvertToTarget, 138 OPC_EmitMergeInputChains, 139 OPC_EmitMergeInputChains1_0, 140 OPC_EmitMergeInputChains1_1, 141 OPC_EmitCopyToReg, 142 OPC_EmitNodeXForm, 143 OPC_EmitNode, 144 OPC_MorphNodeTo, 145 OPC_MarkGlueResults, 146 OPC_CompleteMatch 147 }; 148 149 enum { 150 OPFL_None = 0, // Node has no chain or glue input and isn't variadic. 151 OPFL_Chain = 1, // Node has a chain input. 152 OPFL_GlueInput = 2, // Node has a glue input. 153 OPFL_GlueOutput = 4, // Node has a glue output. 154 OPFL_MemRefs = 8, // Node gets accumulated MemRefs. 155 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs. 156 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs. 157 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs. 158 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs. 159 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs. 160 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs. 161 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs. 162 163 OPFL_VariadicInfo = OPFL_Variadic6 164 }; 165 166 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the 167 /// number of fixed arity values that should be skipped when copying from the 168 /// root. 169 static inline int getNumFixedFromVariadicInfo(unsigned Flags) { 170 return ((Flags&OPFL_VariadicInfo) >> 4)-1; 171 } 172 173 174protected: 175 /// DAGSize - Size of DAG being instruction selected. 176 /// 177 unsigned DAGSize; 178 179 /// ReplaceUses - replace all uses of the old node F with the use 180 /// of the new node T. 181 void ReplaceUses(SDValue F, SDValue T) { 182 CurDAG->ReplaceAllUsesOfValueWith(F, T); 183 } 184 185 /// ReplaceUses - replace all uses of the old nodes F with the use 186 /// of the new nodes T. 187 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) { 188 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num); 189 } 190 191 /// ReplaceUses - replace all uses of the old node F with the use 192 /// of the new node T. 193 void ReplaceUses(SDNode *F, SDNode *T) { 194 CurDAG->ReplaceAllUsesWith(F, T); 195 } 196 197 198 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 199 /// by tblgen. Others should not call it. 200 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops); 201 202 203public: 204 // Calls to these predicates are generated by tblgen. 205 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 206 int64_t DesiredMaskS) const; 207 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 208 int64_t DesiredMaskS) const; 209 210 211 /// CheckPatternPredicate - This function is generated by tblgen in the 212 /// target. It runs the specified pattern predicate and returns true if it 213 /// succeeds or false if it fails. The number is a private implementation 214 /// detail to the code tblgen produces. 215 virtual bool CheckPatternPredicate(unsigned PredNo) const { 216 llvm_unreachable("Tblgen should generate the implementation of this!"); 217 } 218 219 /// CheckNodePredicate - This function is generated by tblgen in the target. 220 /// It runs node predicate number PredNo and returns true if it succeeds or 221 /// false if it fails. The number is a private implementation 222 /// detail to the code tblgen produces. 223 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const { 224 llvm_unreachable("Tblgen should generate the implementation of this!"); 225 } 226 227 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, 228 unsigned PatternNo, 229 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) { 230 llvm_unreachable("Tblgen should generate the implementation of this!"); 231 } 232 233 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) { 234 llvm_unreachable("Tblgen should generate this!"); 235 } 236 237 SDNode *SelectCodeCommon(SDNode *NodeToMatch, 238 const unsigned char *MatcherTable, 239 unsigned TableSize); 240 241 /// \brief Return true if complex patterns for this target can mutate the 242 /// DAG. 243 virtual bool ComplexPatternFuncMutatesDAG() const { 244 return false; 245 } 246 247private: 248 249 // Calls to these functions are generated by tblgen. 250 SDNode *Select_INLINEASM(SDNode *N); 251 SDNode *Select_UNDEF(SDNode *N); 252 void CannotYetSelect(SDNode *N); 253 254private: 255 void DoInstructionSelection(); 256 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs, 257 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo); 258 259 void PrepareEHLandingPad(); 260 261 /// \brief Perform instruction selection on all basic blocks in the function. 262 void SelectAllBasicBlocks(const Function &Fn); 263 264 /// \brief Perform instruction selection on a single basic block, for 265 /// instructions between \p Begin and \p End. \p HadTailCall will be set 266 /// to true if a call in the block was translated as a tail call. 267 void SelectBasicBlock(BasicBlock::const_iterator Begin, 268 BasicBlock::const_iterator End, 269 bool &HadTailCall); 270 void FinishBasicBlock(); 271 272 void CodeGenAndEmitDAG(); 273 274 /// \brief Generate instructions for lowering the incoming arguments of the 275 /// given function. 276 void LowerArguments(const Function &F); 277 278 void ComputeLiveOutVRegInfo(); 279 280 /// Create the scheduler. If a specific scheduler was specified 281 /// via the SchedulerRegistry, use it, otherwise select the 282 /// one preferred by the target. 283 /// 284 ScheduleDAGSDNodes *CreateScheduler(); 285 286 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel 287 /// state machines that start with a OPC_SwitchOpcode node. 288 std::vector<unsigned> OpcodeOffset; 289 290 void UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 291 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 292 SDValue InputGlue, const SmallVectorImpl<SDNode*> &F, 293 bool isMorphNodeTo); 294 295}; 296 297} 298 299#endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */ 300