SelectionDAGISel.h revision 286012
1266989Smarkj//===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===// 2266989Smarkj// 3266989Smarkj// The LLVM Compiler Infrastructure 4266989Smarkj// 5266989Smarkj// This file is distributed under the University of Illinois Open Source 6266989Smarkj// License. See LICENSE.TXT for details. 7266989Smarkj// 8266989Smarkj//===----------------------------------------------------------------------===// 9266989Smarkj// 10266989Smarkj// This file implements the SelectionDAGISel class, which is used as the common 11266989Smarkj// base class for SelectionDAG-based instruction selectors. 12266989Smarkj// 13266989Smarkj//===----------------------------------------------------------------------===// 14266989Smarkj 15266989Smarkj#ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H 16266989Smarkj#define LLVM_CODEGEN_SELECTIONDAGISEL_H 17266989Smarkj 18266989Smarkj#include "llvm/CodeGen/MachineFunctionPass.h" 19266989Smarkj#include "llvm/CodeGen/SelectionDAG.h" 20266989Smarkj#include "llvm/IR/BasicBlock.h" 21266989Smarkj#include "llvm/Pass.h" 22266989Smarkj 23266989Smarkjnamespace llvm { 24266989Smarkj class FastISel; 25266989Smarkj class SelectionDAGBuilder; 26266989Smarkj class SDValue; 27266989Smarkj class MachineRegisterInfo; 28266989Smarkj class MachineBasicBlock; 29266989Smarkj class MachineFunction; 30266989Smarkj class MachineInstr; 31266989Smarkj class TargetLowering; 32266989Smarkj class TargetLibraryInfo; 33266989Smarkj class TargetTransformInfo; 34266989Smarkj class FunctionLoweringInfo; 35266989Smarkj class ScheduleHazardRecognizer; 36266989Smarkj class GCFunctionInfo; 37266989Smarkj class ScheduleDAGSDNodes; 38266989Smarkj class LoadInst; 39266989Smarkj 40266989Smarkj/// SelectionDAGISel - This is the common base class used for SelectionDAG-based 41266989Smarkj/// pattern-matching instruction selectors. 42266989Smarkjclass SelectionDAGISel : public MachineFunctionPass { 43266989Smarkjpublic: 44266989Smarkj TargetMachine &TM; 45266989Smarkj const TargetLibraryInfo *LibInfo; 46266989Smarkj const TargetTransformInfo *TTI; 47266989Smarkj FunctionLoweringInfo *FuncInfo; 48266989Smarkj MachineFunction *MF; 49266989Smarkj MachineRegisterInfo *RegInfo; 50266989Smarkj SelectionDAG *CurDAG; 51266989Smarkj SelectionDAGBuilder *SDB; 52266989Smarkj AliasAnalysis *AA; 53266989Smarkj GCFunctionInfo *GFI; 54266989Smarkj CodeGenOpt::Level OptLevel; 55266989Smarkj static char ID; 56266989Smarkj 57266989Smarkj explicit SelectionDAGISel(TargetMachine &tm, 58266989Smarkj CodeGenOpt::Level OL = CodeGenOpt::Default); 59266989Smarkj virtual ~SelectionDAGISel(); 60266989Smarkj 61266989Smarkj const TargetLowering *getTargetLowering() const { 62266989Smarkj return TM.getTargetLowering(); 63266989Smarkj } 64266989Smarkj 65266989Smarkj virtual void getAnalysisUsage(AnalysisUsage &AU) const; 66266989Smarkj 67266989Smarkj virtual bool runOnMachineFunction(MachineFunction &MF); 68266989Smarkj 69266989Smarkj virtual void EmitFunctionEntryCode() {} 70266989Smarkj 71266989Smarkj /// PreprocessISelDAG - This hook allows targets to hack on the graph before 72266989Smarkj /// instruction selection starts. 73266989Smarkj virtual void PreprocessISelDAG() {} 74266989Smarkj 75266989Smarkj /// PostprocessISelDAG() - This hook allows the target to hack on the graph 76266989Smarkj /// right after selection. 77266989Smarkj virtual void PostprocessISelDAG() {} 78266989Smarkj 79266989Smarkj /// Select - Main hook targets implement to select a node. 80266989Smarkj virtual SDNode *Select(SDNode *N) = 0; 81266989Smarkj 82266989Smarkj /// SelectInlineAsmMemoryOperand - Select the specified address as a target 83266989Smarkj /// addressing mode, according to the specified constraint code. If this does 84 /// not match or is not implemented, return true. The resultant operands 85 /// (which will appear in the machine instruction) should be added to the 86 /// OutOps vector. 87 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 88 char ConstraintCode, 89 std::vector<SDValue> &OutOps) { 90 return true; 91 } 92 93 /// IsProfitableToFold - Returns true if it's profitable to fold the specific 94 /// operand node N of U during instruction selection that starts at Root. 95 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const; 96 97 /// IsLegalToFold - Returns true if the specific operand node N of 98 /// U can be folded during instruction selection that starts at Root. 99 /// FIXME: This is a static member function because the MSP430/X86 100 /// targets, which uses it during isel. This could become a proper member. 101 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 102 CodeGenOpt::Level OptLevel, 103 bool IgnoreChains = false); 104 105 // Opcodes used by the DAG state machine: 106 enum BuiltinOpcodes { 107 OPC_Scope, 108 OPC_RecordNode, 109 OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3, 110 OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7, 111 OPC_RecordMemRef, 112 OPC_CaptureGlueInput, 113 OPC_MoveChild, 114 OPC_MoveParent, 115 OPC_CheckSame, 116 OPC_CheckChild0Same, OPC_CheckChild1Same, 117 OPC_CheckChild2Same, OPC_CheckChild3Same, 118 OPC_CheckPatternPredicate, 119 OPC_CheckPredicate, 120 OPC_CheckOpcode, 121 OPC_SwitchOpcode, 122 OPC_CheckType, 123 OPC_SwitchType, 124 OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type, 125 OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type, 126 OPC_CheckChild6Type, OPC_CheckChild7Type, 127 OPC_CheckInteger, 128 OPC_CheckCondCode, 129 OPC_CheckValueType, 130 OPC_CheckComplexPat, 131 OPC_CheckAndImm, OPC_CheckOrImm, 132 OPC_CheckFoldableChainNode, 133 134 OPC_EmitInteger, 135 OPC_EmitRegister, 136 OPC_EmitRegister2, 137 OPC_EmitConvertToTarget, 138 OPC_EmitMergeInputChains, 139 OPC_EmitMergeInputChains1_0, 140 OPC_EmitMergeInputChains1_1, 141 OPC_EmitCopyToReg, 142 OPC_EmitNodeXForm, 143 OPC_EmitNode, 144 OPC_MorphNodeTo, 145 OPC_MarkGlueResults, 146 OPC_CompleteMatch 147 }; 148 149 enum { 150 OPFL_None = 0, // Node has no chain or glue input and isn't variadic. 151 OPFL_Chain = 1, // Node has a chain input. 152 OPFL_GlueInput = 2, // Node has a glue input. 153 OPFL_GlueOutput = 4, // Node has a glue output. 154 OPFL_MemRefs = 8, // Node gets accumulated MemRefs. 155 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs. 156 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs. 157 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs. 158 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs. 159 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs. 160 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs. 161 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs. 162 163 OPFL_VariadicInfo = OPFL_Variadic6 164 }; 165 166 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the 167 /// number of fixed arity values that should be skipped when copying from the 168 /// root. 169 static inline int getNumFixedFromVariadicInfo(unsigned Flags) { 170 return ((Flags&OPFL_VariadicInfo) >> 4)-1; 171 } 172 173 174protected: 175 /// DAGSize - Size of DAG being instruction selected. 176 /// 177 unsigned DAGSize; 178 179 /// ReplaceUses - replace all uses of the old node F with the use 180 /// of the new node T. 181 void ReplaceUses(SDValue F, SDValue T) { 182 CurDAG->ReplaceAllUsesOfValueWith(F, T); 183 } 184 185 /// ReplaceUses - replace all uses of the old nodes F with the use 186 /// of the new nodes T. 187 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) { 188 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num); 189 } 190 191 /// ReplaceUses - replace all uses of the old node F with the use 192 /// of the new node T. 193 void ReplaceUses(SDNode *F, SDNode *T) { 194 CurDAG->ReplaceAllUsesWith(F, T); 195 } 196 197 198 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 199 /// by tblgen. Others should not call it. 200 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops); 201 202 203public: 204 // Calls to these predicates are generated by tblgen. 205 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 206 int64_t DesiredMaskS) const; 207 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 208 int64_t DesiredMaskS) const; 209 210 211 /// CheckPatternPredicate - This function is generated by tblgen in the 212 /// target. It runs the specified pattern predicate and returns true if it 213 /// succeeds or false if it fails. The number is a private implementation 214 /// detail to the code tblgen produces. 215 virtual bool CheckPatternPredicate(unsigned PredNo) const { 216 llvm_unreachable("Tblgen should generate the implementation of this!"); 217 } 218 219 /// CheckNodePredicate - This function is generated by tblgen in the target. 220 /// It runs node predicate number PredNo and returns true if it succeeds or 221 /// false if it fails. The number is a private implementation 222 /// detail to the code tblgen produces. 223 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const { 224 llvm_unreachable("Tblgen should generate the implementation of this!"); 225 } 226 227 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, 228 unsigned PatternNo, 229 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) { 230 llvm_unreachable("Tblgen should generate the implementation of this!"); 231 } 232 233 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) { 234 llvm_unreachable("Tblgen should generate this!"); 235 } 236 237 SDNode *SelectCodeCommon(SDNode *NodeToMatch, 238 const unsigned char *MatcherTable, 239 unsigned TableSize); 240 241private: 242 243 // Calls to these functions are generated by tblgen. 244 SDNode *Select_INLINEASM(SDNode *N); 245 SDNode *Select_UNDEF(SDNode *N); 246 void CannotYetSelect(SDNode *N); 247 248private: 249 void DoInstructionSelection(); 250 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs, 251 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo); 252 253 void PrepareEHLandingPad(); 254 255 /// \brief Perform instruction selection on all basic blocks in the function. 256 void SelectAllBasicBlocks(const Function &Fn); 257 258 /// \brief Perform instruction selection on a single basic block, for 259 /// instructions between \p Begin and \p End. \p HadTailCall will be set 260 /// to true if a call in the block was translated as a tail call. 261 void SelectBasicBlock(BasicBlock::const_iterator Begin, 262 BasicBlock::const_iterator End, 263 bool &HadTailCall); 264 void FinishBasicBlock(); 265 266 void CodeGenAndEmitDAG(); 267 268 /// \brief Generate instructions for lowering the incoming arguments of the 269 /// given function. 270 void LowerArguments(const Function &F); 271 272 void ComputeLiveOutVRegInfo(); 273 274 /// Create the scheduler. If a specific scheduler was specified 275 /// via the SchedulerRegistry, use it, otherwise select the 276 /// one preferred by the target. 277 /// 278 ScheduleDAGSDNodes *CreateScheduler(); 279 280 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel 281 /// state machines that start with a OPC_SwitchOpcode node. 282 std::vector<unsigned> OpcodeOffset; 283 284 void UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 285 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 286 SDValue InputGlue, const SmallVectorImpl<SDNode*> &F, 287 bool isMorphNodeTo); 288 289}; 290 291} 292 293#endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */ 294