1193323Sed//===-- Passes.h - Target independent code generation passes ----*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file defines interfaces to access the target independent code generation 11193323Sed// passes provided by the LLVM backend. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15193323Sed#ifndef LLVM_CODEGEN_PASSES_H 16193323Sed#define LLVM_CODEGEN_PASSES_H 17193323Sed 18234353Sdim#include "llvm/Pass.h" 19198396Srdivacky#include "llvm/Target/TargetMachine.h" 20193323Sed#include <string> 21193323Sed 22193323Sednamespace llvm { 23193323Sed 24263508Sdimclass FunctionPass; 25263508Sdimclass MachineFunctionPass; 26263508Sdimclass PassConfigImpl; 27263508Sdimclass PassInfo; 28263508Sdimclass ScheduleDAGInstrs; 29263508Sdimclass TargetLowering; 30263508Sdimclass TargetLoweringBase; 31263508Sdimclass TargetRegisterClass; 32263508Sdimclass raw_ostream; 33263508Sdimstruct MachineSchedContext; 34263508Sdim 35263508Sdim// The old pass manager infrastructure is hidden in a legacy namespace now. 36263508Sdimnamespace legacy { 37263508Sdimclass PassManagerBase; 38234353Sdim} 39263508Sdimusing legacy::PassManagerBase; 40193323Sed 41251662Sdim/// Discriminated union of Pass ID types. 42251662Sdim/// 43251662Sdim/// The PassConfig API prefers dealing with IDs because they are safer and more 44251662Sdim/// efficient. IDs decouple configuration from instantiation. This way, when a 45251662Sdim/// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to 46251662Sdim/// refer to a Pass pointer after adding it to a pass manager, which deletes 47251662Sdim/// redundant pass instances. 48251662Sdim/// 49251662Sdim/// However, it is convient to directly instantiate target passes with 50251662Sdim/// non-default ctors. These often don't have a registered PassInfo. Rather than 51251662Sdim/// force all target passes to implement the pass registry boilerplate, allow 52251662Sdim/// the PassConfig API to handle either type. 53251662Sdim/// 54251662Sdim/// AnalysisID is sadly char*, so PointerIntPair won't work. 55251662Sdimclass IdentifyingPassPtr { 56251662Sdim union { 57251662Sdim AnalysisID ID; 58251662Sdim Pass *P; 59251662Sdim }; 60251662Sdim bool IsInstance; 61251662Sdimpublic: 62251662Sdim IdentifyingPassPtr() : P(0), IsInstance(false) {} 63251662Sdim IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr), IsInstance(false) {} 64251662Sdim IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {} 65251662Sdim 66251662Sdim bool isValid() const { return P; } 67251662Sdim bool isInstance() const { return IsInstance; } 68251662Sdim 69251662Sdim AnalysisID getID() const { 70251662Sdim assert(!IsInstance && "Not a Pass ID"); 71251662Sdim return ID; 72251662Sdim } 73251662Sdim Pass *getInstance() const { 74251662Sdim assert(IsInstance && "Not a Pass Instance"); 75251662Sdim return P; 76251662Sdim } 77251662Sdim}; 78251662Sdim 79251662Sdimtemplate <> struct isPodLike<IdentifyingPassPtr> { 80251662Sdim static const bool value = true; 81251662Sdim}; 82251662Sdim 83234353Sdim/// Target-Independent Code Generator Pass Configuration Options. 84234353Sdim/// 85234353Sdim/// This is an ImmutablePass solely for the purpose of exposing CodeGen options 86234353Sdim/// to the internals of other CodeGen passes. 87234353Sdimclass TargetPassConfig : public ImmutablePass { 88234353Sdimpublic: 89234353Sdim /// Pseudo Pass IDs. These are defined within TargetPassConfig because they 90234353Sdim /// are unregistered pass IDs. They are only useful for use with 91234353Sdim /// TargetPassConfig APIs to identify multiple occurrences of the same pass. 92234353Sdim /// 93234353Sdim 94234353Sdim /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early 95234353Sdim /// during codegen, on SSA form. 96234353Sdim static char EarlyTailDuplicateID; 97234353Sdim 98234353Sdim /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine 99234353Sdim /// optimization after regalloc. 100234353Sdim static char PostRAMachineLICMID; 101234353Sdim 102239462Sdimprivate: 103239462Sdim PassManagerBase *PM; 104239462Sdim AnalysisID StartAfter; 105239462Sdim AnalysisID StopAfter; 106239462Sdim bool Started; 107239462Sdim bool Stopped; 108239462Sdim 109234353Sdimprotected: 110234353Sdim TargetMachine *TM; 111234353Sdim PassConfigImpl *Impl; // Internal data structures 112234353Sdim bool Initialized; // Flagged after all passes are configured. 113234353Sdim 114234353Sdim // Target Pass Options 115234353Sdim // Targets provide a default setting, user flags override. 116234353Sdim // 117234353Sdim bool DisableVerify; 118234353Sdim 119234353Sdim /// Default setting for -enable-tail-merge on this target. 120234353Sdim bool EnableTailMerge; 121234353Sdim 122234353Sdimpublic: 123234353Sdim TargetPassConfig(TargetMachine *tm, PassManagerBase &pm); 124234353Sdim // Dummy constructor. 125234353Sdim TargetPassConfig(); 126234353Sdim 127234353Sdim virtual ~TargetPassConfig(); 128234353Sdim 129234353Sdim static char ID; 130234353Sdim 131234353Sdim /// Get the right type of TargetMachine for this target. 132234353Sdim template<typename TMC> TMC &getTM() const { 133234353Sdim return *static_cast<TMC*>(TM); 134234353Sdim } 135234353Sdim 136234353Sdim const TargetLowering *getTargetLowering() const { 137234353Sdim return TM->getTargetLowering(); 138234353Sdim } 139234353Sdim 140234353Sdim // 141234353Sdim void setInitialized() { Initialized = true; } 142234353Sdim 143234353Sdim CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); } 144234353Sdim 145239462Sdim /// setStartStopPasses - Set the StartAfter and StopAfter passes to allow 146239462Sdim /// running only a portion of the normal code-gen pass sequence. If the 147239462Sdim /// Start pass ID is zero, then compilation will begin at the normal point; 148239462Sdim /// otherwise, clear the Started flag to indicate that passes should not be 149239462Sdim /// added until the starting pass is seen. If the Stop pass ID is zero, 150239462Sdim /// then compilation will continue to the end. 151239462Sdim void setStartStopPasses(AnalysisID Start, AnalysisID Stop) { 152239462Sdim StartAfter = Start; 153239462Sdim StopAfter = Stop; 154239462Sdim Started = (StartAfter == 0); 155239462Sdim } 156239462Sdim 157234353Sdim void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); } 158234353Sdim 159234353Sdim bool getEnableTailMerge() const { return EnableTailMerge; } 160234353Sdim void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); } 161234353Sdim 162234353Sdim /// Allow the target to override a specific pass without overriding the pass 163234353Sdim /// pipeline. When passes are added to the standard pipeline at the 164239462Sdim /// point where StandardID is expected, add TargetID in its place. 165251662Sdim void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID); 166234353Sdim 167239462Sdim /// Insert InsertedPassID pass after TargetPassID pass. 168251662Sdim void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID); 169239462Sdim 170234353Sdim /// Allow the target to enable a specific standard pass by default. 171239462Sdim void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); } 172234353Sdim 173234353Sdim /// Allow the target to disable a specific standard pass by default. 174251662Sdim void disablePass(AnalysisID PassID) { 175251662Sdim substitutePass(PassID, IdentifyingPassPtr()); 176251662Sdim } 177234353Sdim 178239462Sdim /// Return the pass substituted for StandardID by the target. 179234353Sdim /// If no substitution exists, return StandardID. 180251662Sdim IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const; 181234353Sdim 182234353Sdim /// Return true if the optimized regalloc pipeline is enabled. 183234353Sdim bool getOptimizeRegAlloc() const; 184234353Sdim 185234353Sdim /// Add common target configurable passes that perform LLVM IR to IR 186234353Sdim /// transforms following machine independent optimization. 187234353Sdim virtual void addIRPasses(); 188234353Sdim 189239462Sdim /// Add passes to lower exception handling for the code generator. 190239462Sdim void addPassesToHandleExceptions(); 191239462Sdim 192249423Sdim /// Add pass to prepare the LLVM IR for code generation. This should be done 193249423Sdim /// before exception handling preparation passes. 194249423Sdim virtual void addCodeGenPrepare(); 195249423Sdim 196234353Sdim /// Add common passes that perform LLVM IR to IR transforms in preparation for 197234353Sdim /// instruction selection. 198234353Sdim virtual void addISelPrepare(); 199234353Sdim 200234353Sdim /// addInstSelector - This method should install an instruction selector pass, 201234353Sdim /// which converts from LLVM code to machine instructions. 202234353Sdim virtual bool addInstSelector() { 203234353Sdim return true; 204234353Sdim } 205234353Sdim 206234353Sdim /// Add the complete, standard set of LLVM CodeGen passes. 207234353Sdim /// Fully developed targets will not generally override this. 208234353Sdim virtual void addMachinePasses(); 209234353Sdim 210263508Sdim /// createTargetScheduler - Create an instance of ScheduleDAGInstrs to be run 211263508Sdim /// within the standard MachineScheduler pass for this function and target at 212263508Sdim /// the current optimization level. 213263508Sdim /// 214263508Sdim /// This can also be used to plug a new MachineSchedStrategy into an instance 215263508Sdim /// of the standard ScheduleDAGMI: 216263508Sdim /// return new ScheduleDAGMI(C, new MyStrategy(C)) 217263508Sdim /// 218263508Sdim /// Return NULL to select the default (generic) machine scheduler. 219263508Sdim virtual ScheduleDAGInstrs * 220263508Sdim createMachineScheduler(MachineSchedContext *C) const { 221263508Sdim return 0; 222263508Sdim } 223263508Sdim 224234353Sdimprotected: 225234353Sdim // Helper to verify the analysis is really immutable. 226234353Sdim void setOpt(bool &Opt, bool Val); 227234353Sdim 228234353Sdim /// Methods with trivial inline returns are convenient points in the common 229234353Sdim /// codegen pass pipeline where targets may insert passes. Methods with 230234353Sdim /// out-of-line standard implementations are major CodeGen stages called by 231234353Sdim /// addMachinePasses. Some targets may override major stages when inserting 232234353Sdim /// passes is insufficient, but maintaining overriden stages is more work. 233234353Sdim /// 234234353Sdim 235234353Sdim /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM 236234353Sdim /// passes (which are run just before instruction selector). 237234353Sdim virtual bool addPreISel() { 238234353Sdim return true; 239234353Sdim } 240234353Sdim 241234353Sdim /// addMachineSSAOptimization - Add standard passes that optimize machine 242234353Sdim /// instructions in SSA form. 243234353Sdim virtual void addMachineSSAOptimization(); 244234353Sdim 245249423Sdim /// Add passes that optimize instruction level parallelism for out-of-order 246249423Sdim /// targets. These passes are run while the machine code is still in SSA 247249423Sdim /// form, so they can use MachineTraceMetrics to control their heuristics. 248249423Sdim /// 249249423Sdim /// All passes added here should preserve the MachineDominatorTree, 250249423Sdim /// MachineLoopInfo, and MachineTraceMetrics analyses. 251249423Sdim virtual bool addILPOpts() { 252249423Sdim return false; 253249423Sdim } 254249423Sdim 255234353Sdim /// addPreRegAlloc - This method may be implemented by targets that want to 256234353Sdim /// run passes immediately before register allocation. This should return 257234353Sdim /// true if -print-machineinstrs should print after these passes. 258234353Sdim virtual bool addPreRegAlloc() { 259234353Sdim return false; 260234353Sdim } 261234353Sdim 262234353Sdim /// createTargetRegisterAllocator - Create the register allocator pass for 263234353Sdim /// this target at the current optimization level. 264234353Sdim virtual FunctionPass *createTargetRegisterAllocator(bool Optimized); 265234353Sdim 266234353Sdim /// addFastRegAlloc - Add the minimum set of target-independent passes that 267234353Sdim /// are required for fast register allocation. 268234353Sdim virtual void addFastRegAlloc(FunctionPass *RegAllocPass); 269234353Sdim 270234353Sdim /// addOptimizedRegAlloc - Add passes related to register allocation. 271234353Sdim /// LLVMTargetMachine provides standard regalloc passes for most targets. 272234353Sdim virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass); 273234353Sdim 274239462Sdim /// addPreRewrite - Add passes to the optimized register allocation pipeline 275239462Sdim /// after register allocation is complete, but before virtual registers are 276239462Sdim /// rewritten to physical registers. 277239462Sdim /// 278239462Sdim /// These passes must preserve VirtRegMap and LiveIntervals, and when running 279239462Sdim /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix. 280239462Sdim /// When these passes run, VirtRegMap contains legal physreg assignments for 281239462Sdim /// all virtual registers. 282239462Sdim virtual bool addPreRewrite() { 283239462Sdim return false; 284239462Sdim } 285239462Sdim 286234353Sdim /// addPostRegAlloc - This method may be implemented by targets that want to 287234353Sdim /// run passes after register allocation pass pipeline but before 288234353Sdim /// prolog-epilog insertion. This should return true if -print-machineinstrs 289234353Sdim /// should print after these passes. 290234353Sdim virtual bool addPostRegAlloc() { 291234353Sdim return false; 292234353Sdim } 293234353Sdim 294234353Sdim /// Add passes that optimize machine instructions after register allocation. 295234353Sdim virtual void addMachineLateOptimization(); 296234353Sdim 297234353Sdim /// addPreSched2 - This method may be implemented by targets that want to 298234353Sdim /// run passes after prolog-epilog insertion and before the second instruction 299234353Sdim /// scheduling pass. This should return true if -print-machineinstrs should 300234353Sdim /// print after these passes. 301234353Sdim virtual bool addPreSched2() { 302234353Sdim return false; 303234353Sdim } 304234353Sdim 305249423Sdim /// addGCPasses - Add late codegen passes that analyze code for garbage 306249423Sdim /// collection. This should return true if GC info should be printed after 307249423Sdim /// these passes. 308249423Sdim virtual bool addGCPasses(); 309249423Sdim 310234353Sdim /// Add standard basic block placement passes. 311234353Sdim virtual void addBlockPlacement(); 312234353Sdim 313234353Sdim /// addPreEmitPass - This pass may be implemented by targets that want to run 314234353Sdim /// passes immediately before machine code is emitted. This should return 315234353Sdim /// true if -print-machineinstrs should print out the code after the passes. 316234353Sdim virtual bool addPreEmitPass() { 317234353Sdim return false; 318234353Sdim } 319234353Sdim 320234353Sdim /// Utilities for targets to add passes to the pass manager. 321234353Sdim /// 322234353Sdim 323234353Sdim /// Add a CodeGen pass at this point in the pipeline after checking overrides. 324239462Sdim /// Return the pass that was added, or zero if no pass was added. 325239462Sdim AnalysisID addPass(AnalysisID PassID); 326234353Sdim 327239462Sdim /// Add a pass to the PassManager if that pass is supposed to be run, as 328263508Sdim /// determined by the StartAfter and StopAfter options. Takes ownership of the 329263508Sdim /// pass. 330239462Sdim void addPass(Pass *P); 331239462Sdim 332234353Sdim /// addMachinePasses helper to create the target-selected or overriden 333234353Sdim /// regalloc pass. 334234353Sdim FunctionPass *createRegAllocPass(bool Optimized); 335234353Sdim 336234353Sdim /// printAndVerify - Add a pass to dump then verify the machine function, if 337234353Sdim /// those steps are enabled. 338234353Sdim /// 339239462Sdim void printAndVerify(const char *Banner); 340234353Sdim}; 341234353Sdim} // namespace llvm 342234353Sdim 343234353Sdim/// List of target independent CodeGen pass IDs. 344234353Sdimnamespace llvm { 345249423Sdim /// \brief Create a basic TargetTransformInfo analysis pass. 346249423Sdim /// 347249423Sdim /// This pass implements the target transform info analysis using the target 348249423Sdim /// independent information available to the LLVM code generator. 349249423Sdim ImmutablePass * 350263508Sdim createBasicTargetTransformInfoPass(const TargetMachine *TM); 351249423Sdim 352193323Sed /// createUnreachableBlockEliminationPass - The LLVM code generator does not 353193323Sed /// work well with unreachable basic blocks (what live ranges make sense for a 354193323Sed /// block that cannot be reached?). As such, a code generator should either 355212904Sdim /// not instruction select unreachable blocks, or run this pass as its 356193323Sed /// last LLVM modifying pass to clean up blocks that are not reachable from 357193323Sed /// the entry block. 358193323Sed FunctionPass *createUnreachableBlockEliminationPass(); 359193323Sed 360193323Sed /// MachineFunctionPrinter pass - This pass prints out the machine function to 361212904Sdim /// the given stream as a debugging tool. 362206124Srdivacky MachineFunctionPass * 363206124Srdivacky createMachineFunctionPrinterPass(raw_ostream &OS, 364206124Srdivacky const std::string &Banner =""); 365193323Sed 366234353Sdim /// MachineLoopInfo - This pass is a loop analysis pass. 367212904Sdim extern char &MachineLoopInfoID; 368193323Sed 369234353Sdim /// MachineDominators - This pass is a machine dominators analysis pass. 370212904Sdim extern char &MachineDominatorsID; 371193323Sed 372218893Sdim /// EdgeBundles analysis - Bundle machine CFG edges. 373218893Sdim extern char &EdgeBundlesID; 374218893Sdim 375234353Sdim /// LiveVariables pass - This pass computes the set of blocks in which each 376234353Sdim /// variable is life and sets machine operand kill flags. 377234353Sdim extern char &LiveVariablesID; 378234353Sdim 379234353Sdim /// PHIElimination - This pass eliminates machine instruction PHI nodes 380193323Sed /// by inserting copy instructions. This destroys SSA information, but is the 381193323Sed /// desired input for some register allocators. This pass is "required" by 382193323Sed /// these register allocator like this: AU.addRequiredID(PHIEliminationID); 383212904Sdim extern char &PHIEliminationID; 384212904Sdim 385239462Sdim /// LiveIntervals - This analysis keeps track of the live ranges of virtual 386239462Sdim /// and physical registers. 387239462Sdim extern char &LiveIntervalsID; 388239462Sdim 389218893Sdim /// LiveStacks pass. An analysis keeping track of the liveness of stack slots. 390218893Sdim extern char &LiveStacksID; 391218893Sdim 392234353Sdim /// TwoAddressInstruction - This pass reduces two-address instructions to 393193323Sed /// use two operands. This destroys SSA information but it is desired by 394193323Sed /// register allocators. 395212904Sdim extern char &TwoAddressInstructionPassID; 396193323Sed 397234353Sdim /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs. 398234353Sdim extern char &ProcessImplicitDefsID; 399226633Sdim 400234353Sdim /// RegisterCoalescer - This pass merges live ranges to eliminate copies. 401234353Sdim extern char &RegisterCoalescerID; 402234353Sdim 403234353Sdim /// MachineScheduler - This pass schedules machine instructions. 404234353Sdim extern char &MachineSchedulerID; 405234353Sdim 406218893Sdim /// SpillPlacement analysis. Suggest optimal placement of spill code between 407218893Sdim /// basic blocks. 408218893Sdim extern char &SpillPlacementID; 409218893Sdim 410239462Sdim /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as 411239462Sdim /// assigned in VirtRegMap. 412239462Sdim extern char &VirtRegRewriterID; 413239462Sdim 414234353Sdim /// UnreachableMachineBlockElimination - This pass removes unreachable 415193323Sed /// machine basic blocks. 416212904Sdim extern char &UnreachableMachineBlockElimID; 417193323Sed 418234353Sdim /// DeadMachineInstructionElim - This pass removes dead machine instructions. 419234353Sdim extern char &DeadMachineInstructionElimID; 420193323Sed 421207618Srdivacky /// FastRegisterAllocation Pass - This pass register allocates as fast as 422207618Srdivacky /// possible. It is best suited for debug code where live ranges are short. 423207618Srdivacky /// 424207618Srdivacky FunctionPass *createFastRegisterAllocator(); 425207618Srdivacky 426218893Sdim /// BasicRegisterAllocation Pass - This pass implements a degenerate global 427218893Sdim /// register allocator using the basic regalloc framework. 428218893Sdim /// 429218893Sdim FunctionPass *createBasicRegisterAllocator(); 430218893Sdim 431218893Sdim /// Greedy register allocation pass - This pass implements a global register 432218893Sdim /// allocator for optimized builds. 433218893Sdim /// 434218893Sdim FunctionPass *createGreedyRegisterAllocator(); 435218893Sdim 436193323Sed /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean 437193323Sed /// Quadratic Prograaming (PBQP) based register allocator. 438193323Sed /// 439218893Sdim FunctionPass *createDefaultPBQPRegisterAllocator(); 440193323Sed 441234353Sdim /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code, 442193323Sed /// and eliminates abstract frame references. 443234353Sdim extern char &PrologEpilogCodeInserterID; 444212904Sdim 445234353Sdim /// ExpandPostRAPseudos - This pass expands pseudo instructions after 446226633Sdim /// register allocation. 447234353Sdim extern char &ExpandPostRAPseudosID; 448193323Sed 449198396Srdivacky /// createPostRAScheduler - This pass performs post register allocation 450198396Srdivacky /// scheduling. 451234353Sdim extern char &PostRASchedulerID; 452193323Sed 453234353Sdim /// BranchFolding - This pass performs machine code CFG based 454193323Sed /// optimizations to delete branches to branches, eliminate branches to 455193323Sed /// successor blocks (creating fall throughs), and eliminating branches over 456193323Sed /// branches. 457234353Sdim extern char &BranchFolderPassID; 458193323Sed 459239462Sdim /// MachineFunctionPrinterPass - This pass prints out MachineInstr's. 460239462Sdim extern char &MachineFunctionPrinterPassID; 461239462Sdim 462234353Sdim /// TailDuplicate - Duplicate blocks with unconditional branches 463199989Srdivacky /// into tails of their predecessors. 464234353Sdim extern char &TailDuplicateID; 465199989Srdivacky 466239462Sdim /// MachineTraceMetrics - This pass computes critical path and CPU resource 467239462Sdim /// usage in an ensemble of traces. 468239462Sdim extern char &MachineTraceMetricsID; 469239462Sdim 470239462Sdim /// EarlyIfConverter - This pass performs if-conversion on SSA form by 471239462Sdim /// inserting cmov instructions. 472239462Sdim extern char &EarlyIfConverterID; 473239462Sdim 474243830Sdim /// StackSlotColoring - This pass performs stack coloring and merging. 475243830Sdim /// It merges disjoint allocas to reduce the stack size. 476243830Sdim extern char &StackColoringID; 477243830Sdim 478234353Sdim /// IfConverter - This pass performs machine code if conversion. 479234353Sdim extern char &IfConverterID; 480193323Sed 481234353Sdim /// MachineBlockPlacement - This pass places basic blocks based on branch 482234353Sdim /// probabilities. 483234353Sdim extern char &MachineBlockPlacementID; 484234353Sdim 485234353Sdim /// MachineBlockPlacementStats - This pass collects statistics about the 486234353Sdim /// basic block placement using branch probabilities and block frequency 487234353Sdim /// information. 488234353Sdim extern char &MachineBlockPlacementStatsID; 489234353Sdim 490234353Sdim /// GCLowering Pass - Performs target-independent LLVM IR transformations for 491234353Sdim /// highly portable strategies. 492234353Sdim /// 493193323Sed FunctionPass *createGCLoweringPass(); 494212904Sdim 495234353Sdim /// GCMachineCodeAnalysis - Target-independent pass to mark safe points 496234353Sdim /// in machine code. Must be added very late during code generation, just 497234353Sdim /// prior to output, and importantly after all CFG transformations (such as 498234353Sdim /// branch folding). 499234353Sdim extern char &GCMachineCodeAnalysisID; 500212904Sdim 501193323Sed /// Creates a pass to print GC metadata. 502212904Sdim /// 503198090Srdivacky FunctionPass *createGCInfoPrinter(raw_ostream &OS); 504212904Sdim 505234353Sdim /// MachineCSE - This pass performs global CSE on machine instructions. 506234353Sdim extern char &MachineCSEID; 507204642Srdivacky 508234353Sdim /// MachineLICM - This pass performs LICM on machine instructions. 509234353Sdim extern char &MachineLICMID; 510193323Sed 511234353Sdim /// MachineSinking - This pass performs sinking on machine instructions. 512234353Sdim extern char &MachineSinkingID; 513193323Sed 514234353Sdim /// MachineCopyPropagation - This pass performs copy propagation on 515234353Sdim /// machine instructions. 516234353Sdim extern char &MachineCopyPropagationID; 517234353Sdim 518234353Sdim /// PeepholeOptimizer - This pass performs peephole optimizations - 519212904Sdim /// like extension and comparison eliminations. 520234353Sdim extern char &PeepholeOptimizerID; 521202375Srdivacky 522234353Sdim /// OptimizePHIs - This pass optimizes machine instruction PHIs 523203954Srdivacky /// to take advantage of opportunities created during DAG legalization. 524234353Sdim extern char &OptimizePHIsID; 525203954Srdivacky 526234353Sdim /// StackSlotColoring - This pass performs stack slot coloring. 527234353Sdim extern char &StackSlotColoringID; 528193323Sed 529193323Sed /// createStackProtectorPass - This pass adds stack protectors to functions. 530234353Sdim /// 531263508Sdim FunctionPass *createStackProtectorPass(const TargetMachine *TM); 532193323Sed 533193323Sed /// createMachineVerifierPass - This pass verifies cenerated machine code 534193323Sed /// instructions for correctness. 535234353Sdim /// 536218893Sdim FunctionPass *createMachineVerifierPass(const char *Banner = 0); 537193323Sed 538193323Sed /// createDwarfEHPass - This pass mulches exception handling code into a form 539193323Sed /// adapted to code generation. Required if using dwarf exception handling. 540263508Sdim FunctionPass *createDwarfEHPass(const TargetMachine *TM); 541193323Sed 542234353Sdim /// createSjLjEHPreparePass - This pass adapts exception handling code to use 543198090Srdivacky /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow. 544234353Sdim /// 545263508Sdim FunctionPass *createSjLjEHPreparePass(const TargetMachine *TM); 546198090Srdivacky 547234353Sdim /// LocalStackSlotAllocation - This pass assigns local frame indices to stack 548234353Sdim /// slots relative to one another and allocates base registers to access them 549234353Sdim /// when it is estimated by the target to be out of range of normal frame 550234353Sdim /// pointer or stack pointer index addressing. 551234353Sdim extern char &LocalStackSlotAllocationID; 552212904Sdim 553234353Sdim /// ExpandISelPseudos - This pass expands pseudo-instructions. 554234353Sdim extern char &ExpandISelPseudosID; 555218893Sdim 556226633Sdim /// createExecutionDependencyFixPass - This pass fixes execution time 557226633Sdim /// problems with dependent instructions, such as switching execution 558226633Sdim /// domains to match. 559226633Sdim /// 560226633Sdim /// The pass will examine instructions using and defining registers in RC. 561226633Sdim /// 562226633Sdim FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC); 563226633Sdim 564234353Sdim /// UnpackMachineBundles - This pass unpack machine instruction bundles. 565234353Sdim extern char &UnpackMachineBundlesID; 566234353Sdim 567234353Sdim /// FinalizeMachineBundles - This pass finalize machine instruction 568234353Sdim /// bundles (created earlier, e.g. during pre-RA scheduling). 569234353Sdim extern char &FinalizeMachineBundlesID; 570234353Sdim 571193323Sed} // End llvm namespace 572193323Sed 573193323Sed#endif 574