ChangeLog.gcc43 revision 259563
12007-08-08 Andrew Haley <aph@redhat.com> (r128087) 2 3 * config/arm/libunwind.S (UNWIND_WRAPPER _Unwind_Backtrace): New. 4 * config/arm/unwind-arm.h (__gnu_Unwind_Backtrace): New. 5 * config/arm/unwind-arm.c (__gnu_Unwind_Backtrace): New. 6 72007-06-05 Joerg Wunsch <j.gnu@uriah.heep.sax.de> (r125346) 8 9 PR preprocessor/23479 10 * doc/extend.texi: Document the 0b-prefixed binary integer 11 constant extension. 12 132007-05-31 Eric Christopher <echristo@apple.com> 14 15 * expr.c (convert_move): Assert that we don't have a BLKmode 16 operand. 17 (store_expr): Handle BLKmode moves by calling emit_block_move. 18 192007-05-24 Richard Sandiford <rsandifo@nildram.co.uk> (r125037) 20 21 * postreload-gcse.c (reg_changed_after_insn_p): New function. 22 (oprs_unchanged_p): Use it to check all registers in a REG. 23 (record_opr_changes): Look for clobbers in CALL_INSN_FUNCTION_USAGE. 24 (reg_set_between_after_reload_p): Delete. 25 (reg_used_between_after_reload_p): Likewise. 26 (reg_set_or_used_since_bb_start): Likewise. 27 (eliminate_partially_redundant_load): Use reg_changed_after_insn_p 28 and reg_used_between_p instead of reg_set_or_used_since_bb_start. 29 Use reg_set_between_p instead of reg_set_between_after_reload_p. 30 * rtlanal.c (reg_set_p): Check whether REG overlaps 31 regs_invalidated_by_call, rather than just checking the 32 membership of REGNO (REG). 33 342007-05-03 Ian Lance Taylor <iant@google.com> (r124381) 35 36 * config/rs6000/rs6000.c (rs6000_override_options): Don't set 37 MASK_PPC_GFXOPT for 8540 or 8548. 38 392007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124341) 40 41 * doc/invoke.texi: Fix typo, 'AMD Family 10h core' instead of 42 'AMD Family 10 core'. 43 442007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124339) 45 46 * config/i386/i386.c (override_options): Accept k8-sse3, opteron-sse3 47 and athlon64-sse3 as improved versions of k8, opteron and athlon64 48 with SSE3 instruction set support. 49 * doc/invoke.texi: Likewise. 50 512007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124330) 52 53 * config/i386/i386.c (override_options): Tuning 32-byte loop 54 alignment for amdfam10 architecture. Increasing the max loop 55 alignment to 24 bytes. 56 572007-04-16 Lawrence Crowl <crowl@google.com> 58 59 * doc/invoke.texi (Debugging Options): Add documentation for the 60 -femit-struct-debug options -femit-struct-debug-baseonly, 61 -femit-struct-debug-reduced, and 62 -femit-struct-debug-detailed[=...]. 63 64 * c-opts.c (c_common_handle_option): Add 65 OPT_femit_struct_debug_baseonly, OPT_femit_struct_debug_reduced, 66 and OPT_femit_struct_debug_detailed_. 67 * c.opt: Add specifications for 68 -femit-struct-debug-baseonly, -femit-struct-debug-reduced, 69 and -femit-struct-debug-detailed[=...]. 70 * opts.c (set_struct_debug_option): Parse the 71 -femit-struct-debug-... options. 72 * opts.c (matches_main_base, main_input_basename, 73 main_input_baselength, base_of_path, matches_main_base): Add 74 variables and functions to compare header base name to compilation 75 unit base name. 76 * opts.c (should_emit_struct_debug): Add to determine to emit a 77 structure based on the option. 78 (dump_struct_debug) Also disabled function to debug this 79 function. 80 * opts.c (handle_options): Save the base name of the 81 compilation unit. 82 83 * langhooks-def.h (LANG_HOOKS_GENERIC_TYPE_P): Define. 84 (LANG_HOOKS_FOR_TYPES_INITIALIZER): Add. 85 This hook indicates if a type is generic. Set it by default 86 to "never generic". 87 * langhooks.h (struct lang_hooks_for_types): Add a new hook 88 to determine if a struct type is generic or not. 89 * cp/cp-tree.h (class_tmpl_impl_spec_p): Declare a C++ hook. 90 * cp/tree.c (class_tmpl_impl_spec_p): Implement the C++ hook. 91 * cp/cp-lang.c (LANG_HOOKS_GENERIC_TYPE_P): Override null C hook 92 with live C++ hook. 93 94 * flags.h (enum debug_info_usage): Add an enumeration to describe 95 a program's use of a structure type. 96 * dwarf2out.c (gen_struct_or_union_type_die): Add a new parameter 97 to indicate the program's usage of the type. Filter structs based 98 on the -femit-struct-debug-... specification. 99 (gen_type_die): Split into two routines, gen_type_die and 100 gen_type_die_with_usage. gen_type_die is now a wrapper 101 that assumes direct usage. 102 (gen_type_die_with_usage): Replace calls to gen_type_die 103 with gen_type_die_with_usage adding the program usage of 104 the referenced type. 105 (dwarf2out_imported_module_or_decl): Suppress struct debug 106 information using should_emit_struct_debug when appropriate. 107 1082007-04-16 Ian Lance Taylor <iant@google.com> (r123906) 109 110 * tree-ssa-propagate.c (cfg_blocks_add): Insert blocks with fewer 111 predecessors at head rather than tail. 112 113 1142007-04-12 Richard Guenther <rguenther@suse.de> (r123736) 115 116 PR tree-optimization/24689 117 PR tree-optimization/31307 118 * fold-const.c (operand_equal_p): Compare INTEGER_CST array 119 indices by value. 120 * gimplify.c (canonicalize_addr_expr): To be consistent with 121 gimplify_compound_lval only set operands two and three of 122 ARRAY_REFs if they are not gimple_min_invariant. This makes 123 it never at this place. 124 * tree-ssa-ccp.c (maybe_fold_offset_to_array_ref): Likewise. 125 1262007-04-07 H.J. Lu <hongjiu.lu@intel.com> (r123639) 127 128 * config/i386/i386.c (ix86_handle_option): Handle SSSE3. 129 1302007-03-28 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r123313) 131 132 * config.gcc: Accept barcelona as a variant of amdfam10. 133 * config/i386/i386.c (override_options): Likewise. 134 * doc/invoke.texi: Likewise. 135 1362007-03-12 Seongbae Park <seongbae.park@gmail.com> 137 138 * c-decl.c (warn_variable_length_array): New function. 139 Refactored from grokdeclarator to handle warn_vla 140 and handle unnamed array case. 141 (grokdeclarator): Refactored VLA warning case. 142 * c.opt (Wvla): New flag. 143 1442007-03-11 Ian Lance Taylor <iant@google.com> (r122831 - partial) 145 146 * tree-vrp.c (vrp_int_const_binop): Handle PLUS_EXPR and 147 the *_DIV_EXPR codes correctly with overflow infinities. 148 1492007-02-09 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r121763) 150 151 * config/i386/driver-i386.c: Turn on -mtune=native for AMDFAM10. 152 (bit_SSE4a): New. 153 1542007-02-08 Harsha Jagasia <harsha.jagasia@amd.com> (r121726) 155 156 * config/i386/xmmintrin.h: Make inclusion of emmintrin.h 157 conditional to __SSE2__. 158 (Entries below should have been added to first ChangeLog 159 entry for amdfam10 dated 2007-02-05) 160 * config/i386/emmintrin.h: Generate #error if __SSE2__ is not 161 defined. 162 * config/i386/pmmintrin.h: Generate #error if __SSE3__ is not 163 defined. 164 * config/i386/tmmintrin.h: Generate #error if __SSSE3__ is not 165 defined. 166 1672007-02-07 Jakub Jelinek <jakub@redhat.com> (r121687) 168 169 * config/i386/i386.c (override_options): Set PTA_SSSE3 for core2. 170 1712007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 172 173 * config/i386/athlon.md (athlon_fldxf_k8, athlon_fld_k8, 174 athlon_fstxf_k8, athlon_fst_k8, athlon_fist, athlon_fmov, 175 athlon_fadd_load, athlon_fadd_load_k8, athlon_fadd, athlon_fmul, 176 athlon_fmul_load, athlon_fmul_load_k8, athlon_fsgn, 177 athlon_fdiv_load, athlon_fdiv_load_k8, athlon_fdiv_k8, 178 athlon_fpspc_load, athlon_fpspc, athlon_fcmov_load, 179 athlon_fcmov_load_k8, athlon_fcmov_k8, athlon_fcomi_load_k8, 180 athlon_fcomi, athlon_fcom_load_k8, athlon_fcom): Added amdfam10. 181 1822007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 183 184 * config/i386/i386.md (x86_sahf_1, cmpfp_i_mixed, cmpfp_i_sse, 185 cmpfp_i_i387, cmpfp_iu_mixed, cmpfp_iu_sse, cmpfp_iu_387, 186 swapsi, swaphi_1, swapqi_1, swapdi_rex64, fix_truncsfdi_sse, 187 fix_truncdfdi_sse, fix_truncsfsi_sse, fix_truncdfsi_sse, 188 x86_fldcw_1, floatsisf2_mixed, floatsisf2_sse, floatdisf2_mixed, 189 floatdisf2_sse, floatsidf2_mixed, floatsidf2_sse, 190 floatdidf2_mixed, floatdidf2_sse, muldi3_1_rex64, mulsi3_1, 191 mulsi3_1_zext, mulhi3_1, mulqi3_1, umulqihi3_1, mulqihi3_insn, 192 umulditi3_insn, umulsidi3_insn, mulditi3_insn, mulsidi3_insn, 193 umuldi3_highpart_rex64, umulsi3_highpart_insn, 194 umulsi3_highpart_zext, smuldi3_highpart_rex64, 195 smulsi3_highpart_insn, smulsi3_highpart_zext, x86_64_shld, 196 x86_shld_1, x86_64_shrd, sqrtsf2_mixed, sqrtsf2_sse, 197 sqrtsf2_i387, sqrtdf2_mixed, sqrtdf2_sse, sqrtdf2_i387, 198 sqrtextendsfdf2_i387, sqrtxf2, sqrtextendsfxf2_i387, 199 sqrtextenddfxf2_i387): Added amdfam10_decode. 200 201 * config/i386/athlon.md (athlon_idirect_amdfam10, 202 athlon_ivector_amdfam10, athlon_idirect_load_amdfam10, 203 athlon_ivector_load_amdfam10, athlon_idirect_both_amdfam10, 204 athlon_ivector_both_amdfam10, athlon_idirect_store_amdfam10, 205 athlon_ivector_store_amdfam10): New define_insn_reservation. 206 (athlon_idirect_loadmov, athlon_idirect_movstore): Added 207 amdfam10. 208 2092007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 210 211 * config/i386/athlon.md (athlon_call_amdfam10, 212 athlon_pop_amdfam10, athlon_lea_amdfam10): New 213 define_insn_reservation. 214 (athlon_branch, athlon_push, athlon_leave_k8, athlon_imul_k8, 215 athlon_imul_k8_DI, athlon_imul_mem_k8, athlon_imul_mem_k8_DI, 216 athlon_idiv, athlon_idiv_mem, athlon_str): Added amdfam10. 217 2182007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 219 220 * config/i386/athlon.md (athlon_sseld_amdfam10, 221 athlon_mmxld_amdfam10, athlon_ssest_amdfam10, 222 athlon_mmxssest_short_amdfam10): New define_insn_reservation. 223 2242007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 225 226 * config/i386/athlon.md (athlon_sseins_amdfam10): New 227 define_insn_reservation. 228 * config/i386/i386.md (sseins): Added sseins to define_attr type 229 and define_attr unit. 230 * config/i386/sse.md: Set type attribute to sseins for insertq 231 and insertqi. 232 2332007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 234 235 * config/i386/athlon.md (sselog_load_amdfam10, sselog_amdfam10, 236 ssecmpvector_load_amdfam10, ssecmpvector_amdfam10, 237 ssecomi_load_amdfam10, ssecomi_amdfam10, 238 sseaddvector_load_amdfam10, sseaddvector_amdfam10): New 239 define_insn_reservation. 240 (ssecmp_load_k8, ssecmp, sseadd_load_k8, seadd): Added amdfam10. 241 2422007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 243 244 * config/i386/athlon.md (cvtss2sd_load_amdfam10, 245 cvtss2sd_amdfam10, cvtps2pd_load_amdfam10, cvtps2pd_amdfam10, 246 cvtsi2sd_load_amdfam10, cvtsi2ss_load_amdfam10, 247 cvtsi2sd_amdfam10, cvtsi2ss_amdfam10, cvtsd2ss_load_amdfam10, 248 cvtsd2ss_amdfam10, cvtpd2ps_load_amdfam10, cvtpd2ps_amdfam10, 249 cvtsX2si_load_amdfam10, cvtsX2si_amdfam10): New 250 define_insn_reservation. 251 252 * config/i386/sse.md (cvtsi2ss, cvtsi2ssq, cvtss2si, 253 cvtss2siq, cvttss2si, cvttss2siq, cvtsi2sd, cvtsi2sdq, 254 cvtsd2si, cvtsd2siq, cvttsd2si, cvttsd2siq, 255 cvtpd2dq, cvttpd2dq, cvtsd2ss, cvtss2sd, 256 cvtpd2ps, cvtps2pd): Added amdfam10_decode attribute. 257 2582007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 259 260 * config/i386/athlon.md (athlon_ssedivvector_amdfam10, 261 athlon_ssedivvector_load_amdfam10, athlon_ssemulvector_amdfam10, 262 athlon_ssemulvector_load_amdfam10): New define_insn_reservation. 263 (athlon_ssediv, athlon_ssediv_load_k8, athlon_ssemul, 264 athlon_ssemul_load_k8): Added amdfam10. 265 2662007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 267 268 * config/i386/i386.h (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL): New macro. 269 (x86_sse_unaligned_move_optimal): New variable. 270 271 * config/i386/i386.c (x86_sse_unaligned_move_optimal): Enable for 272 m_AMDFAM10. 273 (ix86_expand_vector_move_misalign): Add code to generate movupd/movups 274 for unaligned vector SSE double/single precision loads for AMDFAM10. 275 2762007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 277 278 * config/i386/i386.h (TARGET_AMDFAM10): New macro. 279 (TARGET_CPU_CPP_BUILTINS): Add code for amdfam10. 280 Define TARGET_CPU_DEFAULT_amdfam10. 281 (TARGET_CPU_DEFAULT_NAMES): Add amdfam10. 282 (processor_type): Add PROCESSOR_AMDFAM10. 283 284 * config/i386/i386.md: Add amdfam10 as a new cpu attribute to match 285 processor_type in config/i386/i386.h. 286 Enable imul peepholes for TARGET_AMDFAM10. 287 288 * config.gcc: Add support for --with-cpu option for amdfam10. 289 290 * config/i386/i386.c (amdfam10_cost): New variable. 291 (m_AMDFAM10): New macro. 292 (m_ATHLON_K8_AMDFAM10): New macro. 293 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen, 294 x86_cmove, x86_3dnow_a, x86_deep_branch, x86_use_simode_fiop, 295 x86_promote_QImode, x86_integer_DFmode_moves, 296 x86_partial_reg_dependency, x86_memory_mismatch_stall, 297 x86_accumulate_outgoing_args, x86_arch_always_fancy_math_387, 298 x86_sse_partial_reg_dependency, x86_sse_typeless_stores, 299 x86_use_ffreep, x86_use_incdec, x86_four_jump_limit, 300 x86_schedule, x86_use_bt, x86_cmpxchg16b, x86_pad_returns): 301 Enable/disable for amdfam10. 302 (override_options): Add amdfam10_cost to processor_target_table. 303 Set up PROCESSOR_AMDFAM10 for amdfam10 entry in 304 processor_alias_table. 305 (ix86_issue_rate): Add PROCESSOR_AMDFAM10. 306 (ix86_adjust_cost): Add code for amdfam10. 307 3082007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 309 310 * config/i386/i386.opt: Add new Advanced Bit Manipulation (-mabm) 311 instruction set feature flag. Add new (-mpopcnt) flag for popcnt 312 instruction. Add new SSE4A (-msse4a) instruction set feature flag. 313 * config/i386/i386.h: Add builtin definition for SSE4A. 314 * config/i386/i386.md: Add support for ABM instructions 315 (popcnt and lzcnt). 316 * config/i386/sse.md: Add support for SSE4A instructions 317 (movntss, movntsd, extrq, insertq). 318 * config/i386/i386.c: Add support for ABM and SSE4A builtins. 319 Add -march=amdfam10 flag. 320 * config/i386/ammintrin.h: Add support for SSE4A intrinsics. 321 * doc/invoke.texi: Add documentation on flags for sse4a, abm, popcnt 322 and amdfam10. 323 * doc/extend.texi: Add documentation for SSE4A builtins. 324 3252007-01-24 Jakub Jelinek <jakub@redhat.com> (r121140) 326 327 * config/i386/i386.h (x86_cmpxchg16b): Remove const. 328 (TARGET_CMPXCHG16B): Define to x86_cmpxchg16b. 329 * config/i386/i386.c (x86_cmpxchg16b): Remove const. 330 (override_options): Add PTA_CX16 flag. Set x86_cmpxchg16b 331 for CPUs that have PTA_CX16 set. 332 3332007-01-17 Eric Christopher <echristo@apple.com> (r120846) 334 335 * config.gcc: Support core2 processor. 336 3372006-12-13 Ian Lance Taylor <iant@google.com> (r119855) 338 339 PR c++/19564 340 PR c++/19756 341 * c-typeck.c (parser_build_binary_op): Move parentheses warnings 342 to warn_about_parentheses in c-common.c. 343 * c-common.c (warn_about_parentheses): New function. 344 * c-common.h (warn_about_parentheses): Declare. 345 * doc/invoke.texi (Warning Options): Update -Wparentheses 346 description. 347 3482006-12-12 Geoffrey Keating <geoffk@apple.com> (r119820) 349 350 * mips-tdump.c: Replace CROSS_COMPILE with 351 CROSS_DIRECTORY_STRUCTURE. 352 * mips-tfile.c: Likewise. 353 * gcc.c: Likewise. 354 * configure.ac: Likewise. 355 * cppdefault.c: Likewise. 356 * Makefile.in: Likewise. 357 * config/alpha/osf.h: Likewise. 358 * config/i386/cygwin.h: Likewise. 359 * config/i386/beos-elf.h: Likewise. 360 * config/i386/nto.h: Likewise. 361 * config/svr4.h: Likewise. 362 * config/rs6000/aix.h: Likewise. 363 * config/rs6000/sysv4.h: Likewise. 364 * collect2.c: Likewise. 365 * configure: Regenerate. 366 367 * doc/tm.texi (Alignment Output): Document that ASM_OUTPUT_SKIP 368 actually takes an unsigned HOST_WIDE_INT for its second parameter. 369 3702006-12-02 H.J. Lu <hongjiu.lu@intel.com> (r119454 - partial) 371 372 PR target/30040 373 * config/i386/driver-i386.c (bit_SSSE3): New. 374 3752006-11-27 Uros Bizjak <ubizjak@gmail.com> (r119260) 376 377 * config/i386/i386.c (x86_ext_80387_constants): Add m_K8, m_CORE2 378 and m_GENERIC64. 379 3802006-11-18 Vladimir Makarov <vmakarov@redhat.com> (r118973) 381 382 * doc/invoke.texi (core2): Add item. 383 384 * config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New 385 macros. 386 (TARGET_CPU_CPP_BUILTINS): Add code for core2. 387 (TARGET_CPU_DEFAULT_generic): Change value. 388 (TARGET_CPU_DEFAULT_NAMES): Add core2. 389 (processor_type): Add new constant PROCESSOR_CORE2. 390 391 * config/i386/i386.md (cpu): Add core2. 392 393 * config/i386/i386.c (core2_cost): New initialized variable. 394 (m_CORE2): New macro. 395 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen, 396 x86_deep_branch, x86_partial_reg_stall, x86_use_simode_fiop, 397 x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8, 398 x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves, 399 x86_partial_reg_dependency, x86_memory_mismatch_stall, 400 x86_accumulate_outgoing_args, x86_prologue_using_move, 401 x86_epilogue_using_move, x86_arch_always_fancy_math_387, 402 x86_sse_partial_reg_dependency, x86_rep_movl_optimal, 403 x86_use_incdec, x86_four_jump_limit, x86_schedule, 404 x86_pad_returns): Add m_CORE2. 405 (override_options): Add entries for Core2. 406 (ix86_issue_rate): Add case for Core2. 407 4082006-11-07 Eric Christopher <echristo@apple.com> (r118576) 409 410 * libgcc2.c (__bswapdi2): Rename from bswapDI2. 411 (__bswapsi2): Ditto. 412 * libgcc2.h: Remove transformation of bswap routines. 413 * config/i386/i386.md (bswapsi2): New. 414 (bswapdi2): Ditto. 415 4162006-10-31 Geoffrey Keating <geoffk@apple.com> (r118360) 417 418 * coverage.c (coverage_checksum_string): Update comment. 419 * dwarf2out.c (switch_to_eh_frame_section): Update for removal 420 of get_file_function_name. 421 * cgraphunit.c (cgraph_build_static_cdtor): Update for rename 422 of get_file_function_name_long. 423 * tree.c (get_file_function_name): Rename from 424 get_file_function_name_long; improve comment; handle 'I' and 'D' 425 specially when the target has ctor/dtor support; remove special 426 handling for 'F'. 427 (get_file_function_name): Remove. 428 * tree.h (get_file_function_name): Rename from 429 get_file_function_name_long. 430 (get_file_function_name): Remove prototype. 431 4322006-10-31 Geoffrey Keating <geoffk@apple.com> (r118356) 433 434 * c-decl.c (grokdeclarator): Don't set DECL_EXTERNAL on 435 inline static functions in c99 mode. 436 437 PR 16622 438 * doc/extend.texi (Inline): Update. 439 * c-tree.h (struct language_function): Remove field 'extern_inline'. 440 * c-decl.c (current_extern_inline): Delete. 441 (pop_scope): Adjust test for an undefined nested function. 442 Add warning about undeclared inline function. 443 (diagnose_mismatched_decls): Update comments. Disallow overriding 444 of inline functions in a translation unit in C99. Allow inline 445 declarations in C99 at any time. 446 (merge_decls): Boolize variables. Handle C99 'extern inline' 447 semantics. 448 (grokdeclarator): Set DECL_EXTERNAL here for functions. Handle 449 C99 inline semantics. 450 (start_function): Don't clear current_extern_inline. Don't set 451 DECL_EXTERNAL. 452 (c_push_function_context): Don't push current_extern_inline. 453 (c_pop_function_context): Don't restore current_extern_inline. 454 455 PR 11377 456 * c-typeck.c (build_external_ref): Warn about static variables 457 used in extern inline functions. 458 * c-decl.c (start_decl): Warn about static variables declared 459 in extern inline functions. 460 4612006-10-27 Vladimir Makarov <vmakarov@redhat.com> (r118090) 462 463 * config/i386/i386.h (TARGET_GEODE): 464 (TARGET_CPU_CPP_BUILTINS): Add code for geode. 465 (TARGET_CPU_DEFAULT_geode): New macro. 466 (TARGET_CPU_DEFAULT_k6, TARGET_CPU_DEFAULT_k6_2, 467 TARGET_CPU_DEFAULT_k6_3, TARGET_CPU_DEFAULT_athlon, 468 TARGET_CPU_DEFAULT_athlon_sse, TARGET_CPU_DEFAULT_k8, 469 TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_prescott, 470 TARGET_CPU_DEFAULT_nocona, TARGET_CPU_DEFAULT_generic): Increase 471 the macro values. 472 (TARGET_CPU_DEFAULT_NAMES): Add geode. 473 (processor_type): Add PROCESSOR_GEODE. 474 475 * config/i386/i386.md: Include geode.md. 476 (cpu): Add geode. 477 478 * config/i386/i386.c (geode_cost): New initialized global 479 variable. 480 (m_GEODE, m_K6_GEODE): New macros. 481 (x86_use_leave, x86_push_memory, x86_deep_branch, x86_use_sahf, 482 x86_use_himode_fiop, x86_promote_QImode, x86_add_esp_4, 483 x86_add_esp_8, x86_rep_movl_optimal, x86_ext_80387_constants, 484 x86_schedule): Use m_K6_GEODE instead of m_K6. 485 (x86_movx, x86_cmove): Set up m_GEODE. 486 (x86_integer_DFmode_moves): Clear m_GEODE. 487 (processor_target_table): Add entry for geode. 488 (processor_alias_table): Ditto. 489 490 * config/i386/geode.md: New file. 491 492 * doc/invoke.texi: Add entry about geode processor. 493 4942006-10-24 Richard Guenther <rguenther@suse.de> (r118001) 495 496 PR middle-end/28796 497 * builtins.c (fold_builtin_classify): Use HONOR_INFINITIES 498 and HONOR_NANS instead of MODE_HAS_INFINITIES and MODE_HAS_NANS 499 for deciding optimizations in consistency with fold-const.c 500 (fold_builtin_unordered_cmp): Likewise. 501 5022006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117958) 503 504 * config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers. 505 (x86_64-*-*): Likewise. 506 507 * config/i386/i386.c (pta_flags): Add PTA_SSSE3. 508 (override_options): Check SSSE3. 509 (ix86_builtins): Add IX86_BUILTIN_PHADDW, IX86_BUILTIN_PHADDD, 510 IX86_BUILTIN_PHADDSW, IX86_BUILTIN_PHSUBW, IX86_BUILTIN_PHSUBD, 511 IX86_BUILTIN_PHSUBSW, IX86_BUILTIN_PMADDUBSW, 512 IX86_BUILTIN_PMULHRSW, IX86_BUILTIN_PSHUFB, 513 IX86_BUILTIN_PSIGNB, IX86_BUILTIN_PSIGNW, IX86_BUILTIN_PSIGND, 514 IX86_BUILTIN_PALIGNR, IX86_BUILTIN_PABSB, IX86_BUILTIN_PABSW, 515 IX86_BUILTIN_PABSD, IX86_BUILTIN_PHADDW128, 516 IX86_BUILTIN_PHADDD128, IX86_BUILTIN_PHADDSW128, 517 IX86_BUILTIN_PHSUBW128, IX86_BUILTIN_PHSUBD128, 518 IX86_BUILTIN_PHSUBSW128, IX86_BUILTIN_PMADDUBSW128, 519 IX86_BUILTIN_PMULHRSW128, IX86_BUILTIN_PSHUFB128, 520 IX86_BUILTIN_PSIGNB128, IX86_BUILTIN_PSIGNW128, 521 IX86_BUILTIN_PSIGND128, IX86_BUILTIN_PALIGNR128, 522 IX86_BUILTIN_PABSB128, IX86_BUILTIN_PABSW128 and 523 IX86_BUILTIN_PABSD128. 524 (bdesc_2arg): Add SSSE3. 525 (bdesc_1arg): Likewise. 526 (ix86_init_mmx_sse_builtins): Support SSSE3. 527 (ix86_expand_builtin): Likewise. 528 * config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Likewise. 529 530 * config/i386/i386.md (UNSPEC_PSHUFB): New. 531 (UNSPEC_PSIGN): Likewise. 532 (UNSPEC_PALIGNR): Likewise. 533 Include mmx.md before sse.md. 534 535 * config/i386/i386.opt: Add -mssse3. 536 537 * config/i386/sse.md (ssse3_phaddwv8hi3): New pattern for SSSE3. 538 (ssse3_phaddwv4hi3): Likewise. 539 (ssse3_phadddv4si3): Likewise. 540 (ssse3_phadddv2si3): Likewise. 541 (ssse3_phaddswv8hi3): Likewise. 542 (ssse3_phaddswv4hi3): Likewise. 543 (ssse3_phsubwv8hi3): Likewise. 544 (ssse3_phsubwv4hi3): Likewise. 545 (ssse3_phsubdv4si3): Likewise. 546 (ssse3_phsubdv2si3): Likewise. 547 (ssse3_phsubswv8hi3): Likewise. 548 (ssse3_phsubswv4hi3): Likewise. 549 (ssse3_pmaddubswv8hi3): Likewise. 550 (ssse3_pmaddubswv4hi3): Likewise. 551 (ssse3_pmulhrswv8hi3): Likewise. 552 (ssse3_pmulhrswv4hi3): Likewise. 553 (ssse3_pshufbv16qi3): Likewise. 554 (ssse3_pshufbv8qi3): Likewise. 555 (ssse3_psign<mode>3): Likewise. 556 (ssse3_psign<mode>3): Likewise. 557 (ssse3_palignrti): Likewise. 558 (ssse3_palignrdi): Likewise. 559 (abs<mode>2): Likewise. 560 (abs<mode>2): Likewise. 561 562 * config/i386/tmmintrin.h: New file. 563 564 * doc/extend.texi: Document SSSE3 built-in functions. 565 566 * doc/invoke.texi: Document -mssse3/-mno-ssse3 switches. 567 5682006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117959) 569 570 * config/i386/tmmintrin.h: Remove the duplicated content. 571 5722006-10-21 Richard Guenther <rguenther@suse.de> (r117932) 573 574 PR tree-optimization/3511 575 * tree-ssa-pre.c (phi_translate): Fold CALL_EXPRs that 576 got new invariant arguments during PHI translation. 577 5782006-10-21 Richard Guenther <rguenther@suse.de> (r117929) 579 580 * builtins.c (fold_builtin_classify): Fix typo. 581 5822006-09-07 Eric Christopher <echristo@apple.com> (r118361) 583 Falk Hueffner <falk@debian.org> 584 585 * doc/extend.texi (__builtin_bswap32): Document. 586 (__builtin_bswap64): Ditto. 587 * doc/libgcc.texi (bswapsi2): Document. 588 (bswapdi2): Ditto. 589 * doc/rtl.texi (bswap): Document. 590 * optabs.c (expand_unop): Don't widen a bswap. 591 (init_optabs): Init bswap. Set libfuncs explicitly 592 for bswapsi2 and bswapdi2. 593 * optabs.h (OTI_bswap): New. 594 (bswap_optab): Ditto. 595 * genopinit.c (optabs): Handle bswap_optab. 596 * tree.h (tree_index): Add TI_UINT32_TYPE and 597 TI_UINT64_TYPE. 598 (uint32_type_node): New. 599 (uint64_type_node): Ditto. 600 * tree.c (build_common_tree_nodes_2): Initialize 601 uint32_type_node and uint64_type_node. 602 * builtins.c (expand_builtin_bswap): New. 603 (expand_builtin): Call. 604 (fold_builtin_bswap): New. 605 (fold_builtin_1): Call. 606 * fold-const.c (tree_expr_nonnegative_p): Return true 607 for bswap. 608 * builtin-types.def (BT_UINT32): New. 609 (BT_UINT64): Ditto. 610 (BT_FN_UINT32_UINT32): Ditto. 611 (BT_FN_UINT64_UINT64): Ditto. 612 * builtins.def (BUILT_IN_BSWAP32): New. 613 (BUILT_IN_BSWAP64): Ditto. 614 * rtl.def (BSWAP): New. 615 * genattrtab.c (check_attr_value): New. 616 * libgcc2.c (__bswapSI2): New. 617 (__bswapDI2): Ditto. 618 * libgcc2.h (__bswapSI2): Declare. 619 (__bswapDI2): Ditto. 620 * mklibgcc.in (lib2funcs): Add _bswapsi2 and _bswapdi2. 621 * simplify-rtx.c (simplify_const_unary_operation): Return 622 0 for BSWAP. 623 * libgcc-std.ver (__bwapsi2): Add. 624 (__bswapdi2): Ditto. 625 * reload1.c (eliminate_regs_1): Add bswap. 626 (elimination_effects): Ditto. 627 * config/i386/i386.h (x86_bswap): New. 628 (TARGET_BSWAP): Use. 629 * config/i386/i386.c (x86_bswap): Set. 630