i386-opc.h revision 261307 
1/* Declarations for Intel 80386 opcode table
2   Copyright 2007
3   Free Software Foundation, Inc.
4
5   This file is part of GAS, the GNU Assembler.
6
7   GAS is free software; you can redistribute it and/or modify
8   it under the terms of the GNU General Public License as published by
9   the Free Software Foundation; either version 2, or (at your option)
10   any later version.
11
12   GAS is distributed in the hope that it will be useful,
13   but WITHOUT ANY WARRANTY; without even the implied warranty of
14   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15   GNU General Public License for more details.
16
17   You should have received a copy of the GNU General Public License
18   along with GAS; see the file COPYING.  If not, write to the Free
19   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20   02110-1301, USA.  */
21
22#include "opcode/i386.h"
23
24typedef struct template
25{
26  /* instruction name sans width suffix ("mov" for movl insns) */
27  char *name;
28
29  /* how many operands */
30  unsigned int operands;
31
32  /* base_opcode is the fundamental opcode byte without optional
33     prefix(es).  */
34  unsigned int base_opcode;
35#define Opcode_D	0x2 /* Direction bit:
36			       set if Reg --> Regmem;
37			       unset if Regmem --> Reg. */
38#define Opcode_FloatR	0x8 /* Bit to swap src/dest for float insns. */
39#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
40
41  /* extension_opcode is the 3 bit extension for group <n> insns.
42     This field is also used to store the 8-bit opcode suffix for the
43     AMD 3DNow! instructions.
44     If this template has no extension opcode (the usual case) use None */
45  unsigned int extension_opcode;
46#define None 0xffff		/* If no extension_opcode is possible.  */
47
48  /* cpu feature flags */
49  unsigned int cpu_flags;
50#define Cpu186		  0x1	/* i186 or better required */
51#define Cpu286		  0x2	/* i286 or better required */
52#define Cpu386		  0x4	/* i386 or better required */
53#define Cpu486		  0x8	/* i486 or better required */
54#define Cpu586		 0x10	/* i585 or better required */
55#define Cpu686		 0x20	/* i686 or better required */
56#define CpuP4		 0x40	/* Pentium4 or better required */
57#define CpuK6		 0x80	/* AMD K6 or better required*/
58#define CpuSledgehammer 0x100	/* Sledgehammer or better required */
59#define CpuMMX		0x200	/* MMX support required */
60#define CpuMMX2		0x400	/* extended MMX support (with SSE or 3DNow!Ext) required */
61#define CpuSSE		0x800	/* Streaming SIMD extensions required */
62#define CpuSSE2	       0x1000	/* Streaming SIMD extensions 2 required */
63#define Cpu3dnow       0x2000	/* 3dnow! support required */
64#define Cpu3dnowA      0x4000	/* 3dnow!Extensions support required */
65#define CpuSSE3	       0x8000	/* Streaming SIMD extensions 3 required */
66#define CpuPadLock    0x10000	/* VIA PadLock required */
67#define CpuSVME	      0x20000	/* AMD Secure Virtual Machine Ext-s required */
68#define CpuVMX	      0x40000	/* VMX Instructions required */
69#define CpuSSSE3      0x80000	/* Supplemental Streaming SIMD extensions 3 required */
70#define CpuSSE4a     0x100000   /* SSE4a New Instuctions required */
71#define CpuABM       0x200000   /* ABM New Instructions required */
72#define CpuSSE4_1    0x400000	/* SSE4.1 Instructions required */
73#define CpuSSE4_2    0x800000	/* SSE4.2 Instructions required */
74#define CpuXSAVE    0x1000000	/* XSAVE Instructions required */
75#define CpuAES      0x2000000	/* AES Instructions required */
76
77  /* These flags are set by gas depending on the flag_code.  */
78#define Cpu64	     0x4000000   /* 64bit support required  */
79#define CpuNo64      0x8000000   /* Not supported in the 64bit mode  */
80
81#define CpuPCLMUL   0x10000000	/* Carry-less Multiplication extensions */
82#define CpuRdRnd    0x20000000	/* Intel Random Number Generator extensions */
83#define CpuSMAP     0x40000000	/* Intel Supervisor Mode Access Prevention */
84
85/* SSE4.1/4.2 Instructions required */
86#define CpuSSE4	     (CpuSSE4_1|CpuSSE4_2)
87
88  /* The default value for unknown CPUs - enable all features to avoid problems.  */
89#define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
90	|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \
91	|Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuSSE4_1 \
92	|CpuSSE4_2|CpuABM|CpuSSE4a|CpuXSAVE|CpuAES|CpuPCLMUL|CpuRdRnd|CpuSMAP)
93
94  /* the bits in opcode_modifier are used to generate the final opcode from
95     the base_opcode.  These bits also are used to detect alternate forms of
96     the same instruction */
97  unsigned int opcode_modifier;
98
99  /* opcode_modifier bits: */
100#define D		   0x1	/* has direction bit. */
101#define W		   0x2	/* set if operands can be words or dwords
102				   encoded the canonical way */
103#define Modrm		   0x4	/* insn has a modrm byte. */
104#define ShortForm	   0x8	/* register is in low 3 bits of opcode */
105#define Jump		  0x10	/* special case for jump insns.  */
106#define JumpDword	  0x20  /* call and jump */
107#define JumpByte	  0x40  /* loop and jecxz */
108#define JumpInterSegment  0x80	/* special case for intersegment leaps/calls */
109#define FloatMF		 0x100	/* FP insn memory format bit, sized by 0x4 */
110#define FloatR		 0x200	/* src/dest swap for floats. */
111#define FloatD		 0x400	/* has float insn direction bit. */
112#define Size16		 0x800	/* needs size prefix if in 32-bit mode */
113#define Size32		0x1000	/* needs size prefix if in 16-bit mode */
114#define Size64		0x2000	/* needs size prefix if in 64-bit mode */
115#define IgnoreSize      0x4000  /* instruction ignores operand size prefix */
116#define DefaultSize     0x8000  /* default insn size depends on mode */
117#define No_bSuf	       0x10000	/* b suffix on instruction illegal */
118#define No_wSuf	       0x20000	/* w suffix on instruction illegal */
119#define No_lSuf	       0x40000 	/* l suffix on instruction illegal */
120#define No_sSuf	       0x80000	/* s suffix on instruction illegal */
121#define No_qSuf       0x100000  /* q suffix on instruction illegal */
122#define No_xSuf       0x200000  /* x suffix on instruction illegal */
123#define FWait	      0x400000	/* instruction needs FWAIT */
124#define IsString      0x800000	/* quick test for string instructions */
125#define RegKludge    0x1000000	/* fake an extra reg operand for clr, imul
126				   and special register processing for
127				   some instructions.  */
128#define IsPrefix     0x2000000	/* opcode is a prefix */
129#define ImmExt	     0x4000000	/* instruction has extension in 8 bit imm */
130#define NoRex64	     0x8000000  /* instruction don't need Rex64 prefix.  */
131#define Rex64	    0x10000000  /* instruction require Rex64 prefix.  */
132#define Ugh	    0x20000000	/* deprecated fp insn, gets a warning */
133
134#define NoSuf		(No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf)
135
136  /* operand_types[i] describes the type of operand i.  This is made
137     by OR'ing together all of the possible type masks.  (e.g.
138     'operand_types[i] = Reg|Imm' specifies that operand i can be
139     either a register or an immediate operand.  */
140  unsigned int operand_types[MAX_OPERANDS];
141
142  /* operand_types[i] bits */
143  /* register */
144#define Reg8		   0x1	/* 8 bit reg */
145#define Reg16		   0x2	/* 16 bit reg */
146#define Reg32		   0x4	/* 32 bit reg */
147#define Reg64		   0x8	/* 64 bit reg */
148  /* immediate */
149#define Imm8		  0x10	/* 8 bit immediate */
150#define Imm8S		  0x20	/* 8 bit immediate sign extended */
151#define Imm16		  0x40	/* 16 bit immediate */
152#define Imm32		  0x80	/* 32 bit immediate */
153#define Imm32S		 0x100	/* 32 bit immediate sign extended */
154#define Imm64		 0x200	/* 64 bit immediate */
155#define Imm1		 0x400	/* 1 bit immediate */
156  /* memory */
157#define BaseIndex	 0x800
158  /* Disp8,16,32 are used in different ways, depending on the
159     instruction.  For jumps, they specify the size of the PC relative
160     displacement, for baseindex type instructions, they specify the
161     size of the offset relative to the base register, and for memory
162     offset instructions such as `mov 1234,%al' they specify the size of
163     the offset relative to the segment base.  */
164#define Disp8		0x1000	/* 8 bit displacement */
165#define Disp16		0x2000	/* 16 bit displacement */
166#define Disp32		0x4000	/* 32 bit displacement */
167#define Disp32S	        0x8000	/* 32 bit signed displacement */
168#define Disp64	       0x10000	/* 64 bit displacement */
169  /* specials */
170#define InOutPortReg   0x20000	/* register to hold in/out port addr = dx */
171#define ShiftCount     0x40000	/* register to hold shift count = cl */
172#define Control	       0x80000	/* Control register */
173#define Debug	      0x100000	/* Debug register */
174#define Test	      0x200000	/* Test register */
175#define FloatReg      0x400000	/* Float register */
176#define FloatAcc      0x800000	/* Float stack top %st(0) */
177#define SReg2	     0x1000000	/* 2 bit segment register */
178#define SReg3	     0x2000000	/* 3 bit segment register */
179#define Acc	     0x4000000	/* Accumulator %al or %ax or %eax */
180#define JumpAbsolute 0x8000000
181#define RegMMX	    0x10000000	/* MMX register */
182#define RegXMM	    0x20000000	/* XMM registers in PIII */
183#define EsSeg	    0x40000000	/* String insn operand with fixed es segment */
184
185  /* RegMem is for instructions with a modrm byte where the register
186     destination operand should be encoded in the mod and regmem fields.
187     Normally, it will be encoded in the reg field. We add a RegMem
188     flag to the destination register operand to indicate that it should
189     be encoded in the regmem field.  */
190#define RegMem	    0x80000000
191
192#define Reg	(Reg8|Reg16|Reg32|Reg64) /* gen'l register */
193#define WordReg (Reg16|Reg32|Reg64)
194#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
195#define Imm	(Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
196#define EncImm	(Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
197#define Disp	(Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
198#define AnyMem	(Disp8|Disp16|Disp32|Disp32S|BaseIndex)	/* General memory */
199  /* The following aliases are defined because the opcode table
200     carefully specifies the allowed memory types for each instruction.
201     At the moment we can only tell a memory reference size by the
202     instruction suffix, so there's not much point in defining Mem8,
203     Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
204     the suffix directly to check memory operands.  */
205#define LLongMem AnyMem		/* 64 bits (or more) */
206#define LongMem AnyMem		/* 32 bit memory ref */
207#define ShortMem AnyMem		/* 16 bit memory ref */
208#define WordMem AnyMem		/* 16, 32 or 64 bit memory ref */
209#define ByteMem AnyMem		/* 8 bit memory ref */
210}
211template;
212
213extern const template i386_optab[];
214
215/* these are for register name --> number & type hash lookup */
216typedef struct
217{
218  char *reg_name;
219  unsigned int reg_type;
220  unsigned int reg_flags;
221#define RegRex	    0x1  /* Extended register.  */
222#define RegRex64    0x2  /* Extended 8 bit register.  */
223  unsigned int reg_num;
224}
225reg_entry;
226
227/* Entries in i386_regtab.  */
228#define REGNAM_AL 1
229#define REGNAM_AX 25
230#define REGNAM_EAX 41
231
232extern const reg_entry i386_regtab[];
233extern const unsigned int i386_regtab_size;
234
235typedef struct
236{
237  char *seg_name;
238  unsigned int seg_prefix;
239}
240seg_entry;
241
242extern const seg_entry cs;
243extern const seg_entry ds;
244extern const seg_entry ss;
245extern const seg_entry es;
246extern const seg_entry fs;
247extern const seg_entry gs;
248