tc-mips.c revision 292340
1/* tc-mips.c -- assemble code for a MIPS chip. 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 3 2003, 2004, 2005, 2006 Free Software Foundation, Inc. 4 Contributed by the OSF and Ralph Campbell. 5 Written by Keith Knowles and Ralph Campbell, working independently. 6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus 7 Support. 8 9 This file is part of GAS. 10 11 GAS is free software; you can redistribute it and/or modify 12 it under the terms of the GNU General Public License as published by 13 the Free Software Foundation; either version 2, or (at your option) 14 any later version. 15 16 GAS is distributed in the hope that it will be useful, 17 but WITHOUT ANY WARRANTY; without even the implied warranty of 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 GNU General Public License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with GAS; see the file COPYING. If not, write to the Free 23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 24 02110-1301, USA. */ 25 26#include "as.h" 27#include "config.h" 28#include "subsegs.h" 29#include "safe-ctype.h" 30 31#include "opcode/mips.h" 32#include "itbl-ops.h" 33#include "dwarf2dbg.h" 34#include "dw2gencfi.h" 35 36#ifdef DEBUG 37#define DBG(x) printf x 38#else 39#define DBG(x) 40#endif 41 42#ifdef OBJ_MAYBE_ELF 43/* Clean up namespace so we can include obj-elf.h too. */ 44static int mips_output_flavor (void); 45static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } 46#undef OBJ_PROCESS_STAB 47#undef OUTPUT_FLAVOR 48#undef S_GET_ALIGN 49#undef S_GET_SIZE 50#undef S_SET_ALIGN 51#undef S_SET_SIZE 52#undef obj_frob_file 53#undef obj_frob_file_after_relocs 54#undef obj_frob_symbol 55#undef obj_pop_insert 56#undef obj_sec_sym_ok_for_reloc 57#undef OBJ_COPY_SYMBOL_ATTRIBUTES 58 59#include "obj-elf.h" 60/* Fix any of them that we actually care about. */ 61#undef OUTPUT_FLAVOR 62#define OUTPUT_FLAVOR mips_output_flavor() 63#endif 64 65#if defined (OBJ_ELF) 66#include "elf/mips.h" 67#endif 68 69#ifndef ECOFF_DEBUGGING 70#define NO_ECOFF_DEBUGGING 71#define ECOFF_DEBUGGING 0 72#endif 73 74int mips_flag_mdebug = -1; 75 76/* Control generation of .pdr sections. Off by default on IRIX: the native 77 linker doesn't know about and discards them, but relocations against them 78 remain, leading to rld crashes. */ 79#ifdef TE_IRIX 80int mips_flag_pdr = FALSE; 81#else 82int mips_flag_pdr = TRUE; 83#endif 84 85/* Control generation of error message for unsupported instructions in 86 Octeon. Octeon does not have floating point, and all the instructions 87 that use floating point registers are not allowed in Elf targets but 88 are allowed in Linux targets by default. */ 89#ifdef OCTEON_ERROR_ON_UNSUPPORTED 90static int octeon_error_on_unsupported = 1; 91#else 92static int octeon_error_on_unsupported = 0; 93#endif 94 95/* Control generation of Octeon/MIPS unaligned load/store instructions. 96 For ELF target, default to Octeon load/store instructions. 97 For Linux target, default to MIPS load/store instructions. */ 98#ifdef OCTEON_USE_UNALIGN 99static int octeon_use_unalign = 1; 100#else 101static int octeon_use_unalign = 0; 102#endif 103 104#include "ecoff.h" 105 106#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 107static char *mips_regmask_frag; 108#endif 109 110#define ZERO 0 111#define AT 1 112#define TREG 24 113#define PIC_CALL_REG 25 114#define KT0 26 115#define KT1 27 116#define GP 28 117#define SP 29 118#define FP 30 119#define RA 31 120 121#define ILLEGAL_REG (32) 122 123/* Allow override of standard little-endian ECOFF format. */ 124 125#ifndef ECOFF_LITTLE_FORMAT 126#define ECOFF_LITTLE_FORMAT "ecoff-littlemips" 127#endif 128 129extern int target_big_endian; 130 131/* The name of the readonly data section. */ 132#define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ 133 ? ".rdata" \ 134 : OUTPUT_FLAVOR == bfd_target_coff_flavour \ 135 ? ".rdata" \ 136 : OUTPUT_FLAVOR == bfd_target_elf_flavour \ 137 ? ".rodata" \ 138 : (abort (), "")) 139 140/* Information about an instruction, including its format, operands 141 and fixups. */ 142struct mips_cl_insn 143{ 144 /* The opcode's entry in mips_opcodes or mips16_opcodes. */ 145 const struct mips_opcode *insn_mo; 146 147 /* True if this is a mips16 instruction and if we want the extended 148 form of INSN_MO. */ 149 bfd_boolean use_extend; 150 151 /* The 16-bit extension instruction to use when USE_EXTEND is true. */ 152 unsigned short extend; 153 154 /* The 16-bit or 32-bit bitstring of the instruction itself. This is 155 a copy of INSN_MO->match with the operands filled in. */ 156 unsigned long insn_opcode; 157 158 /* The frag that contains the instruction. */ 159 struct frag *frag; 160 161 /* The offset into FRAG of the first instruction byte. */ 162 long where; 163 164 /* The relocs associated with the instruction, if any. */ 165 fixS *fixp[3]; 166 167 /* True if this entry cannot be moved from its current position. */ 168 unsigned int fixed_p : 1; 169 170 /* True if this instruction occurred in a .set noreorder block. */ 171 unsigned int noreorder_p : 1; 172 173 /* True for mips16 instructions that jump to an absolute address. */ 174 unsigned int mips16_absolute_jump_p : 1; 175}; 176 177/* The ABI to use. */ 178enum mips_abi_level 179{ 180 NO_ABI = 0, 181 O32_ABI, 182 O64_ABI, 183 N32_ABI, 184 N64_ABI, 185 EABI_ABI 186}; 187 188/* MIPS ABI we are using for this output file. */ 189static enum mips_abi_level mips_abi = NO_ABI; 190 191/* Whether or not we have code that can call pic code. */ 192int mips_abicalls = FALSE; 193 194/* Whether or not we have code which can be put into a shared 195 library. */ 196static bfd_boolean mips_in_shared = TRUE; 197 198/* This is the set of options which may be modified by the .set 199 pseudo-op. We use a struct so that .set push and .set pop are more 200 reliable. */ 201 202struct mips_set_options 203{ 204 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 205 if it has not been initialized. Changed by `.set mipsN', and the 206 -mipsN command line option, and the default CPU. */ 207 int isa; 208 /* Enabled Application Specific Extensions (ASEs). These are set to -1 209 if they have not been initialized. Changed by `.set <asename>', by 210 command line options, and based on the default architecture. */ 211 int ase_mips3d; 212 int ase_mdmx; 213 int ase_smartmips; 214 int ase_dsp; 215 int ase_dspr2; 216 int ase_mt; 217 /* Whether we are assembling for the mips16 processor. 0 if we are 218 not, 1 if we are, and -1 if the value has not been initialized. 219 Changed by `.set mips16' and `.set nomips16', and the -mips16 and 220 -nomips16 command line options, and the default CPU. */ 221 int mips16; 222 /* Non-zero if we should not reorder instructions. Changed by `.set 223 reorder' and `.set noreorder'. */ 224 int noreorder; 225 /* Non-zero if we should not permit the $at ($1) register to be used 226 in instructions. Changed by `.set at' and `.set noat'. */ 227 int noat; 228 /* Non-zero if we should warn when a macro instruction expands into 229 more than one machine instruction. Changed by `.set nomacro' and 230 `.set macro'. */ 231 int warn_about_macros; 232 /* Non-zero if we should not move instructions. Changed by `.set 233 move', `.set volatile', `.set nomove', and `.set novolatile'. */ 234 int nomove; 235 /* Non-zero if we should not optimize branches by moving the target 236 of the branch into the delay slot. Actually, we don't perform 237 this optimization anyhow. Changed by `.set bopt' and `.set 238 nobopt'. */ 239 int nobopt; 240 /* Non-zero if we should not autoextend mips16 instructions. 241 Changed by `.set autoextend' and `.set noautoextend'. */ 242 int noautoextend; 243 /* Restrict general purpose registers and floating point registers 244 to 32 bit. This is initially determined when -mgp32 or -mfp32 245 is passed but can changed if the assembler code uses .set mipsN. */ 246 int gp32; 247 int fp32; 248 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march 249 command line option, and the default CPU. */ 250 int arch; 251 /* True if ".set sym32" is in effect. */ 252 bfd_boolean sym32; 253}; 254 255/* True if -mgp32 was passed. */ 256static int file_mips_gp32 = -1; 257 258/* True if -mfp32 was passed. */ 259static int file_mips_fp32 = -1; 260 261/* This is the struct we use to hold the current set of options. Note 262 that we must set the isa field to ISA_UNKNOWN and the ASE fields to 263 -1 to indicate that they have not been initialized. */ 264 265static struct mips_set_options mips_opts = 266{ 267 ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE 268}; 269 270/* These variables are filled in with the masks of registers used. 271 The object format code reads them and puts them in the appropriate 272 place. */ 273unsigned long mips_gprmask; 274unsigned long mips_cprmask[4]; 275 276/* MIPS ISA we are using for this output file. */ 277static int file_mips_isa = ISA_UNKNOWN; 278 279/* True if -mips16 was passed or implied by arguments passed on the 280 command line (e.g., by -march). */ 281static int file_ase_mips16; 282 283#define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ 284 || mips_opts.isa == ISA_MIPS32R2 \ 285 || mips_opts.isa == ISA_MIPS64 \ 286 || mips_opts.isa == ISA_MIPS64R2) 287 288/* True if -mips3d was passed or implied by arguments passed on the 289 command line (e.g., by -march). */ 290static int file_ase_mips3d; 291 292/* True if -mdmx was passed or implied by arguments passed on the 293 command line (e.g., by -march). */ 294static int file_ase_mdmx; 295 296/* True if -msmartmips was passed or implied by arguments passed on the 297 command line (e.g., by -march). */ 298static int file_ase_smartmips; 299 300#define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ 301 || mips_opts.isa == ISA_MIPS32R2) 302 303/* True if -mdsp was passed or implied by arguments passed on the 304 command line (e.g., by -march). */ 305static int file_ase_dsp; 306 307#define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ 308 || mips_opts.isa == ISA_MIPS64R2) 309 310#define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) 311 312/* True if -mdspr2 was passed or implied by arguments passed on the 313 command line (e.g., by -march). */ 314static int file_ase_dspr2; 315 316#define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ 317 || mips_opts.isa == ISA_MIPS64R2) 318 319/* True if -mmt was passed or implied by arguments passed on the 320 command line (e.g., by -march). */ 321static int file_ase_mt; 322 323#define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ 324 || mips_opts.isa == ISA_MIPS64R2) 325 326/* The argument of the -march= flag. The architecture we are assembling. */ 327static int file_mips_arch = CPU_UNKNOWN; 328static const char *mips_arch_string; 329 330/* The argument of the -mtune= flag. The architecture for which we 331 are optimizing. */ 332static int mips_tune = CPU_UNKNOWN; 333static const char *mips_tune_string; 334 335/* True when generating 32-bit code for a 64-bit processor. */ 336static int mips_32bitmode = 0; 337 338/* True if the given ABI requires 32-bit registers. */ 339#define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) 340 341/* Likewise 64-bit registers. */ 342#define ABI_NEEDS_64BIT_REGS(ABI) \ 343 ((ABI) == N32_ABI \ 344 || (ABI) == N64_ABI \ 345 || (ABI) == O64_ABI) 346 347/* Return true if ISA supports 64 bit wide gp registers. */ 348#define ISA_HAS_64BIT_REGS(ISA) \ 349 ((ISA) == ISA_MIPS3 \ 350 || (ISA) == ISA_MIPS4 \ 351 || (ISA) == ISA_MIPS5 \ 352 || (ISA) == ISA_MIPS64 \ 353 || (ISA) == ISA_MIPS64R2) 354 355/* Return true if ISA supports 64 bit wide float registers. */ 356#define ISA_HAS_64BIT_FPRS(ISA) \ 357 ((ISA) == ISA_MIPS3 \ 358 || (ISA) == ISA_MIPS4 \ 359 || (ISA) == ISA_MIPS5 \ 360 || (ISA) == ISA_MIPS32R2 \ 361 || (ISA) == ISA_MIPS64 \ 362 || (ISA) == ISA_MIPS64R2) 363 364/* Return true if ISA supports 64-bit right rotate (dror et al.) 365 instructions. */ 366#define ISA_HAS_DROR(ISA) \ 367 ((ISA) == ISA_MIPS64R2) 368 369/* Return true if ISA supports 32-bit right rotate (ror et al.) 370 instructions. */ 371#define ISA_HAS_ROR(ISA) \ 372 ((ISA) == ISA_MIPS32R2 \ 373 || (ISA) == ISA_MIPS64R2 \ 374 || mips_opts.ase_smartmips) 375 376/* Return true if ISA supports ins instructions. */ 377#define ISA_HAS_INS(ISA) \ 378 ((ISA) == ISA_MIPS32R2 \ 379 || (ISA) == ISA_MIPS64R2) 380 381/* Return true if ISA supports single-precision floats in odd registers. */ 382#define ISA_HAS_ODD_SINGLE_FPR(ISA) \ 383 ((ISA) == ISA_MIPS32 \ 384 || (ISA) == ISA_MIPS32R2 \ 385 || (ISA) == ISA_MIPS64 \ 386 || (ISA) == ISA_MIPS64R2) 387 388/* Return true if ISA supports move to/from high part of a 64-bit 389 floating-point register. */ 390#define ISA_HAS_MXHC1(ISA) \ 391 ((ISA) == ISA_MIPS32R2 \ 392 || (ISA) == ISA_MIPS64R2) 393 394#define HAVE_32BIT_GPRS \ 395 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) 396 397#define HAVE_32BIT_FPRS \ 398 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) 399 400#define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) 401#define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) 402 403#define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) 404 405#define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) 406 407/* True if relocations are stored in-place. */ 408#define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) 409 410/* The ABI-derived address size. */ 411#define HAVE_64BIT_ADDRESSES \ 412 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) 413#define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) 414 415/* The size of symbolic constants (i.e., expressions of the form 416 "SYMBOL" or "SYMBOL + OFFSET"). */ 417#define HAVE_32BIT_SYMBOLS \ 418 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) 419#define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) 420 421/* Addresses are loaded in different ways, depending on the address size 422 in use. The n32 ABI Documentation also mandates the use of additions 423 with overflow checking, but existing implementations don't follow it. */ 424#define ADDRESS_ADD_INSN \ 425 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") 426 427#define ADDRESS_ADDI_INSN \ 428 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") 429 430#define ADDRESS_LOAD_INSN \ 431 (HAVE_32BIT_ADDRESSES ? "lw" : "ld") 432 433#define ADDRESS_STORE_INSN \ 434 (HAVE_32BIT_ADDRESSES ? "sw" : "sd") 435 436/* Return true if the given CPU supports the MIPS16 ASE. */ 437#define CPU_HAS_MIPS16(cpu) \ 438 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ 439 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) 440 441/* True if CPU has a dror instruction. */ 442#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) 443 444/* True if CPU has a ror instruction. */ 445#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) 446 447/* True if mflo and mfhi can be immediately followed by instructions 448 which write to the HI and LO registers. 449 450 According to MIPS specifications, MIPS ISAs I, II, and III need 451 (at least) two instructions between the reads of HI/LO and 452 instructions which write them, and later ISAs do not. Contradicting 453 the MIPS specifications, some MIPS IV processor user manuals (e.g. 454 the UM for the NEC Vr5000) document needing the instructions between 455 HI/LO reads and writes, as well. Therefore, we declare only MIPS32, 456 MIPS64 and later ISAs to have the interlocks, plus any specific 457 earlier-ISA CPUs for which CPU documentation declares that the 458 instructions are really interlocked. */ 459#define hilo_interlocks \ 460 (mips_opts.isa == ISA_MIPS32 \ 461 || mips_opts.isa == ISA_MIPS32R2 \ 462 || mips_opts.isa == ISA_MIPS64 \ 463 || mips_opts.isa == ISA_MIPS64R2 \ 464 || mips_opts.arch == CPU_R4010 \ 465 || mips_opts.arch == CPU_R10000 \ 466 || mips_opts.arch == CPU_R12000 \ 467 || mips_opts.arch == CPU_RM7000 \ 468 || mips_opts.arch == CPU_VR5500 \ 469 ) 470 471/* Whether the processor uses hardware interlocks to protect reads 472 from the GPRs after they are loaded from memory, and thus does not 473 require nops to be inserted. This applies to instructions marked 474 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA 475 level I. */ 476#define gpr_interlocks \ 477 (mips_opts.isa != ISA_MIPS1 \ 478 || mips_opts.arch == CPU_R3900) 479 480/* Whether the processor uses hardware interlocks to avoid delays 481 required by coprocessor instructions, and thus does not require 482 nops to be inserted. This applies to instructions marked 483 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays 484 between instructions marked INSN_WRITE_COND_CODE and ones marked 485 INSN_READ_COND_CODE. These nops are only required at MIPS ISA 486 levels I, II, and III. */ 487/* Itbl support may require additional care here. */ 488#define cop_interlocks \ 489 ((mips_opts.isa != ISA_MIPS1 \ 490 && mips_opts.isa != ISA_MIPS2 \ 491 && mips_opts.isa != ISA_MIPS3) \ 492 || mips_opts.arch == CPU_R4300 \ 493 ) 494 495/* Whether the processor uses hardware interlocks to protect reads 496 from coprocessor registers after they are loaded from memory, and 497 thus does not require nops to be inserted. This applies to 498 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only 499 requires at MIPS ISA level I. */ 500#define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) 501 502/* Is this a mfhi or mflo instruction? */ 503#define MF_HILO_INSN(PINFO) \ 504 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) 505 506/* MIPS PIC level. */ 507 508enum mips_pic_level mips_pic; 509 510/* 1 if we should generate 32 bit offsets from the $gp register in 511 SVR4_PIC mode. Currently has no meaning in other modes. */ 512static int mips_big_got = 0; 513 514/* 1 if trap instructions should used for overflow rather than break 515 instructions. */ 516static int mips_trap = 0; 517 518/* 1 if double width floating point constants should not be constructed 519 by assembling two single width halves into two single width floating 520 point registers which just happen to alias the double width destination 521 register. On some architectures this aliasing can be disabled by a bit 522 in the status register, and the setting of this bit cannot be determined 523 automatically at assemble time. */ 524static int mips_disable_float_construction; 525 526/* Non-zero if any .set noreorder directives were used. */ 527 528static int mips_any_noreorder; 529 530/* Non-zero if nops should be inserted when the register referenced in 531 an mfhi/mflo instruction is read in the next two instructions. */ 532static int mips_7000_hilo_fix; 533 534/* The size of objects in the small data section. */ 535static unsigned int g_switch_value = 8; 536/* Whether the -G option was used. */ 537static int g_switch_seen = 0; 538 539#define N_RMASK 0xc4 540#define N_VFP 0xd4 541 542/* If we can determine in advance that GP optimization won't be 543 possible, we can skip the relaxation stuff that tries to produce 544 GP-relative references. This makes delay slot optimization work 545 better. 546 547 This function can only provide a guess, but it seems to work for 548 gcc output. It needs to guess right for gcc, otherwise gcc 549 will put what it thinks is a GP-relative instruction in a branch 550 delay slot. 551 552 I don't know if a fix is needed for the SVR4_PIC mode. I've only 553 fixed it for the non-PIC mode. KR 95/04/07 */ 554static int nopic_need_relax (symbolS *, int); 555 556/* handle of the OPCODE hash table */ 557static struct hash_control *op_hash = NULL; 558 559/* The opcode hash table we use for the mips16. */ 560static struct hash_control *mips16_op_hash = NULL; 561 562/* This array holds the chars that always start a comment. If the 563 pre-processor is disabled, these aren't very useful */ 564const char comment_chars[] = "#"; 565 566/* This array holds the chars that only start a comment at the beginning of 567 a line. If the line seems to have the form '# 123 filename' 568 .line and .file directives will appear in the pre-processed output */ 569/* Note that input_file.c hand checks for '#' at the beginning of the 570 first line of the input file. This is because the compiler outputs 571 #NO_APP at the beginning of its output. */ 572/* Also note that C style comments are always supported. */ 573const char line_comment_chars[] = "#"; 574 575/* This array holds machine specific line separator characters. */ 576const char line_separator_chars[] = ";"; 577 578/* Chars that can be used to separate mant from exp in floating point nums */ 579const char EXP_CHARS[] = "eE"; 580 581/* Chars that mean this number is a floating point constant */ 582/* As in 0f12.456 */ 583/* or 0d1.2345e12 */ 584const char FLT_CHARS[] = "rRsSfFdDxXpP"; 585 586/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 587 changed in read.c . Ideally it shouldn't have to know about it at all, 588 but nothing is ideal around here. 589 */ 590 591static char *insn_error; 592 593static int auto_align = 1; 594 595/* When outputting SVR4 PIC code, the assembler needs to know the 596 offset in the stack frame from which to restore the $gp register. 597 This is set by the .cprestore pseudo-op, and saved in this 598 variable. */ 599static offsetT mips_cprestore_offset = -1; 600 601/* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some 602 more optimizations, it can use a register value instead of a memory-saved 603 offset and even an other register than $gp as global pointer. */ 604static offsetT mips_cpreturn_offset = -1; 605static int mips_cpreturn_register = -1; 606static int mips_gp_register = GP; 607static int mips_gprel_offset = 0; 608 609/* Whether mips_cprestore_offset has been set in the current function 610 (or whether it has already been warned about, if not). */ 611static int mips_cprestore_valid = 0; 612 613/* This is the register which holds the stack frame, as set by the 614 .frame pseudo-op. This is needed to implement .cprestore. */ 615static int mips_frame_reg = SP; 616 617/* Whether mips_frame_reg has been set in the current function 618 (or whether it has already been warned about, if not). */ 619static int mips_frame_reg_valid = 0; 620 621/* To output NOP instructions correctly, we need to keep information 622 about the previous two instructions. */ 623 624/* Whether we are optimizing. The default value of 2 means to remove 625 unneeded NOPs and swap branch instructions when possible. A value 626 of 1 means to not swap branches. A value of 0 means to always 627 insert NOPs. */ 628static int mips_optimize = 2; 629 630/* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is 631 equivalent to seeing no -g option at all. */ 632static int mips_debug = 0; 633 634/* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ 635#define MAX_VR4130_NOPS 4 636 637/* The maximum number of NOPs needed to fill delay slots. */ 638#define MAX_DELAY_NOPS 2 639 640/* The maximum number of NOPs needed for any purpose. */ 641#define MAX_NOPS 4 642 643/* A list of previous instructions, with index 0 being the most recent. 644 We need to look back MAX_NOPS instructions when filling delay slots 645 or working around processor errata. We need to look back one 646 instruction further if we're thinking about using history[0] to 647 fill a branch delay slot. */ 648static struct mips_cl_insn history[1 + MAX_NOPS]; 649 650/* Nop instructions used by emit_nop. */ 651static struct mips_cl_insn nop_insn, mips16_nop_insn; 652 653/* The appropriate nop for the current mode. */ 654#define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) 655 656/* If this is set, it points to a frag holding nop instructions which 657 were inserted before the start of a noreorder section. If those 658 nops turn out to be unnecessary, the size of the frag can be 659 decreased. */ 660static fragS *prev_nop_frag; 661 662/* The number of nop instructions we created in prev_nop_frag. */ 663static int prev_nop_frag_holds; 664 665/* The number of nop instructions that we know we need in 666 prev_nop_frag. */ 667static int prev_nop_frag_required; 668 669/* The number of instructions we've seen since prev_nop_frag. */ 670static int prev_nop_frag_since; 671 672/* For ECOFF and ELF, relocations against symbols are done in two 673 parts, with a HI relocation and a LO relocation. Each relocation 674 has only 16 bits of space to store an addend. This means that in 675 order for the linker to handle carries correctly, it must be able 676 to locate both the HI and the LO relocation. This means that the 677 relocations must appear in order in the relocation table. 678 679 In order to implement this, we keep track of each unmatched HI 680 relocation. We then sort them so that they immediately precede the 681 corresponding LO relocation. */ 682 683struct mips_hi_fixup 684{ 685 /* Next HI fixup. */ 686 struct mips_hi_fixup *next; 687 /* This fixup. */ 688 fixS *fixp; 689 /* The section this fixup is in. */ 690 segT seg; 691}; 692 693/* The list of unmatched HI relocs. */ 694 695static struct mips_hi_fixup *mips_hi_fixup_list; 696 697/* The frag containing the last explicit relocation operator. 698 Null if explicit relocations have not been used. */ 699 700static fragS *prev_reloc_op_frag; 701 702/* Map normal MIPS register numbers to mips16 register numbers. */ 703 704#define X ILLEGAL_REG 705static const int mips32_to_16_reg_map[] = 706{ 707 X, X, 2, 3, 4, 5, 6, 7, 708 X, X, X, X, X, X, X, X, 709 0, 1, X, X, X, X, X, X, 710 X, X, X, X, X, X, X, X 711}; 712#undef X 713 714/* Map mips16 register numbers to normal MIPS register numbers. */ 715 716static const unsigned int mips16_to_32_reg_map[] = 717{ 718 16, 17, 2, 3, 4, 5, 6, 7 719}; 720 721/* Classifies the kind of instructions we're interested in when 722 implementing -mfix-vr4120. */ 723enum fix_vr4120_class { 724 FIX_VR4120_MACC, 725 FIX_VR4120_DMACC, 726 FIX_VR4120_MULT, 727 FIX_VR4120_DMULT, 728 FIX_VR4120_DIV, 729 FIX_VR4120_MTHILO, 730 NUM_FIX_VR4120_CLASSES 731}; 732 733/* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if 734 there must be at least one other instruction between an instruction 735 of type X and an instruction of type Y. */ 736static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; 737 738/* True if -mfix-vr4120 is in force. */ 739static int mips_fix_vr4120; 740 741/* ...likewise -mfix-vr4130. */ 742static int mips_fix_vr4130; 743 744/* We don't relax branches by default, since this causes us to expand 745 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we 746 fail to compute the offset before expanding the macro to the most 747 efficient expansion. */ 748 749static int mips_relax_branch; 750 751/* The expansion of many macros depends on the type of symbol that 752 they refer to. For example, when generating position-dependent code, 753 a macro that refers to a symbol may have two different expansions, 754 one which uses GP-relative addresses and one which uses absolute 755 addresses. When generating SVR4-style PIC, a macro may have 756 different expansions for local and global symbols. 757 758 We handle these situations by generating both sequences and putting 759 them in variant frags. In position-dependent code, the first sequence 760 will be the GP-relative one and the second sequence will be the 761 absolute one. In SVR4 PIC, the first sequence will be for global 762 symbols and the second will be for local symbols. 763 764 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and 765 SECOND are the lengths of the two sequences in bytes. These fields 766 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, 767 the subtype has the following flags: 768 769 RELAX_USE_SECOND 770 Set if it has been decided that we should use the second 771 sequence instead of the first. 772 773 RELAX_SECOND_LONGER 774 Set in the first variant frag if the macro's second implementation 775 is longer than its first. This refers to the macro as a whole, 776 not an individual relaxation. 777 778 RELAX_NOMACRO 779 Set in the first variant frag if the macro appeared in a .set nomacro 780 block and if one alternative requires a warning but the other does not. 781 782 RELAX_DELAY_SLOT 783 Like RELAX_NOMACRO, but indicates that the macro appears in a branch 784 delay slot. 785 786 The frag's "opcode" points to the first fixup for relaxable code. 787 788 Relaxable macros are generated using a sequence such as: 789 790 relax_start (SYMBOL); 791 ... generate first expansion ... 792 relax_switch (); 793 ... generate second expansion ... 794 relax_end (); 795 796 The code and fixups for the unwanted alternative are discarded 797 by md_convert_frag. */ 798#define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) 799 800#define RELAX_FIRST(X) (((X) >> 8) & 0xff) 801#define RELAX_SECOND(X) ((X) & 0xff) 802#define RELAX_USE_SECOND 0x10000 803#define RELAX_SECOND_LONGER 0x20000 804#define RELAX_NOMACRO 0x40000 805#define RELAX_DELAY_SLOT 0x80000 806 807/* Branch without likely bit. If label is out of range, we turn: 808 809 beq reg1, reg2, label 810 delay slot 811 812 into 813 814 bne reg1, reg2, 0f 815 nop 816 j label 817 0: delay slot 818 819 with the following opcode replacements: 820 821 beq <-> bne 822 blez <-> bgtz 823 bltz <-> bgez 824 bc1f <-> bc1t 825 826 bltzal <-> bgezal (with jal label instead of j label) 827 828 Even though keeping the delay slot instruction in the delay slot of 829 the branch would be more efficient, it would be very tricky to do 830 correctly, because we'd have to introduce a variable frag *after* 831 the delay slot instruction, and expand that instead. Let's do it 832 the easy way for now, even if the branch-not-taken case now costs 833 one additional instruction. Out-of-range branches are not supposed 834 to be common, anyway. 835 836 Branch likely. If label is out of range, we turn: 837 838 beql reg1, reg2, label 839 delay slot (annulled if branch not taken) 840 841 into 842 843 beql reg1, reg2, 1f 844 nop 845 beql $0, $0, 2f 846 nop 847 1: j[al] label 848 delay slot (executed only if branch taken) 849 2: 850 851 It would be possible to generate a shorter sequence by losing the 852 likely bit, generating something like: 853 854 bne reg1, reg2, 0f 855 nop 856 j[al] label 857 delay slot (executed only if branch taken) 858 0: 859 860 beql -> bne 861 bnel -> beq 862 blezl -> bgtz 863 bgtzl -> blez 864 bltzl -> bgez 865 bgezl -> bltz 866 bc1fl -> bc1t 867 bc1tl -> bc1f 868 869 bltzall -> bgezal (with jal label instead of j label) 870 bgezall -> bltzal (ditto) 871 872 873 but it's not clear that it would actually improve performance. */ 874#define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ 875 ((relax_substateT) \ 876 (0xc0000000 \ 877 | ((toofar) ? 1 : 0) \ 878 | ((link) ? 2 : 0) \ 879 | ((likely) ? 4 : 0) \ 880 | ((uncond) ? 8 : 0))) 881#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) 882#define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) 883#define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) 884#define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) 885#define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) 886 887/* For mips16 code, we use an entirely different form of relaxation. 888 mips16 supports two versions of most instructions which take 889 immediate values: a small one which takes some small value, and a 890 larger one which takes a 16 bit value. Since branches also follow 891 this pattern, relaxing these values is required. 892 893 We can assemble both mips16 and normal MIPS code in a single 894 object. Therefore, we need to support this type of relaxation at 895 the same time that we support the relaxation described above. We 896 use the high bit of the subtype field to distinguish these cases. 897 898 The information we store for this type of relaxation is the 899 argument code found in the opcode file for this relocation, whether 900 the user explicitly requested a small or extended form, and whether 901 the relocation is in a jump or jal delay slot. That tells us the 902 size of the value, and how it should be stored. We also store 903 whether the fragment is considered to be extended or not. We also 904 store whether this is known to be a branch to a different section, 905 whether we have tried to relax this frag yet, and whether we have 906 ever extended a PC relative fragment because of a shift count. */ 907#define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ 908 (0x80000000 \ 909 | ((type) & 0xff) \ 910 | ((small) ? 0x100 : 0) \ 911 | ((ext) ? 0x200 : 0) \ 912 | ((dslot) ? 0x400 : 0) \ 913 | ((jal_dslot) ? 0x800 : 0)) 914#define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) 915#define RELAX_MIPS16_TYPE(i) ((i) & 0xff) 916#define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) 917#define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) 918#define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) 919#define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) 920#define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) 921#define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) 922#define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) 923#define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) 924#define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) 925#define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) 926 927/* Is the given value a sign-extended 32-bit value? */ 928#define IS_SEXT_32BIT_NUM(x) \ 929 (((x) &~ (offsetT) 0x7fffffff) == 0 \ 930 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) 931 932/* Is the given value a sign-extended 16-bit value? */ 933#define IS_SEXT_16BIT_NUM(x) \ 934 (((x) &~ (offsetT) 0x7fff) == 0 \ 935 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) 936 937/* Is the given value a zero-extended 32-bit value? Or a negated one? */ 938#define IS_ZEXT_32BIT_NUM(x) \ 939 (((x) &~ (offsetT) 0xffffffff) == 0 \ 940 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) 941 942/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in 943 VALUE << SHIFT. VALUE is evaluated exactly once. */ 944#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ 945 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ 946 | (((VALUE) & (MASK)) << (SHIFT))) 947 948/* Extract bits MASK << SHIFT from STRUCT and shift them right 949 SHIFT places. */ 950#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ 951 (((STRUCT) >> (SHIFT)) & (MASK)) 952 953/* Change INSN's opcode so that the operand given by FIELD has value VALUE. 954 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. 955 956 include/opcode/mips.h specifies operand fields using the macros 957 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start 958 with "MIPS16OP" instead of "OP". */ 959#define INSERT_OPERAND(FIELD, INSN, VALUE) \ 960 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) 961#define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ 962 INSERT_BITS ((INSN).insn_opcode, VALUE, \ 963 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) 964 965/* Extract the operand given by FIELD from mips_cl_insn INSN. */ 966#define EXTRACT_OPERAND(FIELD, INSN) \ 967 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) 968#define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ 969 EXTRACT_BITS ((INSN).insn_opcode, \ 970 MIPS16OP_MASK_##FIELD, \ 971 MIPS16OP_SH_##FIELD) 972 973/* Global variables used when generating relaxable macros. See the 974 comment above RELAX_ENCODE for more details about how relaxation 975 is used. */ 976static struct { 977 /* 0 if we're not emitting a relaxable macro. 978 1 if we're emitting the first of the two relaxation alternatives. 979 2 if we're emitting the second alternative. */ 980 int sequence; 981 982 /* The first relaxable fixup in the current frag. (In other words, 983 the first fixup that refers to relaxable code.) */ 984 fixS *first_fixup; 985 986 /* sizes[0] says how many bytes of the first alternative are stored in 987 the current frag. Likewise sizes[1] for the second alternative. */ 988 unsigned int sizes[2]; 989 990 /* The symbol on which the choice of sequence depends. */ 991 symbolS *symbol; 992} mips_relax; 993 994/* Global variables used to decide whether a macro needs a warning. */ 995static struct { 996 /* True if the macro is in a branch delay slot. */ 997 bfd_boolean delay_slot_p; 998 999 /* For relaxable macros, sizes[0] is the length of the first alternative 1000 in bytes and sizes[1] is the length of the second alternative. 1001 For non-relaxable macros, both elements give the length of the 1002 macro in bytes. */ 1003 unsigned int sizes[2]; 1004 1005 /* The first variant frag for this macro. */ 1006 fragS *first_frag; 1007} mips_macro_warning; 1008 1009/* Prototypes for static functions. */ 1010 1011#define internalError() \ 1012 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) 1013 1014enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; 1015 1016static void append_insn 1017 (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); 1018static void mips_no_prev_insn (void); 1019static void mips16_macro_build 1020 (expressionS *, const char *, const char *, va_list); 1021static void load_register (int, expressionS *, int); 1022static void macro_start (void); 1023static void macro_end (void); 1024static void macro (struct mips_cl_insn * ip); 1025static void mips16_macro (struct mips_cl_insn * ip); 1026#ifdef LOSING_COMPILER 1027static void macro2 (struct mips_cl_insn * ip); 1028#endif 1029static void mips_ip (char *str, struct mips_cl_insn * ip); 1030static void mips16_ip (char *str, struct mips_cl_insn * ip); 1031static void mips16_immed 1032 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, 1033 unsigned long *, bfd_boolean *, unsigned short *); 1034static size_t my_getSmallExpression 1035 (expressionS *, bfd_reloc_code_real_type *, char *); 1036static void my_getExpression (expressionS *, char *); 1037static void s_align (int); 1038static void s_change_sec (int); 1039static void s_change_section (int); 1040static void s_cons (int); 1041static void s_float_cons (int); 1042static void s_mips_globl (int); 1043static void s_option (int); 1044static void s_mipsset (int); 1045static void s_abicalls (int); 1046static void s_cpload (int); 1047static void s_cpsetup (int); 1048static void s_cplocal (int); 1049static void s_cprestore (int); 1050static void s_cpreturn (int); 1051static void s_dtprelword (int); 1052static void s_dtpreldword (int); 1053static void s_gpvalue (int); 1054static void s_gpword (int); 1055static void s_gpdword (int); 1056static void s_cpadd (int); 1057static void s_insn (int); 1058static void md_obj_begin (void); 1059static void md_obj_end (void); 1060static void s_mips_ent (int); 1061static void s_mips_end (int); 1062static void s_mips_frame (int); 1063static void s_mips_mask (int reg_type); 1064static void s_mips_stab (int); 1065static void s_mips_weakext (int); 1066static void s_mips_file (int); 1067static void s_mips_loc (int); 1068static bfd_boolean pic_need_relax (symbolS *, asection *); 1069static int relaxed_branch_length (fragS *, asection *, int); 1070static int validate_mips_insn (const struct mips_opcode *); 1071 1072/* Table and functions used to map between CPU/ISA names, and 1073 ISA levels, and CPU numbers. */ 1074 1075struct mips_cpu_info 1076{ 1077 const char *name; /* CPU or ISA name. */ 1078 int flags; /* ASEs available, or ISA flag. */ 1079 int isa; /* ISA level. */ 1080 int cpu; /* CPU number (default CPU if ISA). */ 1081}; 1082 1083#define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ 1084#define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ 1085#define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ 1086#define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ 1087#define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ 1088#define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ 1089#define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ 1090 1091static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); 1092static const struct mips_cpu_info *mips_cpu_info_from_isa (int); 1093static const struct mips_cpu_info *mips_cpu_info_from_arch (int); 1094 1095/* Pseudo-op table. 1096 1097 The following pseudo-ops from the Kane and Heinrich MIPS book 1098 should be defined here, but are currently unsupported: .alias, 1099 .galive, .gjaldef, .gjrlive, .livereg, .noalias. 1100 1101 The following pseudo-ops from the Kane and Heinrich MIPS book are 1102 specific to the type of debugging information being generated, and 1103 should be defined by the object format: .aent, .begin, .bend, 1104 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, 1105 .vreg. 1106 1107 The following pseudo-ops from the Kane and Heinrich MIPS book are 1108 not MIPS CPU specific, but are also not specific to the object file 1109 format. This file is probably the best place to define them, but 1110 they are not currently supported: .asm0, .endr, .lab, .struct. */ 1111 1112static const pseudo_typeS mips_pseudo_table[] = 1113{ 1114 /* MIPS specific pseudo-ops. */ 1115 {"option", s_option, 0}, 1116 {"set", s_mipsset, 0}, 1117 {"rdata", s_change_sec, 'r'}, 1118 {"sdata", s_change_sec, 's'}, 1119 {"livereg", s_ignore, 0}, 1120 {"abicalls", s_abicalls, 0}, 1121 {"cpload", s_cpload, 0}, 1122 {"cpsetup", s_cpsetup, 0}, 1123 {"cplocal", s_cplocal, 0}, 1124 {"cprestore", s_cprestore, 0}, 1125 {"cpreturn", s_cpreturn, 0}, 1126 {"dtprelword", s_dtprelword, 0}, 1127 {"dtpreldword", s_dtpreldword, 0}, 1128 {"gpvalue", s_gpvalue, 0}, 1129 {"gpword", s_gpword, 0}, 1130 {"gpdword", s_gpdword, 0}, 1131 {"cpadd", s_cpadd, 0}, 1132 {"insn", s_insn, 0}, 1133 1134 /* Relatively generic pseudo-ops that happen to be used on MIPS 1135 chips. */ 1136 {"asciiz", stringer, 1}, 1137 {"bss", s_change_sec, 'b'}, 1138 {"err", s_err, 0}, 1139 {"half", s_cons, 1}, 1140 {"dword", s_cons, 3}, 1141 {"weakext", s_mips_weakext, 0}, 1142 {"origin", s_org, 0}, 1143 {"repeat", s_rept, 0}, 1144 1145 /* These pseudo-ops are defined in read.c, but must be overridden 1146 here for one reason or another. */ 1147 {"align", s_align, 0}, 1148 {"byte", s_cons, 0}, 1149 {"data", s_change_sec, 'd'}, 1150 {"double", s_float_cons, 'd'}, 1151 {"float", s_float_cons, 'f'}, 1152 {"globl", s_mips_globl, 0}, 1153 {"global", s_mips_globl, 0}, 1154 {"hword", s_cons, 1}, 1155 {"int", s_cons, 2}, 1156 {"long", s_cons, 2}, 1157 {"octa", s_cons, 4}, 1158 {"quad", s_cons, 3}, 1159 {"section", s_change_section, 0}, 1160 {"short", s_cons, 1}, 1161 {"single", s_float_cons, 'f'}, 1162 {"stabn", s_mips_stab, 'n'}, 1163 {"text", s_change_sec, 't'}, 1164 {"word", s_cons, 2}, 1165 1166 { "extern", ecoff_directive_extern, 0}, 1167 1168 { NULL, NULL, 0 }, 1169}; 1170 1171static const pseudo_typeS mips_nonecoff_pseudo_table[] = 1172{ 1173 /* These pseudo-ops should be defined by the object file format. 1174 However, a.out doesn't support them, so we have versions here. */ 1175 {"aent", s_mips_ent, 1}, 1176 {"bgnb", s_ignore, 0}, 1177 {"end", s_mips_end, 0}, 1178 {"endb", s_ignore, 0}, 1179 {"ent", s_mips_ent, 0}, 1180 {"file", s_mips_file, 0}, 1181 {"fmask", s_mips_mask, 'F'}, 1182 {"frame", s_mips_frame, 0}, 1183 {"loc", s_mips_loc, 0}, 1184 {"mask", s_mips_mask, 'R'}, 1185 {"verstamp", s_ignore, 0}, 1186 { NULL, NULL, 0 }, 1187}; 1188 1189extern void pop_insert (const pseudo_typeS *); 1190 1191void 1192mips_pop_insert (void) 1193{ 1194 pop_insert (mips_pseudo_table); 1195 if (! ECOFF_DEBUGGING) 1196 pop_insert (mips_nonecoff_pseudo_table); 1197} 1198 1199/* Symbols labelling the current insn. */ 1200 1201struct insn_label_list 1202{ 1203 struct insn_label_list *next; 1204 symbolS *label; 1205}; 1206 1207static struct insn_label_list *free_insn_labels; 1208#define label_list tc_segment_info_data 1209 1210static void mips_clear_insn_labels (void); 1211 1212static inline void 1213mips_clear_insn_labels (void) 1214{ 1215 register struct insn_label_list **pl; 1216 segment_info_type *si; 1217 1218 if (now_seg) 1219 { 1220 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) 1221 ; 1222 1223 si = seg_info (now_seg); 1224 *pl = si->label_list; 1225 si->label_list = NULL; 1226 } 1227} 1228 1229 1230static char *expr_end; 1231 1232/* Expressions which appear in instructions. These are set by 1233 mips_ip. */ 1234 1235static expressionS imm_expr; 1236static expressionS imm2_expr; 1237static expressionS offset_expr; 1238 1239/* Relocs associated with imm_expr and offset_expr. */ 1240 1241static bfd_reloc_code_real_type imm_reloc[3] 1242 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 1243static bfd_reloc_code_real_type offset_reloc[3] 1244 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 1245 1246/* These are set by mips16_ip if an explicit extension is used. */ 1247 1248static bfd_boolean mips16_small, mips16_ext; 1249 1250#ifdef OBJ_ELF 1251/* The pdr segment for per procedure frame/regmask info. Not used for 1252 ECOFF debugging. */ 1253 1254static segT pdr_seg; 1255#endif 1256 1257/* The default target format to use. */ 1258 1259const char * 1260mips_target_format (void) 1261{ 1262 switch (OUTPUT_FLAVOR) 1263 { 1264 case bfd_target_ecoff_flavour: 1265 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; 1266 case bfd_target_coff_flavour: 1267 return "pe-mips"; 1268 case bfd_target_elf_flavour: 1269#ifdef TE_VXWORKS 1270 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) 1271 return (target_big_endian 1272 ? "elf32-bigmips-vxworks" 1273 : "elf32-littlemips-vxworks"); 1274#endif 1275#ifdef TE_TMIPS 1276 /* This is traditional mips. */ 1277 return (target_big_endian 1278 ? (HAVE_64BIT_OBJECTS 1279 ? "elf64-tradbigmips" 1280 : (HAVE_NEWABI 1281 ? "elf32-ntradbigmips" : "elf32-tradbigmips")) 1282 : (HAVE_64BIT_OBJECTS 1283 ? "elf64-tradlittlemips" 1284 : (HAVE_NEWABI 1285 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); 1286#else 1287 return (target_big_endian 1288 ? (HAVE_64BIT_OBJECTS 1289 ? "elf64-bigmips" 1290 : (HAVE_NEWABI 1291 ? "elf32-nbigmips" : "elf32-bigmips")) 1292 : (HAVE_64BIT_OBJECTS 1293 ? "elf64-littlemips" 1294 : (HAVE_NEWABI 1295 ? "elf32-nlittlemips" : "elf32-littlemips"))); 1296#endif 1297 default: 1298 abort (); 1299 return NULL; 1300 } 1301} 1302 1303/* Return the length of instruction INSN. */ 1304 1305static inline unsigned int 1306insn_length (const struct mips_cl_insn *insn) 1307{ 1308 if (!mips_opts.mips16) 1309 return 4; 1310 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; 1311} 1312 1313/* Initialise INSN from opcode entry MO. Leave its position unspecified. */ 1314 1315static void 1316create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) 1317{ 1318 size_t i; 1319 1320 insn->insn_mo = mo; 1321 insn->use_extend = FALSE; 1322 insn->extend = 0; 1323 insn->insn_opcode = mo->match; 1324 insn->frag = NULL; 1325 insn->where = 0; 1326 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) 1327 insn->fixp[i] = NULL; 1328 insn->fixed_p = (mips_opts.noreorder > 0); 1329 insn->noreorder_p = (mips_opts.noreorder > 0); 1330 insn->mips16_absolute_jump_p = 0; 1331} 1332 1333/* Install INSN at the location specified by its "frag" and "where" fields. */ 1334 1335static void 1336install_insn (const struct mips_cl_insn *insn) 1337{ 1338 char *f = insn->frag->fr_literal + insn->where; 1339 if (!mips_opts.mips16) 1340 md_number_to_chars (f, insn->insn_opcode, 4); 1341 else if (insn->mips16_absolute_jump_p) 1342 { 1343 md_number_to_chars (f, insn->insn_opcode >> 16, 2); 1344 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); 1345 } 1346 else 1347 { 1348 if (insn->use_extend) 1349 { 1350 md_number_to_chars (f, 0xf000 | insn->extend, 2); 1351 f += 2; 1352 } 1353 md_number_to_chars (f, insn->insn_opcode, 2); 1354 } 1355} 1356 1357/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly 1358 and install the opcode in the new location. */ 1359 1360static void 1361move_insn (struct mips_cl_insn *insn, fragS *frag, long where) 1362{ 1363 size_t i; 1364 1365 insn->frag = frag; 1366 insn->where = where; 1367 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) 1368 if (insn->fixp[i] != NULL) 1369 { 1370 insn->fixp[i]->fx_frag = frag; 1371 insn->fixp[i]->fx_where = where; 1372 } 1373 install_insn (insn); 1374} 1375 1376/* Add INSN to the end of the output. */ 1377 1378static void 1379add_fixed_insn (struct mips_cl_insn *insn) 1380{ 1381 char *f = frag_more (insn_length (insn)); 1382 move_insn (insn, frag_now, f - frag_now->fr_literal); 1383} 1384 1385/* Start a variant frag and move INSN to the start of the variant part, 1386 marking it as fixed. The other arguments are as for frag_var. */ 1387 1388static void 1389add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, 1390 relax_substateT subtype, symbolS *symbol, offsetT offset) 1391{ 1392 frag_grow (max_chars); 1393 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); 1394 insn->fixed_p = 1; 1395 frag_var (rs_machine_dependent, max_chars, var, 1396 subtype, symbol, offset, NULL); 1397} 1398 1399/* Insert N copies of INSN into the history buffer, starting at 1400 position FIRST. Neither FIRST nor N need to be clipped. */ 1401 1402static void 1403insert_into_history (unsigned int first, unsigned int n, 1404 const struct mips_cl_insn *insn) 1405{ 1406 if (mips_relax.sequence != 2) 1407 { 1408 unsigned int i; 1409 1410 for (i = ARRAY_SIZE (history); i-- > first;) 1411 if (i >= first + n) 1412 history[i] = history[i - n]; 1413 else 1414 history[i] = *insn; 1415 } 1416} 1417 1418/* Emit a nop instruction, recording it in the history buffer. */ 1419 1420static void 1421emit_nop (void) 1422{ 1423 add_fixed_insn (NOP_INSN); 1424 insert_into_history (0, 1, NOP_INSN); 1425} 1426 1427/* Initialize vr4120_conflicts. There is a bit of duplication here: 1428 the idea is to make it obvious at a glance that each errata is 1429 included. */ 1430 1431static void 1432init_vr4120_conflicts (void) 1433{ 1434#define CONFLICT(FIRST, SECOND) \ 1435 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND 1436 1437 /* Errata 21 - [D]DIV[U] after [D]MACC */ 1438 CONFLICT (MACC, DIV); 1439 CONFLICT (DMACC, DIV); 1440 1441 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ 1442 CONFLICT (DMULT, DMULT); 1443 CONFLICT (DMULT, DMACC); 1444 CONFLICT (DMACC, DMULT); 1445 CONFLICT (DMACC, DMACC); 1446 1447 /* Errata 24 - MT{LO,HI} after [D]MACC */ 1448 CONFLICT (MACC, MTHILO); 1449 CONFLICT (DMACC, MTHILO); 1450 1451 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU 1452 instruction is executed immediately after a MACC or DMACC 1453 instruction, the result of [either instruction] is incorrect." */ 1454 CONFLICT (MACC, MULT); 1455 CONFLICT (MACC, DMULT); 1456 CONFLICT (DMACC, MULT); 1457 CONFLICT (DMACC, DMULT); 1458 1459 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is 1460 executed immediately after a DMULT, DMULTU, DIV, DIVU, 1461 DDIV or DDIVU instruction, the result of the MACC or 1462 DMACC instruction is incorrect.". */ 1463 CONFLICT (DMULT, MACC); 1464 CONFLICT (DMULT, DMACC); 1465 CONFLICT (DIV, MACC); 1466 CONFLICT (DIV, DMACC); 1467 1468#undef CONFLICT 1469} 1470 1471struct regname { 1472 const char *name; 1473 unsigned int num; 1474}; 1475 1476#define RTYPE_MASK 0x1ff00 1477#define RTYPE_NUM 0x00100 1478#define RTYPE_FPU 0x00200 1479#define RTYPE_FCC 0x00400 1480#define RTYPE_VEC 0x00800 1481#define RTYPE_GP 0x01000 1482#define RTYPE_CP0 0x02000 1483#define RTYPE_PC 0x04000 1484#define RTYPE_ACC 0x08000 1485#define RTYPE_CCC 0x10000 1486#define RNUM_MASK 0x000ff 1487#define RWARN 0x80000 1488 1489#define GENERIC_REGISTER_NUMBERS \ 1490 {"$0", RTYPE_NUM | 0}, \ 1491 {"$1", RTYPE_NUM | 1}, \ 1492 {"$2", RTYPE_NUM | 2}, \ 1493 {"$3", RTYPE_NUM | 3}, \ 1494 {"$4", RTYPE_NUM | 4}, \ 1495 {"$5", RTYPE_NUM | 5}, \ 1496 {"$6", RTYPE_NUM | 6}, \ 1497 {"$7", RTYPE_NUM | 7}, \ 1498 {"$8", RTYPE_NUM | 8}, \ 1499 {"$9", RTYPE_NUM | 9}, \ 1500 {"$10", RTYPE_NUM | 10}, \ 1501 {"$11", RTYPE_NUM | 11}, \ 1502 {"$12", RTYPE_NUM | 12}, \ 1503 {"$13", RTYPE_NUM | 13}, \ 1504 {"$14", RTYPE_NUM | 14}, \ 1505 {"$15", RTYPE_NUM | 15}, \ 1506 {"$16", RTYPE_NUM | 16}, \ 1507 {"$17", RTYPE_NUM | 17}, \ 1508 {"$18", RTYPE_NUM | 18}, \ 1509 {"$19", RTYPE_NUM | 19}, \ 1510 {"$20", RTYPE_NUM | 20}, \ 1511 {"$21", RTYPE_NUM | 21}, \ 1512 {"$22", RTYPE_NUM | 22}, \ 1513 {"$23", RTYPE_NUM | 23}, \ 1514 {"$24", RTYPE_NUM | 24}, \ 1515 {"$25", RTYPE_NUM | 25}, \ 1516 {"$26", RTYPE_NUM | 26}, \ 1517 {"$27", RTYPE_NUM | 27}, \ 1518 {"$28", RTYPE_NUM | 28}, \ 1519 {"$29", RTYPE_NUM | 29}, \ 1520 {"$30", RTYPE_NUM | 30}, \ 1521 {"$31", RTYPE_NUM | 31} 1522 1523#define FPU_REGISTER_NAMES \ 1524 {"$f0", RTYPE_FPU | 0}, \ 1525 {"$f1", RTYPE_FPU | 1}, \ 1526 {"$f2", RTYPE_FPU | 2}, \ 1527 {"$f3", RTYPE_FPU | 3}, \ 1528 {"$f4", RTYPE_FPU | 4}, \ 1529 {"$f5", RTYPE_FPU | 5}, \ 1530 {"$f6", RTYPE_FPU | 6}, \ 1531 {"$f7", RTYPE_FPU | 7}, \ 1532 {"$f8", RTYPE_FPU | 8}, \ 1533 {"$f9", RTYPE_FPU | 9}, \ 1534 {"$f10", RTYPE_FPU | 10}, \ 1535 {"$f11", RTYPE_FPU | 11}, \ 1536 {"$f12", RTYPE_FPU | 12}, \ 1537 {"$f13", RTYPE_FPU | 13}, \ 1538 {"$f14", RTYPE_FPU | 14}, \ 1539 {"$f15", RTYPE_FPU | 15}, \ 1540 {"$f16", RTYPE_FPU | 16}, \ 1541 {"$f17", RTYPE_FPU | 17}, \ 1542 {"$f18", RTYPE_FPU | 18}, \ 1543 {"$f19", RTYPE_FPU | 19}, \ 1544 {"$f20", RTYPE_FPU | 20}, \ 1545 {"$f21", RTYPE_FPU | 21}, \ 1546 {"$f22", RTYPE_FPU | 22}, \ 1547 {"$f23", RTYPE_FPU | 23}, \ 1548 {"$f24", RTYPE_FPU | 24}, \ 1549 {"$f25", RTYPE_FPU | 25}, \ 1550 {"$f26", RTYPE_FPU | 26}, \ 1551 {"$f27", RTYPE_FPU | 27}, \ 1552 {"$f28", RTYPE_FPU | 28}, \ 1553 {"$f29", RTYPE_FPU | 29}, \ 1554 {"$f30", RTYPE_FPU | 30}, \ 1555 {"$f31", RTYPE_FPU | 31} 1556 1557#define FPU_CONDITION_CODE_NAMES \ 1558 {"$fcc0", RTYPE_FCC | 0}, \ 1559 {"$fcc1", RTYPE_FCC | 1}, \ 1560 {"$fcc2", RTYPE_FCC | 2}, \ 1561 {"$fcc3", RTYPE_FCC | 3}, \ 1562 {"$fcc4", RTYPE_FCC | 4}, \ 1563 {"$fcc5", RTYPE_FCC | 5}, \ 1564 {"$fcc6", RTYPE_FCC | 6}, \ 1565 {"$fcc7", RTYPE_FCC | 7} 1566 1567#define COPROC_CONDITION_CODE_NAMES \ 1568 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ 1569 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ 1570 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ 1571 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ 1572 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ 1573 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ 1574 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ 1575 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} 1576 1577#define N32N64_SYMBOLIC_REGISTER_NAMES \ 1578 {"$a4", RTYPE_GP | 8}, \ 1579 {"$a5", RTYPE_GP | 9}, \ 1580 {"$a6", RTYPE_GP | 10}, \ 1581 {"$a7", RTYPE_GP | 11}, \ 1582 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ 1583 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ 1584 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ 1585 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ 1586 {"$t0", RTYPE_GP | 12}, \ 1587 {"$t1", RTYPE_GP | 13}, \ 1588 {"$t2", RTYPE_GP | 14}, \ 1589 {"$t3", RTYPE_GP | 15} 1590 1591#define O32_SYMBOLIC_REGISTER_NAMES \ 1592 {"$t0", RTYPE_GP | 8}, \ 1593 {"$t1", RTYPE_GP | 9}, \ 1594 {"$t2", RTYPE_GP | 10}, \ 1595 {"$t3", RTYPE_GP | 11}, \ 1596 {"$t4", RTYPE_GP | 12}, \ 1597 {"$t5", RTYPE_GP | 13}, \ 1598 {"$t6", RTYPE_GP | 14}, \ 1599 {"$t7", RTYPE_GP | 15}, \ 1600 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ 1601 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ 1602 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ 1603 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ 1604 1605/* Remaining symbolic register names */ 1606#define SYMBOLIC_REGISTER_NAMES \ 1607 {"$zero", RTYPE_GP | 0}, \ 1608 {"$at", RTYPE_GP | 1}, \ 1609 {"$AT", RTYPE_GP | 1}, \ 1610 {"$v0", RTYPE_GP | 2}, \ 1611 {"$v1", RTYPE_GP | 3}, \ 1612 {"$a0", RTYPE_GP | 4}, \ 1613 {"$a1", RTYPE_GP | 5}, \ 1614 {"$a2", RTYPE_GP | 6}, \ 1615 {"$a3", RTYPE_GP | 7}, \ 1616 {"$s0", RTYPE_GP | 16}, \ 1617 {"$s1", RTYPE_GP | 17}, \ 1618 {"$s2", RTYPE_GP | 18}, \ 1619 {"$s3", RTYPE_GP | 19}, \ 1620 {"$s4", RTYPE_GP | 20}, \ 1621 {"$s5", RTYPE_GP | 21}, \ 1622 {"$s6", RTYPE_GP | 22}, \ 1623 {"$s7", RTYPE_GP | 23}, \ 1624 {"$t8", RTYPE_GP | 24}, \ 1625 {"$t9", RTYPE_GP | 25}, \ 1626 {"$k0", RTYPE_GP | 26}, \ 1627 {"$kt0", RTYPE_GP | 26}, \ 1628 {"$k1", RTYPE_GP | 27}, \ 1629 {"$kt1", RTYPE_GP | 27}, \ 1630 {"$gp", RTYPE_GP | 28}, \ 1631 {"$sp", RTYPE_GP | 29}, \ 1632 {"$s8", RTYPE_GP | 30}, \ 1633 {"$fp", RTYPE_GP | 30}, \ 1634 {"$ra", RTYPE_GP | 31} 1635 1636#define MIPS16_SPECIAL_REGISTER_NAMES \ 1637 {"$pc", RTYPE_PC | 0} 1638 1639#define MDMX_VECTOR_REGISTER_NAMES \ 1640 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ 1641 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ 1642 {"$v2", RTYPE_VEC | 2}, \ 1643 {"$v3", RTYPE_VEC | 3}, \ 1644 {"$v4", RTYPE_VEC | 4}, \ 1645 {"$v5", RTYPE_VEC | 5}, \ 1646 {"$v6", RTYPE_VEC | 6}, \ 1647 {"$v7", RTYPE_VEC | 7}, \ 1648 {"$v8", RTYPE_VEC | 8}, \ 1649 {"$v9", RTYPE_VEC | 9}, \ 1650 {"$v10", RTYPE_VEC | 10}, \ 1651 {"$v11", RTYPE_VEC | 11}, \ 1652 {"$v12", RTYPE_VEC | 12}, \ 1653 {"$v13", RTYPE_VEC | 13}, \ 1654 {"$v14", RTYPE_VEC | 14}, \ 1655 {"$v15", RTYPE_VEC | 15}, \ 1656 {"$v16", RTYPE_VEC | 16}, \ 1657 {"$v17", RTYPE_VEC | 17}, \ 1658 {"$v18", RTYPE_VEC | 18}, \ 1659 {"$v19", RTYPE_VEC | 19}, \ 1660 {"$v20", RTYPE_VEC | 20}, \ 1661 {"$v21", RTYPE_VEC | 21}, \ 1662 {"$v22", RTYPE_VEC | 22}, \ 1663 {"$v23", RTYPE_VEC | 23}, \ 1664 {"$v24", RTYPE_VEC | 24}, \ 1665 {"$v25", RTYPE_VEC | 25}, \ 1666 {"$v26", RTYPE_VEC | 26}, \ 1667 {"$v27", RTYPE_VEC | 27}, \ 1668 {"$v28", RTYPE_VEC | 28}, \ 1669 {"$v29", RTYPE_VEC | 29}, \ 1670 {"$v30", RTYPE_VEC | 30}, \ 1671 {"$v31", RTYPE_VEC | 31} 1672 1673#define MIPS_DSP_ACCUMULATOR_NAMES \ 1674 {"$ac0", RTYPE_ACC | 0}, \ 1675 {"$ac1", RTYPE_ACC | 1}, \ 1676 {"$ac2", RTYPE_ACC | 2}, \ 1677 {"$ac3", RTYPE_ACC | 3} 1678 1679static const struct regname reg_names[] = { 1680 GENERIC_REGISTER_NUMBERS, 1681 FPU_REGISTER_NAMES, 1682 FPU_CONDITION_CODE_NAMES, 1683 COPROC_CONDITION_CODE_NAMES, 1684 1685 /* The $txx registers depends on the abi, 1686 these will be added later into the symbol table from 1687 one of the tables below once mips_abi is set after 1688 parsing of arguments from the command line. */ 1689 SYMBOLIC_REGISTER_NAMES, 1690 1691 MIPS16_SPECIAL_REGISTER_NAMES, 1692 MDMX_VECTOR_REGISTER_NAMES, 1693 MIPS_DSP_ACCUMULATOR_NAMES, 1694 {0, 0} 1695}; 1696 1697static const struct regname reg_names_o32[] = { 1698 O32_SYMBOLIC_REGISTER_NAMES, 1699 {0, 0} 1700}; 1701 1702static const struct regname reg_names_n32n64[] = { 1703 N32N64_SYMBOLIC_REGISTER_NAMES, 1704 {0, 0} 1705}; 1706 1707static int 1708reg_lookup (char **s, unsigned int types, unsigned int *regnop) 1709{ 1710 symbolS *symbolP; 1711 char *e; 1712 char save_c; 1713 int reg = -1; 1714 1715 /* Find end of name. */ 1716 e = *s; 1717 if (is_name_beginner (*e)) 1718 ++e; 1719 while (is_part_of_name (*e)) 1720 ++e; 1721 1722 /* Terminate name. */ 1723 save_c = *e; 1724 *e = '\0'; 1725 1726 /* Look for a register symbol. */ 1727 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) 1728 { 1729 int r = S_GET_VALUE (symbolP); 1730 if (r & types) 1731 reg = r & RNUM_MASK; 1732 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) 1733 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ 1734 reg = (r & RNUM_MASK) - 2; 1735 } 1736 /* Else see if this is a register defined in an itbl entry. */ 1737 else if ((types & RTYPE_GP) && itbl_have_entries) 1738 { 1739 char *n = *s; 1740 unsigned long r; 1741 1742 if (*n == '$') 1743 ++n; 1744 if (itbl_get_reg_val (n, &r)) 1745 reg = r & RNUM_MASK; 1746 } 1747 1748 /* Advance to next token if a register was recognised. */ 1749 if (reg >= 0) 1750 *s = e; 1751 else if (types & RWARN) 1752 as_warn ("Unrecognized register name `%s'", *s); 1753 1754 *e = save_c; 1755 if (regnop) 1756 *regnop = reg; 1757 return reg >= 0; 1758} 1759 1760/* This function is called once, at assembler startup time. It should set up 1761 all the tables, etc. that the MD part of the assembler will need. */ 1762 1763void 1764md_begin (void) 1765{ 1766 const char *retval = NULL; 1767 int i = 0; 1768 int broken = 0; 1769 1770 if (mips_pic != NO_PIC) 1771 { 1772 if (g_switch_seen && g_switch_value != 0) 1773 as_bad (_("-G may not be used in position-independent code")); 1774 g_switch_value = 0; 1775 } 1776 1777 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) 1778 as_warn (_("Could not set architecture and machine")); 1779 1780 op_hash = hash_new (); 1781 1782 for (i = 0; i < NUMOPCODES;) 1783 { 1784 const char *name = mips_opcodes[i].name; 1785 1786 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); 1787 if (retval != NULL) 1788 { 1789 fprintf (stderr, _("internal error: can't hash `%s': %s\n"), 1790 mips_opcodes[i].name, retval); 1791 /* Probably a memory allocation problem? Give up now. */ 1792 as_fatal (_("Broken assembler. No assembly attempted.")); 1793 } 1794 do 1795 { 1796 if (mips_opcodes[i].pinfo != INSN_MACRO) 1797 { 1798 if (!validate_mips_insn (&mips_opcodes[i])) 1799 broken = 1; 1800 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) 1801 { 1802 create_insn (&nop_insn, mips_opcodes + i); 1803 nop_insn.fixed_p = 1; 1804 } 1805 } 1806 ++i; 1807 } 1808 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); 1809 } 1810 1811 mips16_op_hash = hash_new (); 1812 1813 i = 0; 1814 while (i < bfd_mips16_num_opcodes) 1815 { 1816 const char *name = mips16_opcodes[i].name; 1817 1818 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); 1819 if (retval != NULL) 1820 as_fatal (_("internal: can't hash `%s': %s"), 1821 mips16_opcodes[i].name, retval); 1822 do 1823 { 1824 if (mips16_opcodes[i].pinfo != INSN_MACRO 1825 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) 1826 != mips16_opcodes[i].match)) 1827 { 1828 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), 1829 mips16_opcodes[i].name, mips16_opcodes[i].args); 1830 broken = 1; 1831 } 1832 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) 1833 { 1834 create_insn (&mips16_nop_insn, mips16_opcodes + i); 1835 mips16_nop_insn.fixed_p = 1; 1836 } 1837 ++i; 1838 } 1839 while (i < bfd_mips16_num_opcodes 1840 && strcmp (mips16_opcodes[i].name, name) == 0); 1841 } 1842 1843 if (broken) 1844 as_fatal (_("Broken assembler. No assembly attempted.")); 1845 1846 /* We add all the general register names to the symbol table. This 1847 helps us detect invalid uses of them. */ 1848 for (i = 0; reg_names[i].name; i++) 1849 symbol_table_insert (symbol_new (reg_names[i].name, reg_section, 1850 reg_names[i].num, // & RNUM_MASK, 1851 &zero_address_frag)); 1852 if (HAVE_NEWABI) 1853 for (i = 0; reg_names_n32n64[i].name; i++) 1854 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, 1855 reg_names_n32n64[i].num, // & RNUM_MASK, 1856 &zero_address_frag)); 1857 else 1858 for (i = 0; reg_names_o32[i].name; i++) 1859 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, 1860 reg_names_o32[i].num, // & RNUM_MASK, 1861 &zero_address_frag)); 1862 1863 mips_no_prev_insn (); 1864 1865 mips_gprmask = 0; 1866 mips_cprmask[0] = 0; 1867 mips_cprmask[1] = 0; 1868 mips_cprmask[2] = 0; 1869 mips_cprmask[3] = 0; 1870 1871 /* set the default alignment for the text section (2**2) */ 1872 record_alignment (text_section, 2); 1873 1874 bfd_set_gp_size (stdoutput, g_switch_value); 1875 1876#ifdef OBJ_ELF 1877 if (IS_ELF) 1878 { 1879 /* On a native system other than VxWorks, sections must be aligned 1880 to 16 byte boundaries. When configured for an embedded ELF 1881 target, we don't bother. */ 1882 if (strcmp (TARGET_OS, "elf") != 0 1883 && strcmp (TARGET_OS, "vxworks") != 0) 1884 { 1885 (void) bfd_set_section_alignment (stdoutput, text_section, 4); 1886 (void) bfd_set_section_alignment (stdoutput, data_section, 4); 1887 (void) bfd_set_section_alignment (stdoutput, bss_section, 4); 1888 } 1889 1890 /* Create a .reginfo section for register masks and a .mdebug 1891 section for debugging information. */ 1892 { 1893 segT seg; 1894 subsegT subseg; 1895 flagword flags; 1896 segT sec; 1897 1898 seg = now_seg; 1899 subseg = now_subseg; 1900 1901 /* The ABI says this section should be loaded so that the 1902 running program can access it. However, we don't load it 1903 if we are configured for an embedded target */ 1904 flags = SEC_READONLY | SEC_DATA; 1905 if (strcmp (TARGET_OS, "elf") != 0) 1906 flags |= SEC_ALLOC | SEC_LOAD; 1907 1908 if (mips_abi != N64_ABI) 1909 { 1910 sec = subseg_new (".reginfo", (subsegT) 0); 1911 1912 bfd_set_section_flags (stdoutput, sec, flags); 1913 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); 1914 1915 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); 1916 } 1917 else 1918 { 1919 /* The 64-bit ABI uses a .MIPS.options section rather than 1920 .reginfo section. */ 1921 sec = subseg_new (".MIPS.options", (subsegT) 0); 1922 bfd_set_section_flags (stdoutput, sec, flags); 1923 bfd_set_section_alignment (stdoutput, sec, 3); 1924 1925 /* Set up the option header. */ 1926 { 1927 Elf_Internal_Options opthdr; 1928 char *f; 1929 1930 opthdr.kind = ODK_REGINFO; 1931 opthdr.size = (sizeof (Elf_External_Options) 1932 + sizeof (Elf64_External_RegInfo)); 1933 opthdr.section = 0; 1934 opthdr.info = 0; 1935 f = frag_more (sizeof (Elf_External_Options)); 1936 bfd_mips_elf_swap_options_out (stdoutput, &opthdr, 1937 (Elf_External_Options *) f); 1938 1939 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); 1940 } 1941 } 1942 1943 if (ECOFF_DEBUGGING) 1944 { 1945 sec = subseg_new (".mdebug", (subsegT) 0); 1946 (void) bfd_set_section_flags (stdoutput, sec, 1947 SEC_HAS_CONTENTS | SEC_READONLY); 1948 (void) bfd_set_section_alignment (stdoutput, sec, 2); 1949 } 1950 else if (mips_flag_pdr) 1951 { 1952 pdr_seg = subseg_new (".pdr", (subsegT) 0); 1953 (void) bfd_set_section_flags (stdoutput, pdr_seg, 1954 SEC_READONLY | SEC_RELOC 1955 | SEC_DEBUGGING); 1956 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); 1957 } 1958 1959 subseg_set (seg, subseg); 1960 } 1961 } 1962#endif /* OBJ_ELF */ 1963 1964 if (! ECOFF_DEBUGGING) 1965 md_obj_begin (); 1966 1967 if (mips_fix_vr4120) 1968 init_vr4120_conflicts (); 1969} 1970 1971void 1972md_mips_end (void) 1973{ 1974 if (! ECOFF_DEBUGGING) 1975 md_obj_end (); 1976} 1977 1978void 1979md_assemble (char *str) 1980{ 1981 struct mips_cl_insn insn; 1982 bfd_reloc_code_real_type unused_reloc[3] 1983 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 1984 1985 imm_expr.X_op = O_absent; 1986 imm2_expr.X_op = O_absent; 1987 offset_expr.X_op = O_absent; 1988 imm_reloc[0] = BFD_RELOC_UNUSED; 1989 imm_reloc[1] = BFD_RELOC_UNUSED; 1990 imm_reloc[2] = BFD_RELOC_UNUSED; 1991 offset_reloc[0] = BFD_RELOC_UNUSED; 1992 offset_reloc[1] = BFD_RELOC_UNUSED; 1993 offset_reloc[2] = BFD_RELOC_UNUSED; 1994 1995 if (mips_opts.mips16) 1996 mips16_ip (str, &insn); 1997 else 1998 { 1999 mips_ip (str, &insn); 2000 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), 2001 str, insn.insn_opcode)); 2002 } 2003 2004 if (insn_error) 2005 { 2006 as_bad ("%s `%s'", insn_error, str); 2007 return; 2008 } 2009 2010 if (insn.insn_mo->pinfo == INSN_MACRO) 2011 { 2012 macro_start (); 2013 if (mips_opts.mips16) 2014 mips16_macro (&insn); 2015 else 2016 macro (&insn); 2017 macro_end (); 2018 } 2019 else 2020 { 2021 if (imm_expr.X_op != O_absent) 2022 append_insn (&insn, &imm_expr, imm_reloc); 2023 else if (offset_expr.X_op != O_absent) 2024 append_insn (&insn, &offset_expr, offset_reloc); 2025 else 2026 append_insn (&insn, NULL, unused_reloc); 2027 } 2028} 2029 2030/* Return true if the given relocation might need a matching %lo(). 2031 This is only "might" because SVR4 R_MIPS_GOT16 relocations only 2032 need a matching %lo() when applied to local symbols. */ 2033 2034static inline bfd_boolean 2035reloc_needs_lo_p (bfd_reloc_code_real_type reloc) 2036{ 2037 return (HAVE_IN_PLACE_ADDENDS 2038 && (reloc == BFD_RELOC_HI16_S 2039 || reloc == BFD_RELOC_MIPS16_HI16_S 2040 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); 2041 all GOT16 relocations evaluate to "G". */ 2042 || (reloc == BFD_RELOC_MIPS_GOT16 && mips_pic != VXWORKS_PIC))); 2043} 2044 2045/* Return true if the given fixup is followed by a matching R_MIPS_LO16 2046 relocation. */ 2047 2048static inline bfd_boolean 2049fixup_has_matching_lo_p (fixS *fixp) 2050{ 2051 return (fixp->fx_next != NULL 2052 && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 2053 || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) 2054 && fixp->fx_addsy == fixp->fx_next->fx_addsy 2055 && fixp->fx_offset == fixp->fx_next->fx_offset); 2056} 2057 2058/* See whether instruction IP reads register REG. CLASS is the type 2059 of register. */ 2060 2061static int 2062insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, 2063 enum mips_regclass class) 2064{ 2065 if (class == MIPS16_REG) 2066 { 2067 assert (mips_opts.mips16); 2068 reg = mips16_to_32_reg_map[reg]; 2069 class = MIPS_GR_REG; 2070 } 2071 2072 /* Don't report on general register ZERO, since it never changes. */ 2073 if (class == MIPS_GR_REG && reg == ZERO) 2074 return 0; 2075 2076 if (class == MIPS_FP_REG) 2077 { 2078 assert (! mips_opts.mips16); 2079 /* If we are called with either $f0 or $f1, we must check $f0. 2080 This is not optimal, because it will introduce an unnecessary 2081 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would 2082 need to distinguish reading both $f0 and $f1 or just one of 2083 them. Note that we don't have to check the other way, 2084 because there is no instruction that sets both $f0 and $f1 2085 and requires a delay. */ 2086 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) 2087 && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) 2088 == (reg &~ (unsigned) 1))) 2089 return 1; 2090 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) 2091 && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) 2092 == (reg &~ (unsigned) 1))) 2093 return 1; 2094 } 2095 else if (! mips_opts.mips16) 2096 { 2097 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) 2098 && EXTRACT_OPERAND (RS, *ip) == reg) 2099 return 1; 2100 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) 2101 && EXTRACT_OPERAND (RT, *ip) == reg) 2102 return 1; 2103 } 2104 else 2105 { 2106 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) 2107 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) 2108 return 1; 2109 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) 2110 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) 2111 return 1; 2112 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) 2113 && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] 2114 == reg)) 2115 return 1; 2116 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) 2117 return 1; 2118 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) 2119 return 1; 2120 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) 2121 return 1; 2122 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) 2123 && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) 2124 return 1; 2125 } 2126 2127 return 0; 2128} 2129 2130/* This function returns true if modifying a register requires a 2131 delay. */ 2132 2133static int 2134reg_needs_delay (unsigned int reg) 2135{ 2136 unsigned long prev_pinfo; 2137 2138 prev_pinfo = history[0].insn_mo->pinfo; 2139 if (! mips_opts.noreorder 2140 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) 2141 && ! gpr_interlocks) 2142 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) 2143 && ! cop_interlocks))) 2144 { 2145 /* A load from a coprocessor or from memory. All load delays 2146 delay the use of general register rt for one instruction. */ 2147 /* Itbl support may require additional care here. */ 2148 know (prev_pinfo & INSN_WRITE_GPR_T); 2149 if (reg == EXTRACT_OPERAND (RT, history[0])) 2150 return 1; 2151 } 2152 2153 return 0; 2154} 2155 2156/* Move all labels in insn_labels to the current insertion point. */ 2157 2158static void 2159mips_move_labels (void) 2160{ 2161 segment_info_type *si = seg_info (now_seg); 2162 struct insn_label_list *l; 2163 valueT val; 2164 2165 for (l = si->label_list; l != NULL; l = l->next) 2166 { 2167 assert (S_GET_SEGMENT (l->label) == now_seg); 2168 symbol_set_frag (l->label, frag_now); 2169 val = (valueT) frag_now_fix (); 2170 /* mips16 text labels are stored as odd. */ 2171 if (mips_opts.mips16) 2172 ++val; 2173 S_SET_VALUE (l->label, val); 2174 } 2175} 2176 2177static bfd_boolean 2178s_is_linkonce (symbolS *sym, segT from_seg) 2179{ 2180 bfd_boolean linkonce = FALSE; 2181 segT symseg = S_GET_SEGMENT (sym); 2182 2183 if (symseg != from_seg && !S_IS_LOCAL (sym)) 2184 { 2185 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) 2186 linkonce = TRUE; 2187#ifdef OBJ_ELF 2188 /* The GNU toolchain uses an extension for ELF: a section 2189 beginning with the magic string .gnu.linkonce is a 2190 linkonce section. */ 2191 if (strncmp (segment_name (symseg), ".gnu.linkonce", 2192 sizeof ".gnu.linkonce" - 1) == 0) 2193 linkonce = TRUE; 2194#endif 2195 } 2196 return linkonce; 2197} 2198 2199/* Mark instruction labels in mips16 mode. This permits the linker to 2200 handle them specially, such as generating jalx instructions when 2201 needed. We also make them odd for the duration of the assembly, in 2202 order to generate the right sort of code. We will make them even 2203 in the adjust_symtab routine, while leaving them marked. This is 2204 convenient for the debugger and the disassembler. The linker knows 2205 to make them odd again. */ 2206 2207static void 2208mips16_mark_labels (void) 2209{ 2210 segment_info_type *si = seg_info (now_seg); 2211 struct insn_label_list *l; 2212 2213 if (!mips_opts.mips16) 2214 return; 2215 2216 for (l = si->label_list; l != NULL; l = l->next) 2217 { 2218 symbolS *label = l->label; 2219 2220#if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) 2221 if (IS_ELF) 2222 S_SET_OTHER (label, STO_MIPS16); 2223#endif 2224 if ((S_GET_VALUE (label) & 1) == 0 2225 /* Don't adjust the address if the label is global or weak, or 2226 in a link-once section, since we'll be emitting symbol reloc 2227 references to it which will be patched up by the linker, and 2228 the final value of the symbol may or may not be MIPS16. */ 2229 && ! S_IS_WEAK (label) 2230 && ! S_IS_EXTERNAL (label) 2231 && ! s_is_linkonce (label, now_seg)) 2232 S_SET_VALUE (label, S_GET_VALUE (label) | 1); 2233 } 2234} 2235 2236/* End the current frag. Make it a variant frag and record the 2237 relaxation info. */ 2238 2239static void 2240relax_close_frag (void) 2241{ 2242 mips_macro_warning.first_frag = frag_now; 2243 frag_var (rs_machine_dependent, 0, 0, 2244 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), 2245 mips_relax.symbol, 0, (char *) mips_relax.first_fixup); 2246 2247 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); 2248 mips_relax.first_fixup = 0; 2249} 2250 2251/* Start a new relaxation sequence whose expansion depends on SYMBOL. 2252 See the comment above RELAX_ENCODE for more details. */ 2253 2254static void 2255relax_start (symbolS *symbol) 2256{ 2257 assert (mips_relax.sequence == 0); 2258 mips_relax.sequence = 1; 2259 mips_relax.symbol = symbol; 2260} 2261 2262/* Start generating the second version of a relaxable sequence. 2263 See the comment above RELAX_ENCODE for more details. */ 2264 2265static void 2266relax_switch (void) 2267{ 2268 assert (mips_relax.sequence == 1); 2269 mips_relax.sequence = 2; 2270} 2271 2272/* End the current relaxable sequence. */ 2273 2274static void 2275relax_end (void) 2276{ 2277 assert (mips_relax.sequence == 2); 2278 relax_close_frag (); 2279 mips_relax.sequence = 0; 2280} 2281 2282/* Classify an instruction according to the FIX_VR4120_* enumeration. 2283 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected 2284 by VR4120 errata. */ 2285 2286static unsigned int 2287classify_vr4120_insn (const char *name) 2288{ 2289 if (strncmp (name, "macc", 4) == 0) 2290 return FIX_VR4120_MACC; 2291 if (strncmp (name, "dmacc", 5) == 0) 2292 return FIX_VR4120_DMACC; 2293 if (strncmp (name, "mult", 4) == 0) 2294 return FIX_VR4120_MULT; 2295 if (strncmp (name, "dmult", 5) == 0) 2296 return FIX_VR4120_DMULT; 2297 if (strstr (name, "div")) 2298 return FIX_VR4120_DIV; 2299 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) 2300 return FIX_VR4120_MTHILO; 2301 return NUM_FIX_VR4120_CLASSES; 2302} 2303 2304/* Return the number of instructions that must separate INSN1 and INSN2, 2305 where INSN1 is the earlier instruction. Return the worst-case value 2306 for any INSN2 if INSN2 is null. */ 2307 2308static unsigned int 2309insns_between (const struct mips_cl_insn *insn1, 2310 const struct mips_cl_insn *insn2) 2311{ 2312 unsigned long pinfo1, pinfo2; 2313 2314 /* This function needs to know which pinfo flags are set for INSN2 2315 and which registers INSN2 uses. The former is stored in PINFO2 and 2316 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 2317 will have every flag set and INSN2_USES_REG will always return true. */ 2318 pinfo1 = insn1->insn_mo->pinfo; 2319 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; 2320 2321#define INSN2_USES_REG(REG, CLASS) \ 2322 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) 2323 2324 /* For most targets, write-after-read dependencies on the HI and LO 2325 registers must be separated by at least two instructions. */ 2326 if (!hilo_interlocks) 2327 { 2328 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) 2329 return 2; 2330 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) 2331 return 2; 2332 } 2333 2334 /* If we're working around r7000 errata, there must be two instructions 2335 between an mfhi or mflo and any instruction that uses the result. */ 2336 if (mips_7000_hilo_fix 2337 && MF_HILO_INSN (pinfo1) 2338 && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) 2339 return 2; 2340 2341 /* If working around VR4120 errata, check for combinations that need 2342 a single intervening instruction. */ 2343 if (mips_fix_vr4120) 2344 { 2345 unsigned int class1, class2; 2346 2347 class1 = classify_vr4120_insn (insn1->insn_mo->name); 2348 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) 2349 { 2350 if (insn2 == NULL) 2351 return 1; 2352 class2 = classify_vr4120_insn (insn2->insn_mo->name); 2353 if (vr4120_conflicts[class1] & (1 << class2)) 2354 return 1; 2355 } 2356 } 2357 2358 if (!mips_opts.mips16) 2359 { 2360 /* Check for GPR or coprocessor load delays. All such delays 2361 are on the RT register. */ 2362 /* Itbl support may require additional care here. */ 2363 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) 2364 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) 2365 { 2366 know (pinfo1 & INSN_WRITE_GPR_T); 2367 if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) 2368 return 1; 2369 } 2370 2371 /* Check for generic coprocessor hazards. 2372 2373 This case is not handled very well. There is no special 2374 knowledge of CP0 handling, and the coprocessors other than 2375 the floating point unit are not distinguished at all. */ 2376 /* Itbl support may require additional care here. FIXME! 2377 Need to modify this to include knowledge about 2378 user specified delays! */ 2379 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) 2380 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) 2381 { 2382 /* Handle cases where INSN1 writes to a known general coprocessor 2383 register. There must be a one instruction delay before INSN2 2384 if INSN2 reads that register, otherwise no delay is needed. */ 2385 if (pinfo1 & INSN_WRITE_FPR_T) 2386 { 2387 if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) 2388 return 1; 2389 } 2390 else if (pinfo1 & INSN_WRITE_FPR_S) 2391 { 2392 if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) 2393 return 1; 2394 } 2395 else 2396 { 2397 /* Read-after-write dependencies on the control registers 2398 require a two-instruction gap. */ 2399 if ((pinfo1 & INSN_WRITE_COND_CODE) 2400 && (pinfo2 & INSN_READ_COND_CODE)) 2401 return 2; 2402 2403 /* We don't know exactly what INSN1 does. If INSN2 is 2404 also a coprocessor instruction, assume there must be 2405 a one instruction gap. */ 2406 if (pinfo2 & INSN_COP) 2407 return 1; 2408 } 2409 } 2410 2411 /* Check for read-after-write dependencies on the coprocessor 2412 control registers in cases where INSN1 does not need a general 2413 coprocessor delay. This means that INSN1 is a floating point 2414 comparison instruction. */ 2415 /* Itbl support may require additional care here. */ 2416 else if (!cop_interlocks 2417 && (pinfo1 & INSN_WRITE_COND_CODE) 2418 && (pinfo2 & INSN_READ_COND_CODE)) 2419 return 1; 2420 } 2421 2422#undef INSN2_USES_REG 2423 2424 return 0; 2425} 2426 2427/* Return the number of nops that would be needed to work around the 2428 VR4130 mflo/mfhi errata if instruction INSN immediately followed 2429 the MAX_VR4130_NOPS instructions described by HISTORY. */ 2430 2431static int 2432nops_for_vr4130 (const struct mips_cl_insn *history, 2433 const struct mips_cl_insn *insn) 2434{ 2435 int i, j, reg; 2436 2437 /* Check if the instruction writes to HI or LO. MTHI and MTLO 2438 are not affected by the errata. */ 2439 if (insn != 0 2440 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 2441 || strcmp (insn->insn_mo->name, "mtlo") == 0 2442 || strcmp (insn->insn_mo->name, "mthi") == 0)) 2443 return 0; 2444 2445 /* Search for the first MFLO or MFHI. */ 2446 for (i = 0; i < MAX_VR4130_NOPS; i++) 2447 if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo)) 2448 { 2449 /* Extract the destination register. */ 2450 if (mips_opts.mips16) 2451 reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])]; 2452 else 2453 reg = EXTRACT_OPERAND (RD, history[i]); 2454 2455 /* No nops are needed if INSN reads that register. */ 2456 if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) 2457 return 0; 2458 2459 /* ...or if any of the intervening instructions do. */ 2460 for (j = 0; j < i; j++) 2461 if (insn_uses_reg (&history[j], reg, MIPS_GR_REG)) 2462 return 0; 2463 2464 return MAX_VR4130_NOPS - i; 2465 } 2466 return 0; 2467} 2468 2469/* Return the number of nops that would be needed if instruction INSN 2470 immediately followed the MAX_NOPS instructions given by HISTORY, 2471 where HISTORY[0] is the most recent instruction. If INSN is null, 2472 return the worse-case number of nops for any instruction. */ 2473 2474static int 2475nops_for_insn (const struct mips_cl_insn *history, 2476 const struct mips_cl_insn *insn) 2477{ 2478 int i, nops, tmp_nops; 2479 2480 nops = 0; 2481 for (i = 0; i < MAX_DELAY_NOPS; i++) 2482 if (!history[i].noreorder_p) 2483 { 2484 tmp_nops = insns_between (history + i, insn) - i; 2485 if (tmp_nops > nops) 2486 nops = tmp_nops; 2487 } 2488 2489 if (mips_fix_vr4130) 2490 { 2491 tmp_nops = nops_for_vr4130 (history, insn); 2492 if (tmp_nops > nops) 2493 nops = tmp_nops; 2494 } 2495 2496 return nops; 2497} 2498 2499/* The variable arguments provide NUM_INSNS extra instructions that 2500 might be added to HISTORY. Return the largest number of nops that 2501 would be needed after the extended sequence. */ 2502 2503static int 2504nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...) 2505{ 2506 va_list args; 2507 struct mips_cl_insn buffer[MAX_NOPS]; 2508 struct mips_cl_insn *cursor; 2509 int nops; 2510 2511 va_start (args, history); 2512 cursor = buffer + num_insns; 2513 memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor)); 2514 while (cursor > buffer) 2515 *--cursor = *va_arg (args, const struct mips_cl_insn *); 2516 2517 nops = nops_for_insn (buffer, NULL); 2518 va_end (args); 2519 return nops; 2520} 2521 2522/* Like nops_for_insn, but if INSN is a branch, take into account the 2523 worst-case delay for the branch target. */ 2524 2525static int 2526nops_for_insn_or_target (const struct mips_cl_insn *history, 2527 const struct mips_cl_insn *insn) 2528{ 2529 int nops, tmp_nops; 2530 2531 nops = nops_for_insn (history, insn); 2532 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY 2533 | INSN_COND_BRANCH_DELAY 2534 | INSN_COND_BRANCH_LIKELY)) 2535 { 2536 tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN); 2537 if (tmp_nops > nops) 2538 nops = tmp_nops; 2539 } 2540 else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH)) 2541 { 2542 tmp_nops = nops_for_sequence (1, history, insn); 2543 if (tmp_nops > nops) 2544 nops = tmp_nops; 2545 } 2546 return nops; 2547} 2548 2549/* Output an instruction. IP is the instruction information. 2550 ADDRESS_EXPR is an operand of the instruction to be used with 2551 RELOC_TYPE. */ 2552 2553static void 2554append_insn (struct mips_cl_insn *ip, expressionS *address_expr, 2555 bfd_reloc_code_real_type *reloc_type) 2556{ 2557 unsigned long prev_pinfo, pinfo; 2558 relax_stateT prev_insn_frag_type = 0; 2559 bfd_boolean relaxed_branch = FALSE; 2560 segment_info_type *si = seg_info (now_seg); 2561 2562 /* Mark instruction labels in mips16 mode. */ 2563 mips16_mark_labels (); 2564 2565 prev_pinfo = history[0].insn_mo->pinfo; 2566 pinfo = ip->insn_mo->pinfo; 2567 2568 if (mips_relax.sequence != 2 && !mips_opts.noreorder) 2569 { 2570 /* There are a lot of optimizations we could do that we don't. 2571 In particular, we do not, in general, reorder instructions. 2572 If you use gcc with optimization, it will reorder 2573 instructions and generally do much more optimization then we 2574 do here; repeating all that work in the assembler would only 2575 benefit hand written assembly code, and does not seem worth 2576 it. */ 2577 int nops = (mips_optimize == 0 2578 ? nops_for_insn (history, NULL) 2579 : nops_for_insn_or_target (history, ip)); 2580 if (nops > 0) 2581 { 2582 fragS *old_frag; 2583 unsigned long old_frag_offset; 2584 int i; 2585 2586 old_frag = frag_now; 2587 old_frag_offset = frag_now_fix (); 2588 2589 for (i = 0; i < nops; i++) 2590 emit_nop (); 2591 2592 if (listing) 2593 { 2594 listing_prev_line (); 2595 /* We may be at the start of a variant frag. In case we 2596 are, make sure there is enough space for the frag 2597 after the frags created by listing_prev_line. The 2598 argument to frag_grow here must be at least as large 2599 as the argument to all other calls to frag_grow in 2600 this file. We don't have to worry about being in the 2601 middle of a variant frag, because the variants insert 2602 all needed nop instructions themselves. */ 2603 frag_grow (40); 2604 } 2605 2606 mips_move_labels (); 2607 2608#ifndef NO_ECOFF_DEBUGGING 2609 if (ECOFF_DEBUGGING) 2610 ecoff_fix_loc (old_frag, old_frag_offset); 2611#endif 2612 } 2613 } 2614 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) 2615 { 2616 /* Work out how many nops in prev_nop_frag are needed by IP. */ 2617 int nops = nops_for_insn_or_target (history, ip); 2618 assert (nops <= prev_nop_frag_holds); 2619 2620 /* Enforce NOPS as a minimum. */ 2621 if (nops > prev_nop_frag_required) 2622 prev_nop_frag_required = nops; 2623 2624 if (prev_nop_frag_holds == prev_nop_frag_required) 2625 { 2626 /* Settle for the current number of nops. Update the history 2627 accordingly (for the benefit of any future .set reorder code). */ 2628 prev_nop_frag = NULL; 2629 insert_into_history (prev_nop_frag_since, 2630 prev_nop_frag_holds, NOP_INSN); 2631 } 2632 else 2633 { 2634 /* Allow this instruction to replace one of the nops that was 2635 tentatively added to prev_nop_frag. */ 2636 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; 2637 prev_nop_frag_holds--; 2638 prev_nop_frag_since++; 2639 } 2640 } 2641 2642#ifdef OBJ_ELF 2643 /* The value passed to dwarf2_emit_insn is the distance between 2644 the beginning of the current instruction and the address that 2645 should be recorded in the debug tables. For MIPS16 debug info 2646 we want to use ISA-encoded addresses, so we pass -1 for an 2647 address higher by one than the current. */ 2648 dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); 2649#endif 2650 2651 /* Record the frag type before frag_var. */ 2652 if (history[0].frag) 2653 prev_insn_frag_type = history[0].frag->fr_type; 2654 2655 if (address_expr 2656 && *reloc_type == BFD_RELOC_16_PCREL_S2 2657 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY 2658 || pinfo & INSN_COND_BRANCH_LIKELY) 2659 && mips_relax_branch 2660 /* Don't try branch relaxation within .set nomacro, or within 2661 .set noat if we use $at for PIC computations. If it turns 2662 out that the branch was out-of-range, we'll get an error. */ 2663 && !mips_opts.warn_about_macros 2664 && !(mips_opts.noat && mips_pic != NO_PIC) 2665 && !mips_opts.mips16) 2666 { 2667 relaxed_branch = TRUE; 2668 add_relaxed_insn (ip, (relaxed_branch_length 2669 (NULL, NULL, 2670 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 2671 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 2672 : 0)), 4, 2673 RELAX_BRANCH_ENCODE 2674 (pinfo & INSN_UNCOND_BRANCH_DELAY, 2675 pinfo & INSN_COND_BRANCH_LIKELY, 2676 pinfo & INSN_WRITE_GPR_31, 2677 0), 2678 address_expr->X_add_symbol, 2679 address_expr->X_add_number); 2680 *reloc_type = BFD_RELOC_UNUSED; 2681 } 2682 else if (*reloc_type > BFD_RELOC_UNUSED) 2683 { 2684 /* We need to set up a variant frag. */ 2685 assert (mips_opts.mips16 && address_expr != NULL); 2686 add_relaxed_insn (ip, 4, 0, 2687 RELAX_MIPS16_ENCODE 2688 (*reloc_type - BFD_RELOC_UNUSED, 2689 mips16_small, mips16_ext, 2690 prev_pinfo & INSN_UNCOND_BRANCH_DELAY, 2691 history[0].mips16_absolute_jump_p), 2692 make_expr_symbol (address_expr), 0); 2693 } 2694 else if (mips_opts.mips16 2695 && ! ip->use_extend 2696 && *reloc_type != BFD_RELOC_MIPS16_JMP) 2697 { 2698 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) 2699 /* Make sure there is enough room to swap this instruction with 2700 a following jump instruction. */ 2701 frag_grow (6); 2702 add_fixed_insn (ip); 2703 } 2704 else 2705 { 2706 if (mips_opts.mips16 2707 && mips_opts.noreorder 2708 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 2709 as_warn (_("extended instruction in delay slot")); 2710 2711 if (mips_relax.sequence) 2712 { 2713 /* If we've reached the end of this frag, turn it into a variant 2714 frag and record the information for the instructions we've 2715 written so far. */ 2716 if (frag_room () < 4) 2717 relax_close_frag (); 2718 mips_relax.sizes[mips_relax.sequence - 1] += 4; 2719 } 2720 2721 if (mips_relax.sequence != 2) 2722 mips_macro_warning.sizes[0] += 4; 2723 if (mips_relax.sequence != 1) 2724 mips_macro_warning.sizes[1] += 4; 2725 2726 if (mips_opts.mips16) 2727 { 2728 ip->fixed_p = 1; 2729 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); 2730 } 2731 add_fixed_insn (ip); 2732 } 2733 2734 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) 2735 { 2736 if (address_expr->X_op == O_constant) 2737 { 2738 unsigned int tmp; 2739 2740 switch (*reloc_type) 2741 { 2742 case BFD_RELOC_32: 2743 ip->insn_opcode |= address_expr->X_add_number; 2744 break; 2745 2746 case BFD_RELOC_MIPS_HIGHEST: 2747 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; 2748 ip->insn_opcode |= tmp & 0xffff; 2749 break; 2750 2751 case BFD_RELOC_MIPS_HIGHER: 2752 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; 2753 ip->insn_opcode |= tmp & 0xffff; 2754 break; 2755 2756 case BFD_RELOC_HI16_S: 2757 tmp = (address_expr->X_add_number + 0x8000) >> 16; 2758 ip->insn_opcode |= tmp & 0xffff; 2759 break; 2760 2761 case BFD_RELOC_HI16: 2762 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; 2763 break; 2764 2765 case BFD_RELOC_UNUSED: 2766 case BFD_RELOC_LO16: 2767 case BFD_RELOC_MIPS_GOT_DISP: 2768 ip->insn_opcode |= address_expr->X_add_number & 0xffff; 2769 break; 2770 2771 case BFD_RELOC_MIPS_JMP: 2772 if ((address_expr->X_add_number & 3) != 0) 2773 as_bad (_("jump to misaligned address (0x%lx)"), 2774 (unsigned long) address_expr->X_add_number); 2775 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; 2776 break; 2777 2778 case BFD_RELOC_MIPS16_JMP: 2779 if ((address_expr->X_add_number & 3) != 0) 2780 as_bad (_("jump to misaligned address (0x%lx)"), 2781 (unsigned long) address_expr->X_add_number); 2782 ip->insn_opcode |= 2783 (((address_expr->X_add_number & 0x7c0000) << 3) 2784 | ((address_expr->X_add_number & 0xf800000) >> 7) 2785 | ((address_expr->X_add_number & 0x3fffc) >> 2)); 2786 break; 2787 2788 case BFD_RELOC_16_PCREL_S2: 2789 if ((address_expr->X_add_number & 3) != 0) 2790 as_bad (_("branch to misaligned address (0x%lx)"), 2791 (unsigned long) address_expr->X_add_number); 2792 if (mips_relax_branch) 2793 goto need_reloc; 2794 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff) 2795 as_bad (_("branch address range overflow (0x%lx)"), 2796 (unsigned long) address_expr->X_add_number); 2797 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff; 2798 break; 2799 2800 default: 2801 internalError (); 2802 } 2803 } 2804 else if (*reloc_type < BFD_RELOC_UNUSED) 2805 need_reloc: 2806 { 2807 reloc_howto_type *howto; 2808 int i; 2809 2810 /* In a compound relocation, it is the final (outermost) 2811 operator that determines the relocated field. */ 2812 for (i = 1; i < 3; i++) 2813 if (reloc_type[i] == BFD_RELOC_UNUSED) 2814 break; 2815 2816 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); 2817 ip->fixp[0] = fix_new_exp (ip->frag, ip->where, 2818 bfd_get_reloc_size (howto), 2819 address_expr, 2820 reloc_type[0] == BFD_RELOC_16_PCREL_S2, 2821 reloc_type[0]); 2822 2823 /* Tag symbols that have a R_MIPS16_26 relocation against them. */ 2824 if (reloc_type[0] == BFD_RELOC_MIPS16_JMP 2825 && ip->fixp[0]->fx_addsy) 2826 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; 2827 2828 /* These relocations can have an addend that won't fit in 2829 4 octets for 64bit assembly. */ 2830 if (HAVE_64BIT_GPRS 2831 && ! howto->partial_inplace 2832 && (reloc_type[0] == BFD_RELOC_16 2833 || reloc_type[0] == BFD_RELOC_32 2834 || reloc_type[0] == BFD_RELOC_MIPS_JMP 2835 || reloc_type[0] == BFD_RELOC_HI16_S 2836 || reloc_type[0] == BFD_RELOC_LO16 2837 || reloc_type[0] == BFD_RELOC_GPREL16 2838 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL 2839 || reloc_type[0] == BFD_RELOC_GPREL32 2840 || reloc_type[0] == BFD_RELOC_64 2841 || reloc_type[0] == BFD_RELOC_CTOR 2842 || reloc_type[0] == BFD_RELOC_MIPS_SUB 2843 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST 2844 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER 2845 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP 2846 || reloc_type[0] == BFD_RELOC_MIPS_REL16 2847 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT 2848 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL 2849 || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S 2850 || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) 2851 ip->fixp[0]->fx_no_overflow = 1; 2852 2853 if (mips_relax.sequence) 2854 { 2855 if (mips_relax.first_fixup == 0) 2856 mips_relax.first_fixup = ip->fixp[0]; 2857 } 2858 else if (reloc_needs_lo_p (*reloc_type)) 2859 { 2860 struct mips_hi_fixup *hi_fixup; 2861 2862 /* Reuse the last entry if it already has a matching %lo. */ 2863 hi_fixup = mips_hi_fixup_list; 2864 if (hi_fixup == 0 2865 || !fixup_has_matching_lo_p (hi_fixup->fixp)) 2866 { 2867 hi_fixup = ((struct mips_hi_fixup *) 2868 xmalloc (sizeof (struct mips_hi_fixup))); 2869 hi_fixup->next = mips_hi_fixup_list; 2870 mips_hi_fixup_list = hi_fixup; 2871 } 2872 hi_fixup->fixp = ip->fixp[0]; 2873 hi_fixup->seg = now_seg; 2874 } 2875 2876 /* Add fixups for the second and third relocations, if given. 2877 Note that the ABI allows the second relocation to be 2878 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the 2879 moment we only use RSS_UNDEF, but we could add support 2880 for the others if it ever becomes necessary. */ 2881 for (i = 1; i < 3; i++) 2882 if (reloc_type[i] != BFD_RELOC_UNUSED) 2883 { 2884 ip->fixp[i] = fix_new (ip->frag, ip->where, 2885 ip->fixp[0]->fx_size, NULL, 0, 2886 FALSE, reloc_type[i]); 2887 2888 /* Use fx_tcbit to mark compound relocs. */ 2889 ip->fixp[0]->fx_tcbit = 1; 2890 ip->fixp[i]->fx_tcbit = 1; 2891 } 2892 } 2893 } 2894 install_insn (ip); 2895 2896 /* Update the register mask information. */ 2897 if (! mips_opts.mips16) 2898 { 2899 if (pinfo & INSN_WRITE_GPR_D) 2900 mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); 2901 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) 2902 mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); 2903 if (pinfo & INSN_READ_GPR_S) 2904 mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); 2905 if (pinfo & INSN_WRITE_GPR_31) 2906 mips_gprmask |= 1 << RA; 2907 if (pinfo & INSN_WRITE_FPR_D) 2908 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); 2909 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) 2910 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); 2911 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) 2912 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); 2913 if ((pinfo & INSN_READ_FPR_R) != 0) 2914 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); 2915 if (pinfo & INSN_COP) 2916 { 2917 /* We don't keep enough information to sort these cases out. 2918 The itbl support does keep this information however, although 2919 we currently don't support itbl fprmats as part of the cop 2920 instruction. May want to add this support in the future. */ 2921 } 2922 /* Never set the bit for $0, which is always zero. */ 2923 mips_gprmask &= ~1 << 0; 2924 } 2925 else 2926 { 2927 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) 2928 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); 2929 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) 2930 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); 2931 if (pinfo & MIPS16_INSN_WRITE_Z) 2932 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); 2933 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) 2934 mips_gprmask |= 1 << TREG; 2935 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) 2936 mips_gprmask |= 1 << SP; 2937 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) 2938 mips_gprmask |= 1 << RA; 2939 if (pinfo & MIPS16_INSN_WRITE_GPR_Y) 2940 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); 2941 if (pinfo & MIPS16_INSN_READ_Z) 2942 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); 2943 if (pinfo & MIPS16_INSN_READ_GPR_X) 2944 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); 2945 } 2946 2947 if (mips_relax.sequence != 2 && !mips_opts.noreorder) 2948 { 2949 /* Filling the branch delay slot is more complex. We try to 2950 switch the branch with the previous instruction, which we can 2951 do if the previous instruction does not set up a condition 2952 that the branch tests and if the branch is not itself the 2953 target of any branch. */ 2954 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) 2955 || (pinfo & INSN_COND_BRANCH_DELAY)) 2956 { 2957 if (mips_optimize < 2 2958 /* If we have seen .set volatile or .set nomove, don't 2959 optimize. */ 2960 || mips_opts.nomove != 0 2961 /* We can't swap if the previous instruction's position 2962 is fixed. */ 2963 || history[0].fixed_p 2964 /* If the previous previous insn was in a .set 2965 noreorder, we can't swap. Actually, the MIPS 2966 assembler will swap in this situation. However, gcc 2967 configured -with-gnu-as will generate code like 2968 .set noreorder 2969 lw $4,XXX 2970 .set reorder 2971 INSN 2972 bne $4,$0,foo 2973 in which we can not swap the bne and INSN. If gcc is 2974 not configured -with-gnu-as, it does not output the 2975 .set pseudo-ops. */ 2976 || history[1].noreorder_p 2977 /* If the branch is itself the target of a branch, we 2978 can not swap. We cheat on this; all we check for is 2979 whether there is a label on this instruction. If 2980 there are any branches to anything other than a 2981 label, users must use .set noreorder. */ 2982 || si->label_list != NULL 2983 /* If the previous instruction is in a variant frag 2984 other than this branch's one, we cannot do the swap. 2985 This does not apply to the mips16, which uses variant 2986 frags for different purposes. */ 2987 || (! mips_opts.mips16 2988 && prev_insn_frag_type == rs_machine_dependent) 2989 /* Check for conflicts between the branch and the instructions 2990 before the candidate delay slot. */ 2991 || nops_for_insn (history + 1, ip) > 0 2992 /* Check for conflicts between the swapped sequence and the 2993 target of the branch. */ 2994 || nops_for_sequence (2, history + 1, ip, history) > 0 2995 /* We do not swap with a trap instruction, since it 2996 complicates trap handlers to have the trap 2997 instruction be in a delay slot. */ 2998 || (prev_pinfo & INSN_TRAP) 2999 /* If the branch reads a register that the previous 3000 instruction sets, we can not swap. */ 3001 || (! mips_opts.mips16 3002 && (prev_pinfo & INSN_WRITE_GPR_T) 3003 && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), 3004 MIPS_GR_REG)) 3005 || (! mips_opts.mips16 3006 && (prev_pinfo & INSN_WRITE_GPR_D) 3007 && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), 3008 MIPS_GR_REG)) 3009 || (mips_opts.mips16 3010 && (((prev_pinfo & MIPS16_INSN_WRITE_X) 3011 && (insn_uses_reg 3012 (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), 3013 MIPS16_REG))) 3014 || ((prev_pinfo & MIPS16_INSN_WRITE_Y) 3015 && (insn_uses_reg 3016 (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), 3017 MIPS16_REG))) 3018 || ((prev_pinfo & MIPS16_INSN_WRITE_Z) 3019 && (insn_uses_reg 3020 (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), 3021 MIPS16_REG))) 3022 || ((prev_pinfo & MIPS16_INSN_WRITE_T) 3023 && insn_uses_reg (ip, TREG, MIPS_GR_REG)) 3024 || ((prev_pinfo & MIPS16_INSN_WRITE_31) 3025 && insn_uses_reg (ip, RA, MIPS_GR_REG)) 3026 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) 3027 && insn_uses_reg (ip, 3028 MIPS16OP_EXTRACT_REG32R 3029 (history[0].insn_opcode), 3030 MIPS_GR_REG)))) 3031 /* If the branch writes a register that the previous 3032 instruction sets, we can not swap (we know that 3033 branches write only to RD or to $31). */ 3034 || (! mips_opts.mips16 3035 && (prev_pinfo & INSN_WRITE_GPR_T) 3036 && (((pinfo & INSN_WRITE_GPR_D) 3037 && (EXTRACT_OPERAND (RT, history[0]) 3038 == EXTRACT_OPERAND (RD, *ip))) 3039 || ((pinfo & INSN_WRITE_GPR_31) 3040 && EXTRACT_OPERAND (RT, history[0]) == RA))) 3041 || (! mips_opts.mips16 3042 && (prev_pinfo & INSN_WRITE_GPR_D) 3043 && (((pinfo & INSN_WRITE_GPR_D) 3044 && (EXTRACT_OPERAND (RD, history[0]) 3045 == EXTRACT_OPERAND (RD, *ip))) 3046 || ((pinfo & INSN_WRITE_GPR_31) 3047 && EXTRACT_OPERAND (RD, history[0]) == RA))) 3048 || (mips_opts.mips16 3049 && (pinfo & MIPS16_INSN_WRITE_31) 3050 && ((prev_pinfo & MIPS16_INSN_WRITE_31) 3051 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) 3052 && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) 3053 == RA)))) 3054 /* If the branch writes a register that the previous 3055 instruction reads, we can not swap (we know that 3056 branches only write to RD or to $31). */ 3057 || (! mips_opts.mips16 3058 && (pinfo & INSN_WRITE_GPR_D) 3059 && insn_uses_reg (&history[0], 3060 EXTRACT_OPERAND (RD, *ip), 3061 MIPS_GR_REG)) 3062 || (! mips_opts.mips16 3063 && (pinfo & INSN_WRITE_GPR_31) 3064 && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) 3065 || (mips_opts.mips16 3066 && (pinfo & MIPS16_INSN_WRITE_31) 3067 && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) 3068 /* If one instruction sets a condition code and the 3069 other one uses a condition code, we can not swap. */ 3070 || ((pinfo & INSN_READ_COND_CODE) 3071 && (prev_pinfo & INSN_WRITE_COND_CODE)) 3072 || ((pinfo & INSN_WRITE_COND_CODE) 3073 && (prev_pinfo & INSN_READ_COND_CODE)) 3074 /* If the previous instruction uses the PC, we can not 3075 swap. */ 3076 || (mips_opts.mips16 3077 && (prev_pinfo & MIPS16_INSN_READ_PC)) 3078 /* If the previous instruction had a fixup in mips16 3079 mode, we can not swap. This normally means that the 3080 previous instruction was a 4 byte branch anyhow. */ 3081 || (mips_opts.mips16 && history[0].fixp[0]) 3082 /* If the previous instruction is a sync, sync.l, or 3083 sync.p, we can not swap. */ 3084 || (prev_pinfo & INSN_SYNC)) 3085 { 3086 if (mips_opts.mips16 3087 && (pinfo & INSN_UNCOND_BRANCH_DELAY) 3088 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)) 3089 && ISA_SUPPORTS_MIPS16E) 3090 { 3091 /* Convert MIPS16 jr/jalr into a "compact" jump. */ 3092 ip->insn_opcode |= 0x0080; 3093 install_insn (ip); 3094 insert_into_history (0, 1, ip); 3095 } 3096 else 3097 { 3098 /* We could do even better for unconditional branches to 3099 portions of this object file; we could pick up the 3100 instruction at the destination, put it in the delay 3101 slot, and bump the destination address. */ 3102 insert_into_history (0, 1, ip); 3103 emit_nop (); 3104 } 3105 3106 if (mips_relax.sequence) 3107 mips_relax.sizes[mips_relax.sequence - 1] += 4; 3108 } 3109 else 3110 { 3111 /* It looks like we can actually do the swap. */ 3112 struct mips_cl_insn delay = history[0]; 3113 if (mips_opts.mips16) 3114 { 3115 know (delay.frag == ip->frag); 3116 move_insn (ip, delay.frag, delay.where); 3117 move_insn (&delay, ip->frag, ip->where + insn_length (ip)); 3118 } 3119 else if (relaxed_branch) 3120 { 3121 /* Add the delay slot instruction to the end of the 3122 current frag and shrink the fixed part of the 3123 original frag. If the branch occupies the tail of 3124 the latter, move it backwards to cover the gap. */ 3125 delay.frag->fr_fix -= 4; 3126 if (delay.frag == ip->frag) 3127 move_insn (ip, ip->frag, ip->where - 4); 3128 add_fixed_insn (&delay); 3129 } 3130 else 3131 { 3132 move_insn (&delay, ip->frag, ip->where); 3133 move_insn (ip, history[0].frag, history[0].where); 3134 } 3135 history[0] = *ip; 3136 delay.fixed_p = 1; 3137 insert_into_history (0, 1, &delay); 3138 } 3139 3140 /* If that was an unconditional branch, forget the previous 3141 insn information. */ 3142 if (pinfo & INSN_UNCOND_BRANCH_DELAY) 3143 mips_no_prev_insn (); 3144 } 3145 else if (pinfo & INSN_COND_BRANCH_LIKELY) 3146 { 3147 /* We don't yet optimize a branch likely. What we should do 3148 is look at the target, copy the instruction found there 3149 into the delay slot, and increment the branch to jump to 3150 the next instruction. */ 3151 insert_into_history (0, 1, ip); 3152 emit_nop (); 3153 } 3154 else 3155 insert_into_history (0, 1, ip); 3156 } 3157 else 3158 insert_into_history (0, 1, ip); 3159 3160 /* We just output an insn, so the next one doesn't have a label. */ 3161 mips_clear_insn_labels (); 3162} 3163 3164/* Forget that there was any previous instruction or label. */ 3165 3166static void 3167mips_no_prev_insn (void) 3168{ 3169 prev_nop_frag = NULL; 3170 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); 3171 mips_clear_insn_labels (); 3172} 3173 3174/* This function must be called before we emit something other than 3175 instructions. It is like mips_no_prev_insn except that it inserts 3176 any NOPS that might be needed by previous instructions. */ 3177 3178void 3179mips_emit_delays (void) 3180{ 3181 if (! mips_opts.noreorder) 3182 { 3183 int nops = nops_for_insn (history, NULL); 3184 if (nops > 0) 3185 { 3186 while (nops-- > 0) 3187 add_fixed_insn (NOP_INSN); 3188 mips_move_labels (); 3189 } 3190 } 3191 mips_no_prev_insn (); 3192} 3193 3194/* Start a (possibly nested) noreorder block. */ 3195 3196static void 3197start_noreorder (void) 3198{ 3199 if (mips_opts.noreorder == 0) 3200 { 3201 unsigned int i; 3202 int nops; 3203 3204 /* None of the instructions before the .set noreorder can be moved. */ 3205 for (i = 0; i < ARRAY_SIZE (history); i++) 3206 history[i].fixed_p = 1; 3207 3208 /* Insert any nops that might be needed between the .set noreorder 3209 block and the previous instructions. We will later remove any 3210 nops that turn out not to be needed. */ 3211 nops = nops_for_insn (history, NULL); 3212 if (nops > 0) 3213 { 3214 if (mips_optimize != 0) 3215 { 3216 /* Record the frag which holds the nop instructions, so 3217 that we can remove them if we don't need them. */ 3218 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); 3219 prev_nop_frag = frag_now; 3220 prev_nop_frag_holds = nops; 3221 prev_nop_frag_required = 0; 3222 prev_nop_frag_since = 0; 3223 } 3224 3225 for (; nops > 0; --nops) 3226 add_fixed_insn (NOP_INSN); 3227 3228 /* Move on to a new frag, so that it is safe to simply 3229 decrease the size of prev_nop_frag. */ 3230 frag_wane (frag_now); 3231 frag_new (0); 3232 mips_move_labels (); 3233 } 3234 mips16_mark_labels (); 3235 mips_clear_insn_labels (); 3236 } 3237 mips_opts.noreorder++; 3238 mips_any_noreorder = 1; 3239} 3240 3241/* End a nested noreorder block. */ 3242 3243static void 3244end_noreorder (void) 3245{ 3246 mips_opts.noreorder--; 3247 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) 3248 { 3249 /* Commit to inserting prev_nop_frag_required nops and go back to 3250 handling nop insertion the .set reorder way. */ 3251 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) 3252 * (mips_opts.mips16 ? 2 : 4)); 3253 insert_into_history (prev_nop_frag_since, 3254 prev_nop_frag_required, NOP_INSN); 3255 prev_nop_frag = NULL; 3256 } 3257} 3258 3259/* Set up global variables for the start of a new macro. */ 3260 3261static void 3262macro_start (void) 3263{ 3264 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); 3265 mips_macro_warning.delay_slot_p = (mips_opts.noreorder 3266 && (history[0].insn_mo->pinfo 3267 & (INSN_UNCOND_BRANCH_DELAY 3268 | INSN_COND_BRANCH_DELAY 3269 | INSN_COND_BRANCH_LIKELY)) != 0); 3270} 3271 3272/* Given that a macro is longer than 4 bytes, return the appropriate warning 3273 for it. Return null if no warning is needed. SUBTYPE is a bitmask of 3274 RELAX_DELAY_SLOT and RELAX_NOMACRO. */ 3275 3276static const char * 3277macro_warning (relax_substateT subtype) 3278{ 3279 if (subtype & RELAX_DELAY_SLOT) 3280 return _("Macro instruction expanded into multiple instructions" 3281 " in a branch delay slot"); 3282 else if (subtype & RELAX_NOMACRO) 3283 return _("Macro instruction expanded into multiple instructions"); 3284 else 3285 return 0; 3286} 3287 3288/* Finish up a macro. Emit warnings as appropriate. */ 3289 3290static void 3291macro_end (void) 3292{ 3293 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) 3294 { 3295 relax_substateT subtype; 3296 3297 /* Set up the relaxation warning flags. */ 3298 subtype = 0; 3299 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) 3300 subtype |= RELAX_SECOND_LONGER; 3301 if (mips_opts.warn_about_macros) 3302 subtype |= RELAX_NOMACRO; 3303 if (mips_macro_warning.delay_slot_p) 3304 subtype |= RELAX_DELAY_SLOT; 3305 3306 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) 3307 { 3308 /* Either the macro has a single implementation or both 3309 implementations are longer than 4 bytes. Emit the 3310 warning now. */ 3311 const char *msg = macro_warning (subtype); 3312 if (msg != 0) 3313 as_warn (msg); 3314 } 3315 else 3316 { 3317 /* One implementation might need a warning but the other 3318 definitely doesn't. */ 3319 mips_macro_warning.first_frag->fr_subtype |= subtype; 3320 } 3321 } 3322} 3323 3324/* Read a macro's relocation codes from *ARGS and store them in *R. 3325 The first argument in *ARGS will be either the code for a single 3326 relocation or -1 followed by the three codes that make up a 3327 composite relocation. */ 3328 3329static void 3330macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) 3331{ 3332 int i, next; 3333 3334 next = va_arg (*args, int); 3335 if (next >= 0) 3336 r[0] = (bfd_reloc_code_real_type) next; 3337 else 3338 for (i = 0; i < 3; i++) 3339 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); 3340} 3341 3342/* Build an instruction created by a macro expansion. This is passed 3343 a pointer to the count of instructions created so far, an 3344 expression, the name of the instruction to build, an operand format 3345 string, and corresponding arguments. */ 3346 3347static void 3348macro_build (expressionS *ep, const char *name, const char *fmt, ...) 3349{ 3350 const struct mips_opcode *mo; 3351 struct mips_cl_insn insn; 3352 bfd_reloc_code_real_type r[3]; 3353 va_list args; 3354 3355 va_start (args, fmt); 3356 3357 if (mips_opts.mips16) 3358 { 3359 mips16_macro_build (ep, name, fmt, args); 3360 va_end (args); 3361 return; 3362 } 3363 3364 r[0] = BFD_RELOC_UNUSED; 3365 r[1] = BFD_RELOC_UNUSED; 3366 r[2] = BFD_RELOC_UNUSED; 3367 mo = (struct mips_opcode *) hash_find (op_hash, name); 3368 assert (mo); 3369 assert (strcmp (name, mo->name) == 0); 3370 3371 while (1) 3372 { 3373 /* Search until we get a match for NAME. It is assumed here that 3374 macros will never generate MDMX, MIPS-3D, or MT instructions. */ 3375 if (strcmp (fmt, mo->args) == 0 3376 && mo->pinfo != INSN_MACRO 3377 && OPCODE_IS_MEMBER (mo, 3378 (mips_opts.isa 3379 | (mips_opts.mips16 ? INSN_MIPS16 : 0) 3380 | (mips_opts.ase_dsp ? INSN_DSP : 0) 3381 | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) 3382 ? INSN_DSP64 : 0) 3383 | (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0) 3384 | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)), 3385 mips_opts.arch) 3386 && (mips_opts.arch != CPU_R4650 || (mo->pinfo & FP_D) == 0)) 3387 break; 3388 3389 ++mo; 3390 assert (mo->name); 3391 assert (strcmp (name, mo->name) == 0); 3392 } 3393 3394 create_insn (&insn, mo); 3395 for (;;) 3396 { 3397 switch (*fmt++) 3398 { 3399 case '\0': 3400 break; 3401 3402 case ',': 3403 case '(': 3404 case ')': 3405 continue; 3406 3407 case '+': 3408 switch (*fmt++) 3409 { 3410 case 'A': 3411 case 'E': 3412 INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); 3413 continue; 3414 3415 case 'B': 3416 case 'F': 3417 /* Note that in the macro case, these arguments are already 3418 in MSB form. (When handling the instruction in the 3419 non-macro case, these arguments are sizes from which 3420 MSB values must be calculated.) */ 3421 INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); 3422 continue; 3423 3424 case 'C': 3425 case 'G': 3426 case 'H': 3427 /* Note that in the macro case, these arguments are already 3428 in MSBD form. (When handling the instruction in the 3429 non-macro case, these arguments are sizes from which 3430 MSBD values must be calculated.) */ 3431 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); 3432 continue; 3433 3434 default: 3435 internalError (); 3436 } 3437 continue; 3438 3439 case '2': 3440 INSERT_OPERAND (BP, insn, va_arg (args, int)); 3441 continue; 3442 3443 case 't': 3444 case 'w': 3445 case 'E': 3446 INSERT_OPERAND (RT, insn, va_arg (args, int)); 3447 continue; 3448 3449 case 'c': 3450 INSERT_OPERAND (CODE, insn, va_arg (args, int)); 3451 continue; 3452 3453 case 'T': 3454 case 'W': 3455 INSERT_OPERAND (FT, insn, va_arg (args, int)); 3456 continue; 3457 3458 case 'd': 3459 case 'G': 3460 case 'K': 3461 INSERT_OPERAND (RD, insn, va_arg (args, int)); 3462 continue; 3463 3464 case 'U': 3465 { 3466 int tmp = va_arg (args, int); 3467 3468 INSERT_OPERAND (RT, insn, tmp); 3469 INSERT_OPERAND (RD, insn, tmp); 3470 continue; 3471 } 3472 3473 case 'V': 3474 case 'S': 3475 INSERT_OPERAND (FS, insn, va_arg (args, int)); 3476 continue; 3477 3478 case 'z': 3479 continue; 3480 3481 case '<': 3482 INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); 3483 continue; 3484 3485 case 'D': 3486 INSERT_OPERAND (FD, insn, va_arg (args, int)); 3487 continue; 3488 3489 case 'B': 3490 INSERT_OPERAND (CODE20, insn, va_arg (args, int)); 3491 continue; 3492 3493 case 'J': 3494 INSERT_OPERAND (CODE19, insn, va_arg (args, int)); 3495 continue; 3496 3497 case 'q': 3498 INSERT_OPERAND (CODE2, insn, va_arg (args, int)); 3499 continue; 3500 3501 case 'b': 3502 case 's': 3503 case 'r': 3504 case 'v': 3505 INSERT_OPERAND (RS, insn, va_arg (args, int)); 3506 continue; 3507 3508 case 'i': 3509 case 'j': 3510 case 'o': 3511 macro_read_relocs (&args, r); 3512 assert (*r == BFD_RELOC_GPREL16 3513 || *r == BFD_RELOC_MIPS_LITERAL 3514 || *r == BFD_RELOC_MIPS_HIGHER 3515 || *r == BFD_RELOC_HI16_S 3516 || *r == BFD_RELOC_LO16 3517 || *r == BFD_RELOC_MIPS_GOT16 3518 || *r == BFD_RELOC_MIPS_CALL16 3519 || *r == BFD_RELOC_MIPS_GOT_DISP 3520 || *r == BFD_RELOC_MIPS_GOT_PAGE 3521 || *r == BFD_RELOC_MIPS_GOT_OFST 3522 || *r == BFD_RELOC_MIPS_GOT_LO16 3523 || *r == BFD_RELOC_MIPS_CALL_LO16); 3524 continue; 3525 3526 case 'u': 3527 macro_read_relocs (&args, r); 3528 assert (ep != NULL 3529 && (ep->X_op == O_constant 3530 || (ep->X_op == O_symbol 3531 && (*r == BFD_RELOC_MIPS_HIGHEST 3532 || *r == BFD_RELOC_HI16_S 3533 || *r == BFD_RELOC_HI16 3534 || *r == BFD_RELOC_GPREL16 3535 || *r == BFD_RELOC_MIPS_GOT_HI16 3536 || *r == BFD_RELOC_MIPS_CALL_HI16)))); 3537 continue; 3538 3539 case 'p': 3540 assert (ep != NULL); 3541 3542 /* 3543 * This allows macro() to pass an immediate expression for 3544 * creating short branches without creating a symbol. 3545 * 3546 * We don't allow branch relaxation for these branches, as 3547 * they should only appear in ".set nomacro" anyway. 3548 */ 3549 if (ep->X_op == O_constant) 3550 { 3551 if ((ep->X_add_number & 3) != 0) 3552 as_bad (_("branch to misaligned address (0x%lx)"), 3553 (unsigned long) ep->X_add_number); 3554 if ((ep->X_add_number + 0x20000) & ~0x3ffff) 3555 as_bad (_("branch address range overflow (0x%lx)"), 3556 (unsigned long) ep->X_add_number); 3557 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; 3558 ep = NULL; 3559 } 3560 else 3561 *r = BFD_RELOC_16_PCREL_S2; 3562 continue; 3563 3564 case 'a': 3565 assert (ep != NULL); 3566 *r = BFD_RELOC_MIPS_JMP; 3567 continue; 3568 3569 case 'C': 3570 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long)); 3571 continue; 3572 3573 case 'k': 3574 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long)); 3575 continue; 3576 3577 default: 3578 internalError (); 3579 } 3580 break; 3581 } 3582 va_end (args); 3583 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); 3584 3585 append_insn (&insn, ep, r); 3586} 3587 3588static void 3589mips16_macro_build (expressionS *ep, const char *name, const char *fmt, 3590 va_list args) 3591{ 3592 struct mips_opcode *mo; 3593 struct mips_cl_insn insn; 3594 bfd_reloc_code_real_type r[3] 3595 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 3596 3597 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); 3598 assert (mo); 3599 assert (strcmp (name, mo->name) == 0); 3600 3601 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) 3602 { 3603 ++mo; 3604 assert (mo->name); 3605 assert (strcmp (name, mo->name) == 0); 3606 } 3607 3608 create_insn (&insn, mo); 3609 for (;;) 3610 { 3611 int c; 3612 3613 c = *fmt++; 3614 switch (c) 3615 { 3616 case '\0': 3617 break; 3618 3619 case ',': 3620 case '(': 3621 case ')': 3622 continue; 3623 3624 case 'y': 3625 case 'w': 3626 MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int)); 3627 continue; 3628 3629 case 'x': 3630 case 'v': 3631 MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int)); 3632 continue; 3633 3634 case 'z': 3635 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int)); 3636 continue; 3637 3638 case 'Z': 3639 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int)); 3640 continue; 3641 3642 case '0': 3643 case 'S': 3644 case 'P': 3645 case 'R': 3646 continue; 3647 3648 case 'X': 3649 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int)); 3650 continue; 3651 3652 case 'Y': 3653 { 3654 int regno; 3655 3656 regno = va_arg (args, int); 3657 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); 3658 MIPS16_INSERT_OPERAND (REG32R, insn, regno); 3659 } 3660 continue; 3661 3662 case '<': 3663 case '>': 3664 case '4': 3665 case '5': 3666 case 'H': 3667 case 'W': 3668 case 'D': 3669 case 'j': 3670 case '8': 3671 case 'V': 3672 case 'C': 3673 case 'U': 3674 case 'k': 3675 case 'K': 3676 case 'p': 3677 case 'q': 3678 { 3679 assert (ep != NULL); 3680 3681 if (ep->X_op != O_constant) 3682 *r = (int) BFD_RELOC_UNUSED + c; 3683 else 3684 { 3685 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, 3686 FALSE, &insn.insn_opcode, &insn.use_extend, 3687 &insn.extend); 3688 ep = NULL; 3689 *r = BFD_RELOC_UNUSED; 3690 } 3691 } 3692 continue; 3693 3694 case '6': 3695 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int)); 3696 continue; 3697 } 3698 3699 break; 3700 } 3701 3702 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); 3703 3704 append_insn (&insn, ep, r); 3705} 3706 3707/* 3708 * Sign-extend 32-bit mode constants that have bit 31 set and all 3709 * higher bits unset. 3710 */ 3711static void 3712normalize_constant_expr (expressionS *ex) 3713{ 3714 if (ex->X_op == O_constant 3715 && IS_ZEXT_32BIT_NUM (ex->X_add_number)) 3716 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) 3717 - 0x80000000); 3718} 3719 3720/* 3721 * Sign-extend 32-bit mode address offsets that have bit 31 set and 3722 * all higher bits unset. 3723 */ 3724static void 3725normalize_address_expr (expressionS *ex) 3726{ 3727 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) 3728 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) 3729 && IS_ZEXT_32BIT_NUM (ex->X_add_number)) 3730 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) 3731 - 0x80000000); 3732} 3733 3734/* 3735 * Generate a "jalr" instruction with a relocation hint to the called 3736 * function. This occurs in NewABI PIC code. 3737 */ 3738static void 3739macro_build_jalr (expressionS *ep) 3740{ 3741 char *f = NULL; 3742 3743 if (HAVE_NEWABI) 3744 { 3745 frag_grow (8); 3746 f = frag_more (0); 3747 } 3748 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); 3749 if (HAVE_NEWABI) 3750 fix_new_exp (frag_now, f - frag_now->fr_literal, 3751 4, ep, FALSE, BFD_RELOC_MIPS_JALR); 3752} 3753 3754/* 3755 * Generate a "lui" instruction. 3756 */ 3757static void 3758macro_build_lui (expressionS *ep, int regnum) 3759{ 3760 expressionS high_expr; 3761 const struct mips_opcode *mo; 3762 struct mips_cl_insn insn; 3763 bfd_reloc_code_real_type r[3] 3764 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 3765 const char *name = "lui"; 3766 const char *fmt = "t,u"; 3767 3768 assert (! mips_opts.mips16); 3769 3770 high_expr = *ep; 3771 3772 if (high_expr.X_op == O_constant) 3773 { 3774 /* We can compute the instruction now without a relocation entry. */ 3775 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) 3776 >> 16) & 0xffff; 3777 *r = BFD_RELOC_UNUSED; 3778 } 3779 else 3780 { 3781 assert (ep->X_op == O_symbol); 3782 /* _gp_disp is a special case, used from s_cpload. 3783 __gnu_local_gp is used if mips_no_shared. */ 3784 assert (mips_pic == NO_PIC 3785 || (! HAVE_NEWABI 3786 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) 3787 || (! mips_in_shared 3788 && strcmp (S_GET_NAME (ep->X_add_symbol), 3789 "__gnu_local_gp") == 0)); 3790 *r = BFD_RELOC_HI16_S; 3791 } 3792 3793 mo = hash_find (op_hash, name); 3794 assert (strcmp (name, mo->name) == 0); 3795 assert (strcmp (fmt, mo->args) == 0); 3796 create_insn (&insn, mo); 3797 3798 insn.insn_opcode = insn.insn_mo->match; 3799 INSERT_OPERAND (RT, insn, regnum); 3800 if (*r == BFD_RELOC_UNUSED) 3801 { 3802 insn.insn_opcode |= high_expr.X_add_number; 3803 append_insn (&insn, NULL, r); 3804 } 3805 else 3806 append_insn (&insn, &high_expr, r); 3807} 3808 3809/* Generate a sequence of instructions to do a load or store from a constant 3810 offset off of a base register (breg) into/from a target register (treg), 3811 using AT if necessary. */ 3812static void 3813macro_build_ldst_constoffset (expressionS *ep, const char *op, 3814 int treg, int breg, int dbl) 3815{ 3816 assert (ep->X_op == O_constant); 3817 3818 /* Sign-extending 32-bit constants makes their handling easier. */ 3819 if (!dbl) 3820 normalize_constant_expr (ep); 3821 3822 /* Right now, this routine can only handle signed 32-bit constants. */ 3823 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) 3824 as_warn (_("operand overflow")); 3825 3826 if (IS_SEXT_16BIT_NUM(ep->X_add_number)) 3827 { 3828 /* Signed 16-bit offset will fit in the op. Easy! */ 3829 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); 3830 } 3831 else 3832 { 3833 /* 32-bit offset, need multiple instructions and AT, like: 3834 lui $tempreg,const_hi (BFD_RELOC_HI16_S) 3835 addu $tempreg,$tempreg,$breg 3836 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) 3837 to handle the complete offset. */ 3838 macro_build_lui (ep, AT); 3839 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); 3840 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); 3841 3842 if (mips_opts.noat) 3843 as_bad (_("Macro used $at after \".set noat\"")); 3844 } 3845} 3846 3847/* set_at() 3848 * Generates code to set the $at register to true (one) 3849 * if reg is less than the immediate expression. 3850 */ 3851static void 3852set_at (int reg, int unsignedp) 3853{ 3854 if (imm_expr.X_op == O_constant 3855 && imm_expr.X_add_number >= -0x8000 3856 && imm_expr.X_add_number < 0x8000) 3857 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", 3858 AT, reg, BFD_RELOC_LO16); 3859 else 3860 { 3861 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 3862 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); 3863 } 3864} 3865 3866/* Warn if an expression is not a constant. */ 3867 3868static void 3869check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) 3870{ 3871 if (ex->X_op == O_big) 3872 as_bad (_("unsupported large constant")); 3873 else if (ex->X_op != O_constant) 3874 as_bad (_("Instruction %s requires absolute expression"), 3875 ip->insn_mo->name); 3876 3877 if (HAVE_32BIT_GPRS) 3878 normalize_constant_expr (ex); 3879} 3880 3881/* Count the leading zeroes by performing a binary chop. This is a 3882 bulky bit of source, but performance is a LOT better for the 3883 majority of values than a simple loop to count the bits: 3884 for (lcnt = 0; (lcnt < 32); lcnt++) 3885 if ((v) & (1 << (31 - lcnt))) 3886 break; 3887 However it is not code size friendly, and the gain will drop a bit 3888 on certain cached systems. 3889*/ 3890#define COUNT_TOP_ZEROES(v) \ 3891 (((v) & ~0xffff) == 0 \ 3892 ? ((v) & ~0xff) == 0 \ 3893 ? ((v) & ~0xf) == 0 \ 3894 ? ((v) & ~0x3) == 0 \ 3895 ? ((v) & ~0x1) == 0 \ 3896 ? !(v) \ 3897 ? 32 \ 3898 : 31 \ 3899 : 30 \ 3900 : ((v) & ~0x7) == 0 \ 3901 ? 29 \ 3902 : 28 \ 3903 : ((v) & ~0x3f) == 0 \ 3904 ? ((v) & ~0x1f) == 0 \ 3905 ? 27 \ 3906 : 26 \ 3907 : ((v) & ~0x7f) == 0 \ 3908 ? 25 \ 3909 : 24 \ 3910 : ((v) & ~0xfff) == 0 \ 3911 ? ((v) & ~0x3ff) == 0 \ 3912 ? ((v) & ~0x1ff) == 0 \ 3913 ? 23 \ 3914 : 22 \ 3915 : ((v) & ~0x7ff) == 0 \ 3916 ? 21 \ 3917 : 20 \ 3918 : ((v) & ~0x3fff) == 0 \ 3919 ? ((v) & ~0x1fff) == 0 \ 3920 ? 19 \ 3921 : 18 \ 3922 : ((v) & ~0x7fff) == 0 \ 3923 ? 17 \ 3924 : 16 \ 3925 : ((v) & ~0xffffff) == 0 \ 3926 ? ((v) & ~0xfffff) == 0 \ 3927 ? ((v) & ~0x3ffff) == 0 \ 3928 ? ((v) & ~0x1ffff) == 0 \ 3929 ? 15 \ 3930 : 14 \ 3931 : ((v) & ~0x7ffff) == 0 \ 3932 ? 13 \ 3933 : 12 \ 3934 : ((v) & ~0x3fffff) == 0 \ 3935 ? ((v) & ~0x1fffff) == 0 \ 3936 ? 11 \ 3937 : 10 \ 3938 : ((v) & ~0x7fffff) == 0 \ 3939 ? 9 \ 3940 : 8 \ 3941 : ((v) & ~0xfffffff) == 0 \ 3942 ? ((v) & ~0x3ffffff) == 0 \ 3943 ? ((v) & ~0x1ffffff) == 0 \ 3944 ? 7 \ 3945 : 6 \ 3946 : ((v) & ~0x7ffffff) == 0 \ 3947 ? 5 \ 3948 : 4 \ 3949 : ((v) & ~0x3fffffff) == 0 \ 3950 ? ((v) & ~0x1fffffff) == 0 \ 3951 ? 3 \ 3952 : 2 \ 3953 : ((v) & ~0x7fffffff) == 0 \ 3954 ? 1 \ 3955 : 0) 3956 3957/* load_register() 3958 * This routine generates the least number of instructions necessary to load 3959 * an absolute expression value into a register. 3960 */ 3961static void 3962load_register (int reg, expressionS *ep, int dbl) 3963{ 3964 int freg; 3965 expressionS hi32, lo32; 3966 3967 if (ep->X_op != O_big) 3968 { 3969 assert (ep->X_op == O_constant); 3970 3971 /* Sign-extending 32-bit constants makes their handling easier. */ 3972 if (!dbl) 3973 normalize_constant_expr (ep); 3974 3975 if (IS_SEXT_16BIT_NUM (ep->X_add_number)) 3976 { 3977 /* We can handle 16 bit signed values with an addiu to 3978 $zero. No need to ever use daddiu here, since $zero and 3979 the result are always correct in 32 bit mode. */ 3980 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 3981 return; 3982 } 3983 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) 3984 { 3985 /* We can handle 16 bit unsigned values with an ori to 3986 $zero. */ 3987 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); 3988 return; 3989 } 3990 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) 3991 { 3992 /* 32 bit values require an lui. */ 3993 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); 3994 if ((ep->X_add_number & 0xffff) != 0) 3995 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); 3996 return; 3997 } 3998 } 3999 4000 /* The value is larger than 32 bits. */ 4001 4002 if (!dbl || HAVE_32BIT_GPRS) 4003 { 4004 char value[32]; 4005 4006 sprintf_vma (value, ep->X_add_number); 4007 as_bad (_("Number (0x%s) larger than 32 bits"), value); 4008 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 4009 return; 4010 } 4011 4012 if (ep->X_op != O_big) 4013 { 4014 hi32 = *ep; 4015 hi32.X_add_number = (valueT) hi32.X_add_number >> 16; 4016 hi32.X_add_number = (valueT) hi32.X_add_number >> 16; 4017 hi32.X_add_number &= 0xffffffff; 4018 lo32 = *ep; 4019 lo32.X_add_number &= 0xffffffff; 4020 } 4021 else 4022 { 4023 assert (ep->X_add_number > 2); 4024 if (ep->X_add_number == 3) 4025 generic_bignum[3] = 0; 4026 else if (ep->X_add_number > 4) 4027 as_bad (_("Number larger than 64 bits")); 4028 lo32.X_op = O_constant; 4029 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); 4030 hi32.X_op = O_constant; 4031 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); 4032 } 4033 4034 if (hi32.X_add_number == 0) 4035 freg = 0; 4036 else 4037 { 4038 int shift, bit; 4039 unsigned long hi, lo; 4040 4041 if (hi32.X_add_number == (offsetT) 0xffffffff) 4042 { 4043 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) 4044 { 4045 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 4046 return; 4047 } 4048 if (lo32.X_add_number & 0x80000000) 4049 { 4050 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); 4051 if (lo32.X_add_number & 0xffff) 4052 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); 4053 return; 4054 } 4055 } 4056 4057 /* Check for 16bit shifted constant. We know that hi32 is 4058 non-zero, so start the mask on the first bit of the hi32 4059 value. */ 4060 shift = 17; 4061 do 4062 { 4063 unsigned long himask, lomask; 4064 4065 if (shift < 32) 4066 { 4067 himask = 0xffff >> (32 - shift); 4068 lomask = (0xffff << shift) & 0xffffffff; 4069 } 4070 else 4071 { 4072 himask = 0xffff << (shift - 32); 4073 lomask = 0; 4074 } 4075 if ((hi32.X_add_number & ~(offsetT) himask) == 0 4076 && (lo32.X_add_number & ~(offsetT) lomask) == 0) 4077 { 4078 expressionS tmp; 4079 4080 tmp.X_op = O_constant; 4081 if (shift < 32) 4082 tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) 4083 | (lo32.X_add_number >> shift)); 4084 else 4085 tmp.X_add_number = hi32.X_add_number >> (shift - 32); 4086 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); 4087 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", 4088 reg, reg, (shift >= 32) ? shift - 32 : shift); 4089 return; 4090 } 4091 ++shift; 4092 } 4093 while (shift <= (64 - 16)); 4094 4095 /* Find the bit number of the lowest one bit, and store the 4096 shifted value in hi/lo. */ 4097 hi = (unsigned long) (hi32.X_add_number & 0xffffffff); 4098 lo = (unsigned long) (lo32.X_add_number & 0xffffffff); 4099 if (lo != 0) 4100 { 4101 bit = 0; 4102 while ((lo & 1) == 0) 4103 { 4104 lo >>= 1; 4105 ++bit; 4106 } 4107 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); 4108 hi >>= bit; 4109 } 4110 else 4111 { 4112 bit = 32; 4113 while ((hi & 1) == 0) 4114 { 4115 hi >>= 1; 4116 ++bit; 4117 } 4118 lo = hi; 4119 hi = 0; 4120 } 4121 4122 /* Optimize if the shifted value is a (power of 2) - 1. */ 4123 if ((hi == 0 && ((lo + 1) & lo) == 0) 4124 || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) 4125 { 4126 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); 4127 if (shift != 0) 4128 { 4129 expressionS tmp; 4130 4131 /* This instruction will set the register to be all 4132 ones. */ 4133 tmp.X_op = O_constant; 4134 tmp.X_add_number = (offsetT) -1; 4135 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 4136 if (bit != 0) 4137 { 4138 bit += shift; 4139 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", 4140 reg, reg, (bit >= 32) ? bit - 32 : bit); 4141 } 4142 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", 4143 reg, reg, (shift >= 32) ? shift - 32 : shift); 4144 return; 4145 } 4146 } 4147 4148 /* Sign extend hi32 before calling load_register, because we can 4149 generally get better code when we load a sign extended value. */ 4150 if ((hi32.X_add_number & 0x80000000) != 0) 4151 hi32.X_add_number |= ~(offsetT) 0xffffffff; 4152 load_register (reg, &hi32, 0); 4153 freg = reg; 4154 } 4155 if ((lo32.X_add_number & 0xffff0000) == 0) 4156 { 4157 if (freg != 0) 4158 { 4159 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); 4160 freg = reg; 4161 } 4162 } 4163 else 4164 { 4165 expressionS mid16; 4166 4167 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) 4168 { 4169 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); 4170 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); 4171 return; 4172 } 4173 4174 if (freg != 0) 4175 { 4176 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); 4177 freg = reg; 4178 } 4179 mid16 = lo32; 4180 mid16.X_add_number >>= 16; 4181 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); 4182 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); 4183 freg = reg; 4184 } 4185 if ((lo32.X_add_number & 0xffff) != 0) 4186 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); 4187} 4188 4189static inline void 4190load_delay_nop (void) 4191{ 4192 if (!gpr_interlocks) 4193 macro_build (NULL, "nop", ""); 4194} 4195 4196/* Load an address into a register. */ 4197 4198static void 4199load_address (int reg, expressionS *ep, int *used_at) 4200{ 4201 if (ep->X_op != O_constant 4202 && ep->X_op != O_symbol) 4203 { 4204 as_bad (_("expression too complex")); 4205 ep->X_op = O_constant; 4206 } 4207 4208 if (ep->X_op == O_constant) 4209 { 4210 load_register (reg, ep, HAVE_64BIT_ADDRESSES); 4211 return; 4212 } 4213 4214 if (mips_pic == NO_PIC) 4215 { 4216 /* If this is a reference to a GP relative symbol, we want 4217 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) 4218 Otherwise we want 4219 lui $reg,<sym> (BFD_RELOC_HI16_S) 4220 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 4221 If we have an addend, we always use the latter form. 4222 4223 With 64bit address space and a usable $at we want 4224 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) 4225 lui $at,<sym> (BFD_RELOC_HI16_S) 4226 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) 4227 daddiu $at,<sym> (BFD_RELOC_LO16) 4228 dsll32 $reg,0 4229 daddu $reg,$reg,$at 4230 4231 If $at is already in use, we use a path which is suboptimal 4232 on superscalar processors. 4233 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) 4234 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) 4235 dsll $reg,16 4236 daddiu $reg,<sym> (BFD_RELOC_HI16_S) 4237 dsll $reg,16 4238 daddiu $reg,<sym> (BFD_RELOC_LO16) 4239 4240 For GP relative symbols in 64bit address space we can use 4241 the same sequence as in 32bit address space. */ 4242 if (HAVE_64BIT_SYMBOLS) 4243 { 4244 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET 4245 && !nopic_need_relax (ep->X_add_symbol, 1)) 4246 { 4247 relax_start (ep->X_add_symbol); 4248 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, 4249 mips_gp_register, BFD_RELOC_GPREL16); 4250 relax_switch (); 4251 } 4252 4253 if (*used_at == 0 && !mips_opts.noat) 4254 { 4255 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); 4256 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); 4257 macro_build (ep, "daddiu", "t,r,j", reg, reg, 4258 BFD_RELOC_MIPS_HIGHER); 4259 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); 4260 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); 4261 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); 4262 *used_at = 1; 4263 } 4264 else 4265 { 4266 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); 4267 macro_build (ep, "daddiu", "t,r,j", reg, reg, 4268 BFD_RELOC_MIPS_HIGHER); 4269 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); 4270 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); 4271 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); 4272 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); 4273 } 4274 4275 if (mips_relax.sequence) 4276 relax_end (); 4277 } 4278 else 4279 { 4280 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET 4281 && !nopic_need_relax (ep->X_add_symbol, 1)) 4282 { 4283 relax_start (ep->X_add_symbol); 4284 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, 4285 mips_gp_register, BFD_RELOC_GPREL16); 4286 relax_switch (); 4287 } 4288 macro_build_lui (ep, reg); 4289 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", 4290 reg, reg, BFD_RELOC_LO16); 4291 if (mips_relax.sequence) 4292 relax_end (); 4293 } 4294 } 4295 else if (!mips_big_got) 4296 { 4297 expressionS ex; 4298 4299 /* If this is a reference to an external symbol, we want 4300 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 4301 Otherwise we want 4302 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 4303 nop 4304 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 4305 If there is a constant, it must be added in after. 4306 4307 If we have NewABI, we want 4308 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) 4309 unless we're referencing a global symbol with a non-zero 4310 offset, in which case cst must be added separately. */ 4311 if (HAVE_NEWABI) 4312 { 4313 if (ep->X_add_number) 4314 { 4315 ex.X_add_number = ep->X_add_number; 4316 ep->X_add_number = 0; 4317 relax_start (ep->X_add_symbol); 4318 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 4319 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 4320 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 4321 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 4322 ex.X_op = O_constant; 4323 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", 4324 reg, reg, BFD_RELOC_LO16); 4325 ep->X_add_number = ex.X_add_number; 4326 relax_switch (); 4327 } 4328 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 4329 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 4330 if (mips_relax.sequence) 4331 relax_end (); 4332 } 4333 else 4334 { 4335 ex.X_add_number = ep->X_add_number; 4336 ep->X_add_number = 0; 4337 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 4338 BFD_RELOC_MIPS_GOT16, mips_gp_register); 4339 load_delay_nop (); 4340 relax_start (ep->X_add_symbol); 4341 relax_switch (); 4342 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 4343 BFD_RELOC_LO16); 4344 relax_end (); 4345 4346 if (ex.X_add_number != 0) 4347 { 4348 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 4349 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 4350 ex.X_op = O_constant; 4351 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", 4352 reg, reg, BFD_RELOC_LO16); 4353 } 4354 } 4355 } 4356 else if (mips_big_got) 4357 { 4358 expressionS ex; 4359 4360 /* This is the large GOT case. If this is a reference to an 4361 external symbol, we want 4362 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 4363 addu $reg,$reg,$gp 4364 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) 4365 4366 Otherwise, for a reference to a local symbol in old ABI, we want 4367 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 4368 nop 4369 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 4370 If there is a constant, it must be added in after. 4371 4372 In the NewABI, for local symbols, with or without offsets, we want: 4373 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 4374 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) 4375 */ 4376 if (HAVE_NEWABI) 4377 { 4378 ex.X_add_number = ep->X_add_number; 4379 ep->X_add_number = 0; 4380 relax_start (ep->X_add_symbol); 4381 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); 4382 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 4383 reg, reg, mips_gp_register); 4384 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", 4385 reg, BFD_RELOC_MIPS_GOT_LO16, reg); 4386 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 4387 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 4388 else if (ex.X_add_number) 4389 { 4390 ex.X_op = O_constant; 4391 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 4392 BFD_RELOC_LO16); 4393 } 4394 4395 ep->X_add_number = ex.X_add_number; 4396 relax_switch (); 4397 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 4398 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 4399 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 4400 BFD_RELOC_MIPS_GOT_OFST); 4401 relax_end (); 4402 } 4403 else 4404 { 4405 ex.X_add_number = ep->X_add_number; 4406 ep->X_add_number = 0; 4407 relax_start (ep->X_add_symbol); 4408 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); 4409 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 4410 reg, reg, mips_gp_register); 4411 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", 4412 reg, BFD_RELOC_MIPS_GOT_LO16, reg); 4413 relax_switch (); 4414 if (reg_needs_delay (mips_gp_register)) 4415 { 4416 /* We need a nop before loading from $gp. This special 4417 check is required because the lui which starts the main 4418 instruction stream does not refer to $gp, and so will not 4419 insert the nop which may be required. */ 4420 macro_build (NULL, "nop", ""); 4421 } 4422 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 4423 BFD_RELOC_MIPS_GOT16, mips_gp_register); 4424 load_delay_nop (); 4425 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 4426 BFD_RELOC_LO16); 4427 relax_end (); 4428 4429 if (ex.X_add_number != 0) 4430 { 4431 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 4432 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 4433 ex.X_op = O_constant; 4434 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 4435 BFD_RELOC_LO16); 4436 } 4437 } 4438 } 4439 else 4440 abort (); 4441 4442 if (mips_opts.noat && *used_at == 1) 4443 as_bad (_("Macro used $at after \".set noat\"")); 4444} 4445 4446/* Move the contents of register SOURCE into register DEST. */ 4447 4448static void 4449move_register (int dest, int source) 4450{ 4451 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", 4452 dest, source, 0); 4453} 4454 4455/* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where 4456 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. 4457 The two alternatives are: 4458 4459 Global symbol Local sybmol 4460 ------------- ------------ 4461 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) 4462 ... ... 4463 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) 4464 4465 load_got_offset emits the first instruction and add_got_offset 4466 emits the second for a 16-bit offset or add_got_offset_hilo emits 4467 a sequence to add a 32-bit offset using a scratch register. */ 4468 4469static void 4470load_got_offset (int dest, expressionS *local) 4471{ 4472 expressionS global; 4473 4474 global = *local; 4475 global.X_add_number = 0; 4476 4477 relax_start (local->X_add_symbol); 4478 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, 4479 BFD_RELOC_MIPS_GOT16, mips_gp_register); 4480 relax_switch (); 4481 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, 4482 BFD_RELOC_MIPS_GOT16, mips_gp_register); 4483 relax_end (); 4484} 4485 4486static void 4487add_got_offset (int dest, expressionS *local) 4488{ 4489 expressionS global; 4490 4491 global.X_op = O_constant; 4492 global.X_op_symbol = NULL; 4493 global.X_add_symbol = NULL; 4494 global.X_add_number = local->X_add_number; 4495 4496 relax_start (local->X_add_symbol); 4497 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", 4498 dest, dest, BFD_RELOC_LO16); 4499 relax_switch (); 4500 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); 4501 relax_end (); 4502} 4503 4504static void 4505add_got_offset_hilo (int dest, expressionS *local, int tmp) 4506{ 4507 expressionS global; 4508 int hold_mips_optimize; 4509 4510 global.X_op = O_constant; 4511 global.X_op_symbol = NULL; 4512 global.X_add_symbol = NULL; 4513 global.X_add_number = local->X_add_number; 4514 4515 relax_start (local->X_add_symbol); 4516 load_register (tmp, &global, HAVE_64BIT_ADDRESSES); 4517 relax_switch (); 4518 /* Set mips_optimize around the lui instruction to avoid 4519 inserting an unnecessary nop after the lw. */ 4520 hold_mips_optimize = mips_optimize; 4521 mips_optimize = 2; 4522 macro_build_lui (&global, tmp); 4523 mips_optimize = hold_mips_optimize; 4524 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); 4525 relax_end (); 4526 4527 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); 4528} 4529 4530/* 4531 * Build macros 4532 * This routine implements the seemingly endless macro or synthesized 4533 * instructions and addressing modes in the mips assembly language. Many 4534 * of these macros are simple and are similar to each other. These could 4535 * probably be handled by some kind of table or grammar approach instead of 4536 * this verbose method. Others are not simple macros but are more like 4537 * optimizing code generation. 4538 * One interesting optimization is when several store macros appear 4539 * consecutively that would load AT with the upper half of the same address. 4540 * The ensuing load upper instructions are ommited. This implies some kind 4541 * of global optimization. We currently only optimize within a single macro. 4542 * For many of the load and store macros if the address is specified as a 4543 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we 4544 * first load register 'at' with zero and use it as the base register. The 4545 * mips assembler simply uses register $zero. Just one tiny optimization 4546 * we're missing. 4547 */ 4548static void 4549macro (struct mips_cl_insn *ip) 4550{ 4551 int treg, sreg, dreg, breg; 4552 int tempreg; 4553 int mask; 4554 int used_at = 0; 4555 expressionS expr1; 4556 const char *s; 4557 const char *s2; 4558 const char *fmt; 4559 int likely = 0; 4560 int dbl = 0; 4561 int coproc = 0; 4562 int lr = 0; 4563 int imm = 0; 4564 int call = 0; 4565 int off; 4566 offsetT maxnum; 4567 bfd_reloc_code_real_type r; 4568 int hold_mips_optimize; 4569 4570 assert (! mips_opts.mips16); 4571 4572 treg = (ip->insn_opcode >> 16) & 0x1f; 4573 dreg = (ip->insn_opcode >> 11) & 0x1f; 4574 sreg = breg = (ip->insn_opcode >> 21) & 0x1f; 4575 mask = ip->insn_mo->mask; 4576 4577 expr1.X_op = O_constant; 4578 expr1.X_op_symbol = NULL; 4579 expr1.X_add_symbol = NULL; 4580 expr1.X_add_number = 1; 4581 4582 switch (mask) 4583 { 4584 case M_DABS: 4585 dbl = 1; 4586 case M_ABS: 4587 /* bgez $a0,.+12 4588 move v0,$a0 4589 sub v0,$zero,$a0 4590 */ 4591 4592 start_noreorder (); 4593 4594 expr1.X_add_number = 8; 4595 macro_build (&expr1, "bgez", "s,p", sreg); 4596 if (dreg == sreg) 4597 macro_build (NULL, "nop", "", 0); 4598 else 4599 move_register (dreg, sreg); 4600 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); 4601 4602 end_noreorder (); 4603 break; 4604 4605 case M_ADD_I: 4606 s = "addi"; 4607 s2 = "add"; 4608 goto do_addi; 4609 case M_ADDU_I: 4610 s = "addiu"; 4611 s2 = "addu"; 4612 goto do_addi; 4613 case M_DADD_I: 4614 dbl = 1; 4615 s = "daddi"; 4616 s2 = "dadd"; 4617 goto do_addi; 4618 case M_DADDU_I: 4619 dbl = 1; 4620 s = "daddiu"; 4621 s2 = "daddu"; 4622 do_addi: 4623 if (imm_expr.X_op == O_constant 4624 && imm_expr.X_add_number >= -0x8000 4625 && imm_expr.X_add_number < 0x8000) 4626 { 4627 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); 4628 break; 4629 } 4630 used_at = 1; 4631 load_register (AT, &imm_expr, dbl); 4632 macro_build (NULL, s2, "d,v,t", treg, sreg, AT); 4633 break; 4634 4635 case M_AND_I: 4636 s = "andi"; 4637 s2 = "and"; 4638 goto do_bit; 4639 case M_OR_I: 4640 s = "ori"; 4641 s2 = "or"; 4642 goto do_bit; 4643 case M_NOR_I: 4644 s = ""; 4645 s2 = "nor"; 4646 goto do_bit; 4647 case M_XOR_I: 4648 s = "xori"; 4649 s2 = "xor"; 4650 do_bit: 4651 if (imm_expr.X_op == O_constant 4652 && imm_expr.X_add_number >= 0 4653 && imm_expr.X_add_number < 0x10000) 4654 { 4655 if (mask != M_NOR_I) 4656 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); 4657 else 4658 { 4659 macro_build (&imm_expr, "ori", "t,r,i", 4660 treg, sreg, BFD_RELOC_LO16); 4661 macro_build (NULL, "nor", "d,v,t", treg, treg, 0); 4662 } 4663 break; 4664 } 4665 4666 used_at = 1; 4667 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 4668 macro_build (NULL, s2, "d,v,t", treg, sreg, AT); 4669 break; 4670 4671 case M_BALIGN: 4672 switch (imm_expr.X_add_number) 4673 { 4674 case 0: 4675 macro_build (NULL, "nop", ""); 4676 break; 4677 case 2: 4678 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); 4679 break; 4680 default: 4681 macro_build (NULL, "balign", "t,s,2", treg, sreg, 4682 (int)imm_expr.X_add_number); 4683 break; 4684 } 4685 break; 4686 4687 case M_BEQ_I: 4688 s = "beq"; 4689 goto beq_i; 4690 case M_BEQL_I: 4691 s = "beql"; 4692 likely = 1; 4693 goto beq_i; 4694 case M_BNE_I: 4695 s = "bne"; 4696 goto beq_i; 4697 case M_BNEL_I: 4698 s = "bnel"; 4699 likely = 1; 4700 beq_i: 4701 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 4702 { 4703 macro_build (&offset_expr, s, "s,t,p", sreg, 0); 4704 break; 4705 } 4706 used_at = 1; 4707 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 4708 macro_build (&offset_expr, s, "s,t,p", sreg, AT); 4709 break; 4710 4711 case M_BGEL: 4712 likely = 1; 4713 case M_BGE: 4714 if (treg == 0) 4715 { 4716 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); 4717 break; 4718 } 4719 if (sreg == 0) 4720 { 4721 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); 4722 break; 4723 } 4724 used_at = 1; 4725 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); 4726 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); 4727 break; 4728 4729 case M_BGTL_I: 4730 likely = 1; 4731 case M_BGT_I: 4732 /* check for > max integer */ 4733 maxnum = 0x7fffffff; 4734 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) 4735 { 4736 maxnum <<= 16; 4737 maxnum |= 0xffff; 4738 maxnum <<= 16; 4739 maxnum |= 0xffff; 4740 } 4741 if (imm_expr.X_op == O_constant 4742 && imm_expr.X_add_number >= maxnum 4743 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) 4744 { 4745 do_false: 4746 /* result is always false */ 4747 if (! likely) 4748 macro_build (NULL, "nop", "", 0); 4749 else 4750 macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); 4751 break; 4752 } 4753 if (imm_expr.X_op != O_constant) 4754 as_bad (_("Unsupported large constant")); 4755 ++imm_expr.X_add_number; 4756 /* FALLTHROUGH */ 4757 case M_BGE_I: 4758 case M_BGEL_I: 4759 if (mask == M_BGEL_I) 4760 likely = 1; 4761 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 4762 { 4763 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); 4764 break; 4765 } 4766 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) 4767 { 4768 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); 4769 break; 4770 } 4771 maxnum = 0x7fffffff; 4772 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) 4773 { 4774 maxnum <<= 16; 4775 maxnum |= 0xffff; 4776 maxnum <<= 16; 4777 maxnum |= 0xffff; 4778 } 4779 maxnum = - maxnum - 1; 4780 if (imm_expr.X_op == O_constant 4781 && imm_expr.X_add_number <= maxnum 4782 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) 4783 { 4784 do_true: 4785 /* result is always true */ 4786 as_warn (_("Branch %s is always true"), ip->insn_mo->name); 4787 macro_build (&offset_expr, "b", "p"); 4788 break; 4789 } 4790 used_at = 1; 4791 set_at (sreg, 0); 4792 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); 4793 break; 4794 4795 case M_BGEUL: 4796 likely = 1; 4797 case M_BGEU: 4798 if (treg == 0) 4799 goto do_true; 4800 if (sreg == 0) 4801 { 4802 macro_build (&offset_expr, likely ? "beql" : "beq", 4803 "s,t,p", 0, treg); 4804 break; 4805 } 4806 used_at = 1; 4807 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); 4808 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); 4809 break; 4810 4811 case M_BGTUL_I: 4812 likely = 1; 4813 case M_BGTU_I: 4814 if (sreg == 0 4815 || (HAVE_32BIT_GPRS 4816 && imm_expr.X_op == O_constant 4817 && imm_expr.X_add_number == (offsetT) 0xffffffff)) 4818 goto do_false; 4819 if (imm_expr.X_op != O_constant) 4820 as_bad (_("Unsupported large constant")); 4821 ++imm_expr.X_add_number; 4822 /* FALLTHROUGH */ 4823 case M_BGEU_I: 4824 case M_BGEUL_I: 4825 if (mask == M_BGEUL_I) 4826 likely = 1; 4827 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 4828 goto do_true; 4829 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) 4830 { 4831 macro_build (&offset_expr, likely ? "bnel" : "bne", 4832 "s,t,p", sreg, 0); 4833 break; 4834 } 4835 used_at = 1; 4836 set_at (sreg, 1); 4837 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); 4838 break; 4839 4840 case M_BGTL: 4841 likely = 1; 4842 case M_BGT: 4843 if (treg == 0) 4844 { 4845 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); 4846 break; 4847 } 4848 if (sreg == 0) 4849 { 4850 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); 4851 break; 4852 } 4853 used_at = 1; 4854 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); 4855 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); 4856 break; 4857 4858 case M_BGTUL: 4859 likely = 1; 4860 case M_BGTU: 4861 if (treg == 0) 4862 { 4863 macro_build (&offset_expr, likely ? "bnel" : "bne", 4864 "s,t,p", sreg, 0); 4865 break; 4866 } 4867 if (sreg == 0) 4868 goto do_false; 4869 used_at = 1; 4870 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); 4871 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); 4872 break; 4873 4874 case M_BLEL: 4875 likely = 1; 4876 case M_BLE: 4877 if (treg == 0) 4878 { 4879 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); 4880 break; 4881 } 4882 if (sreg == 0) 4883 { 4884 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); 4885 break; 4886 } 4887 used_at = 1; 4888 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); 4889 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); 4890 break; 4891 4892 case M_BLEL_I: 4893 likely = 1; 4894 case M_BLE_I: 4895 maxnum = 0x7fffffff; 4896 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) 4897 { 4898 maxnum <<= 16; 4899 maxnum |= 0xffff; 4900 maxnum <<= 16; 4901 maxnum |= 0xffff; 4902 } 4903 if (imm_expr.X_op == O_constant 4904 && imm_expr.X_add_number >= maxnum 4905 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) 4906 goto do_true; 4907 if (imm_expr.X_op != O_constant) 4908 as_bad (_("Unsupported large constant")); 4909 ++imm_expr.X_add_number; 4910 /* FALLTHROUGH */ 4911 case M_BLT_I: 4912 case M_BLTL_I: 4913 if (mask == M_BLTL_I) 4914 likely = 1; 4915 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 4916 { 4917 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); 4918 break; 4919 } 4920 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) 4921 { 4922 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); 4923 break; 4924 } 4925 used_at = 1; 4926 set_at (sreg, 0); 4927 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); 4928 break; 4929 4930 case M_BLEUL: 4931 likely = 1; 4932 case M_BLEU: 4933 if (treg == 0) 4934 { 4935 macro_build (&offset_expr, likely ? "beql" : "beq", 4936 "s,t,p", sreg, 0); 4937 break; 4938 } 4939 if (sreg == 0) 4940 goto do_true; 4941 used_at = 1; 4942 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); 4943 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); 4944 break; 4945 4946 case M_BLEUL_I: 4947 likely = 1; 4948 case M_BLEU_I: 4949 if (sreg == 0 4950 || (HAVE_32BIT_GPRS 4951 && imm_expr.X_op == O_constant 4952 && imm_expr.X_add_number == (offsetT) 0xffffffff)) 4953 goto do_true; 4954 if (imm_expr.X_op != O_constant) 4955 as_bad (_("Unsupported large constant")); 4956 ++imm_expr.X_add_number; 4957 /* FALLTHROUGH */ 4958 case M_BLTU_I: 4959 case M_BLTUL_I: 4960 if (mask == M_BLTUL_I) 4961 likely = 1; 4962 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 4963 goto do_false; 4964 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) 4965 { 4966 macro_build (&offset_expr, likely ? "beql" : "beq", 4967 "s,t,p", sreg, 0); 4968 break; 4969 } 4970 used_at = 1; 4971 set_at (sreg, 1); 4972 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); 4973 break; 4974 4975 case M_BLTL: 4976 likely = 1; 4977 case M_BLT: 4978 if (treg == 0) 4979 { 4980 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); 4981 break; 4982 } 4983 if (sreg == 0) 4984 { 4985 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); 4986 break; 4987 } 4988 used_at = 1; 4989 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); 4990 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); 4991 break; 4992 4993 case M_BLTUL: 4994 likely = 1; 4995 case M_BLTU: 4996 if (treg == 0) 4997 goto do_false; 4998 if (sreg == 0) 4999 { 5000 macro_build (&offset_expr, likely ? "bnel" : "bne", 5001 "s,t,p", 0, treg); 5002 break; 5003 } 5004 used_at = 1; 5005 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); 5006 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); 5007 break; 5008 5009 case M_DEXT: 5010 { 5011 unsigned long pos; 5012 unsigned long size; 5013 5014 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) 5015 { 5016 as_bad (_("Unsupported large constant")); 5017 pos = size = 1; 5018 } 5019 else 5020 { 5021 pos = (unsigned long) imm_expr.X_add_number; 5022 size = (unsigned long) imm2_expr.X_add_number; 5023 } 5024 5025 if (pos > 63) 5026 { 5027 as_bad (_("Improper position (%lu)"), pos); 5028 pos = 1; 5029 } 5030 if (size == 0 || size > 64 5031 || (pos + size - 1) > 63) 5032 { 5033 as_bad (_("Improper extract size (%lu, position %lu)"), 5034 size, pos); 5035 size = 1; 5036 } 5037 5038 if (size <= 32 && pos < 32) 5039 { 5040 s = "dext"; 5041 fmt = "t,r,+A,+C"; 5042 } 5043 else if (size <= 32) 5044 { 5045 s = "dextu"; 5046 fmt = "t,r,+E,+H"; 5047 } 5048 else 5049 { 5050 s = "dextm"; 5051 fmt = "t,r,+A,+G"; 5052 } 5053 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); 5054 } 5055 break; 5056 5057 case M_DINS: 5058 { 5059 unsigned long pos; 5060 unsigned long size; 5061 5062 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) 5063 { 5064 as_bad (_("Unsupported large constant")); 5065 pos = size = 1; 5066 } 5067 else 5068 { 5069 pos = (unsigned long) imm_expr.X_add_number; 5070 size = (unsigned long) imm2_expr.X_add_number; 5071 } 5072 5073 if (pos > 63) 5074 { 5075 as_bad (_("Improper position (%lu)"), pos); 5076 pos = 1; 5077 } 5078 if (size == 0 || size > 64 5079 || (pos + size - 1) > 63) 5080 { 5081 as_bad (_("Improper insert size (%lu, position %lu)"), 5082 size, pos); 5083 size = 1; 5084 } 5085 5086 if (pos < 32 && (pos + size - 1) < 32) 5087 { 5088 s = "dins"; 5089 fmt = "t,r,+A,+B"; 5090 } 5091 else if (pos >= 32) 5092 { 5093 s = "dinsu"; 5094 fmt = "t,r,+E,+F"; 5095 } 5096 else 5097 { 5098 s = "dinsm"; 5099 fmt = "t,r,+A,+F"; 5100 } 5101 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, 5102 pos + size - 1); 5103 } 5104 break; 5105 5106 case M_DDIV_3: 5107 dbl = 1; 5108 case M_DIV_3: 5109 s = "mflo"; 5110 goto do_div3; 5111 case M_DREM_3: 5112 dbl = 1; 5113 case M_REM_3: 5114 s = "mfhi"; 5115 do_div3: 5116 if (treg == 0) 5117 { 5118 as_warn (_("Divide by zero.")); 5119 if (mips_trap) 5120 macro_build (NULL, "teq", "s,t,q", 0, 0, 7); 5121 else 5122 macro_build (NULL, "break", "c", 7); 5123 break; 5124 } 5125 5126 start_noreorder (); 5127 if (mips_trap) 5128 { 5129 macro_build (NULL, "teq", "s,t,q", treg, 0, 7); 5130 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); 5131 } 5132 else 5133 { 5134 expr1.X_add_number = 8; 5135 macro_build (&expr1, "bne", "s,t,p", treg, 0); 5136 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); 5137 macro_build (NULL, "break", "c", 7); 5138 } 5139 expr1.X_add_number = -1; 5140 used_at = 1; 5141 load_register (AT, &expr1, dbl); 5142 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); 5143 macro_build (&expr1, "bne", "s,t,p", treg, AT); 5144 if (dbl) 5145 { 5146 expr1.X_add_number = 1; 5147 load_register (AT, &expr1, dbl); 5148 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); 5149 } 5150 else 5151 { 5152 expr1.X_add_number = 0x80000000; 5153 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); 5154 } 5155 if (mips_trap) 5156 { 5157 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); 5158 /* We want to close the noreorder block as soon as possible, so 5159 that later insns are available for delay slot filling. */ 5160 end_noreorder (); 5161 } 5162 else 5163 { 5164 expr1.X_add_number = 8; 5165 macro_build (&expr1, "bne", "s,t,p", sreg, AT); 5166 macro_build (NULL, "nop", "", 0); 5167 5168 /* We want to close the noreorder block as soon as possible, so 5169 that later insns are available for delay slot filling. */ 5170 end_noreorder (); 5171 5172 macro_build (NULL, "break", "c", 6); 5173 } 5174 macro_build (NULL, s, "d", dreg); 5175 break; 5176 5177 case M_DIV_3I: 5178 s = "div"; 5179 s2 = "mflo"; 5180 goto do_divi; 5181 case M_DIVU_3I: 5182 s = "divu"; 5183 s2 = "mflo"; 5184 goto do_divi; 5185 case M_REM_3I: 5186 s = "div"; 5187 s2 = "mfhi"; 5188 goto do_divi; 5189 case M_REMU_3I: 5190 s = "divu"; 5191 s2 = "mfhi"; 5192 goto do_divi; 5193 case M_DDIV_3I: 5194 dbl = 1; 5195 s = "ddiv"; 5196 s2 = "mflo"; 5197 goto do_divi; 5198 case M_DDIVU_3I: 5199 dbl = 1; 5200 s = "ddivu"; 5201 s2 = "mflo"; 5202 goto do_divi; 5203 case M_DREM_3I: 5204 dbl = 1; 5205 s = "ddiv"; 5206 s2 = "mfhi"; 5207 goto do_divi; 5208 case M_DREMU_3I: 5209 dbl = 1; 5210 s = "ddivu"; 5211 s2 = "mfhi"; 5212 do_divi: 5213 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 5214 { 5215 as_warn (_("Divide by zero.")); 5216 if (mips_trap) 5217 macro_build (NULL, "teq", "s,t,q", 0, 0, 7); 5218 else 5219 macro_build (NULL, "break", "c", 7); 5220 break; 5221 } 5222 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) 5223 { 5224 if (strcmp (s2, "mflo") == 0) 5225 move_register (dreg, sreg); 5226 else 5227 move_register (dreg, 0); 5228 break; 5229 } 5230 if (imm_expr.X_op == O_constant 5231 && imm_expr.X_add_number == -1 5232 && s[strlen (s) - 1] != 'u') 5233 { 5234 if (strcmp (s2, "mflo") == 0) 5235 { 5236 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); 5237 } 5238 else 5239 move_register (dreg, 0); 5240 break; 5241 } 5242 5243 used_at = 1; 5244 load_register (AT, &imm_expr, dbl); 5245 macro_build (NULL, s, "z,s,t", sreg, AT); 5246 macro_build (NULL, s2, "d", dreg); 5247 break; 5248 5249 case M_DIVU_3: 5250 s = "divu"; 5251 s2 = "mflo"; 5252 goto do_divu3; 5253 case M_REMU_3: 5254 s = "divu"; 5255 s2 = "mfhi"; 5256 goto do_divu3; 5257 case M_DDIVU_3: 5258 s = "ddivu"; 5259 s2 = "mflo"; 5260 goto do_divu3; 5261 case M_DREMU_3: 5262 s = "ddivu"; 5263 s2 = "mfhi"; 5264 do_divu3: 5265 start_noreorder (); 5266 if (mips_trap) 5267 { 5268 macro_build (NULL, "teq", "s,t,q", treg, 0, 7); 5269 macro_build (NULL, s, "z,s,t", sreg, treg); 5270 /* We want to close the noreorder block as soon as possible, so 5271 that later insns are available for delay slot filling. */ 5272 end_noreorder (); 5273 } 5274 else 5275 { 5276 expr1.X_add_number = 8; 5277 macro_build (&expr1, "bne", "s,t,p", treg, 0); 5278 macro_build (NULL, s, "z,s,t", sreg, treg); 5279 5280 /* We want to close the noreorder block as soon as possible, so 5281 that later insns are available for delay slot filling. */ 5282 end_noreorder (); 5283 macro_build (NULL, "break", "c", 7); 5284 } 5285 macro_build (NULL, s2, "d", dreg); 5286 break; 5287 5288 case M_DLCA_AB: 5289 dbl = 1; 5290 case M_LCA_AB: 5291 call = 1; 5292 goto do_la; 5293 case M_DLA_AB: 5294 dbl = 1; 5295 case M_LA_AB: 5296 do_la: 5297 /* Load the address of a symbol into a register. If breg is not 5298 zero, we then add a base register to it. */ 5299 5300 if (dbl && HAVE_32BIT_GPRS) 5301 as_warn (_("dla used to load 32-bit register")); 5302 5303 if (! dbl && HAVE_64BIT_OBJECTS) 5304 as_warn (_("la used to load 64-bit address")); 5305 5306 if (offset_expr.X_op == O_constant 5307 && offset_expr.X_add_number >= -0x8000 5308 && offset_expr.X_add_number < 0x8000) 5309 { 5310 macro_build (&offset_expr, ADDRESS_ADDI_INSN, 5311 "t,r,j", treg, sreg, BFD_RELOC_LO16); 5312 break; 5313 } 5314 5315 if (!mips_opts.noat && (treg == breg)) 5316 { 5317 tempreg = AT; 5318 used_at = 1; 5319 } 5320 else 5321 { 5322 tempreg = treg; 5323 } 5324 5325 if (offset_expr.X_op != O_symbol 5326 && offset_expr.X_op != O_constant) 5327 { 5328 as_bad (_("expression too complex")); 5329 offset_expr.X_op = O_constant; 5330 } 5331 5332 if (offset_expr.X_op == O_constant) 5333 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); 5334 else if (mips_pic == NO_PIC) 5335 { 5336 /* If this is a reference to a GP relative symbol, we want 5337 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) 5338 Otherwise we want 5339 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 5340 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 5341 If we have a constant, we need two instructions anyhow, 5342 so we may as well always use the latter form. 5343 5344 With 64bit address space and a usable $at we want 5345 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 5346 lui $at,<sym> (BFD_RELOC_HI16_S) 5347 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 5348 daddiu $at,<sym> (BFD_RELOC_LO16) 5349 dsll32 $tempreg,0 5350 daddu $tempreg,$tempreg,$at 5351 5352 If $at is already in use, we use a path which is suboptimal 5353 on superscalar processors. 5354 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 5355 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 5356 dsll $tempreg,16 5357 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 5358 dsll $tempreg,16 5359 daddiu $tempreg,<sym> (BFD_RELOC_LO16) 5360 5361 For GP relative symbols in 64bit address space we can use 5362 the same sequence as in 32bit address space. */ 5363 if (HAVE_64BIT_SYMBOLS) 5364 { 5365 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 5366 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 5367 { 5368 relax_start (offset_expr.X_add_symbol); 5369 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 5370 tempreg, mips_gp_register, BFD_RELOC_GPREL16); 5371 relax_switch (); 5372 } 5373 5374 if (used_at == 0 && !mips_opts.noat) 5375 { 5376 macro_build (&offset_expr, "lui", "t,u", 5377 tempreg, BFD_RELOC_MIPS_HIGHEST); 5378 macro_build (&offset_expr, "lui", "t,u", 5379 AT, BFD_RELOC_HI16_S); 5380 macro_build (&offset_expr, "daddiu", "t,r,j", 5381 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); 5382 macro_build (&offset_expr, "daddiu", "t,r,j", 5383 AT, AT, BFD_RELOC_LO16); 5384 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); 5385 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); 5386 used_at = 1; 5387 } 5388 else 5389 { 5390 macro_build (&offset_expr, "lui", "t,u", 5391 tempreg, BFD_RELOC_MIPS_HIGHEST); 5392 macro_build (&offset_expr, "daddiu", "t,r,j", 5393 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); 5394 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); 5395 macro_build (&offset_expr, "daddiu", "t,r,j", 5396 tempreg, tempreg, BFD_RELOC_HI16_S); 5397 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); 5398 macro_build (&offset_expr, "daddiu", "t,r,j", 5399 tempreg, tempreg, BFD_RELOC_LO16); 5400 } 5401 5402 if (mips_relax.sequence) 5403 relax_end (); 5404 } 5405 else 5406 { 5407 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 5408 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 5409 { 5410 relax_start (offset_expr.X_add_symbol); 5411 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 5412 tempreg, mips_gp_register, BFD_RELOC_GPREL16); 5413 relax_switch (); 5414 } 5415 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) 5416 as_bad (_("offset too large")); 5417 macro_build_lui (&offset_expr, tempreg); 5418 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 5419 tempreg, tempreg, BFD_RELOC_LO16); 5420 if (mips_relax.sequence) 5421 relax_end (); 5422 } 5423 } 5424 else if (!mips_big_got && !HAVE_NEWABI) 5425 { 5426 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 5427 5428 /* If this is a reference to an external symbol, and there 5429 is no constant, we want 5430 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5431 or for lca or if tempreg is PIC_CALL_REG 5432 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 5433 For a local symbol, we want 5434 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5435 nop 5436 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 5437 5438 If we have a small constant, and this is a reference to 5439 an external symbol, we want 5440 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5441 nop 5442 addiu $tempreg,$tempreg,<constant> 5443 For a local symbol, we want the same instruction 5444 sequence, but we output a BFD_RELOC_LO16 reloc on the 5445 addiu instruction. 5446 5447 If we have a large constant, and this is a reference to 5448 an external symbol, we want 5449 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5450 lui $at,<hiconstant> 5451 addiu $at,$at,<loconstant> 5452 addu $tempreg,$tempreg,$at 5453 For a local symbol, we want the same instruction 5454 sequence, but we output a BFD_RELOC_LO16 reloc on the 5455 addiu instruction. 5456 */ 5457 5458 if (offset_expr.X_add_number == 0) 5459 { 5460 if (mips_pic == SVR4_PIC 5461 && breg == 0 5462 && (call || tempreg == PIC_CALL_REG)) 5463 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; 5464 5465 relax_start (offset_expr.X_add_symbol); 5466 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5467 lw_reloc_type, mips_gp_register); 5468 if (breg != 0) 5469 { 5470 /* We're going to put in an addu instruction using 5471 tempreg, so we may as well insert the nop right 5472 now. */ 5473 load_delay_nop (); 5474 } 5475 relax_switch (); 5476 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5477 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); 5478 load_delay_nop (); 5479 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 5480 tempreg, tempreg, BFD_RELOC_LO16); 5481 relax_end (); 5482 /* FIXME: If breg == 0, and the next instruction uses 5483 $tempreg, then if this variant case is used an extra 5484 nop will be generated. */ 5485 } 5486 else if (offset_expr.X_add_number >= -0x8000 5487 && offset_expr.X_add_number < 0x8000) 5488 { 5489 load_got_offset (tempreg, &offset_expr); 5490 load_delay_nop (); 5491 add_got_offset (tempreg, &offset_expr); 5492 } 5493 else 5494 { 5495 expr1.X_add_number = offset_expr.X_add_number; 5496 offset_expr.X_add_number = 5497 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; 5498 load_got_offset (tempreg, &offset_expr); 5499 offset_expr.X_add_number = expr1.X_add_number; 5500 /* If we are going to add in a base register, and the 5501 target register and the base register are the same, 5502 then we are using AT as a temporary register. Since 5503 we want to load the constant into AT, we add our 5504 current AT (from the global offset table) and the 5505 register into the register now, and pretend we were 5506 not using a base register. */ 5507 if (breg == treg) 5508 { 5509 load_delay_nop (); 5510 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5511 treg, AT, breg); 5512 breg = 0; 5513 tempreg = treg; 5514 } 5515 add_got_offset_hilo (tempreg, &offset_expr, AT); 5516 used_at = 1; 5517 } 5518 } 5519 else if (!mips_big_got && HAVE_NEWABI) 5520 { 5521 int add_breg_early = 0; 5522 5523 /* If this is a reference to an external, and there is no 5524 constant, or local symbol (*), with or without a 5525 constant, we want 5526 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 5527 or for lca or if tempreg is PIC_CALL_REG 5528 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 5529 5530 If we have a small constant, and this is a reference to 5531 an external symbol, we want 5532 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 5533 addiu $tempreg,$tempreg,<constant> 5534 5535 If we have a large constant, and this is a reference to 5536 an external symbol, we want 5537 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 5538 lui $at,<hiconstant> 5539 addiu $at,$at,<loconstant> 5540 addu $tempreg,$tempreg,$at 5541 5542 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for 5543 local symbols, even though it introduces an additional 5544 instruction. */ 5545 5546 if (offset_expr.X_add_number) 5547 { 5548 expr1.X_add_number = offset_expr.X_add_number; 5549 offset_expr.X_add_number = 0; 5550 5551 relax_start (offset_expr.X_add_symbol); 5552 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5553 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 5554 5555 if (expr1.X_add_number >= -0x8000 5556 && expr1.X_add_number < 0x8000) 5557 { 5558 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 5559 tempreg, tempreg, BFD_RELOC_LO16); 5560 } 5561 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) 5562 { 5563 int dreg; 5564 5565 /* If we are going to add in a base register, and the 5566 target register and the base register are the same, 5567 then we are using AT as a temporary register. Since 5568 we want to load the constant into AT, we add our 5569 current AT (from the global offset table) and the 5570 register into the register now, and pretend we were 5571 not using a base register. */ 5572 if (breg != treg) 5573 dreg = tempreg; 5574 else 5575 { 5576 assert (tempreg == AT); 5577 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5578 treg, AT, breg); 5579 dreg = treg; 5580 add_breg_early = 1; 5581 } 5582 5583 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 5584 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5585 dreg, dreg, AT); 5586 5587 used_at = 1; 5588 } 5589 else 5590 as_bad (_("PIC code offset overflow (max 32 signed bits)")); 5591 5592 relax_switch (); 5593 offset_expr.X_add_number = expr1.X_add_number; 5594 5595 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5596 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 5597 if (add_breg_early) 5598 { 5599 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5600 treg, tempreg, breg); 5601 breg = 0; 5602 tempreg = treg; 5603 } 5604 relax_end (); 5605 } 5606 else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) 5607 { 5608 relax_start (offset_expr.X_add_symbol); 5609 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5610 BFD_RELOC_MIPS_CALL16, mips_gp_register); 5611 relax_switch (); 5612 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5613 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 5614 relax_end (); 5615 } 5616 else 5617 { 5618 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5619 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 5620 } 5621 } 5622 else if (mips_big_got && !HAVE_NEWABI) 5623 { 5624 int gpdelay; 5625 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; 5626 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; 5627 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 5628 5629 /* This is the large GOT case. If this is a reference to an 5630 external symbol, and there is no constant, we want 5631 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 5632 addu $tempreg,$tempreg,$gp 5633 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 5634 or for lca or if tempreg is PIC_CALL_REG 5635 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) 5636 addu $tempreg,$tempreg,$gp 5637 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) 5638 For a local symbol, we want 5639 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5640 nop 5641 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 5642 5643 If we have a small constant, and this is a reference to 5644 an external symbol, we want 5645 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 5646 addu $tempreg,$tempreg,$gp 5647 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 5648 nop 5649 addiu $tempreg,$tempreg,<constant> 5650 For a local symbol, we want 5651 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5652 nop 5653 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) 5654 5655 If we have a large constant, and this is a reference to 5656 an external symbol, we want 5657 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 5658 addu $tempreg,$tempreg,$gp 5659 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 5660 lui $at,<hiconstant> 5661 addiu $at,$at,<loconstant> 5662 addu $tempreg,$tempreg,$at 5663 For a local symbol, we want 5664 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5665 lui $at,<hiconstant> 5666 addiu $at,$at,<loconstant> (BFD_RELOC_LO16) 5667 addu $tempreg,$tempreg,$at 5668 */ 5669 5670 expr1.X_add_number = offset_expr.X_add_number; 5671 offset_expr.X_add_number = 0; 5672 relax_start (offset_expr.X_add_symbol); 5673 gpdelay = reg_needs_delay (mips_gp_register); 5674 if (expr1.X_add_number == 0 && breg == 0 5675 && (call || tempreg == PIC_CALL_REG)) 5676 { 5677 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; 5678 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; 5679 } 5680 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); 5681 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5682 tempreg, tempreg, mips_gp_register); 5683 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5684 tempreg, lw_reloc_type, tempreg); 5685 if (expr1.X_add_number == 0) 5686 { 5687 if (breg != 0) 5688 { 5689 /* We're going to put in an addu instruction using 5690 tempreg, so we may as well insert the nop right 5691 now. */ 5692 load_delay_nop (); 5693 } 5694 } 5695 else if (expr1.X_add_number >= -0x8000 5696 && expr1.X_add_number < 0x8000) 5697 { 5698 load_delay_nop (); 5699 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 5700 tempreg, tempreg, BFD_RELOC_LO16); 5701 } 5702 else 5703 { 5704 int dreg; 5705 5706 /* If we are going to add in a base register, and the 5707 target register and the base register are the same, 5708 then we are using AT as a temporary register. Since 5709 we want to load the constant into AT, we add our 5710 current AT (from the global offset table) and the 5711 register into the register now, and pretend we were 5712 not using a base register. */ 5713 if (breg != treg) 5714 dreg = tempreg; 5715 else 5716 { 5717 assert (tempreg == AT); 5718 load_delay_nop (); 5719 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5720 treg, AT, breg); 5721 dreg = treg; 5722 } 5723 5724 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 5725 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); 5726 5727 used_at = 1; 5728 } 5729 offset_expr.X_add_number = 5730 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; 5731 relax_switch (); 5732 5733 if (gpdelay) 5734 { 5735 /* This is needed because this instruction uses $gp, but 5736 the first instruction on the main stream does not. */ 5737 macro_build (NULL, "nop", ""); 5738 } 5739 5740 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5741 local_reloc_type, mips_gp_register); 5742 if (expr1.X_add_number >= -0x8000 5743 && expr1.X_add_number < 0x8000) 5744 { 5745 load_delay_nop (); 5746 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 5747 tempreg, tempreg, BFD_RELOC_LO16); 5748 /* FIXME: If add_number is 0, and there was no base 5749 register, the external symbol case ended with a load, 5750 so if the symbol turns out to not be external, and 5751 the next instruction uses tempreg, an unnecessary nop 5752 will be inserted. */ 5753 } 5754 else 5755 { 5756 if (breg == treg) 5757 { 5758 /* We must add in the base register now, as in the 5759 external symbol case. */ 5760 assert (tempreg == AT); 5761 load_delay_nop (); 5762 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5763 treg, AT, breg); 5764 tempreg = treg; 5765 /* We set breg to 0 because we have arranged to add 5766 it in in both cases. */ 5767 breg = 0; 5768 } 5769 5770 macro_build_lui (&expr1, AT); 5771 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 5772 AT, AT, BFD_RELOC_LO16); 5773 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5774 tempreg, tempreg, AT); 5775 used_at = 1; 5776 } 5777 relax_end (); 5778 } 5779 else if (mips_big_got && HAVE_NEWABI) 5780 { 5781 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; 5782 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; 5783 int add_breg_early = 0; 5784 5785 /* This is the large GOT case. If this is a reference to an 5786 external symbol, and there is no constant, we want 5787 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 5788 add $tempreg,$tempreg,$gp 5789 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 5790 or for lca or if tempreg is PIC_CALL_REG 5791 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) 5792 add $tempreg,$tempreg,$gp 5793 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) 5794 5795 If we have a small constant, and this is a reference to 5796 an external symbol, we want 5797 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 5798 add $tempreg,$tempreg,$gp 5799 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 5800 addi $tempreg,$tempreg,<constant> 5801 5802 If we have a large constant, and this is a reference to 5803 an external symbol, we want 5804 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 5805 addu $tempreg,$tempreg,$gp 5806 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 5807 lui $at,<hiconstant> 5808 addi $at,$at,<loconstant> 5809 add $tempreg,$tempreg,$at 5810 5811 If we have NewABI, and we know it's a local symbol, we want 5812 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 5813 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) 5814 otherwise we have to resort to GOT_HI16/GOT_LO16. */ 5815 5816 relax_start (offset_expr.X_add_symbol); 5817 5818 expr1.X_add_number = offset_expr.X_add_number; 5819 offset_expr.X_add_number = 0; 5820 5821 if (expr1.X_add_number == 0 && breg == 0 5822 && (call || tempreg == PIC_CALL_REG)) 5823 { 5824 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; 5825 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; 5826 } 5827 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); 5828 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5829 tempreg, tempreg, mips_gp_register); 5830 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5831 tempreg, lw_reloc_type, tempreg); 5832 5833 if (expr1.X_add_number == 0) 5834 ; 5835 else if (expr1.X_add_number >= -0x8000 5836 && expr1.X_add_number < 0x8000) 5837 { 5838 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 5839 tempreg, tempreg, BFD_RELOC_LO16); 5840 } 5841 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) 5842 { 5843 int dreg; 5844 5845 /* If we are going to add in a base register, and the 5846 target register and the base register are the same, 5847 then we are using AT as a temporary register. Since 5848 we want to load the constant into AT, we add our 5849 current AT (from the global offset table) and the 5850 register into the register now, and pretend we were 5851 not using a base register. */ 5852 if (breg != treg) 5853 dreg = tempreg; 5854 else 5855 { 5856 assert (tempreg == AT); 5857 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5858 treg, AT, breg); 5859 dreg = treg; 5860 add_breg_early = 1; 5861 } 5862 5863 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 5864 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); 5865 5866 used_at = 1; 5867 } 5868 else 5869 as_bad (_("PIC code offset overflow (max 32 signed bits)")); 5870 5871 relax_switch (); 5872 offset_expr.X_add_number = expr1.X_add_number; 5873 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5874 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 5875 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 5876 tempreg, BFD_RELOC_MIPS_GOT_OFST); 5877 if (add_breg_early) 5878 { 5879 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5880 treg, tempreg, breg); 5881 breg = 0; 5882 tempreg = treg; 5883 } 5884 relax_end (); 5885 } 5886 else 5887 abort (); 5888 5889 if (breg != 0) 5890 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); 5891 break; 5892 5893 case M_J_A: 5894 /* The j instruction may not be used in PIC code, since it 5895 requires an absolute address. We convert it to a b 5896 instruction. */ 5897 if (mips_pic == NO_PIC) 5898 macro_build (&offset_expr, "j", "a"); 5899 else 5900 macro_build (&offset_expr, "b", "p"); 5901 break; 5902 5903 /* The jal instructions must be handled as macros because when 5904 generating PIC code they expand to multi-instruction 5905 sequences. Normally they are simple instructions. */ 5906 case M_JAL_1: 5907 dreg = RA; 5908 /* Fall through. */ 5909 case M_JAL_2: 5910 if (mips_pic == NO_PIC) 5911 macro_build (NULL, "jalr", "d,s", dreg, sreg); 5912 else 5913 { 5914 if (sreg != PIC_CALL_REG) 5915 as_warn (_("MIPS PIC call to register other than $25")); 5916 5917 macro_build (NULL, "jalr", "d,s", dreg, sreg); 5918 if (mips_pic == SVR4_PIC && !HAVE_NEWABI) 5919 { 5920 if (mips_cprestore_offset < 0) 5921 as_warn (_("No .cprestore pseudo-op used in PIC code")); 5922 else 5923 { 5924 if (! mips_frame_reg_valid) 5925 { 5926 as_warn (_("No .frame pseudo-op used in PIC code")); 5927 /* Quiet this warning. */ 5928 mips_frame_reg_valid = 1; 5929 } 5930 if (! mips_cprestore_valid) 5931 { 5932 as_warn (_("No .cprestore pseudo-op used in PIC code")); 5933 /* Quiet this warning. */ 5934 mips_cprestore_valid = 1; 5935 } 5936 expr1.X_add_number = mips_cprestore_offset; 5937 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, 5938 mips_gp_register, 5939 mips_frame_reg, 5940 HAVE_64BIT_ADDRESSES); 5941 } 5942 } 5943 } 5944 5945 break; 5946 5947 case M_JAL_A: 5948 if (mips_pic == NO_PIC) 5949 macro_build (&offset_expr, "jal", "a"); 5950 else if (mips_pic == SVR4_PIC) 5951 { 5952 /* If this is a reference to an external symbol, and we are 5953 using a small GOT, we want 5954 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 5955 nop 5956 jalr $ra,$25 5957 nop 5958 lw $gp,cprestore($sp) 5959 The cprestore value is set using the .cprestore 5960 pseudo-op. If we are using a big GOT, we want 5961 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) 5962 addu $25,$25,$gp 5963 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) 5964 nop 5965 jalr $ra,$25 5966 nop 5967 lw $gp,cprestore($sp) 5968 If the symbol is not external, we want 5969 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5970 nop 5971 addiu $25,$25,<sym> (BFD_RELOC_LO16) 5972 jalr $ra,$25 5973 nop 5974 lw $gp,cprestore($sp) 5975 5976 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 5977 sequences above, minus nops, unless the symbol is local, 5978 which enables us to use GOT_PAGE/GOT_OFST (big got) or 5979 GOT_DISP. */ 5980 if (HAVE_NEWABI) 5981 { 5982 if (! mips_big_got) 5983 { 5984 relax_start (offset_expr.X_add_symbol); 5985 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5986 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, 5987 mips_gp_register); 5988 relax_switch (); 5989 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5990 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, 5991 mips_gp_register); 5992 relax_end (); 5993 } 5994 else 5995 { 5996 relax_start (offset_expr.X_add_symbol); 5997 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, 5998 BFD_RELOC_MIPS_CALL_HI16); 5999 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, 6000 PIC_CALL_REG, mips_gp_register); 6001 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 6002 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, 6003 PIC_CALL_REG); 6004 relax_switch (); 6005 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 6006 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, 6007 mips_gp_register); 6008 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 6009 PIC_CALL_REG, PIC_CALL_REG, 6010 BFD_RELOC_MIPS_GOT_OFST); 6011 relax_end (); 6012 } 6013 6014 macro_build_jalr (&offset_expr); 6015 } 6016 else 6017 { 6018 relax_start (offset_expr.X_add_symbol); 6019 if (! mips_big_got) 6020 { 6021 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 6022 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, 6023 mips_gp_register); 6024 load_delay_nop (); 6025 relax_switch (); 6026 } 6027 else 6028 { 6029 int gpdelay; 6030 6031 gpdelay = reg_needs_delay (mips_gp_register); 6032 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, 6033 BFD_RELOC_MIPS_CALL_HI16); 6034 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, 6035 PIC_CALL_REG, mips_gp_register); 6036 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 6037 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, 6038 PIC_CALL_REG); 6039 load_delay_nop (); 6040 relax_switch (); 6041 if (gpdelay) 6042 macro_build (NULL, "nop", ""); 6043 } 6044 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 6045 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, 6046 mips_gp_register); 6047 load_delay_nop (); 6048 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 6049 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); 6050 relax_end (); 6051 macro_build_jalr (&offset_expr); 6052 6053 if (mips_cprestore_offset < 0) 6054 as_warn (_("No .cprestore pseudo-op used in PIC code")); 6055 else 6056 { 6057 if (! mips_frame_reg_valid) 6058 { 6059 as_warn (_("No .frame pseudo-op used in PIC code")); 6060 /* Quiet this warning. */ 6061 mips_frame_reg_valid = 1; 6062 } 6063 if (! mips_cprestore_valid) 6064 { 6065 as_warn (_("No .cprestore pseudo-op used in PIC code")); 6066 /* Quiet this warning. */ 6067 mips_cprestore_valid = 1; 6068 } 6069 if (mips_opts.noreorder) 6070 macro_build (NULL, "nop", ""); 6071 expr1.X_add_number = mips_cprestore_offset; 6072 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, 6073 mips_gp_register, 6074 mips_frame_reg, 6075 HAVE_64BIT_ADDRESSES); 6076 } 6077 } 6078 } 6079 else if (mips_pic == VXWORKS_PIC) 6080 as_bad (_("Non-PIC jump used in PIC library")); 6081 else 6082 abort (); 6083 6084 break; 6085 6086 case M_LB_AB: 6087 s = "lb"; 6088 goto ld; 6089 case M_LBU_AB: 6090 s = "lbu"; 6091 goto ld; 6092 case M_LH_AB: 6093 s = "lh"; 6094 goto ld; 6095 case M_LHU_AB: 6096 s = "lhu"; 6097 goto ld; 6098 case M_LW_AB: 6099 s = "lw"; 6100 goto ld; 6101 case M_LWC0_AB: 6102 s = "lwc0"; 6103 /* Itbl support may require additional care here. */ 6104 coproc = 1; 6105 goto ld; 6106 case M_LWC1_AB: 6107 s = "lwc1"; 6108 /* Itbl support may require additional care here. */ 6109 coproc = 1; 6110 goto ld; 6111 case M_LWC2_AB: 6112 s = "lwc2"; 6113 /* Itbl support may require additional care here. */ 6114 coproc = 1; 6115 goto ld; 6116 case M_LWC3_AB: 6117 s = "lwc3"; 6118 /* Itbl support may require additional care here. */ 6119 coproc = 1; 6120 goto ld; 6121 case M_LWL_AB: 6122 s = "lwl"; 6123 lr = 1; 6124 goto ld; 6125 case M_LWR_AB: 6126 s = "lwr"; 6127 lr = 1; 6128 goto ld; 6129 case M_LDC1_AB: 6130 if (mips_opts.arch == CPU_R4650) 6131 { 6132 as_bad (_("opcode not supported on this processor")); 6133 break; 6134 } 6135 s = "ldc1"; 6136 /* Itbl support may require additional care here. */ 6137 coproc = 1; 6138 goto ld; 6139 case M_LDC2_AB: 6140 s = "ldc2"; 6141 /* Itbl support may require additional care here. */ 6142 coproc = 1; 6143 goto ld; 6144 case M_LDC3_AB: 6145 s = "ldc3"; 6146 /* Itbl support may require additional care here. */ 6147 coproc = 1; 6148 goto ld; 6149 case M_LDL_AB: 6150 s = "ldl"; 6151 lr = 1; 6152 goto ld; 6153 case M_LDR_AB: 6154 s = "ldr"; 6155 lr = 1; 6156 goto ld; 6157 case M_LL_AB: 6158 s = "ll"; 6159 goto ld; 6160 case M_LLD_AB: 6161 s = "lld"; 6162 goto ld; 6163 case M_LWU_AB: 6164 s = "lwu"; 6165 ld: 6166 if (mips_opts.arch == CPU_OCTEON 6167 && octeon_error_on_unsupported 6168 && (mask == M_LDC1_AB || mask == M_LDC2_AB || mask == M_LDC3_AB 6169 || mask == M_L_DOB || mask == M_L_DAB 6170 || mask == M_LI_D || mask == M_LI_DD 6171 || mask == M_LI_S || mask == M_LI_SS)) 6172 { 6173 as_bad (_("opcode not implemented in Octeon `%s'"), ip->insn_mo->name); 6174 return; 6175 } 6176 if (breg == treg || coproc || lr) 6177 { 6178 tempreg = AT; 6179 used_at = 1; 6180 } 6181 else 6182 { 6183 tempreg = treg; 6184 } 6185 goto ld_st; 6186 case M_SB_AB: 6187 s = "sb"; 6188 goto st; 6189 case M_SH_AB: 6190 s = "sh"; 6191 goto st; 6192 case M_SW_AB: 6193 s = "sw"; 6194 goto st; 6195 case M_SWC0_AB: 6196 s = "swc0"; 6197 /* Itbl support may require additional care here. */ 6198 coproc = 1; 6199 goto st; 6200 case M_SWC1_AB: 6201 s = "swc1"; 6202 /* Itbl support may require additional care here. */ 6203 coproc = 1; 6204 goto st; 6205 case M_SWC2_AB: 6206 s = "swc2"; 6207 /* Itbl support may require additional care here. */ 6208 coproc = 1; 6209 goto st; 6210 case M_SWC3_AB: 6211 s = "swc3"; 6212 /* Itbl support may require additional care here. */ 6213 coproc = 1; 6214 goto st; 6215 case M_SWL_AB: 6216 s = "swl"; 6217 goto st; 6218 case M_SWR_AB: 6219 s = "swr"; 6220 goto st; 6221 case M_SC_AB: 6222 s = "sc"; 6223 goto st; 6224 case M_SCD_AB: 6225 s = "scd"; 6226 goto st; 6227 case M_CACHE_AB: 6228 s = "cache"; 6229 goto st; 6230 case M_SDC1_AB: 6231 if (mips_opts.arch == CPU_R4650) 6232 { 6233 as_bad (_("opcode not supported on this processor")); 6234 break; 6235 } 6236 s = "sdc1"; 6237 coproc = 1; 6238 /* Itbl support may require additional care here. */ 6239 goto st; 6240 case M_SDC2_AB: 6241 s = "sdc2"; 6242 /* Itbl support may require additional care here. */ 6243 coproc = 1; 6244 goto st; 6245 case M_SDC3_AB: 6246 s = "sdc3"; 6247 /* Itbl support may require additional care here. */ 6248 coproc = 1; 6249 goto st; 6250 case M_SDL_AB: 6251 s = "sdl"; 6252 goto st; 6253 case M_SDR_AB: 6254 s = "sdr"; 6255 st: 6256 if (mips_opts.arch == CPU_OCTEON 6257 && octeon_error_on_unsupported 6258 && (mask == M_SWC0_AB || mask == M_SWC1_AB || mask == M_SWC2_AB 6259 || mask == M_SDC1_AB || mask == M_SDC2_AB || mask == M_SDC3_AB 6260 || mask == M_S_DAB || mask == M_S_DOB)) 6261 { 6262 as_bad (_("opcode not implemented in Octeon `%s'"), ip->insn_mo->name); 6263 return; 6264 } 6265 tempreg = AT; 6266 used_at = 1; 6267 ld_st: 6268 /* Itbl support may require additional care here. */ 6269 if (mask == M_LWC1_AB 6270 || mask == M_SWC1_AB 6271 || mask == M_LDC1_AB 6272 || mask == M_SDC1_AB 6273 || mask == M_L_DAB 6274 || mask == M_S_DAB) 6275 fmt = "T,o(b)"; 6276 else if (mask == M_CACHE_AB) 6277 fmt = "k,o(b)"; 6278 else if (coproc) 6279 fmt = "E,o(b)"; 6280 else 6281 fmt = "t,o(b)"; 6282 6283 if (offset_expr.X_op != O_constant 6284 && offset_expr.X_op != O_symbol) 6285 { 6286 as_bad (_("expression too complex")); 6287 offset_expr.X_op = O_constant; 6288 } 6289 6290 if (HAVE_32BIT_ADDRESSES 6291 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) 6292 { 6293 char value [32]; 6294 6295 sprintf_vma (value, offset_expr.X_add_number); 6296 as_bad (_("Number (0x%s) larger than 32 bits"), value); 6297 } 6298 6299 /* A constant expression in PIC code can be handled just as it 6300 is in non PIC code. */ 6301 if (offset_expr.X_op == O_constant) 6302 { 6303 expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) 6304 & ~(bfd_vma) 0xffff); 6305 normalize_address_expr (&expr1); 6306 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); 6307 if (breg != 0) 6308 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6309 tempreg, tempreg, breg); 6310 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); 6311 } 6312 else if (mips_pic == NO_PIC) 6313 { 6314 /* If this is a reference to a GP relative symbol, and there 6315 is no base register, we want 6316 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) 6317 Otherwise, if there is no base register, we want 6318 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 6319 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) 6320 If we have a constant, we need two instructions anyhow, 6321 so we always use the latter form. 6322 6323 If we have a base register, and this is a reference to a 6324 GP relative symbol, we want 6325 addu $tempreg,$breg,$gp 6326 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) 6327 Otherwise we want 6328 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 6329 addu $tempreg,$tempreg,$breg 6330 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) 6331 With a constant we always use the latter case. 6332 6333 With 64bit address space and no base register and $at usable, 6334 we want 6335 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 6336 lui $at,<sym> (BFD_RELOC_HI16_S) 6337 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 6338 dsll32 $tempreg,0 6339 daddu $tempreg,$at 6340 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) 6341 If we have a base register, we want 6342 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 6343 lui $at,<sym> (BFD_RELOC_HI16_S) 6344 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 6345 daddu $at,$breg 6346 dsll32 $tempreg,0 6347 daddu $tempreg,$at 6348 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) 6349 6350 Without $at we can't generate the optimal path for superscalar 6351 processors here since this would require two temporary registers. 6352 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 6353 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 6354 dsll $tempreg,16 6355 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 6356 dsll $tempreg,16 6357 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) 6358 If we have a base register, we want 6359 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 6360 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 6361 dsll $tempreg,16 6362 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 6363 dsll $tempreg,16 6364 daddu $tempreg,$tempreg,$breg 6365 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) 6366 6367 For GP relative symbols in 64bit address space we can use 6368 the same sequence as in 32bit address space. */ 6369 if (HAVE_64BIT_SYMBOLS) 6370 { 6371 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 6372 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 6373 { 6374 relax_start (offset_expr.X_add_symbol); 6375 if (breg == 0) 6376 { 6377 macro_build (&offset_expr, s, fmt, treg, 6378 BFD_RELOC_GPREL16, mips_gp_register); 6379 } 6380 else 6381 { 6382 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6383 tempreg, breg, mips_gp_register); 6384 macro_build (&offset_expr, s, fmt, treg, 6385 BFD_RELOC_GPREL16, tempreg); 6386 } 6387 relax_switch (); 6388 } 6389 6390 if (used_at == 0 && !mips_opts.noat) 6391 { 6392 macro_build (&offset_expr, "lui", "t,u", tempreg, 6393 BFD_RELOC_MIPS_HIGHEST); 6394 macro_build (&offset_expr, "lui", "t,u", AT, 6395 BFD_RELOC_HI16_S); 6396 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 6397 tempreg, BFD_RELOC_MIPS_HIGHER); 6398 if (breg != 0) 6399 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); 6400 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); 6401 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); 6402 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, 6403 tempreg); 6404 used_at = 1; 6405 } 6406 else 6407 { 6408 macro_build (&offset_expr, "lui", "t,u", tempreg, 6409 BFD_RELOC_MIPS_HIGHEST); 6410 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 6411 tempreg, BFD_RELOC_MIPS_HIGHER); 6412 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); 6413 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 6414 tempreg, BFD_RELOC_HI16_S); 6415 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); 6416 if (breg != 0) 6417 macro_build (NULL, "daddu", "d,v,t", 6418 tempreg, tempreg, breg); 6419 macro_build (&offset_expr, s, fmt, treg, 6420 BFD_RELOC_LO16, tempreg); 6421 } 6422 6423 if (mips_relax.sequence) 6424 relax_end (); 6425 break; 6426 } 6427 6428 if (breg == 0) 6429 { 6430 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 6431 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 6432 { 6433 relax_start (offset_expr.X_add_symbol); 6434 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, 6435 mips_gp_register); 6436 relax_switch (); 6437 } 6438 macro_build_lui (&offset_expr, tempreg); 6439 macro_build (&offset_expr, s, fmt, treg, 6440 BFD_RELOC_LO16, tempreg); 6441 if (mips_relax.sequence) 6442 relax_end (); 6443 } 6444 else 6445 { 6446 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 6447 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 6448 { 6449 relax_start (offset_expr.X_add_symbol); 6450 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6451 tempreg, breg, mips_gp_register); 6452 macro_build (&offset_expr, s, fmt, treg, 6453 BFD_RELOC_GPREL16, tempreg); 6454 relax_switch (); 6455 } 6456 macro_build_lui (&offset_expr, tempreg); 6457 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6458 tempreg, tempreg, breg); 6459 macro_build (&offset_expr, s, fmt, treg, 6460 BFD_RELOC_LO16, tempreg); 6461 if (mips_relax.sequence) 6462 relax_end (); 6463 } 6464 } 6465 else if (!mips_big_got) 6466 { 6467 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 6468 6469 /* If this is a reference to an external symbol, we want 6470 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 6471 nop 6472 <op> $treg,0($tempreg) 6473 Otherwise we want 6474 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 6475 nop 6476 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 6477 <op> $treg,0($tempreg) 6478 6479 For NewABI, we want 6480 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 6481 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) 6482 6483 If there is a base register, we add it to $tempreg before 6484 the <op>. If there is a constant, we stick it in the 6485 <op> instruction. We don't handle constants larger than 6486 16 bits, because we have no way to load the upper 16 bits 6487 (actually, we could handle them for the subset of cases 6488 in which we are not using $at). */ 6489 assert (offset_expr.X_op == O_symbol); 6490 if (HAVE_NEWABI) 6491 { 6492 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 6493 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 6494 if (breg != 0) 6495 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6496 tempreg, tempreg, breg); 6497 macro_build (&offset_expr, s, fmt, treg, 6498 BFD_RELOC_MIPS_GOT_OFST, tempreg); 6499 break; 6500 } 6501 expr1.X_add_number = offset_expr.X_add_number; 6502 offset_expr.X_add_number = 0; 6503 if (expr1.X_add_number < -0x8000 6504 || expr1.X_add_number >= 0x8000) 6505 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 6506 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 6507 lw_reloc_type, mips_gp_register); 6508 load_delay_nop (); 6509 relax_start (offset_expr.X_add_symbol); 6510 relax_switch (); 6511 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 6512 tempreg, BFD_RELOC_LO16); 6513 relax_end (); 6514 if (breg != 0) 6515 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6516 tempreg, tempreg, breg); 6517 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); 6518 } 6519 else if (mips_big_got && !HAVE_NEWABI) 6520 { 6521 int gpdelay; 6522 6523 /* If this is a reference to an external symbol, we want 6524 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 6525 addu $tempreg,$tempreg,$gp 6526 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 6527 <op> $treg,0($tempreg) 6528 Otherwise we want 6529 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 6530 nop 6531 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 6532 <op> $treg,0($tempreg) 6533 If there is a base register, we add it to $tempreg before 6534 the <op>. If there is a constant, we stick it in the 6535 <op> instruction. We don't handle constants larger than 6536 16 bits, because we have no way to load the upper 16 bits 6537 (actually, we could handle them for the subset of cases 6538 in which we are not using $at). */ 6539 assert (offset_expr.X_op == O_symbol); 6540 expr1.X_add_number = offset_expr.X_add_number; 6541 offset_expr.X_add_number = 0; 6542 if (expr1.X_add_number < -0x8000 6543 || expr1.X_add_number >= 0x8000) 6544 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 6545 gpdelay = reg_needs_delay (mips_gp_register); 6546 relax_start (offset_expr.X_add_symbol); 6547 macro_build (&offset_expr, "lui", "t,u", tempreg, 6548 BFD_RELOC_MIPS_GOT_HI16); 6549 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, 6550 mips_gp_register); 6551 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 6552 BFD_RELOC_MIPS_GOT_LO16, tempreg); 6553 relax_switch (); 6554 if (gpdelay) 6555 macro_build (NULL, "nop", ""); 6556 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 6557 BFD_RELOC_MIPS_GOT16, mips_gp_register); 6558 load_delay_nop (); 6559 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 6560 tempreg, BFD_RELOC_LO16); 6561 relax_end (); 6562 6563 if (breg != 0) 6564 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6565 tempreg, tempreg, breg); 6566 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); 6567 } 6568 else if (mips_big_got && HAVE_NEWABI) 6569 { 6570 /* If this is a reference to an external symbol, we want 6571 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 6572 add $tempreg,$tempreg,$gp 6573 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 6574 <op> $treg,<ofst>($tempreg) 6575 Otherwise, for local symbols, we want: 6576 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 6577 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ 6578 assert (offset_expr.X_op == O_symbol); 6579 expr1.X_add_number = offset_expr.X_add_number; 6580 offset_expr.X_add_number = 0; 6581 if (expr1.X_add_number < -0x8000 6582 || expr1.X_add_number >= 0x8000) 6583 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 6584 relax_start (offset_expr.X_add_symbol); 6585 macro_build (&offset_expr, "lui", "t,u", tempreg, 6586 BFD_RELOC_MIPS_GOT_HI16); 6587 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, 6588 mips_gp_register); 6589 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 6590 BFD_RELOC_MIPS_GOT_LO16, tempreg); 6591 if (breg != 0) 6592 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6593 tempreg, tempreg, breg); 6594 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); 6595 6596 relax_switch (); 6597 offset_expr.X_add_number = expr1.X_add_number; 6598 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 6599 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 6600 if (breg != 0) 6601 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6602 tempreg, tempreg, breg); 6603 macro_build (&offset_expr, s, fmt, treg, 6604 BFD_RELOC_MIPS_GOT_OFST, tempreg); 6605 relax_end (); 6606 } 6607 else 6608 abort (); 6609 6610 break; 6611 6612 case M_LI: 6613 case M_LI_S: 6614 load_register (treg, &imm_expr, 0); 6615 break; 6616 6617 case M_DLI: 6618 load_register (treg, &imm_expr, 1); 6619 break; 6620 6621 case M_LI_SS: 6622 if (imm_expr.X_op == O_constant) 6623 { 6624 used_at = 1; 6625 load_register (AT, &imm_expr, 0); 6626 macro_build (NULL, "mtc1", "t,G", AT, treg); 6627 break; 6628 } 6629 else 6630 { 6631 assert (offset_expr.X_op == O_symbol 6632 && strcmp (segment_name (S_GET_SEGMENT 6633 (offset_expr.X_add_symbol)), 6634 ".lit4") == 0 6635 && offset_expr.X_add_number == 0); 6636 macro_build (&offset_expr, "lwc1", "T,o(b)", treg, 6637 BFD_RELOC_MIPS_LITERAL, mips_gp_register); 6638 break; 6639 } 6640 6641 case M_LI_D: 6642 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits 6643 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high 6644 order 32 bits of the value and the low order 32 bits are either 6645 zero or in OFFSET_EXPR. */ 6646 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) 6647 { 6648 if (HAVE_64BIT_GPRS) 6649 load_register (treg, &imm_expr, 1); 6650 else 6651 { 6652 int hreg, lreg; 6653 6654 if (target_big_endian) 6655 { 6656 hreg = treg; 6657 lreg = treg + 1; 6658 } 6659 else 6660 { 6661 hreg = treg + 1; 6662 lreg = treg; 6663 } 6664 6665 if (hreg <= 31) 6666 load_register (hreg, &imm_expr, 0); 6667 if (lreg <= 31) 6668 { 6669 if (offset_expr.X_op == O_absent) 6670 move_register (lreg, 0); 6671 else 6672 { 6673 assert (offset_expr.X_op == O_constant); 6674 load_register (lreg, &offset_expr, 0); 6675 } 6676 } 6677 } 6678 break; 6679 } 6680 6681 /* We know that sym is in the .rdata section. First we get the 6682 upper 16 bits of the address. */ 6683 if (mips_pic == NO_PIC) 6684 { 6685 macro_build_lui (&offset_expr, AT); 6686 used_at = 1; 6687 } 6688 else 6689 { 6690 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 6691 BFD_RELOC_MIPS_GOT16, mips_gp_register); 6692 used_at = 1; 6693 } 6694 6695 /* Now we load the register(s). */ 6696 if (HAVE_64BIT_GPRS) 6697 { 6698 used_at = 1; 6699 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); 6700 } 6701 else 6702 { 6703 used_at = 1; 6704 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); 6705 if (treg != RA) 6706 { 6707 /* FIXME: How in the world do we deal with the possible 6708 overflow here? */ 6709 offset_expr.X_add_number += 4; 6710 macro_build (&offset_expr, "lw", "t,o(b)", 6711 treg + 1, BFD_RELOC_LO16, AT); 6712 } 6713 } 6714 break; 6715 6716 case M_LI_DD: 6717 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits 6718 wide, IMM_EXPR is the entire value and the GPRs are known to be 64 6719 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of 6720 the value and the low order 32 bits are either zero or in 6721 OFFSET_EXPR. */ 6722 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) 6723 { 6724 used_at = 1; 6725 load_register (AT, &imm_expr, HAVE_64BIT_FPRS); 6726 if (HAVE_64BIT_FPRS) 6727 { 6728 assert (HAVE_64BIT_GPRS); 6729 macro_build (NULL, "dmtc1", "t,S", AT, treg); 6730 } 6731 else 6732 { 6733 macro_build (NULL, "mtc1", "t,G", AT, treg + 1); 6734 if (offset_expr.X_op == O_absent) 6735 macro_build (NULL, "mtc1", "t,G", 0, treg); 6736 else 6737 { 6738 assert (offset_expr.X_op == O_constant); 6739 load_register (AT, &offset_expr, 0); 6740 macro_build (NULL, "mtc1", "t,G", AT, treg); 6741 } 6742 } 6743 break; 6744 } 6745 6746 assert (offset_expr.X_op == O_symbol 6747 && offset_expr.X_add_number == 0); 6748 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); 6749 if (strcmp (s, ".lit8") == 0) 6750 { 6751 if (mips_opts.isa != ISA_MIPS1) 6752 { 6753 macro_build (&offset_expr, "ldc1", "T,o(b)", treg, 6754 BFD_RELOC_MIPS_LITERAL, mips_gp_register); 6755 break; 6756 } 6757 breg = mips_gp_register; 6758 r = BFD_RELOC_MIPS_LITERAL; 6759 goto dob; 6760 } 6761 else 6762 { 6763 assert (strcmp (s, RDATA_SECTION_NAME) == 0); 6764 used_at = 1; 6765 if (mips_pic != NO_PIC) 6766 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 6767 BFD_RELOC_MIPS_GOT16, mips_gp_register); 6768 else 6769 { 6770 /* FIXME: This won't work for a 64 bit address. */ 6771 macro_build_lui (&offset_expr, AT); 6772 } 6773 6774 if (mips_opts.isa != ISA_MIPS1) 6775 { 6776 macro_build (&offset_expr, "ldc1", "T,o(b)", 6777 treg, BFD_RELOC_LO16, AT); 6778 break; 6779 } 6780 breg = AT; 6781 r = BFD_RELOC_LO16; 6782 goto dob; 6783 } 6784 6785 case M_L_DOB: 6786 if (mips_opts.arch == CPU_R4650) 6787 { 6788 as_bad (_("opcode not supported on this processor")); 6789 break; 6790 } 6791 /* Even on a big endian machine $fn comes before $fn+1. We have 6792 to adjust when loading from memory. */ 6793 r = BFD_RELOC_LO16; 6794 dob: 6795 assert (mips_opts.isa == ISA_MIPS1); 6796 macro_build (&offset_expr, "lwc1", "T,o(b)", 6797 target_big_endian ? treg + 1 : treg, r, breg); 6798 /* FIXME: A possible overflow which I don't know how to deal 6799 with. */ 6800 offset_expr.X_add_number += 4; 6801 macro_build (&offset_expr, "lwc1", "T,o(b)", 6802 target_big_endian ? treg : treg + 1, r, breg); 6803 break; 6804 6805 case M_L_DAB: 6806 /* 6807 * The MIPS assembler seems to check for X_add_number not 6808 * being double aligned and generating: 6809 * lui at,%hi(foo+1) 6810 * addu at,at,v1 6811 * addiu at,at,%lo(foo+1) 6812 * lwc1 f2,0(at) 6813 * lwc1 f3,4(at) 6814 * But, the resulting address is the same after relocation so why 6815 * generate the extra instruction? 6816 */ 6817 if (mips_opts.arch == CPU_R4650) 6818 { 6819 as_bad (_("opcode not supported on this processor")); 6820 break; 6821 } 6822 /* Itbl support may require additional care here. */ 6823 coproc = 1; 6824 if (mips_opts.isa != ISA_MIPS1) 6825 { 6826 s = "ldc1"; 6827 goto ld; 6828 } 6829 6830 s = "lwc1"; 6831 fmt = "T,o(b)"; 6832 goto ldd_std; 6833 6834 case M_S_DAB: 6835 if (mips_opts.arch == CPU_R4650) 6836 { 6837 as_bad (_("opcode not supported on this processor")); 6838 break; 6839 } 6840 6841 if (mips_opts.isa != ISA_MIPS1) 6842 { 6843 s = "sdc1"; 6844 goto st; 6845 } 6846 6847 s = "swc1"; 6848 fmt = "T,o(b)"; 6849 /* Itbl support may require additional care here. */ 6850 coproc = 1; 6851 goto ldd_std; 6852 6853 case M_LD_AB: 6854 if (HAVE_64BIT_GPRS) 6855 { 6856 s = "ld"; 6857 goto ld; 6858 } 6859 6860 s = "lw"; 6861 fmt = "t,o(b)"; 6862 goto ldd_std; 6863 6864 case M_SD_AB: 6865 if (HAVE_64BIT_GPRS) 6866 { 6867 s = "sd"; 6868 goto st; 6869 } 6870 6871 s = "sw"; 6872 fmt = "t,o(b)"; 6873 6874 ldd_std: 6875 if (offset_expr.X_op != O_symbol 6876 && offset_expr.X_op != O_constant) 6877 { 6878 as_bad (_("expression too complex")); 6879 offset_expr.X_op = O_constant; 6880 } 6881 6882 if (HAVE_32BIT_ADDRESSES 6883 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) 6884 { 6885 char value [32]; 6886 6887 sprintf_vma (value, offset_expr.X_add_number); 6888 as_bad (_("Number (0x%s) larger than 32 bits"), value); 6889 } 6890 6891 /* Even on a big endian machine $fn comes before $fn+1. We have 6892 to adjust when loading from memory. We set coproc if we must 6893 load $fn+1 first. */ 6894 /* Itbl support may require additional care here. */ 6895 if (! target_big_endian) 6896 coproc = 0; 6897 6898 if (mips_pic == NO_PIC 6899 || offset_expr.X_op == O_constant) 6900 { 6901 /* If this is a reference to a GP relative symbol, we want 6902 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) 6903 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) 6904 If we have a base register, we use this 6905 addu $at,$breg,$gp 6906 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) 6907 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) 6908 If this is not a GP relative symbol, we want 6909 lui $at,<sym> (BFD_RELOC_HI16_S) 6910 <op> $treg,<sym>($at) (BFD_RELOC_LO16) 6911 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) 6912 If there is a base register, we add it to $at after the 6913 lui instruction. If there is a constant, we always use 6914 the last case. */ 6915 if (offset_expr.X_op == O_symbol 6916 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 6917 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 6918 { 6919 relax_start (offset_expr.X_add_symbol); 6920 if (breg == 0) 6921 { 6922 tempreg = mips_gp_register; 6923 } 6924 else 6925 { 6926 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6927 AT, breg, mips_gp_register); 6928 tempreg = AT; 6929 used_at = 1; 6930 } 6931 6932 /* Itbl support may require additional care here. */ 6933 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, 6934 BFD_RELOC_GPREL16, tempreg); 6935 offset_expr.X_add_number += 4; 6936 6937 /* Set mips_optimize to 2 to avoid inserting an 6938 undesired nop. */ 6939 hold_mips_optimize = mips_optimize; 6940 mips_optimize = 2; 6941 /* Itbl support may require additional care here. */ 6942 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, 6943 BFD_RELOC_GPREL16, tempreg); 6944 mips_optimize = hold_mips_optimize; 6945 6946 relax_switch (); 6947 6948 /* We just generated two relocs. When tc_gen_reloc 6949 handles this case, it will skip the first reloc and 6950 handle the second. The second reloc already has an 6951 extra addend of 4, which we added above. We must 6952 subtract it out, and then subtract another 4 to make 6953 the first reloc come out right. The second reloc 6954 will come out right because we are going to add 4 to 6955 offset_expr when we build its instruction below. 6956 6957 If we have a symbol, then we don't want to include 6958 the offset, because it will wind up being included 6959 when we generate the reloc. */ 6960 6961 if (offset_expr.X_op == O_constant) 6962 offset_expr.X_add_number -= 8; 6963 else 6964 { 6965 offset_expr.X_add_number = -4; 6966 offset_expr.X_op = O_constant; 6967 } 6968 } 6969 used_at = 1; 6970 macro_build_lui (&offset_expr, AT); 6971 if (breg != 0) 6972 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 6973 /* Itbl support may require additional care here. */ 6974 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, 6975 BFD_RELOC_LO16, AT); 6976 /* FIXME: How do we handle overflow here? */ 6977 offset_expr.X_add_number += 4; 6978 /* Itbl support may require additional care here. */ 6979 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, 6980 BFD_RELOC_LO16, AT); 6981 if (mips_relax.sequence) 6982 relax_end (); 6983 } 6984 else if (!mips_big_got) 6985 { 6986 /* If this is a reference to an external symbol, we want 6987 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 6988 nop 6989 <op> $treg,0($at) 6990 <op> $treg+1,4($at) 6991 Otherwise we want 6992 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 6993 nop 6994 <op> $treg,<sym>($at) (BFD_RELOC_LO16) 6995 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) 6996 If there is a base register we add it to $at before the 6997 lwc1 instructions. If there is a constant we include it 6998 in the lwc1 instructions. */ 6999 used_at = 1; 7000 expr1.X_add_number = offset_expr.X_add_number; 7001 if (expr1.X_add_number < -0x8000 7002 || expr1.X_add_number >= 0x8000 - 4) 7003 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 7004 load_got_offset (AT, &offset_expr); 7005 load_delay_nop (); 7006 if (breg != 0) 7007 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 7008 7009 /* Set mips_optimize to 2 to avoid inserting an undesired 7010 nop. */ 7011 hold_mips_optimize = mips_optimize; 7012 mips_optimize = 2; 7013 7014 /* Itbl support may require additional care here. */ 7015 relax_start (offset_expr.X_add_symbol); 7016 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, 7017 BFD_RELOC_LO16, AT); 7018 expr1.X_add_number += 4; 7019 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, 7020 BFD_RELOC_LO16, AT); 7021 relax_switch (); 7022 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, 7023 BFD_RELOC_LO16, AT); 7024 offset_expr.X_add_number += 4; 7025 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, 7026 BFD_RELOC_LO16, AT); 7027 relax_end (); 7028 7029 mips_optimize = hold_mips_optimize; 7030 } 7031 else if (mips_big_got) 7032 { 7033 int gpdelay; 7034 7035 /* If this is a reference to an external symbol, we want 7036 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) 7037 addu $at,$at,$gp 7038 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) 7039 nop 7040 <op> $treg,0($at) 7041 <op> $treg+1,4($at) 7042 Otherwise we want 7043 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 7044 nop 7045 <op> $treg,<sym>($at) (BFD_RELOC_LO16) 7046 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) 7047 If there is a base register we add it to $at before the 7048 lwc1 instructions. If there is a constant we include it 7049 in the lwc1 instructions. */ 7050 used_at = 1; 7051 expr1.X_add_number = offset_expr.X_add_number; 7052 offset_expr.X_add_number = 0; 7053 if (expr1.X_add_number < -0x8000 7054 || expr1.X_add_number >= 0x8000 - 4) 7055 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 7056 gpdelay = reg_needs_delay (mips_gp_register); 7057 relax_start (offset_expr.X_add_symbol); 7058 macro_build (&offset_expr, "lui", "t,u", 7059 AT, BFD_RELOC_MIPS_GOT_HI16); 7060 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 7061 AT, AT, mips_gp_register); 7062 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 7063 AT, BFD_RELOC_MIPS_GOT_LO16, AT); 7064 load_delay_nop (); 7065 if (breg != 0) 7066 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 7067 /* Itbl support may require additional care here. */ 7068 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, 7069 BFD_RELOC_LO16, AT); 7070 expr1.X_add_number += 4; 7071 7072 /* Set mips_optimize to 2 to avoid inserting an undesired 7073 nop. */ 7074 hold_mips_optimize = mips_optimize; 7075 mips_optimize = 2; 7076 /* Itbl support may require additional care here. */ 7077 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, 7078 BFD_RELOC_LO16, AT); 7079 mips_optimize = hold_mips_optimize; 7080 expr1.X_add_number -= 4; 7081 7082 relax_switch (); 7083 offset_expr.X_add_number = expr1.X_add_number; 7084 if (gpdelay) 7085 macro_build (NULL, "nop", ""); 7086 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 7087 BFD_RELOC_MIPS_GOT16, mips_gp_register); 7088 load_delay_nop (); 7089 if (breg != 0) 7090 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 7091 /* Itbl support may require additional care here. */ 7092 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, 7093 BFD_RELOC_LO16, AT); 7094 offset_expr.X_add_number += 4; 7095 7096 /* Set mips_optimize to 2 to avoid inserting an undesired 7097 nop. */ 7098 hold_mips_optimize = mips_optimize; 7099 mips_optimize = 2; 7100 /* Itbl support may require additional care here. */ 7101 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, 7102 BFD_RELOC_LO16, AT); 7103 mips_optimize = hold_mips_optimize; 7104 relax_end (); 7105 } 7106 else 7107 abort (); 7108 7109 break; 7110 7111 case M_LD_OB: 7112 s = "lw"; 7113 goto sd_ob; 7114 case M_SD_OB: 7115 s = "sw"; 7116 sd_ob: 7117 assert (HAVE_32BIT_ADDRESSES); 7118 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); 7119 offset_expr.X_add_number += 4; 7120 macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); 7121 break; 7122 7123 case M_SAA_AB: 7124 s = "saa"; 7125 goto saa_saad; 7126 7127 case M_SAAD_AB: 7128 s = "saad"; 7129 7130 saa_saad: 7131 /* The "saa/saad" instructions are new in CN58XX. These instructions 7132 do not specify offset. When invoked with address or symbol, then 7133 load the address or value of symbol in a register using the dla macro 7134 into AT, and pass the register for emitting "saa/saad" instruction. 7135 This will get expanded to 7136 7137 dla AT, constant/label 7138 saa/saad $treg,(AT) */ 7139 { 7140 char *name = "dla"; 7141 char *fmt = "t,A(b)"; 7142 const struct mips_opcode *mo; 7143 struct mips_cl_insn insn; 7144 7145 mo = hash_find (op_hash, name); 7146 assert (strcmp (name, mo->name) == 0); 7147 assert (strcmp (fmt, mo->args) == 0); 7148 create_insn (&insn, mo); 7149 7150 insn.insn_opcode = insn.insn_mo->match; 7151 7152 used_at = 1; 7153 INSERT_OPERAND (RT, insn, AT); 7154 if (breg) 7155 INSERT_OPERAND (RS, insn, breg); 7156 7157 /* The address part is forwarded through the global offset_expr. */ 7158 macro (&insn); 7159 7160 macro_build (NULL, s, "t,(b)", treg, AT); 7161 break; 7162 } 7163 7164 /* New code added to support COPZ instructions. 7165 This code builds table entries out of the macros in mip_opcodes. 7166 R4000 uses interlocks to handle coproc delays. 7167 Other chips (like the R3000) require nops to be inserted for delays. 7168 7169 FIXME: Currently, we require that the user handle delays. 7170 In order to fill delay slots for non-interlocked chips, 7171 we must have a way to specify delays based on the coprocessor. 7172 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. 7173 What are the side-effects of the cop instruction? 7174 What cache support might we have and what are its effects? 7175 Both coprocessor & memory require delays. how long??? 7176 What registers are read/set/modified? 7177 7178 If an itbl is provided to interpret cop instructions, 7179 this knowledge can be encoded in the itbl spec. */ 7180 7181 case M_COP0: 7182 s = "c0"; 7183 goto copz; 7184 case M_COP1: 7185 s = "c1"; 7186 goto copz; 7187 case M_COP2: 7188 s = "c2"; 7189 goto copz; 7190 case M_COP3: 7191 s = "c3"; 7192 copz: 7193 if (!strcmp (s,"c2") && mips_opts.arch == CPU_OCTEON 7194 && octeon_error_on_unsupported) 7195 { 7196 as_bad (_("opcode not implemented in Octeon `%s'"), ip->insn_mo->name); 7197 return; 7198 } 7199 /* For now we just do C (same as Cz). The parameter will be 7200 stored in insn_opcode by mips_ip. */ 7201 macro_build (NULL, s, "C", ip->insn_opcode); 7202 break; 7203 7204 case M_MOVE: 7205 move_register (dreg, sreg); 7206 break; 7207 7208#ifdef LOSING_COMPILER 7209 default: 7210 /* Try and see if this is a new itbl instruction. 7211 This code builds table entries out of the macros in mip_opcodes. 7212 FIXME: For now we just assemble the expression and pass it's 7213 value along as a 32-bit immediate. 7214 We may want to have the assembler assemble this value, 7215 so that we gain the assembler's knowledge of delay slots, 7216 symbols, etc. 7217 Would it be more efficient to use mask (id) here? */ 7218 if (itbl_have_entries 7219 && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) 7220 { 7221 s = ip->insn_mo->name; 7222 s2 = "cop3"; 7223 coproc = ITBL_DECODE_PNUM (immed_expr);; 7224 macro_build (&immed_expr, s, "C"); 7225 break; 7226 } 7227 macro2 (ip); 7228 break; 7229 } 7230 if (mips_opts.noat && used_at) 7231 as_bad (_("Macro used $at after \".set noat\"")); 7232} 7233 7234static void 7235macro2 (struct mips_cl_insn *ip) 7236{ 7237 int treg, sreg, dreg, breg; 7238 int tempreg; 7239 int mask; 7240 int used_at; 7241 expressionS expr1; 7242 const char *s; 7243 const char *s2; 7244 const char *fmt; 7245 int likely = 0; 7246 int dbl = 0; 7247 int coproc = 0; 7248 int lr = 0; 7249 int imm = 0; 7250 int off; 7251 offsetT maxnum; 7252 bfd_reloc_code_real_type r; 7253 7254 treg = (ip->insn_opcode >> 16) & 0x1f; 7255 dreg = (ip->insn_opcode >> 11) & 0x1f; 7256 sreg = breg = (ip->insn_opcode >> 21) & 0x1f; 7257 mask = ip->insn_mo->mask; 7258 7259 expr1.X_op = O_constant; 7260 expr1.X_op_symbol = NULL; 7261 expr1.X_add_symbol = NULL; 7262 expr1.X_add_number = 1; 7263 7264 switch (mask) 7265 { 7266#endif /* LOSING_COMPILER */ 7267 7268 case M_DMUL: 7269 dbl = 1; 7270 case M_MUL: 7271 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); 7272 macro_build (NULL, "mflo", "d", dreg); 7273 break; 7274 7275 case M_DMUL_I: 7276 dbl = 1; 7277 case M_MUL_I: 7278 /* The MIPS assembler some times generates shifts and adds. I'm 7279 not trying to be that fancy. GCC should do this for us 7280 anyway. */ 7281 used_at = 1; 7282 load_register (AT, &imm_expr, dbl); 7283 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); 7284 macro_build (NULL, "mflo", "d", dreg); 7285 break; 7286 7287 case M_DMULO_I: 7288 dbl = 1; 7289 case M_MULO_I: 7290 imm = 1; 7291 goto do_mulo; 7292 7293 case M_DMULO: 7294 dbl = 1; 7295 case M_MULO: 7296 do_mulo: 7297 start_noreorder (); 7298 used_at = 1; 7299 if (imm) 7300 load_register (AT, &imm_expr, dbl); 7301 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); 7302 macro_build (NULL, "mflo", "d", dreg); 7303 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); 7304 macro_build (NULL, "mfhi", "d", AT); 7305 if (mips_trap) 7306 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); 7307 else 7308 { 7309 expr1.X_add_number = 8; 7310 macro_build (&expr1, "beq", "s,t,p", dreg, AT); 7311 macro_build (NULL, "nop", "", 0); 7312 macro_build (NULL, "break", "c", 6); 7313 } 7314 end_noreorder (); 7315 macro_build (NULL, "mflo", "d", dreg); 7316 break; 7317 7318 case M_DMULOU_I: 7319 dbl = 1; 7320 case M_MULOU_I: 7321 imm = 1; 7322 goto do_mulou; 7323 7324 case M_DMULOU: 7325 dbl = 1; 7326 case M_MULOU: 7327 do_mulou: 7328 start_noreorder (); 7329 used_at = 1; 7330 if (imm) 7331 load_register (AT, &imm_expr, dbl); 7332 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", 7333 sreg, imm ? AT : treg); 7334 macro_build (NULL, "mfhi", "d", AT); 7335 macro_build (NULL, "mflo", "d", dreg); 7336 if (mips_trap) 7337 macro_build (NULL, "tne", "s,t,q", AT, 0, 6); 7338 else 7339 { 7340 expr1.X_add_number = 8; 7341 macro_build (&expr1, "beq", "s,t,p", AT, 0); 7342 macro_build (NULL, "nop", "", 0); 7343 macro_build (NULL, "break", "c", 6); 7344 } 7345 end_noreorder (); 7346 break; 7347 7348 case M_DROL: 7349 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 7350 { 7351 if (dreg == sreg) 7352 { 7353 tempreg = AT; 7354 used_at = 1; 7355 } 7356 else 7357 { 7358 tempreg = dreg; 7359 } 7360 macro_build (NULL, "dnegu", "d,w", tempreg, treg); 7361 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); 7362 break; 7363 } 7364 used_at = 1; 7365 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); 7366 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); 7367 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); 7368 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7369 break; 7370 7371 case M_ROL: 7372 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 7373 { 7374 if (dreg == sreg) 7375 { 7376 tempreg = AT; 7377 used_at = 1; 7378 } 7379 else 7380 { 7381 tempreg = dreg; 7382 } 7383 macro_build (NULL, "negu", "d,w", tempreg, treg); 7384 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); 7385 break; 7386 } 7387 used_at = 1; 7388 macro_build (NULL, "subu", "d,v,t", AT, 0, treg); 7389 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); 7390 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); 7391 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7392 break; 7393 7394 case M_DROL_I: 7395 { 7396 unsigned int rot; 7397 char *l, *r; 7398 7399 if (imm_expr.X_op != O_constant) 7400 as_bad (_("Improper rotate count")); 7401 rot = imm_expr.X_add_number & 0x3f; 7402 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 7403 { 7404 rot = (64 - rot) & 0x3f; 7405 if (rot >= 32) 7406 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); 7407 else 7408 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); 7409 break; 7410 } 7411 if (rot == 0) 7412 { 7413 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); 7414 break; 7415 } 7416 l = (rot < 0x20) ? "dsll" : "dsll32"; 7417 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; 7418 rot &= 0x1f; 7419 used_at = 1; 7420 macro_build (NULL, l, "d,w,<", AT, sreg, rot); 7421 macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); 7422 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7423 } 7424 break; 7425 7426 case M_ROL_I: 7427 { 7428 unsigned int rot; 7429 7430 if (imm_expr.X_op != O_constant) 7431 as_bad (_("Improper rotate count")); 7432 rot = imm_expr.X_add_number & 0x1f; 7433 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 7434 { 7435 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); 7436 break; 7437 } 7438 if (rot == 0) 7439 { 7440 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); 7441 break; 7442 } 7443 used_at = 1; 7444 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); 7445 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); 7446 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7447 } 7448 break; 7449 7450 case M_DROR: 7451 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 7452 { 7453 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); 7454 break; 7455 } 7456 used_at = 1; 7457 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); 7458 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); 7459 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); 7460 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7461 break; 7462 7463 case M_ROR: 7464 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 7465 { 7466 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); 7467 break; 7468 } 7469 used_at = 1; 7470 macro_build (NULL, "subu", "d,v,t", AT, 0, treg); 7471 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); 7472 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); 7473 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7474 break; 7475 7476 case M_DROR_I: 7477 { 7478 unsigned int rot; 7479 char *l, *r; 7480 7481 if (imm_expr.X_op != O_constant) 7482 as_bad (_("Improper rotate count")); 7483 rot = imm_expr.X_add_number & 0x3f; 7484 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 7485 { 7486 if (rot >= 32) 7487 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); 7488 else 7489 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); 7490 break; 7491 } 7492 if (rot == 0) 7493 { 7494 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); 7495 break; 7496 } 7497 r = (rot < 0x20) ? "dsrl" : "dsrl32"; 7498 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; 7499 rot &= 0x1f; 7500 used_at = 1; 7501 macro_build (NULL, r, "d,w,<", AT, sreg, rot); 7502 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); 7503 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7504 } 7505 break; 7506 7507 case M_ROR_I: 7508 { 7509 unsigned int rot; 7510 7511 if (imm_expr.X_op != O_constant) 7512 as_bad (_("Improper rotate count")); 7513 rot = imm_expr.X_add_number & 0x1f; 7514 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 7515 { 7516 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); 7517 break; 7518 } 7519 if (rot == 0) 7520 { 7521 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); 7522 break; 7523 } 7524 used_at = 1; 7525 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); 7526 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); 7527 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7528 } 7529 break; 7530 7531 case M_S_DOB: 7532 if (mips_opts.arch == CPU_R4650) 7533 { 7534 as_bad (_("opcode not supported on this processor")); 7535 break; 7536 } 7537 assert (mips_opts.isa == ISA_MIPS1); 7538 /* Even on a big endian machine $fn comes before $fn+1. We have 7539 to adjust when storing to memory. */ 7540 macro_build (&offset_expr, "swc1", "T,o(b)", 7541 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); 7542 offset_expr.X_add_number += 4; 7543 macro_build (&offset_expr, "swc1", "T,o(b)", 7544 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); 7545 break; 7546 7547 case M_SEQ: 7548 if (sreg == 0) 7549 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); 7550 else if (treg == 0) 7551 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); 7552 else 7553 { 7554 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); 7555 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); 7556 } 7557 break; 7558 7559 case M_SEQ_I: 7560 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 7561 { 7562 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); 7563 break; 7564 } 7565 if (sreg == 0) 7566 { 7567 as_warn (_("Instruction %s: result is always false"), 7568 ip->insn_mo->name); 7569 move_register (dreg, 0); 7570 break; 7571 } 7572 if (imm_expr.X_op == O_constant 7573 && imm_expr.X_add_number >= 0 7574 && imm_expr.X_add_number < 0x10000) 7575 { 7576 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); 7577 } 7578 else if (imm_expr.X_op == O_constant 7579 && imm_expr.X_add_number > -0x8000 7580 && imm_expr.X_add_number < 0) 7581 { 7582 imm_expr.X_add_number = -imm_expr.X_add_number; 7583 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", 7584 "t,r,j", dreg, sreg, BFD_RELOC_LO16); 7585 } 7586 else 7587 { 7588 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7589 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); 7590 used_at = 1; 7591 } 7592 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); 7593 break; 7594 7595 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ 7596 s = "slt"; 7597 goto sge; 7598 case M_SGEU: 7599 s = "sltu"; 7600 sge: 7601 macro_build (NULL, s, "d,v,t", dreg, sreg, treg); 7602 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); 7603 break; 7604 7605 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ 7606 case M_SGEU_I: 7607 if (imm_expr.X_op == O_constant 7608 && imm_expr.X_add_number >= -0x8000 7609 && imm_expr.X_add_number < 0x8000) 7610 { 7611 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", 7612 dreg, sreg, BFD_RELOC_LO16); 7613 } 7614 else 7615 { 7616 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7617 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", 7618 dreg, sreg, AT); 7619 used_at = 1; 7620 } 7621 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); 7622 break; 7623 7624 case M_SGT: /* sreg > treg <==> treg < sreg */ 7625 s = "slt"; 7626 goto sgt; 7627 case M_SGTU: 7628 s = "sltu"; 7629 sgt: 7630 macro_build (NULL, s, "d,v,t", dreg, treg, sreg); 7631 break; 7632 7633 case M_SGT_I: /* sreg > I <==> I < sreg */ 7634 s = "slt"; 7635 goto sgti; 7636 case M_SGTU_I: 7637 s = "sltu"; 7638 sgti: 7639 used_at = 1; 7640 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7641 macro_build (NULL, s, "d,v,t", dreg, AT, sreg); 7642 break; 7643 7644 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ 7645 s = "slt"; 7646 goto sle; 7647 case M_SLEU: 7648 s = "sltu"; 7649 sle: 7650 macro_build (NULL, s, "d,v,t", dreg, treg, sreg); 7651 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); 7652 break; 7653 7654 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ 7655 s = "slt"; 7656 goto slei; 7657 case M_SLEU_I: 7658 s = "sltu"; 7659 slei: 7660 used_at = 1; 7661 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7662 macro_build (NULL, s, "d,v,t", dreg, AT, sreg); 7663 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); 7664 break; 7665 7666 case M_SLT_I: 7667 if (imm_expr.X_op == O_constant 7668 && imm_expr.X_add_number >= -0x8000 7669 && imm_expr.X_add_number < 0x8000) 7670 { 7671 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); 7672 break; 7673 } 7674 used_at = 1; 7675 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7676 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); 7677 break; 7678 7679 case M_SLTU_I: 7680 if (imm_expr.X_op == O_constant 7681 && imm_expr.X_add_number >= -0x8000 7682 && imm_expr.X_add_number < 0x8000) 7683 { 7684 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, 7685 BFD_RELOC_LO16); 7686 break; 7687 } 7688 used_at = 1; 7689 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7690 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); 7691 break; 7692 7693 case M_SNE: 7694 if (sreg == 0) 7695 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); 7696 else if (treg == 0) 7697 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); 7698 else 7699 { 7700 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); 7701 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); 7702 } 7703 break; 7704 7705 case M_SNE_I: 7706 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 7707 { 7708 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); 7709 break; 7710 } 7711 if (sreg == 0) 7712 { 7713 as_warn (_("Instruction %s: result is always true"), 7714 ip->insn_mo->name); 7715 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", 7716 dreg, 0, BFD_RELOC_LO16); 7717 break; 7718 } 7719 if (imm_expr.X_op == O_constant 7720 && imm_expr.X_add_number >= 0 7721 && imm_expr.X_add_number < 0x10000) 7722 { 7723 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); 7724 } 7725 else if (imm_expr.X_op == O_constant 7726 && imm_expr.X_add_number > -0x8000 7727 && imm_expr.X_add_number < 0) 7728 { 7729 imm_expr.X_add_number = -imm_expr.X_add_number; 7730 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", 7731 "t,r,j", dreg, sreg, BFD_RELOC_LO16); 7732 } 7733 else 7734 { 7735 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7736 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); 7737 used_at = 1; 7738 } 7739 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); 7740 break; 7741 7742 case M_DSUB_I: 7743 dbl = 1; 7744 case M_SUB_I: 7745 if (imm_expr.X_op == O_constant 7746 && imm_expr.X_add_number > -0x8000 7747 && imm_expr.X_add_number <= 0x8000) 7748 { 7749 imm_expr.X_add_number = -imm_expr.X_add_number; 7750 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", 7751 dreg, sreg, BFD_RELOC_LO16); 7752 break; 7753 } 7754 used_at = 1; 7755 load_register (AT, &imm_expr, dbl); 7756 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); 7757 break; 7758 7759 case M_DSUBU_I: 7760 dbl = 1; 7761 case M_SUBU_I: 7762 if (imm_expr.X_op == O_constant 7763 && imm_expr.X_add_number > -0x8000 7764 && imm_expr.X_add_number <= 0x8000) 7765 { 7766 imm_expr.X_add_number = -imm_expr.X_add_number; 7767 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", 7768 dreg, sreg, BFD_RELOC_LO16); 7769 break; 7770 } 7771 used_at = 1; 7772 load_register (AT, &imm_expr, dbl); 7773 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); 7774 break; 7775 7776 case M_TEQ_I: 7777 s = "teq"; 7778 goto trap; 7779 case M_TGE_I: 7780 s = "tge"; 7781 goto trap; 7782 case M_TGEU_I: 7783 s = "tgeu"; 7784 goto trap; 7785 case M_TLT_I: 7786 s = "tlt"; 7787 goto trap; 7788 case M_TLTU_I: 7789 s = "tltu"; 7790 goto trap; 7791 case M_TNE_I: 7792 s = "tne"; 7793 trap: 7794 used_at = 1; 7795 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7796 macro_build (NULL, s, "s,t", sreg, AT); 7797 break; 7798 7799 case M_TRUNCWS: 7800 case M_TRUNCWD: 7801 if (mips_opts.arch == CPU_OCTEON && octeon_error_on_unsupported) 7802 { 7803 as_bad (_("opcode not implemented in Octeon `%s'"), ip->insn_mo->name); 7804 return; 7805 } 7806 assert (mips_opts.isa == ISA_MIPS1); 7807 used_at = 1; 7808 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ 7809 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ 7810 7811 /* 7812 * Is the double cfc1 instruction a bug in the mips assembler; 7813 * or is there a reason for it? 7814 */ 7815 start_noreorder (); 7816 macro_build (NULL, "cfc1", "t,G", treg, RA); 7817 macro_build (NULL, "cfc1", "t,G", treg, RA); 7818 macro_build (NULL, "nop", ""); 7819 expr1.X_add_number = 3; 7820 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); 7821 expr1.X_add_number = 2; 7822 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); 7823 macro_build (NULL, "ctc1", "t,G", AT, RA); 7824 macro_build (NULL, "nop", ""); 7825 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", 7826 dreg, sreg); 7827 macro_build (NULL, "ctc1", "t,G", treg, RA); 7828 macro_build (NULL, "nop", ""); 7829 end_noreorder (); 7830 break; 7831 7832 case M_ULH: 7833 s = "lb"; 7834 goto ulh; 7835 case M_ULHU: 7836 s = "lbu"; 7837 ulh: 7838 used_at = 1; 7839 if (offset_expr.X_add_number >= 0x7fff) 7840 as_bad (_("operand overflow")); 7841 /* Expand the ulh to "lb, lbu, ins" instead of "lb, lbu, sll, ori". */ 7842 if (! target_big_endian) 7843 ++offset_expr.X_add_number; 7844 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); 7845 if (! target_big_endian) 7846 --offset_expr.X_add_number; 7847 else 7848 ++offset_expr.X_add_number; 7849 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); 7850 if (ISA_HAS_INS (mips_opts.isa)) 7851 macro_build (NULL, "ins", "t,r,+A,+B", treg, AT, 8, 31); 7852 else 7853 { 7854 macro_build (NULL, "sll", "d,w,<", AT, AT, 8); 7855 macro_build (NULL, "or", "d,v,t", treg, treg, AT); 7856 } 7857 break; 7858 7859 case M_ULD: 7860 s = "ldl"; 7861 s2 = "ldr"; 7862 off = 7; 7863 goto ulw; 7864 case M_ULW: 7865 s = "lwl"; 7866 s2 = "lwr"; 7867 off = 3; 7868 ulw: 7869 if (offset_expr.X_add_number >= 0x8000 - off) 7870 as_bad (_("operand overflow")); 7871 if (treg != breg) 7872 tempreg = treg; 7873 else 7874 { 7875 used_at = 1; 7876 tempreg = AT; 7877 } 7878 7879 /* For small variables the compiler uses gp_rel to load the value of 7880 the variables. While parsing instructions "uld $2,%gp_rel(var)($28)" 7881 the offset_reloc[0] is set to BFD_RELOC_GPREL16. Use this relocation 7882 type while emitting instructions otherwise use BFD_RELOC_LO16. */ 7883 if (offset_reloc[0] == BFD_RELOC_UNUSED) 7884 offset_reloc[0] = BFD_RELOC_LO16; 7885 7886 if (octeon_use_unalign && mips_opts.arch == CPU_OCTEON) 7887 { 7888 /* Reset used_at as tempreg is not used while generating Octeon 7889 unaligned load/store. */ 7890 used_at = 0; 7891 macro_build (&offset_expr, (mask == M_ULW ? "ulw" : "uld"), "t,o(b)", 7892 treg, offset_reloc[0], breg); 7893 break; 7894 } 7895 7896 if (! target_big_endian) 7897 offset_expr.X_add_number += off; 7898 macro_build (&offset_expr, s, "t,o(b)", tempreg, offset_reloc[0], breg); 7899 if (! target_big_endian) 7900 offset_expr.X_add_number -= off; 7901 else 7902 offset_expr.X_add_number += off; 7903 macro_build (&offset_expr, s2, "t,o(b)", tempreg, offset_reloc[0], breg); 7904 7905 /* If necessary, move the result in tempreg the final destination. */ 7906 if (treg == tempreg) 7907 break; 7908 /* Protect second load's delay slot. */ 7909 load_delay_nop (); 7910 move_register (treg, tempreg); 7911 break; 7912 7913 case M_ULD_A: 7914 s = "ldl"; 7915 s2 = "ldr"; 7916 off = 7; 7917 goto ulwa; 7918 case M_ULW_A: 7919 s = "lwl"; 7920 s2 = "lwr"; 7921 off = 3; 7922 ulwa: 7923 used_at = 1; 7924 load_address (AT, &offset_expr, &used_at); 7925 if (breg != 0) 7926 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); 7927 7928 /* For small variables the compiler uses gp_rel to load the value of 7929 the variables. While parsing instructions "uld $2,%gp_rel(var)($28)" 7930 the offset_reloc[0] is set to BFD_RELOC_GPREL16. Use this relocation 7931 type while emitting instructions otherwise use BFD_RELOC_LO16. */ 7932 if (offset_reloc[0] == BFD_RELOC_UNUSED) 7933 offset_reloc[0] = BFD_RELOC_LO16; 7934 7935 if (octeon_use_unalign && mips_opts.arch == CPU_OCTEON) 7936 { 7937 macro_build (&offset_expr, (mask == M_ULW_A ? "ulw" : "uld"), 7938 "t,o(b)", treg, offset_reloc[0], AT); 7939 break; 7940 } 7941 7942 if (! target_big_endian) 7943 expr1.X_add_number = off; 7944 else 7945 expr1.X_add_number = 0; 7946 macro_build (&expr1, s, "t,o(b)", treg, offset_reloc[0], AT); 7947 if (! target_big_endian) 7948 expr1.X_add_number = 0; 7949 else 7950 expr1.X_add_number = off; 7951 macro_build (&expr1, s2, "t,o(b)", treg, offset_reloc[0], AT); 7952 break; 7953 7954 case M_ULH_A: 7955 case M_ULHU_A: 7956 used_at = 1; 7957 load_address (AT, &offset_expr, &used_at); 7958 if (breg != 0) 7959 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); 7960 7961 if (ISA_HAS_INS (mips_opts.isa)) 7962 { 7963 if (target_big_endian) 7964 expr1.X_add_number = 1; 7965 else 7966 expr1.X_add_number = 0; 7967 macro_build (&expr1, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, AT); 7968 if (target_big_endian) 7969 expr1.X_add_number = 0; 7970 else 7971 expr1.X_add_number = 1; 7972 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", 7973 AT, BFD_RELOC_LO16, AT); 7974 macro_build (NULL, "ins", "t,r,+A,+B", treg, AT, 8, 31); 7975 break; 7976 } 7977 if (target_big_endian) 7978 expr1.X_add_number = 0; 7979 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", 7980 treg, BFD_RELOC_LO16, AT); 7981 if (target_big_endian) 7982 expr1.X_add_number = 1; 7983 else 7984 expr1.X_add_number = 0; 7985 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); 7986 macro_build (NULL, "sll", "d,w,<", treg, treg, 8); 7987 macro_build (NULL, "or", "d,v,t", treg, treg, AT); 7988 break; 7989 7990 case M_USH: 7991 used_at = 1; 7992 if (offset_expr.X_add_number >= 0x7fff) 7993 as_bad (_("operand overflow")); 7994 if (target_big_endian) 7995 ++offset_expr.X_add_number; 7996 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); 7997 macro_build (NULL, "srl", "d,w,<", AT, treg, 8); 7998 if (target_big_endian) 7999 --offset_expr.X_add_number; 8000 else 8001 ++offset_expr.X_add_number; 8002 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); 8003 break; 8004 8005 case M_USD: 8006 s = "sdl"; 8007 s2 = "sdr"; 8008 off = 7; 8009 goto usw; 8010 case M_USW: 8011 s = "swl"; 8012 s2 = "swr"; 8013 off = 3; 8014 usw: 8015 if (offset_expr.X_add_number >= 0x8000 - off) 8016 as_bad (_("operand overflow")); 8017 8018 /* For small variables the compiler uses gp_rel to load the value of 8019 the variables. While parsing instructions "uld $2,%gp_rel(var)($28)" 8020 the offset_reloc[0] is set to BFD_RELOC_GPREL16. Use this relocation 8021 type while emitting instructions otherwise use BFD_RELOC_LO16. */ 8022 if (offset_reloc[0] == BFD_RELOC_UNUSED) 8023 offset_reloc[0] = BFD_RELOC_LO16; 8024 8025 if (octeon_use_unalign && mips_opts.arch == CPU_OCTEON) 8026 { 8027 macro_build (&offset_expr, (mask == M_USD ? "usd" : "usw"), 8028 "t,o(b)", treg, offset_reloc[0], breg); 8029 break; 8030 } 8031 if (! target_big_endian) 8032 offset_expr.X_add_number += off; 8033 macro_build (&offset_expr, s, "t,o(b)", treg, offset_reloc[0], breg); 8034 if (! target_big_endian) 8035 offset_expr.X_add_number -= off; 8036 else 8037 offset_expr.X_add_number += off; 8038 macro_build (&offset_expr, s2, "t,o(b)", treg, offset_reloc[0], breg); 8039 break; 8040 8041 case M_USD_A: 8042 s = "sdl"; 8043 s2 = "sdr"; 8044 off = 7; 8045 goto uswa; 8046 case M_USW_A: 8047 s = "swl"; 8048 s2 = "swr"; 8049 off = 3; 8050 uswa: 8051 used_at = 1; 8052 load_address (AT, &offset_expr, &used_at); 8053 if (breg != 0) 8054 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); 8055 8056 /* For small variables the compiler uses gp_rel to load the value of 8057 the variables. While parsing instructions "uld $2,%gp_rel(var)($28)" 8058 the offset_reloc[0] is set to BFD_RELOC_GPREL16. Use this relocation 8059 type while emitting instructions otherwise use BFD_RELOC_LO16. */ 8060 if (offset_reloc[0] == BFD_RELOC_UNUSED) 8061 offset_reloc[0] = BFD_RELOC_LO16; 8062 8063 if (octeon_use_unalign && mips_opts.arch == CPU_OCTEON) 8064 { 8065 macro_build (&offset_expr, (mask == M_USW_A ? "usw" : "usd"), 8066 "t,o(b)", treg, offset_reloc[0], AT); 8067 break; 8068 } 8069 if (! target_big_endian) 8070 expr1.X_add_number = off; 8071 else 8072 expr1.X_add_number = 0; 8073 macro_build (&expr1, s, "t,o(b)", treg, offset_reloc[0], AT); 8074 if (! target_big_endian) 8075 expr1.X_add_number = 0; 8076 else 8077 expr1.X_add_number = off; 8078 macro_build (&expr1, s2, "t,o(b)", treg, offset_reloc[0], AT); 8079 break; 8080 8081 case M_USH_A: 8082 used_at = 1; 8083 load_address (AT, &offset_expr, &used_at); 8084 if (breg != 0) 8085 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); 8086 if (! target_big_endian) 8087 expr1.X_add_number = 0; 8088 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); 8089 macro_build (NULL, "srl", "d,w,<", treg, treg, 8); 8090 if (! target_big_endian) 8091 expr1.X_add_number = 1; 8092 else 8093 expr1.X_add_number = 0; 8094 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); 8095 if (! target_big_endian) 8096 expr1.X_add_number = 0; 8097 else 8098 expr1.X_add_number = 1; 8099 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); 8100 macro_build (NULL, "sll", "d,w,<", treg, treg, 8); 8101 macro_build (NULL, "or", "d,v,t", treg, treg, AT); 8102 break; 8103 8104 default: 8105 /* FIXME: Check if this is one of the itbl macros, since they 8106 are added dynamically. */ 8107 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); 8108 break; 8109 } 8110 if (mips_opts.noat && used_at) 8111 as_bad (_("Macro used $at after \".set noat\"")); 8112} 8113 8114/* Implement macros in mips16 mode. */ 8115 8116static void 8117mips16_macro (struct mips_cl_insn *ip) 8118{ 8119 int mask; 8120 int xreg, yreg, zreg, tmp; 8121 expressionS expr1; 8122 int dbl; 8123 const char *s, *s2, *s3; 8124 8125 mask = ip->insn_mo->mask; 8126 8127 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); 8128 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); 8129 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); 8130 8131 expr1.X_op = O_constant; 8132 expr1.X_op_symbol = NULL; 8133 expr1.X_add_symbol = NULL; 8134 expr1.X_add_number = 1; 8135 8136 dbl = 0; 8137 8138 switch (mask) 8139 { 8140 default: 8141 internalError (); 8142 8143 case M_DDIV_3: 8144 dbl = 1; 8145 case M_DIV_3: 8146 s = "mflo"; 8147 goto do_div3; 8148 case M_DREM_3: 8149 dbl = 1; 8150 case M_REM_3: 8151 s = "mfhi"; 8152 do_div3: 8153 start_noreorder (); 8154 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); 8155 expr1.X_add_number = 2; 8156 macro_build (&expr1, "bnez", "x,p", yreg); 8157 macro_build (NULL, "break", "6", 7); 8158 8159 /* FIXME: The normal code checks for of -1 / -0x80000000 here, 8160 since that causes an overflow. We should do that as well, 8161 but I don't see how to do the comparisons without a temporary 8162 register. */ 8163 end_noreorder (); 8164 macro_build (NULL, s, "x", zreg); 8165 break; 8166 8167 case M_DIVU_3: 8168 s = "divu"; 8169 s2 = "mflo"; 8170 goto do_divu3; 8171 case M_REMU_3: 8172 s = "divu"; 8173 s2 = "mfhi"; 8174 goto do_divu3; 8175 case M_DDIVU_3: 8176 s = "ddivu"; 8177 s2 = "mflo"; 8178 goto do_divu3; 8179 case M_DREMU_3: 8180 s = "ddivu"; 8181 s2 = "mfhi"; 8182 do_divu3: 8183 start_noreorder (); 8184 macro_build (NULL, s, "0,x,y", xreg, yreg); 8185 expr1.X_add_number = 2; 8186 macro_build (&expr1, "bnez", "x,p", yreg); 8187 macro_build (NULL, "break", "6", 7); 8188 end_noreorder (); 8189 macro_build (NULL, s2, "x", zreg); 8190 break; 8191 8192 case M_DMUL: 8193 dbl = 1; 8194 case M_MUL: 8195 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); 8196 macro_build (NULL, "mflo", "x", zreg); 8197 break; 8198 8199 case M_DSUBU_I: 8200 dbl = 1; 8201 goto do_subu; 8202 case M_SUBU_I: 8203 do_subu: 8204 if (imm_expr.X_op != O_constant) 8205 as_bad (_("Unsupported large constant")); 8206 imm_expr.X_add_number = -imm_expr.X_add_number; 8207 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); 8208 break; 8209 8210 case M_SUBU_I_2: 8211 if (imm_expr.X_op != O_constant) 8212 as_bad (_("Unsupported large constant")); 8213 imm_expr.X_add_number = -imm_expr.X_add_number; 8214 macro_build (&imm_expr, "addiu", "x,k", xreg); 8215 break; 8216 8217 case M_DSUBU_I_2: 8218 if (imm_expr.X_op != O_constant) 8219 as_bad (_("Unsupported large constant")); 8220 imm_expr.X_add_number = -imm_expr.X_add_number; 8221 macro_build (&imm_expr, "daddiu", "y,j", yreg); 8222 break; 8223 8224 case M_BEQ: 8225 s = "cmp"; 8226 s2 = "bteqz"; 8227 goto do_branch; 8228 case M_BNE: 8229 s = "cmp"; 8230 s2 = "btnez"; 8231 goto do_branch; 8232 case M_BLT: 8233 s = "slt"; 8234 s2 = "btnez"; 8235 goto do_branch; 8236 case M_BLTU: 8237 s = "sltu"; 8238 s2 = "btnez"; 8239 goto do_branch; 8240 case M_BLE: 8241 s = "slt"; 8242 s2 = "bteqz"; 8243 goto do_reverse_branch; 8244 case M_BLEU: 8245 s = "sltu"; 8246 s2 = "bteqz"; 8247 goto do_reverse_branch; 8248 case M_BGE: 8249 s = "slt"; 8250 s2 = "bteqz"; 8251 goto do_branch; 8252 case M_BGEU: 8253 s = "sltu"; 8254 s2 = "bteqz"; 8255 goto do_branch; 8256 case M_BGT: 8257 s = "slt"; 8258 s2 = "btnez"; 8259 goto do_reverse_branch; 8260 case M_BGTU: 8261 s = "sltu"; 8262 s2 = "btnez"; 8263 8264 do_reverse_branch: 8265 tmp = xreg; 8266 xreg = yreg; 8267 yreg = tmp; 8268 8269 do_branch: 8270 macro_build (NULL, s, "x,y", xreg, yreg); 8271 macro_build (&offset_expr, s2, "p"); 8272 break; 8273 8274 case M_BEQ_I: 8275 s = "cmpi"; 8276 s2 = "bteqz"; 8277 s3 = "x,U"; 8278 goto do_branch_i; 8279 case M_BNE_I: 8280 s = "cmpi"; 8281 s2 = "btnez"; 8282 s3 = "x,U"; 8283 goto do_branch_i; 8284 case M_BLT_I: 8285 s = "slti"; 8286 s2 = "btnez"; 8287 s3 = "x,8"; 8288 goto do_branch_i; 8289 case M_BLTU_I: 8290 s = "sltiu"; 8291 s2 = "btnez"; 8292 s3 = "x,8"; 8293 goto do_branch_i; 8294 case M_BLE_I: 8295 s = "slti"; 8296 s2 = "btnez"; 8297 s3 = "x,8"; 8298 goto do_addone_branch_i; 8299 case M_BLEU_I: 8300 s = "sltiu"; 8301 s2 = "btnez"; 8302 s3 = "x,8"; 8303 goto do_addone_branch_i; 8304 case M_BGE_I: 8305 s = "slti"; 8306 s2 = "bteqz"; 8307 s3 = "x,8"; 8308 goto do_branch_i; 8309 case M_BGEU_I: 8310 s = "sltiu"; 8311 s2 = "bteqz"; 8312 s3 = "x,8"; 8313 goto do_branch_i; 8314 case M_BGT_I: 8315 s = "slti"; 8316 s2 = "bteqz"; 8317 s3 = "x,8"; 8318 goto do_addone_branch_i; 8319 case M_BGTU_I: 8320 s = "sltiu"; 8321 s2 = "bteqz"; 8322 s3 = "x,8"; 8323 8324 do_addone_branch_i: 8325 if (imm_expr.X_op != O_constant) 8326 as_bad (_("Unsupported large constant")); 8327 ++imm_expr.X_add_number; 8328 8329 do_branch_i: 8330 macro_build (&imm_expr, s, s3, xreg); 8331 macro_build (&offset_expr, s2, "p"); 8332 break; 8333 8334 case M_ABS: 8335 expr1.X_add_number = 0; 8336 macro_build (&expr1, "slti", "x,8", yreg); 8337 if (xreg != yreg) 8338 move_register (xreg, yreg); 8339 expr1.X_add_number = 2; 8340 macro_build (&expr1, "bteqz", "p"); 8341 macro_build (NULL, "neg", "x,w", xreg, xreg); 8342 } 8343} 8344 8345/* For consistency checking, verify that all bits are specified either 8346 by the match/mask part of the instruction definition, or by the 8347 operand list. */ 8348static int 8349validate_mips_insn (const struct mips_opcode *opc) 8350{ 8351 const char *p = opc->args; 8352 char c; 8353 unsigned long used_bits = opc->mask; 8354 8355 if ((used_bits & opc->match) != opc->match) 8356 { 8357 as_bad (_("internal: bad mips opcode (mask error): %s %s"), 8358 opc->name, opc->args); 8359 return 0; 8360 } 8361#define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) 8362 while (*p) 8363 switch (c = *p++) 8364 { 8365 case ',': break; 8366 case '(': break; 8367 case ')': break; 8368 case '^': USE_BITS (OP_MASK_BITIND, OP_SH_BITIND); break; 8369 case '~': USE_BITS (OP_MASK_BITIND, OP_SH_BITIND); break; 8370 case '+': 8371 switch (c = *p++) 8372 { 8373 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; 8374 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; 8375 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; 8376 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; 8377 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; 8378 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; 8379 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; 8380 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); 8381 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; 8382 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; 8383 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; 8384 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; 8385 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; 8386 case 'I': break; 8387 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; 8388 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); 8389 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; 8390 default: 8391 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), 8392 c, opc->name, opc->args); 8393 return 0; 8394 } 8395 break; 8396 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; 8397 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; 8398 case 'A': break; 8399 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; 8400 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; 8401 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; 8402 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; 8403 case 'F': break; 8404 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; 8405 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; 8406 case 'I': break; 8407 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; 8408 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; 8409 case 'L': break; 8410 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; 8411 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; 8412 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; 8413 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); 8414 USE_BITS (OP_MASK_FT, OP_SH_FT); break; 8415 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; 8416 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; 8417 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; 8418 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; 8419 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; 8420 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; 8421 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; 8422 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; 8423 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; 8424 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; 8425 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; 8426 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; 8427 case 'f': break; 8428 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; 8429 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; 8430 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; 8431 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; 8432 case 'l': break; 8433 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; 8434 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; 8435 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; 8436 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; 8437 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; 8438 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; 8439 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; 8440 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; 8441 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; 8442 case 'x': break; 8443 case 'y': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; 8444 case 'z': break; 8445 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; 8446 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); 8447 USE_BITS (OP_MASK_RT, OP_SH_RT); break; 8448 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; 8449 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; 8450 case '[': break; 8451 case ']': break; 8452 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; 8453 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; 8454 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; 8455 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; 8456 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; 8457 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; 8458 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; 8459 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; 8460 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; 8461 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; 8462 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; 8463 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; 8464 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; 8465 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; 8466 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; 8467 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; 8468 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; 8469 default: 8470 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), 8471 c, opc->name, opc->args); 8472 return 0; 8473 } 8474#undef USE_BITS 8475 if (used_bits != 0xffffffff) 8476 { 8477 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), 8478 ~used_bits & 0xffffffff, opc->name, opc->args); 8479 return 0; 8480 } 8481 return 1; 8482} 8483 8484/* UDI immediates. */ 8485struct mips_immed { 8486 char type; 8487 unsigned int shift; 8488 unsigned long mask; 8489 const char * desc; 8490}; 8491 8492static const struct mips_immed mips_immed[] = { 8493 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, 8494 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, 8495 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, 8496 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, 8497 { 0,0,0,0 } 8498}; 8499 8500/* Check whether an odd floating-point register is allowed. */ 8501static int 8502mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) 8503{ 8504 const char *s = insn->name; 8505 8506 if (insn->pinfo == INSN_MACRO) 8507 /* Let a macro pass, we'll catch it later when it is expanded. */ 8508 return 1; 8509 8510 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) 8511 { 8512 /* Allow odd registers for single-precision ops. */ 8513 switch (insn->pinfo & (FP_S | FP_D)) 8514 { 8515 case FP_S: 8516 case 0: 8517 return 1; /* both single precision - ok */ 8518 case FP_D: 8519 return 0; /* both double precision - fail */ 8520 default: 8521 break; 8522 } 8523 8524 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ 8525 s = strchr (insn->name, '.'); 8526 if (argnum == 2) 8527 s = s != NULL ? strchr (s + 1, '.') : NULL; 8528 return (s != NULL && (s[1] == 'w' || s[1] == 's')); 8529 } 8530 8531 /* Single-precision coprocessor loads and moves are OK too. */ 8532 if ((insn->pinfo & FP_S) 8533 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY 8534 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) 8535 return 1; 8536 8537 return 0; 8538} 8539 8540/* This routine assembles an instruction into its binary format. As a 8541 side effect, it sets one of the global variables imm_reloc or 8542 offset_reloc to the type of relocation to do if one of the operands 8543 is an address expression. */ 8544 8545static void 8546mips_ip (char *str, struct mips_cl_insn *ip) 8547{ 8548 char *s; 8549 const char *args; 8550 char c = 0; 8551 struct mips_opcode *insn; 8552 char *argsStart; 8553 unsigned int regno; 8554 unsigned int lastregno = 0; 8555 unsigned int lastpos = 0; 8556 unsigned int limlo, limhi; 8557 char *s_reset; 8558 char save_c = 0; 8559 offsetT min_range, max_range; 8560 int argnum; 8561 unsigned int rtype; 8562 8563 insn_error = NULL; 8564 8565 /* If the instruction contains a '.', we first try to match an instruction 8566 including the '.'. Then we try again without the '.'. */ 8567 insn = NULL; 8568 for (s = str; *s != '\0' && !ISSPACE (*s); ++s) 8569 continue; 8570 8571 /* If we stopped on whitespace, then replace the whitespace with null for 8572 the call to hash_find. Save the character we replaced just in case we 8573 have to re-parse the instruction. */ 8574 if (ISSPACE (*s)) 8575 { 8576 save_c = *s; 8577 *s++ = '\0'; 8578 } 8579 8580 insn = (struct mips_opcode *) hash_find (op_hash, str); 8581 8582 /* If we didn't find the instruction in the opcode table, try again, but 8583 this time with just the instruction up to, but not including the 8584 first '.'. */ 8585 if (insn == NULL) 8586 { 8587 /* Restore the character we overwrite above (if any). */ 8588 if (save_c) 8589 *(--s) = save_c; 8590 8591 /* Scan up to the first '.' or whitespace. */ 8592 for (s = str; 8593 *s != '\0' && *s != '.' && !ISSPACE (*s); 8594 ++s) 8595 continue; 8596 8597 /* If we did not find a '.', then we can quit now. */ 8598 if (*s != '.') 8599 { 8600 insn_error = "unrecognized opcode"; 8601 return; 8602 } 8603 8604 /* Lookup the instruction in the hash table. */ 8605 *s++ = '\0'; 8606 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) 8607 { 8608 insn_error = "unrecognized opcode"; 8609 return; 8610 } 8611 } 8612 8613 argsStart = s; 8614 for (;;) 8615 { 8616 bfd_boolean ok; 8617 8618 assert (strcmp (insn->name, str) == 0); 8619 8620 if (OPCODE_IS_MEMBER (insn, 8621 (mips_opts.isa 8622 /* We don't check for mips_opts.mips16 here since 8623 we want to allow jalx if -mips16 was specified 8624 on the command line. */ 8625 | (file_ase_mips16 ? INSN_MIPS16 : 0) 8626 | (mips_opts.ase_mdmx ? INSN_MDMX : 0) 8627 | (mips_opts.ase_dsp ? INSN_DSP : 0) 8628 | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) 8629 ? INSN_DSP64 : 0) 8630 | (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0) 8631 | (mips_opts.ase_mt ? INSN_MT : 0) 8632 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0) 8633 | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)), 8634 mips_opts.arch)) 8635 ok = TRUE; 8636 else 8637 ok = FALSE; 8638 8639 if (insn->pinfo != INSN_MACRO) 8640 { 8641 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) 8642 ok = FALSE; 8643 8644 if (mips_opts.arch == CPU_OCTEON 8645 && octeon_error_on_unsupported 8646 && ((insn->pinfo & FP_D) != 0 8647 || (insn->pinfo & FP_S) !=0 8648 || strcmp (insn->name, "prefx") == 0)) 8649 { 8650 insn_error = "opcode not implemented in Octeon"; 8651 return; 8652 } 8653 8654 if (mips_opts.arch == CPU_OCTEON 8655 && octeon_error_on_unsupported 8656 && (strcmp (insn->name, "swc2") == 0 8657 || strcmp (insn->name, "lwc2") == 0 8658 || strcmp (insn->name, "sdc2") == 0 8659 || strcmp (insn->name, "ldc2") == 0 8660 || strcmp (insn->name, "bc2f") == 0 8661 || strcmp (insn->name, "bc2t") == 0 8662 || strcmp (insn->name, "mfc2") == 0 8663 || strcmp (insn->name, "mtc2") == 0 8664 || strcmp (insn->name, "ctc2") == 0 8665 || strcmp (insn->name, "cfc2") == 0 8666 || strcmp (insn->name, "mfhc2") == 0 8667 || strcmp (insn->name, "mthc2") == 0)) 8668 { 8669 insn_error = "opcode not implemented in Octeon"; 8670 return; 8671 } 8672 8673 /* Issue a warning message for Octeon unaligned load/store 8674 instructions used when octeon_use_unalign is not set. */ 8675 if (mips_opts.arch == CPU_OCTEON && ! octeon_use_unalign 8676 && (strcmp (insn->name, "ulw") == 0 8677 || strcmp (insn->name, "uld") == 0 8678 || strcmp (insn->name, "usw") == 0 8679 || strcmp (insn->name, "usd") == 0)) 8680 { 8681 static char buf[120]; 8682 sprintf (buf, _("Octeon specific unaligned load/store instructions are not allowed with -mno-octeon-useun")); 8683 insn_error = buf; 8684 return; 8685 } 8686 8687 /* Issue a warning message for MIPS unaligned load/store 8688 instructions used when octeon_use_unalign is set. */ 8689 if (mips_opts.arch == CPU_OCTEON && octeon_use_unalign 8690 && (strcmp (insn->name, "lwl") == 0 8691 || strcmp (insn->name, "lwr") == 0 8692 || strcmp (insn->name, "ldl") == 0 8693 || strcmp (insn->name, "ldr") == 0 8694 || strcmp (insn->name, "sdl") == 0 8695 || strcmp (insn->name, "sdr") == 0 8696 || strcmp (insn->name, "swr") == 0 8697 || strcmp (insn->name, "swl") == 0)) 8698 { 8699 static char buf[100]; 8700 sprintf (buf, _("Unaligned load/store instructions are not allowed with -mocteon-useun")); 8701 insn_error = buf; 8702 return; 8703 } 8704 } 8705 8706 /* Octeon has its own version of dmtc2/dmfc2 instructions, error on 8707 other formats. */ 8708 if (mips_opts.arch == CPU_OCTEON 8709 && (strcmp (insn->name, "dmtc2") == 0 8710 || strcmp (insn->name, "dmfc2") == 0) 8711 && (insn->membership & INSN_OCTEON) != INSN_OCTEON) 8712 { 8713 static char buf[100]; 8714 sprintf (buf, 8715 _("opcode not supported in %s"), 8716 mips_cpu_info_from_arch (mips_opts.arch)->name); 8717 insn_error = buf; 8718 ok = FALSE; 8719 } 8720 8721 if (! ok) 8722 { 8723 if (insn + 1 < &mips_opcodes[NUMOPCODES] 8724 && strcmp (insn->name, insn[1].name) == 0) 8725 { 8726 ++insn; 8727 continue; 8728 } 8729 else 8730 { 8731 if (!insn_error) 8732 { 8733 static char buf[100]; 8734 sprintf (buf, 8735 _("opcode not supported on this processor: %s (%s)"), 8736 mips_cpu_info_from_arch (mips_opts.arch)->name, 8737 mips_cpu_info_from_isa (mips_opts.isa)->name); 8738 insn_error = buf; 8739 } 8740 if (save_c) 8741 *(--s) = save_c; 8742 return; 8743 } 8744 } 8745 8746 create_insn (ip, insn); 8747 insn_error = NULL; 8748 argnum = 1; 8749 for (args = insn->args;; ++args) 8750 { 8751 int is_mdmx; 8752 8753 s += strspn (s, " \t"); 8754 is_mdmx = 0; 8755 switch (*args) 8756 { 8757 case '\0': /* end of args */ 8758 if (*s == '\0') 8759 return; 8760 break; 8761 8762 case '2': /* dsp 2-bit unsigned immediate in bit 11 */ 8763 my_getExpression (&imm_expr, s); 8764 check_absolute_expr (ip, &imm_expr); 8765 if ((unsigned long) imm_expr.X_add_number != 1 8766 && (unsigned long) imm_expr.X_add_number != 3) 8767 { 8768 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), 8769 (unsigned long) imm_expr.X_add_number); 8770 } 8771 INSERT_OPERAND (BP, *ip, imm_expr.X_add_number); 8772 imm_expr.X_op = O_absent; 8773 s = expr_end; 8774 continue; 8775 8776 case '3': /* dsp 3-bit unsigned immediate in bit 21 */ 8777 my_getExpression (&imm_expr, s); 8778 check_absolute_expr (ip, &imm_expr); 8779 if (imm_expr.X_add_number & ~OP_MASK_SA3) 8780 { 8781 as_bad (_("DSP immediate not in range 0..%d (%lu)"), 8782 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); 8783 } 8784 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number); 8785 imm_expr.X_op = O_absent; 8786 s = expr_end; 8787 continue; 8788 8789 case '4': /* dsp 4-bit unsigned immediate in bit 21 */ 8790 my_getExpression (&imm_expr, s); 8791 check_absolute_expr (ip, &imm_expr); 8792 if (imm_expr.X_add_number & ~OP_MASK_SA4) 8793 { 8794 as_bad (_("DSP immediate not in range 0..%d (%lu)"), 8795 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); 8796 } 8797 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number); 8798 imm_expr.X_op = O_absent; 8799 s = expr_end; 8800 continue; 8801 8802 case '5': /* dsp 8-bit unsigned immediate in bit 16 */ 8803 my_getExpression (&imm_expr, s); 8804 check_absolute_expr (ip, &imm_expr); 8805 if (imm_expr.X_add_number & ~OP_MASK_IMM8) 8806 { 8807 as_bad (_("DSP immediate not in range 0..%d (%lu)"), 8808 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); 8809 } 8810 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number); 8811 imm_expr.X_op = O_absent; 8812 s = expr_end; 8813 continue; 8814 8815 case '6': /* dsp 5-bit unsigned immediate in bit 21 */ 8816 my_getExpression (&imm_expr, s); 8817 check_absolute_expr (ip, &imm_expr); 8818 if (imm_expr.X_add_number & ~OP_MASK_RS) 8819 { 8820 as_bad (_("DSP immediate not in range 0..%d (%lu)"), 8821 OP_MASK_RS, (unsigned long) imm_expr.X_add_number); 8822 } 8823 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number); 8824 imm_expr.X_op = O_absent; 8825 s = expr_end; 8826 continue; 8827 8828 case '7': /* four dsp accumulators in bits 11,12 */ 8829 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && 8830 s[3] >= '0' && s[3] <= '3') 8831 { 8832 regno = s[3] - '0'; 8833 s += 4; 8834 INSERT_OPERAND (DSPACC, *ip, regno); 8835 continue; 8836 } 8837 else 8838 as_bad (_("Invalid dsp acc register")); 8839 break; 8840 8841 case '8': /* dsp 6-bit unsigned immediate in bit 11 */ 8842 my_getExpression (&imm_expr, s); 8843 check_absolute_expr (ip, &imm_expr); 8844 if (imm_expr.X_add_number & ~OP_MASK_WRDSP) 8845 { 8846 as_bad (_("DSP immediate not in range 0..%d (%lu)"), 8847 OP_MASK_WRDSP, 8848 (unsigned long) imm_expr.X_add_number); 8849 } 8850 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number); 8851 imm_expr.X_op = O_absent; 8852 s = expr_end; 8853 continue; 8854 8855 case '9': /* four dsp accumulators in bits 21,22 */ 8856 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && 8857 s[3] >= '0' && s[3] <= '3') 8858 { 8859 regno = s[3] - '0'; 8860 s += 4; 8861 INSERT_OPERAND (DSPACC_S, *ip, regno); 8862 continue; 8863 } 8864 else 8865 as_bad (_("Invalid dsp acc register")); 8866 break; 8867 8868 case '0': /* dsp 6-bit signed immediate in bit 20 */ 8869 my_getExpression (&imm_expr, s); 8870 check_absolute_expr (ip, &imm_expr); 8871 min_range = -((OP_MASK_DSPSFT + 1) >> 1); 8872 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; 8873 if (imm_expr.X_add_number < min_range || 8874 imm_expr.X_add_number > max_range) 8875 { 8876 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), 8877 (long) min_range, (long) max_range, 8878 (long) imm_expr.X_add_number); 8879 } 8880 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number); 8881 imm_expr.X_op = O_absent; 8882 s = expr_end; 8883 continue; 8884 8885 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */ 8886 my_getExpression (&imm_expr, s); 8887 check_absolute_expr (ip, &imm_expr); 8888 if (imm_expr.X_add_number & ~OP_MASK_RDDSP) 8889 { 8890 as_bad (_("DSP immediate not in range 0..%d (%lu)"), 8891 OP_MASK_RDDSP, 8892 (unsigned long) imm_expr.X_add_number); 8893 } 8894 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number); 8895 imm_expr.X_op = O_absent; 8896 s = expr_end; 8897 continue; 8898 8899 case ':': /* dsp 7-bit signed immediate in bit 19 */ 8900 my_getExpression (&imm_expr, s); 8901 check_absolute_expr (ip, &imm_expr); 8902 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); 8903 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; 8904 if (imm_expr.X_add_number < min_range || 8905 imm_expr.X_add_number > max_range) 8906 { 8907 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), 8908 (long) min_range, (long) max_range, 8909 (long) imm_expr.X_add_number); 8910 } 8911 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number); 8912 imm_expr.X_op = O_absent; 8913 s = expr_end; 8914 continue; 8915 8916 case '@': /* dsp 10-bit signed immediate in bit 16 */ 8917 my_getExpression (&imm_expr, s); 8918 check_absolute_expr (ip, &imm_expr); 8919 min_range = -((OP_MASK_IMM10 + 1) >> 1); 8920 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; 8921 if (imm_expr.X_add_number < min_range || 8922 imm_expr.X_add_number > max_range) 8923 { 8924 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), 8925 (long) min_range, (long) max_range, 8926 (long) imm_expr.X_add_number); 8927 } 8928 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number); 8929 imm_expr.X_op = O_absent; 8930 s = expr_end; 8931 continue; 8932 8933 case '!': /* MT usermode flag bit. */ 8934 my_getExpression (&imm_expr, s); 8935 check_absolute_expr (ip, &imm_expr); 8936 if (imm_expr.X_add_number & ~OP_MASK_MT_U) 8937 as_bad (_("MT usermode bit not 0 or 1 (%lu)"), 8938 (unsigned long) imm_expr.X_add_number); 8939 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number); 8940 imm_expr.X_op = O_absent; 8941 s = expr_end; 8942 continue; 8943 8944 case '$': /* MT load high flag bit. */ 8945 my_getExpression (&imm_expr, s); 8946 check_absolute_expr (ip, &imm_expr); 8947 if (imm_expr.X_add_number & ~OP_MASK_MT_H) 8948 as_bad (_("MT load high bit not 0 or 1 (%lu)"), 8949 (unsigned long) imm_expr.X_add_number); 8950 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number); 8951 imm_expr.X_op = O_absent; 8952 s = expr_end; 8953 continue; 8954 8955 case '*': /* four dsp accumulators in bits 18,19 */ 8956 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && 8957 s[3] >= '0' && s[3] <= '3') 8958 { 8959 regno = s[3] - '0'; 8960 s += 4; 8961 INSERT_OPERAND (MTACC_T, *ip, regno); 8962 continue; 8963 } 8964 else 8965 as_bad (_("Invalid dsp/smartmips acc register")); 8966 break; 8967 8968 case '&': /* four dsp accumulators in bits 13,14 */ 8969 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && 8970 s[3] >= '0' && s[3] <= '3') 8971 { 8972 regno = s[3] - '0'; 8973 s += 4; 8974 INSERT_OPERAND (MTACC_D, *ip, regno); 8975 continue; 8976 } 8977 else 8978 as_bad (_("Invalid dsp/smartmips acc register")); 8979 break; 8980 8981 case ',': 8982 ++argnum; 8983 if (*s++ == *args) 8984 continue; 8985 s--; 8986 switch (*++args) 8987 { 8988 case 'r': 8989 case 'v': 8990 INSERT_OPERAND (RS, *ip, lastregno); 8991 continue; 8992 8993 case 'w': 8994 INSERT_OPERAND (RT, *ip, lastregno); 8995 continue; 8996 8997 case 'W': 8998 INSERT_OPERAND (FT, *ip, lastregno); 8999 continue; 9000 9001 case 'V': 9002 INSERT_OPERAND (FS, *ip, lastregno); 9003 continue; 9004 } 9005 break; 9006 9007 case '(': 9008 /* Handle optional base register. 9009 Either the base register is omitted or 9010 we must have a left paren. */ 9011 /* This is dependent on the next operand specifier 9012 is a base register specification. */ 9013 assert (args[1] == 'b' || args[1] == '5' 9014 || args[1] == '-' || args[1] == '4'); 9015 if (*s == '\0') 9016 return; 9017 9018 case ')': /* these must match exactly */ 9019 case '[': 9020 case ']': 9021 if (*s++ == *args) 9022 continue; 9023 break; 9024 9025 case '+': /* Opcode extension character. */ 9026 switch (*++args) 9027 { 9028 case '1': /* UDI immediates. */ 9029 case '2': 9030 case '3': 9031 case '4': 9032 { 9033 const struct mips_immed *imm = mips_immed; 9034 9035 while (imm->type && imm->type != *args) 9036 ++imm; 9037 if (! imm->type) 9038 internalError (); 9039 my_getExpression (&imm_expr, s); 9040 check_absolute_expr (ip, &imm_expr); 9041 if ((unsigned long) imm_expr.X_add_number & ~imm->mask) 9042 { 9043 as_warn (_("Illegal %s number (%lu, 0x%lx)"), 9044 imm->desc ? imm->desc : ip->insn_mo->name, 9045 (unsigned long) imm_expr.X_add_number, 9046 (unsigned long) imm_expr.X_add_number); 9047 imm_expr.X_add_number &= imm->mask; 9048 } 9049 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number 9050 << imm->shift); 9051 imm_expr.X_op = O_absent; 9052 s = expr_end; 9053 } 9054 continue; 9055 9056 case 'A': /* ins/ext position, becomes LSB. */ 9057 limlo = 0; 9058 limhi = 31; 9059 goto do_lsb; 9060 case 'E': 9061 limlo = 32; 9062 limhi = 63; 9063 goto do_lsb; 9064do_lsb: 9065 my_getExpression (&imm_expr, s); 9066 check_absolute_expr (ip, &imm_expr); 9067 if ((unsigned long) imm_expr.X_add_number < limlo 9068 || (unsigned long) imm_expr.X_add_number > limhi) 9069 { 9070 as_bad (_("Improper position (%lu)"), 9071 (unsigned long) imm_expr.X_add_number); 9072 imm_expr.X_add_number = limlo; 9073 } 9074 lastpos = imm_expr.X_add_number; 9075 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); 9076 imm_expr.X_op = O_absent; 9077 s = expr_end; 9078 continue; 9079 9080 case 'B': /* ins size, becomes MSB. */ 9081 limlo = 1; 9082 limhi = 32; 9083 goto do_msb; 9084 case 'F': 9085 limlo = 33; 9086 limhi = 64; 9087 goto do_msb; 9088do_msb: 9089 my_getExpression (&imm_expr, s); 9090 check_absolute_expr (ip, &imm_expr); 9091 /* Check for negative input so that small negative numbers 9092 will not succeed incorrectly. The checks against 9093 (pos+size) transitively check "size" itself, 9094 assuming that "pos" is reasonable. */ 9095 if ((long) imm_expr.X_add_number < 0 9096 || ((unsigned long) imm_expr.X_add_number 9097 + lastpos) < limlo 9098 || ((unsigned long) imm_expr.X_add_number 9099 + lastpos) > limhi) 9100 { 9101 as_bad (_("Improper insert size (%lu, position %lu)"), 9102 (unsigned long) imm_expr.X_add_number, 9103 (unsigned long) lastpos); 9104 imm_expr.X_add_number = limlo - lastpos; 9105 } 9106 INSERT_OPERAND (INSMSB, *ip, 9107 lastpos + imm_expr.X_add_number - 1); 9108 imm_expr.X_op = O_absent; 9109 s = expr_end; 9110 continue; 9111 9112 case 'C': /* ext size, becomes MSBD. */ 9113 limlo = 1; 9114 limhi = 32; 9115 goto do_msbd; 9116 case 'G': 9117 limlo = 33; 9118 limhi = 64; 9119 goto do_msbd; 9120 case 'H': 9121 limlo = 33; 9122 limhi = 64; 9123 goto do_msbd; 9124do_msbd: 9125 my_getExpression (&imm_expr, s); 9126 check_absolute_expr (ip, &imm_expr); 9127 /* Check for negative input so that small negative numbers 9128 will not succeed incorrectly. The checks against 9129 (pos+size) transitively check "size" itself, 9130 assuming that "pos" is reasonable. */ 9131 if ((long) imm_expr.X_add_number < 0 9132 || ((unsigned long) imm_expr.X_add_number 9133 + lastpos) < limlo 9134 || ((unsigned long) imm_expr.X_add_number 9135 + lastpos) > limhi) 9136 { 9137 as_bad (_("Improper extract size (%lu, position %lu)"), 9138 (unsigned long) imm_expr.X_add_number, 9139 (unsigned long) lastpos); 9140 imm_expr.X_add_number = limlo - lastpos; 9141 } 9142 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); 9143 imm_expr.X_op = O_absent; 9144 s = expr_end; 9145 continue; 9146 9147 case 'D': 9148 /* +D is for disassembly only; never match. */ 9149 break; 9150 9151 case 'I': 9152 /* "+I" is like "I", except that imm2_expr is used. */ 9153 my_getExpression (&imm2_expr, s); 9154 if (imm2_expr.X_op != O_big 9155 && imm2_expr.X_op != O_constant) 9156 insn_error = _("absolute expression required"); 9157 if (HAVE_32BIT_GPRS) 9158 normalize_constant_expr (&imm2_expr); 9159 s = expr_end; 9160 continue; 9161 9162 case 'T': /* Coprocessor register. */ 9163 /* +T is for disassembly only; never match. */ 9164 break; 9165 9166 case 't': /* Coprocessor register number. */ 9167 if (s[0] == '$' && ISDIGIT (s[1])) 9168 { 9169 ++s; 9170 regno = 0; 9171 do 9172 { 9173 regno *= 10; 9174 regno += *s - '0'; 9175 ++s; 9176 } 9177 while (ISDIGIT (*s)); 9178 if (regno > 31) 9179 as_bad (_("Invalid register number (%d)"), regno); 9180 else 9181 { 9182 INSERT_OPERAND (RT, *ip, regno); 9183 continue; 9184 } 9185 } 9186 else 9187 as_bad (_("Invalid coprocessor 0 register number")); 9188 break; 9189 9190 default: 9191 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), 9192 *args, insn->name, insn->args); 9193 /* Further processing is fruitless. */ 9194 return; 9195 } 9196 break; 9197 9198 case '<': /* must be at least one digit */ 9199 /* 9200 * According to the manual, if the shift amount is greater 9201 * than 31 or less than 0, then the shift amount should be 9202 * mod 32. In reality the mips assembler issues an error. 9203 * We issue a warning and mask out all but the low 5 bits. 9204 */ 9205 my_getExpression (&imm_expr, s); 9206 check_absolute_expr (ip, &imm_expr); 9207 if ((unsigned long) imm_expr.X_add_number > 31) 9208 as_warn (_("Improper shift amount (%lu)"), 9209 (unsigned long) imm_expr.X_add_number); 9210 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); 9211 imm_expr.X_op = O_absent; 9212 s = expr_end; 9213 continue; 9214 9215 case '>': /* shift amount minus 32 */ 9216 my_getExpression (&imm_expr, s); 9217 check_absolute_expr (ip, &imm_expr); 9218 if ((unsigned long) imm_expr.X_add_number < 32 9219 || (unsigned long) imm_expr.X_add_number > 63) 9220 break; 9221 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); 9222 imm_expr.X_op = O_absent; 9223 s = expr_end; 9224 continue; 9225 9226 case '^': /* must be at least one digit */ 9227 /* Decode 5-bits of bbit0/1's bit index amount. If the value is 9228 greater than 31, issue a warning and mask out all but the low 9229 5 bits. */ 9230 my_getExpression (&imm_expr, s); 9231 check_absolute_expr (ip, &imm_expr); 9232 if ((unsigned long) imm_expr.X_add_number > 31) 9233 { 9234 as_warn (_("Improper bit index amount (%lu)"), 9235 (unsigned long) imm_expr.X_add_number); 9236 imm_expr.X_add_number &= OP_MASK_BITIND; 9237 } 9238 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_BITIND; 9239 imm_expr.X_op = O_absent; 9240 s = expr_end; 9241 continue; 9242 9243 case '~': /* bit index minus 32 */ 9244 my_getExpression (&imm_expr, s); 9245 check_absolute_expr (ip, &imm_expr); 9246 if ((unsigned long) imm_expr.X_add_number < 32 9247 || (unsigned long) imm_expr.X_add_number > 63) 9248 break; 9249 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_BITIND; 9250 imm_expr.X_op = O_absent; 9251 s = expr_end; 9252 continue; 9253 9254 case 'k': /* cache code */ 9255 case 'h': /* prefx code */ 9256 my_getExpression (&imm_expr, s); 9257 check_absolute_expr (ip, &imm_expr); 9258 if ((unsigned long) imm_expr.X_add_number > 31) 9259 as_warn (_("Invalid value for `%s' (%lu)"), 9260 ip->insn_mo->name, 9261 (unsigned long) imm_expr.X_add_number); 9262 if (*args == 'k') 9263 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); 9264 else 9265 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); 9266 imm_expr.X_op = O_absent; 9267 s = expr_end; 9268 continue; 9269 9270 case 'c': /* break code */ 9271 my_getExpression (&imm_expr, s); 9272 check_absolute_expr (ip, &imm_expr); 9273 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE) 9274 as_warn (_("Code for %s not in range 0..1023 (%lu)"), 9275 ip->insn_mo->name, 9276 (unsigned long) imm_expr.X_add_number); 9277 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); 9278 imm_expr.X_op = O_absent; 9279 s = expr_end; 9280 continue; 9281 9282 case 'q': /* lower break code */ 9283 my_getExpression (&imm_expr, s); 9284 check_absolute_expr (ip, &imm_expr); 9285 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2) 9286 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"), 9287 ip->insn_mo->name, 9288 (unsigned long) imm_expr.X_add_number); 9289 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); 9290 imm_expr.X_op = O_absent; 9291 s = expr_end; 9292 continue; 9293 9294 case 'y': 9295 /* Decode 10-bits of seqi/snei's signed constant offset. Issue 9296 a warning message if the value is not within the range. */ 9297 my_getExpression (&imm_expr, s); 9298 check_absolute_expr (ip, &imm_expr); 9299 if (((unsigned long) imm_expr.X_add_number + 0x200) > 1023) 9300 { 9301 as_warn (_("Illegal 10-bit signed constant (%lu)"), 9302 (unsigned long) imm_expr.X_add_number); 9303 imm_expr.X_add_number &= OP_MASK_CODE2; 9304 } 9305 ip->insn_opcode |= (imm_expr.X_add_number & OP_MASK_CODE2) 9306 << OP_SH_CODE2; 9307 imm_expr.X_op = O_absent; 9308 s = expr_end; 9309 continue; 9310 9311 case 'B': /* 20-bit syscall/break code. */ 9312 my_getExpression (&imm_expr, s); 9313 check_absolute_expr (ip, &imm_expr); 9314 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) 9315 as_warn (_("Code for %s not in range 0..1048575 (%lu)"), 9316 ip->insn_mo->name, 9317 (unsigned long) imm_expr.X_add_number); 9318 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); 9319 imm_expr.X_op = O_absent; 9320 s = expr_end; 9321 continue; 9322 9323 case 'C': /* Coprocessor code */ 9324 my_getExpression (&imm_expr, s); 9325 check_absolute_expr (ip, &imm_expr); 9326 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ) 9327 { 9328 as_warn (_("Coproccesor code > 25 bits (%lu)"), 9329 (unsigned long) imm_expr.X_add_number); 9330 imm_expr.X_add_number &= OP_MASK_COPZ; 9331 } 9332 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number); 9333 imm_expr.X_op = O_absent; 9334 s = expr_end; 9335 continue; 9336 9337 case 'J': /* 19-bit wait code. */ 9338 my_getExpression (&imm_expr, s); 9339 check_absolute_expr (ip, &imm_expr); 9340 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) 9341 { 9342 as_warn (_("Illegal 19-bit code (%lu)"), 9343 (unsigned long) imm_expr.X_add_number); 9344 imm_expr.X_add_number &= OP_MASK_CODE19; 9345 } 9346 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); 9347 imm_expr.X_op = O_absent; 9348 s = expr_end; 9349 continue; 9350 9351 case 'P': /* Performance register. */ 9352 my_getExpression (&imm_expr, s); 9353 check_absolute_expr (ip, &imm_expr); 9354 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) 9355 as_warn (_("Invalid performance register (%lu)"), 9356 (unsigned long) imm_expr.X_add_number); 9357 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); 9358 imm_expr.X_op = O_absent; 9359 s = expr_end; 9360 continue; 9361 9362 case 'G': /* Coprocessor destination register. */ 9363 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0) 9364 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no); 9365 else 9366 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); 9367 INSERT_OPERAND (RD, *ip, regno); 9368 if (ok) 9369 { 9370 lastregno = regno; 9371 continue; 9372 } 9373 else 9374 break; 9375 9376 case 'b': /* base register */ 9377 case 'd': /* destination register */ 9378 case 's': /* source register */ 9379 case 't': /* target register */ 9380 case 'r': /* both target and source */ 9381 case 'v': /* both dest and source */ 9382 case 'w': /* both dest and target */ 9383 case 'E': /* coprocessor target register */ 9384 case 'K': /* 'rdhwr' destination register */ 9385 case 'x': /* ignore register name */ 9386 case 'z': /* must be zero register */ 9387 case 'U': /* destination register (clo/clz). */ 9388 case 'g': /* coprocessor destination register */ 9389 s_reset = s; 9390 if (*args == 'E' || *args == 'K') 9391 ok = reg_lookup (&s, RTYPE_NUM, ®no); 9392 else 9393 { 9394 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); 9395 if (regno == AT && ! mips_opts.noat) 9396 as_warn ("Used $at without \".set noat\""); 9397 } 9398 if (ok) 9399 { 9400 c = *args; 9401 if (*s == ' ') 9402 ++s; 9403 if (args[1] != *s) 9404 { 9405 if (c == 'r' || c == 'v' || c == 'w') 9406 { 9407 regno = lastregno; 9408 s = s_reset; 9409 ++args; 9410 } 9411 } 9412 /* 'z' only matches $0. */ 9413 if (c == 'z' && regno != 0) 9414 break; 9415 9416 /* Now that we have assembled one operand, we use the args string 9417 * to figure out where it goes in the instruction. */ 9418 switch (c) 9419 { 9420 case 'r': 9421 case 's': 9422 case 'v': 9423 case 'b': 9424 INSERT_OPERAND (RS, *ip, regno); 9425 break; 9426 case 'd': 9427 case 'G': 9428 case 'K': 9429 case 'g': 9430 INSERT_OPERAND (RD, *ip, regno); 9431 break; 9432 case 'U': 9433 INSERT_OPERAND (RD, *ip, regno); 9434 INSERT_OPERAND (RT, *ip, regno); 9435 break; 9436 case 'w': 9437 case 't': 9438 case 'E': 9439 INSERT_OPERAND (RT, *ip, regno); 9440 break; 9441 case 'x': 9442 /* This case exists because on the r3000 trunc 9443 expands into a macro which requires a gp 9444 register. On the r6000 or r4000 it is 9445 assembled into a single instruction which 9446 ignores the register. Thus the insn version 9447 is MIPS_ISA2 and uses 'x', and the macro 9448 version is MIPS_ISA1 and uses 't'. */ 9449 break; 9450 case 'z': 9451 /* This case is for the div instruction, which 9452 acts differently if the destination argument 9453 is $0. This only matches $0, and is checked 9454 outside the switch. */ 9455 break; 9456 case 'D': 9457 /* Itbl operand; not yet implemented. FIXME ?? */ 9458 break; 9459 /* What about all other operands like 'i', which 9460 can be specified in the opcode table? */ 9461 } 9462 lastregno = regno; 9463 continue; 9464 } 9465 switch (*args++) 9466 { 9467 case 'r': 9468 case 'v': 9469 INSERT_OPERAND (RS, *ip, lastregno); 9470 continue; 9471 case 'w': 9472 INSERT_OPERAND (RT, *ip, lastregno); 9473 continue; 9474 } 9475 break; 9476 9477 case 'O': /* MDMX alignment immediate constant. */ 9478 my_getExpression (&imm_expr, s); 9479 check_absolute_expr (ip, &imm_expr); 9480 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) 9481 as_warn ("Improper align amount (%ld), using low bits", 9482 (long) imm_expr.X_add_number); 9483 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); 9484 imm_expr.X_op = O_absent; 9485 s = expr_end; 9486 continue; 9487 9488 case 'Q': /* MDMX vector, element sel, or const. */ 9489 if (s[0] != '$') 9490 { 9491 /* MDMX Immediate. */ 9492 my_getExpression (&imm_expr, s); 9493 check_absolute_expr (ip, &imm_expr); 9494 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) 9495 as_warn (_("Invalid MDMX Immediate (%ld)"), 9496 (long) imm_expr.X_add_number); 9497 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); 9498 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) 9499 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; 9500 else 9501 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; 9502 imm_expr.X_op = O_absent; 9503 s = expr_end; 9504 continue; 9505 } 9506 /* Not MDMX Immediate. Fall through. */ 9507 case 'X': /* MDMX destination register. */ 9508 case 'Y': /* MDMX source register. */ 9509 case 'Z': /* MDMX target register. */ 9510 is_mdmx = 1; 9511 case 'D': /* floating point destination register */ 9512 case 'S': /* floating point source register */ 9513 case 'T': /* floating point target register */ 9514 case 'R': /* floating point source register */ 9515 case 'V': 9516 case 'W': 9517 rtype = RTYPE_FPU; 9518 if (is_mdmx 9519 || (mips_opts.ase_mdmx 9520 && (ip->insn_mo->pinfo & FP_D) 9521 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY 9522 | INSN_COPROC_MEMORY_DELAY 9523 | INSN_LOAD_COPROC_DELAY 9524 | INSN_LOAD_MEMORY_DELAY 9525 | INSN_STORE_MEMORY)))) 9526 rtype |= RTYPE_VEC; 9527 s_reset = s; 9528 if (mips_opts.arch == CPU_OCTEON && octeon_error_on_unsupported) 9529 { 9530 insn_error = "opcode not implemented in Octeon"; 9531 return; 9532 } 9533 if (reg_lookup (&s, rtype, ®no)) 9534 { 9535 if ((regno & 1) != 0 9536 && HAVE_32BIT_FPRS 9537 && ! mips_oddfpreg_ok (ip->insn_mo, argnum)) 9538 as_warn (_("Float register should be even, was %d"), 9539 regno); 9540 9541 c = *args; 9542 if (*s == ' ') 9543 ++s; 9544 if (args[1] != *s) 9545 { 9546 if (c == 'V' || c == 'W') 9547 { 9548 regno = lastregno; 9549 s = s_reset; 9550 ++args; 9551 } 9552 } 9553 switch (c) 9554 { 9555 case 'D': 9556 case 'X': 9557 INSERT_OPERAND (FD, *ip, regno); 9558 break; 9559 case 'V': 9560 case 'S': 9561 case 'Y': 9562 INSERT_OPERAND (FS, *ip, regno); 9563 break; 9564 case 'Q': 9565 /* This is like 'Z', but also needs to fix the MDMX 9566 vector/scalar select bits. Note that the 9567 scalar immediate case is handled above. */ 9568 if (*s == '[') 9569 { 9570 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); 9571 int max_el = (is_qh ? 3 : 7); 9572 s++; 9573 my_getExpression(&imm_expr, s); 9574 check_absolute_expr (ip, &imm_expr); 9575 s = expr_end; 9576 if (imm_expr.X_add_number > max_el) 9577 as_bad(_("Bad element selector %ld"), 9578 (long) imm_expr.X_add_number); 9579 imm_expr.X_add_number &= max_el; 9580 ip->insn_opcode |= (imm_expr.X_add_number 9581 << (OP_SH_VSEL + 9582 (is_qh ? 2 : 1))); 9583 imm_expr.X_op = O_absent; 9584 if (*s != ']') 9585 as_warn(_("Expecting ']' found '%s'"), s); 9586 else 9587 s++; 9588 } 9589 else 9590 { 9591 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) 9592 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH 9593 << OP_SH_VSEL); 9594 else 9595 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << 9596 OP_SH_VSEL); 9597 } 9598 /* Fall through */ 9599 case 'W': 9600 case 'T': 9601 case 'Z': 9602 INSERT_OPERAND (FT, *ip, regno); 9603 break; 9604 case 'R': 9605 INSERT_OPERAND (FR, *ip, regno); 9606 break; 9607 } 9608 lastregno = regno; 9609 continue; 9610 } 9611 9612 switch (*args++) 9613 { 9614 case 'V': 9615 INSERT_OPERAND (FS, *ip, lastregno); 9616 continue; 9617 case 'W': 9618 INSERT_OPERAND (FT, *ip, lastregno); 9619 continue; 9620 } 9621 break; 9622 9623 case 'I': 9624 my_getExpression (&imm_expr, s); 9625 if (imm_expr.X_op != O_big 9626 && imm_expr.X_op != O_constant) 9627 insn_error = _("absolute expression required"); 9628 if (HAVE_32BIT_GPRS) 9629 normalize_constant_expr (&imm_expr); 9630 s = expr_end; 9631 continue; 9632 9633 case 'A': 9634 my_getExpression (&offset_expr, s); 9635 normalize_address_expr (&offset_expr); 9636 *imm_reloc = BFD_RELOC_32; 9637 s = expr_end; 9638 continue; 9639 9640 case 'F': 9641 case 'L': 9642 case 'f': 9643 case 'l': 9644 { 9645 int f64; 9646 int using_gprs; 9647 char *save_in; 9648 char *err; 9649 unsigned char temp[8]; 9650 int len; 9651 unsigned int length; 9652 segT seg; 9653 subsegT subseg; 9654 char *p; 9655 9656 /* These only appear as the last operand in an 9657 instruction, and every instruction that accepts 9658 them in any variant accepts them in all variants. 9659 This means we don't have to worry about backing out 9660 any changes if the instruction does not match. 9661 9662 The difference between them is the size of the 9663 floating point constant and where it goes. For 'F' 9664 and 'L' the constant is 64 bits; for 'f' and 'l' it 9665 is 32 bits. Where the constant is placed is based 9666 on how the MIPS assembler does things: 9667 F -- .rdata 9668 L -- .lit8 9669 f -- immediate value 9670 l -- .lit4 9671 9672 The .lit4 and .lit8 sections are only used if 9673 permitted by the -G argument. 9674 9675 The code below needs to know whether the target register 9676 is 32 or 64 bits wide. It relies on the fact 'f' and 9677 'F' are used with GPR-based instructions and 'l' and 9678 'L' are used with FPR-based instructions. */ 9679 9680 f64 = *args == 'F' || *args == 'L'; 9681 using_gprs = *args == 'F' || *args == 'f'; 9682 9683 save_in = input_line_pointer; 9684 input_line_pointer = s; 9685 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); 9686 length = len; 9687 s = input_line_pointer; 9688 input_line_pointer = save_in; 9689 if (err != NULL && *err != '\0') 9690 { 9691 as_bad (_("Bad floating point constant: %s"), err); 9692 memset (temp, '\0', sizeof temp); 9693 length = f64 ? 8 : 4; 9694 } 9695 9696 assert (length == (unsigned) (f64 ? 8 : 4)); 9697 9698 if (*args == 'f' 9699 || (*args == 'l' 9700 && (g_switch_value < 4 9701 || (temp[0] == 0 && temp[1] == 0) 9702 || (temp[2] == 0 && temp[3] == 0)))) 9703 { 9704 imm_expr.X_op = O_constant; 9705 if (! target_big_endian) 9706 imm_expr.X_add_number = bfd_getl32 (temp); 9707 else 9708 imm_expr.X_add_number = bfd_getb32 (temp); 9709 } 9710 else if (length > 4 9711 && ! mips_disable_float_construction 9712 /* Constants can only be constructed in GPRs and 9713 copied to FPRs if the GPRs are at least as wide 9714 as the FPRs. Force the constant into memory if 9715 we are using 64-bit FPRs but the GPRs are only 9716 32 bits wide. */ 9717 && (using_gprs 9718 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) 9719 && ((temp[0] == 0 && temp[1] == 0) 9720 || (temp[2] == 0 && temp[3] == 0)) 9721 && ((temp[4] == 0 && temp[5] == 0) 9722 || (temp[6] == 0 && temp[7] == 0))) 9723 { 9724 /* The value is simple enough to load with a couple of 9725 instructions. If using 32-bit registers, set 9726 imm_expr to the high order 32 bits and offset_expr to 9727 the low order 32 bits. Otherwise, set imm_expr to 9728 the entire 64 bit constant. */ 9729 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) 9730 { 9731 imm_expr.X_op = O_constant; 9732 offset_expr.X_op = O_constant; 9733 if (! target_big_endian) 9734 { 9735 imm_expr.X_add_number = bfd_getl32 (temp + 4); 9736 offset_expr.X_add_number = bfd_getl32 (temp); 9737 } 9738 else 9739 { 9740 imm_expr.X_add_number = bfd_getb32 (temp); 9741 offset_expr.X_add_number = bfd_getb32 (temp + 4); 9742 } 9743 if (offset_expr.X_add_number == 0) 9744 offset_expr.X_op = O_absent; 9745 } 9746 else if (sizeof (imm_expr.X_add_number) > 4) 9747 { 9748 imm_expr.X_op = O_constant; 9749 if (! target_big_endian) 9750 imm_expr.X_add_number = bfd_getl64 (temp); 9751 else 9752 imm_expr.X_add_number = bfd_getb64 (temp); 9753 } 9754 else 9755 { 9756 imm_expr.X_op = O_big; 9757 imm_expr.X_add_number = 4; 9758 if (! target_big_endian) 9759 { 9760 generic_bignum[0] = bfd_getl16 (temp); 9761 generic_bignum[1] = bfd_getl16 (temp + 2); 9762 generic_bignum[2] = bfd_getl16 (temp + 4); 9763 generic_bignum[3] = bfd_getl16 (temp + 6); 9764 } 9765 else 9766 { 9767 generic_bignum[0] = bfd_getb16 (temp + 6); 9768 generic_bignum[1] = bfd_getb16 (temp + 4); 9769 generic_bignum[2] = bfd_getb16 (temp + 2); 9770 generic_bignum[3] = bfd_getb16 (temp); 9771 } 9772 } 9773 } 9774 else 9775 { 9776 const char *newname; 9777 segT new_seg; 9778 9779 /* Switch to the right section. */ 9780 seg = now_seg; 9781 subseg = now_subseg; 9782 switch (*args) 9783 { 9784 default: /* unused default case avoids warnings. */ 9785 case 'L': 9786 newname = RDATA_SECTION_NAME; 9787 if (g_switch_value >= 8) 9788 newname = ".lit8"; 9789 break; 9790 case 'F': 9791 newname = RDATA_SECTION_NAME; 9792 break; 9793 case 'l': 9794 assert (g_switch_value >= 4); 9795 newname = ".lit4"; 9796 break; 9797 } 9798 new_seg = subseg_new (newname, (subsegT) 0); 9799 if (IS_ELF) 9800 bfd_set_section_flags (stdoutput, new_seg, 9801 (SEC_ALLOC 9802 | SEC_LOAD 9803 | SEC_READONLY 9804 | SEC_DATA)); 9805 frag_align (*args == 'l' ? 2 : 3, 0, 0); 9806 if (IS_ELF && strcmp (TARGET_OS, "elf") != 0) 9807 record_alignment (new_seg, 4); 9808 else 9809 record_alignment (new_seg, *args == 'l' ? 2 : 3); 9810 if (seg == now_seg) 9811 as_bad (_("Can't use floating point insn in this section")); 9812 9813 /* Set the argument to the current address in the 9814 section. */ 9815 offset_expr.X_op = O_symbol; 9816 offset_expr.X_add_symbol = 9817 symbol_new ("L0\001", now_seg, 9818 (valueT) frag_now_fix (), frag_now); 9819 offset_expr.X_add_number = 0; 9820 9821 /* Put the floating point number into the section. */ 9822 p = frag_more ((int) length); 9823 memcpy (p, temp, length); 9824 9825 /* Switch back to the original section. */ 9826 subseg_set (seg, subseg); 9827 } 9828 } 9829 continue; 9830 9831 case 'i': /* 16 bit unsigned immediate */ 9832 case 'j': /* 16 bit signed immediate */ 9833 *imm_reloc = BFD_RELOC_LO16; 9834 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) 9835 { 9836 int more; 9837 offsetT minval, maxval; 9838 9839 more = (insn + 1 < &mips_opcodes[NUMOPCODES] 9840 && strcmp (insn->name, insn[1].name) == 0); 9841 9842 /* If the expression was written as an unsigned number, 9843 only treat it as signed if there are no more 9844 alternatives. */ 9845 if (more 9846 && *args == 'j' 9847 && sizeof (imm_expr.X_add_number) <= 4 9848 && imm_expr.X_op == O_constant 9849 && imm_expr.X_add_number < 0 9850 && imm_expr.X_unsigned 9851 && HAVE_64BIT_GPRS) 9852 break; 9853 9854 /* For compatibility with older assemblers, we accept 9855 0x8000-0xffff as signed 16-bit numbers when only 9856 signed numbers are allowed. */ 9857 if (*args == 'i') 9858 minval = 0, maxval = 0xffff; 9859 else if (more) 9860 minval = -0x8000, maxval = 0x7fff; 9861 else 9862 minval = -0x8000, maxval = 0xffff; 9863 9864 if (imm_expr.X_op != O_constant 9865 || imm_expr.X_add_number < minval 9866 || imm_expr.X_add_number > maxval) 9867 { 9868 if (more) 9869 break; 9870 if (imm_expr.X_op == O_constant 9871 || imm_expr.X_op == O_big) 9872 as_bad (_("expression out of range")); 9873 } 9874 } 9875 s = expr_end; 9876 continue; 9877 9878 case 'o': /* 16 bit offset */ 9879 /* Check whether there is only a single bracketed expression 9880 left. If so, it must be the base register and the 9881 constant must be zero. */ 9882 if (*s == '(' && strchr (s + 1, '(') == 0) 9883 { 9884 offset_expr.X_op = O_constant; 9885 offset_expr.X_add_number = 0; 9886 continue; 9887 } 9888 9889 /* If this value won't fit into a 16 bit offset, then go 9890 find a macro that will generate the 32 bit offset 9891 code pattern. */ 9892 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 9893 && (offset_expr.X_op != O_constant 9894 || offset_expr.X_add_number >= 0x8000 9895 || offset_expr.X_add_number < -0x8000)) 9896 break; 9897 9898 s = expr_end; 9899 continue; 9900 9901 case 'p': /* pc relative offset */ 9902 *offset_reloc = BFD_RELOC_16_PCREL_S2; 9903 my_getExpression (&offset_expr, s); 9904 s = expr_end; 9905 continue; 9906 9907 case 'u': /* upper 16 bits */ 9908 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 9909 && imm_expr.X_op == O_constant 9910 && (imm_expr.X_add_number < 0 9911 || imm_expr.X_add_number >= 0x10000)) 9912 as_bad (_("lui expression not in range 0..65535")); 9913 s = expr_end; 9914 continue; 9915 9916 case 'a': /* 26 bit address */ 9917 my_getExpression (&offset_expr, s); 9918 s = expr_end; 9919 *offset_reloc = BFD_RELOC_MIPS_JMP; 9920 continue; 9921 9922 case 'N': /* 3 bit branch condition code */ 9923 case 'M': /* 3 bit compare condition code */ 9924 rtype = RTYPE_CCC; 9925 if (ip->insn_mo->pinfo & (FP_D| FP_S)) 9926 rtype |= RTYPE_FCC; 9927 if (!reg_lookup (&s, rtype, ®no)) 9928 break; 9929 if ((strcmp(str + strlen(str) - 3, ".ps") == 0 9930 || strcmp(str + strlen(str) - 5, "any2f") == 0 9931 || strcmp(str + strlen(str) - 5, "any2t") == 0) 9932 && (regno & 1) != 0) 9933 as_warn(_("Condition code register should be even for %s, was %d"), 9934 str, regno); 9935 if ((strcmp(str + strlen(str) - 5, "any4f") == 0 9936 || strcmp(str + strlen(str) - 5, "any4t") == 0) 9937 && (regno & 3) != 0) 9938 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), 9939 str, regno); 9940 if (*args == 'N') 9941 INSERT_OPERAND (BCC, *ip, regno); 9942 else 9943 INSERT_OPERAND (CCC, *ip, regno); 9944 continue; 9945 9946 case 'H': 9947 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) 9948 s += 2; 9949 if (ISDIGIT (*s)) 9950 { 9951 c = 0; 9952 do 9953 { 9954 c *= 10; 9955 c += *s - '0'; 9956 ++s; 9957 } 9958 while (ISDIGIT (*s)); 9959 } 9960 else 9961 c = 8; /* Invalid sel value. */ 9962 9963 if (c > 7) 9964 as_bad (_("invalid coprocessor sub-selection value (0-7)")); 9965 ip->insn_opcode |= c; 9966 continue; 9967 9968 case 'e': 9969 /* Must be at least one digit. */ 9970 my_getExpression (&imm_expr, s); 9971 check_absolute_expr (ip, &imm_expr); 9972 9973 if ((unsigned long) imm_expr.X_add_number 9974 > (unsigned long) OP_MASK_VECBYTE) 9975 { 9976 as_bad (_("bad byte vector index (%ld)"), 9977 (long) imm_expr.X_add_number); 9978 imm_expr.X_add_number = 0; 9979 } 9980 9981 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); 9982 imm_expr.X_op = O_absent; 9983 s = expr_end; 9984 continue; 9985 9986 case '%': 9987 my_getExpression (&imm_expr, s); 9988 check_absolute_expr (ip, &imm_expr); 9989 9990 if ((unsigned long) imm_expr.X_add_number 9991 > (unsigned long) OP_MASK_VECALIGN) 9992 { 9993 as_bad (_("bad byte vector index (%ld)"), 9994 (long) imm_expr.X_add_number); 9995 imm_expr.X_add_number = 0; 9996 } 9997 9998 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); 9999 imm_expr.X_op = O_absent; 10000 s = expr_end; 10001 continue; 10002 10003 default: 10004 as_bad (_("bad char = '%c'\n"), *args); 10005 internalError (); 10006 } 10007 break; 10008 } 10009 /* Args don't match. */ 10010 if (insn + 1 < &mips_opcodes[NUMOPCODES] && 10011 !strcmp (insn->name, insn[1].name)) 10012 { 10013 ++insn; 10014 s = argsStart; 10015 insn_error = _("illegal operands"); 10016 continue; 10017 } 10018 if (save_c) 10019 *(--s) = save_c; 10020 insn_error = _("illegal operands"); 10021 return; 10022 } 10023} 10024 10025#define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } 10026 10027/* This routine assembles an instruction into its binary format when 10028 assembling for the mips16. As a side effect, it sets one of the 10029 global variables imm_reloc or offset_reloc to the type of 10030 relocation to do if one of the operands is an address expression. 10031 It also sets mips16_small and mips16_ext if the user explicitly 10032 requested a small or extended instruction. */ 10033 10034static void 10035mips16_ip (char *str, struct mips_cl_insn *ip) 10036{ 10037 char *s; 10038 const char *args; 10039 struct mips_opcode *insn; 10040 char *argsstart; 10041 unsigned int regno; 10042 unsigned int lastregno = 0; 10043 char *s_reset; 10044 size_t i; 10045 10046 insn_error = NULL; 10047 10048 mips16_small = FALSE; 10049 mips16_ext = FALSE; 10050 10051 for (s = str; ISLOWER (*s); ++s) 10052 ; 10053 switch (*s) 10054 { 10055 case '\0': 10056 break; 10057 10058 case ' ': 10059 *s++ = '\0'; 10060 break; 10061 10062 case '.': 10063 if (s[1] == 't' && s[2] == ' ') 10064 { 10065 *s = '\0'; 10066 mips16_small = TRUE; 10067 s += 3; 10068 break; 10069 } 10070 else if (s[1] == 'e' && s[2] == ' ') 10071 { 10072 *s = '\0'; 10073 mips16_ext = TRUE; 10074 s += 3; 10075 break; 10076 } 10077 /* Fall through. */ 10078 default: 10079 insn_error = _("unknown opcode"); 10080 return; 10081 } 10082 10083 if (mips_opts.noautoextend && ! mips16_ext) 10084 mips16_small = TRUE; 10085 10086 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) 10087 { 10088 insn_error = _("unrecognized opcode"); 10089 return; 10090 } 10091 10092 argsstart = s; 10093 for (;;) 10094 { 10095 bfd_boolean ok; 10096 10097 assert (strcmp (insn->name, str) == 0); 10098 10099 if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_opts.arch)) 10100 ok = TRUE; 10101 else 10102 ok = FALSE; 10103 10104 if (! ok) 10105 { 10106 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] 10107 && strcmp (insn->name, insn[1].name) == 0) 10108 { 10109 ++insn; 10110 continue; 10111 } 10112 else 10113 { 10114 if (!insn_error) 10115 { 10116 static char buf[100]; 10117 sprintf (buf, 10118 _("opcode not supported on this processor: %s (%s)"), 10119 mips_cpu_info_from_arch (mips_opts.arch)->name, 10120 mips_cpu_info_from_isa (mips_opts.isa)->name); 10121 insn_error = buf; 10122 } 10123 return; 10124 } 10125 } 10126 10127 create_insn (ip, insn); 10128 imm_expr.X_op = O_absent; 10129 imm_reloc[0] = BFD_RELOC_UNUSED; 10130 imm_reloc[1] = BFD_RELOC_UNUSED; 10131 imm_reloc[2] = BFD_RELOC_UNUSED; 10132 imm2_expr.X_op = O_absent; 10133 offset_expr.X_op = O_absent; 10134 offset_reloc[0] = BFD_RELOC_UNUSED; 10135 offset_reloc[1] = BFD_RELOC_UNUSED; 10136 offset_reloc[2] = BFD_RELOC_UNUSED; 10137 for (args = insn->args; 1; ++args) 10138 { 10139 int c; 10140 10141 if (*s == ' ') 10142 ++s; 10143 10144 /* In this switch statement we call break if we did not find 10145 a match, continue if we did find a match, or return if we 10146 are done. */ 10147 10148 c = *args; 10149 switch (c) 10150 { 10151 case '\0': 10152 if (*s == '\0') 10153 { 10154 /* Stuff the immediate value in now, if we can. */ 10155 if (imm_expr.X_op == O_constant 10156 && *imm_reloc > BFD_RELOC_UNUSED 10157 && insn->pinfo != INSN_MACRO) 10158 { 10159 valueT tmp; 10160 10161 switch (*offset_reloc) 10162 { 10163 case BFD_RELOC_MIPS16_HI16_S: 10164 tmp = (imm_expr.X_add_number + 0x8000) >> 16; 10165 break; 10166 10167 case BFD_RELOC_MIPS16_HI16: 10168 tmp = imm_expr.X_add_number >> 16; 10169 break; 10170 10171 case BFD_RELOC_MIPS16_LO16: 10172 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) 10173 - 0x8000; 10174 break; 10175 10176 case BFD_RELOC_UNUSED: 10177 tmp = imm_expr.X_add_number; 10178 break; 10179 10180 default: 10181 internalError (); 10182 } 10183 *offset_reloc = BFD_RELOC_UNUSED; 10184 10185 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, 10186 tmp, TRUE, mips16_small, 10187 mips16_ext, &ip->insn_opcode, 10188 &ip->use_extend, &ip->extend); 10189 imm_expr.X_op = O_absent; 10190 *imm_reloc = BFD_RELOC_UNUSED; 10191 } 10192 10193 return; 10194 } 10195 break; 10196 10197 case ',': 10198 if (*s++ == c) 10199 continue; 10200 s--; 10201 switch (*++args) 10202 { 10203 case 'v': 10204 MIPS16_INSERT_OPERAND (RX, *ip, lastregno); 10205 continue; 10206 case 'w': 10207 MIPS16_INSERT_OPERAND (RY, *ip, lastregno); 10208 continue; 10209 } 10210 break; 10211 10212 case '(': 10213 case ')': 10214 if (*s++ == c) 10215 continue; 10216 break; 10217 10218 case 'v': 10219 case 'w': 10220 if (s[0] != '$') 10221 { 10222 if (c == 'v') 10223 MIPS16_INSERT_OPERAND (RX, *ip, lastregno); 10224 else 10225 MIPS16_INSERT_OPERAND (RY, *ip, lastregno); 10226 ++args; 10227 continue; 10228 } 10229 /* Fall through. */ 10230 case 'x': 10231 case 'y': 10232 case 'z': 10233 case 'Z': 10234 case '0': 10235 case 'S': 10236 case 'R': 10237 case 'X': 10238 case 'Y': 10239 s_reset = s; 10240 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) 10241 { 10242 if (c == 'v' || c == 'w') 10243 { 10244 if (c == 'v') 10245 MIPS16_INSERT_OPERAND (RX, *ip, lastregno); 10246 else 10247 MIPS16_INSERT_OPERAND (RY, *ip, lastregno); 10248 ++args; 10249 continue; 10250 } 10251 break; 10252 } 10253 10254 if (*s == ' ') 10255 ++s; 10256 if (args[1] != *s) 10257 { 10258 if (c == 'v' || c == 'w') 10259 { 10260 regno = mips16_to_32_reg_map[lastregno]; 10261 s = s_reset; 10262 ++args; 10263 } 10264 } 10265 10266 switch (c) 10267 { 10268 case 'x': 10269 case 'y': 10270 case 'z': 10271 case 'v': 10272 case 'w': 10273 case 'Z': 10274 regno = mips32_to_16_reg_map[regno]; 10275 break; 10276 10277 case '0': 10278 if (regno != 0) 10279 regno = ILLEGAL_REG; 10280 break; 10281 10282 case 'S': 10283 if (regno != SP) 10284 regno = ILLEGAL_REG; 10285 break; 10286 10287 case 'R': 10288 if (regno != RA) 10289 regno = ILLEGAL_REG; 10290 break; 10291 10292 case 'X': 10293 case 'Y': 10294 if (regno == AT && ! mips_opts.noat) 10295 as_warn (_("used $at without \".set noat\"")); 10296 break; 10297 10298 default: 10299 internalError (); 10300 } 10301 10302 if (regno == ILLEGAL_REG) 10303 break; 10304 10305 switch (c) 10306 { 10307 case 'x': 10308 case 'v': 10309 MIPS16_INSERT_OPERAND (RX, *ip, regno); 10310 break; 10311 case 'y': 10312 case 'w': 10313 MIPS16_INSERT_OPERAND (RY, *ip, regno); 10314 break; 10315 case 'z': 10316 MIPS16_INSERT_OPERAND (RZ, *ip, regno); 10317 break; 10318 case 'Z': 10319 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); 10320 case '0': 10321 case 'S': 10322 case 'R': 10323 break; 10324 case 'X': 10325 MIPS16_INSERT_OPERAND (REGR32, *ip, regno); 10326 break; 10327 case 'Y': 10328 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); 10329 MIPS16_INSERT_OPERAND (REG32R, *ip, regno); 10330 break; 10331 default: 10332 internalError (); 10333 } 10334 10335 lastregno = regno; 10336 continue; 10337 10338 case 'P': 10339 if (strncmp (s, "$pc", 3) == 0) 10340 { 10341 s += 3; 10342 continue; 10343 } 10344 break; 10345 10346 case '5': 10347 case 'H': 10348 case 'W': 10349 case 'D': 10350 case 'j': 10351 case 'V': 10352 case 'C': 10353 case 'U': 10354 case 'k': 10355 case 'K': 10356 i = my_getSmallExpression (&imm_expr, imm_reloc, s); 10357 if (i > 0) 10358 { 10359 if (imm_expr.X_op != O_constant) 10360 { 10361 mips16_ext = TRUE; 10362 ip->use_extend = TRUE; 10363 ip->extend = 0; 10364 } 10365 else 10366 { 10367 /* We need to relax this instruction. */ 10368 *offset_reloc = *imm_reloc; 10369 *imm_reloc = (int) BFD_RELOC_UNUSED + c; 10370 } 10371 s = expr_end; 10372 continue; 10373 } 10374 *imm_reloc = BFD_RELOC_UNUSED; 10375 /* Fall through. */ 10376 case '<': 10377 case '>': 10378 case '[': 10379 case ']': 10380 case '4': 10381 case '8': 10382 my_getExpression (&imm_expr, s); 10383 if (imm_expr.X_op == O_register) 10384 { 10385 /* What we thought was an expression turned out to 10386 be a register. */ 10387 10388 if (s[0] == '(' && args[1] == '(') 10389 { 10390 /* It looks like the expression was omitted 10391 before a register indirection, which means 10392 that the expression is implicitly zero. We 10393 still set up imm_expr, so that we handle 10394 explicit extensions correctly. */ 10395 imm_expr.X_op = O_constant; 10396 imm_expr.X_add_number = 0; 10397 *imm_reloc = (int) BFD_RELOC_UNUSED + c; 10398 continue; 10399 } 10400 10401 break; 10402 } 10403 10404 /* We need to relax this instruction. */ 10405 *imm_reloc = (int) BFD_RELOC_UNUSED + c; 10406 s = expr_end; 10407 continue; 10408 10409 case 'p': 10410 case 'q': 10411 case 'A': 10412 case 'B': 10413 case 'E': 10414 /* We use offset_reloc rather than imm_reloc for the PC 10415 relative operands. This lets macros with both 10416 immediate and address operands work correctly. */ 10417 my_getExpression (&offset_expr, s); 10418 10419 if (offset_expr.X_op == O_register) 10420 break; 10421 10422 /* We need to relax this instruction. */ 10423 *offset_reloc = (int) BFD_RELOC_UNUSED + c; 10424 s = expr_end; 10425 continue; 10426 10427 case '6': /* break code */ 10428 my_getExpression (&imm_expr, s); 10429 check_absolute_expr (ip, &imm_expr); 10430 if ((unsigned long) imm_expr.X_add_number > 63) 10431 as_warn (_("Invalid value for `%s' (%lu)"), 10432 ip->insn_mo->name, 10433 (unsigned long) imm_expr.X_add_number); 10434 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); 10435 imm_expr.X_op = O_absent; 10436 s = expr_end; 10437 continue; 10438 10439 case 'a': /* 26 bit address */ 10440 my_getExpression (&offset_expr, s); 10441 s = expr_end; 10442 *offset_reloc = BFD_RELOC_MIPS16_JMP; 10443 ip->insn_opcode <<= 16; 10444 continue; 10445 10446 case 'l': /* register list for entry macro */ 10447 case 'L': /* register list for exit macro */ 10448 { 10449 int mask; 10450 10451 if (c == 'l') 10452 mask = 0; 10453 else 10454 mask = 7 << 3; 10455 while (*s != '\0') 10456 { 10457 unsigned int freg, reg1, reg2; 10458 10459 while (*s == ' ' || *s == ',') 10460 ++s; 10461 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) 10462 freg = 0; 10463 else if (reg_lookup (&s, RTYPE_FPU, ®1)) 10464 freg = 1; 10465 else 10466 { 10467 as_bad (_("can't parse register list")); 10468 break; 10469 } 10470 if (*s == ' ') 10471 ++s; 10472 if (*s != '-') 10473 reg2 = reg1; 10474 else 10475 { 10476 ++s; 10477 if (!reg_lookup (&s, freg ? RTYPE_FPU 10478 : (RTYPE_GP | RTYPE_NUM), ®2)) 10479 { 10480 as_bad (_("invalid register list")); 10481 break; 10482 } 10483 } 10484 if (freg && reg1 == 0 && reg2 == 0 && c == 'L') 10485 { 10486 mask &= ~ (7 << 3); 10487 mask |= 5 << 3; 10488 } 10489 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') 10490 { 10491 mask &= ~ (7 << 3); 10492 mask |= 6 << 3; 10493 } 10494 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') 10495 mask |= (reg2 - 3) << 3; 10496 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) 10497 mask |= (reg2 - 15) << 1; 10498 else if (reg1 == RA && reg2 == RA) 10499 mask |= 1; 10500 else 10501 { 10502 as_bad (_("invalid register list")); 10503 break; 10504 } 10505 } 10506 /* The mask is filled in in the opcode table for the 10507 benefit of the disassembler. We remove it before 10508 applying the actual mask. */ 10509 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); 10510 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; 10511 } 10512 continue; 10513 10514 case 'm': /* Register list for save insn. */ 10515 case 'M': /* Register list for restore insn. */ 10516 { 10517 int opcode = 0; 10518 int framesz = 0, seen_framesz = 0; 10519 int args = 0, statics = 0, sregs = 0; 10520 10521 while (*s != '\0') 10522 { 10523 unsigned int reg1, reg2; 10524 10525 SKIP_SPACE_TABS (s); 10526 while (*s == ',') 10527 ++s; 10528 SKIP_SPACE_TABS (s); 10529 10530 my_getExpression (&imm_expr, s); 10531 if (imm_expr.X_op == O_constant) 10532 { 10533 /* Handle the frame size. */ 10534 if (seen_framesz) 10535 { 10536 as_bad (_("more than one frame size in list")); 10537 break; 10538 } 10539 seen_framesz = 1; 10540 framesz = imm_expr.X_add_number; 10541 imm_expr.X_op = O_absent; 10542 s = expr_end; 10543 continue; 10544 } 10545 10546 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) 10547 { 10548 as_bad (_("can't parse register list")); 10549 break; 10550 } 10551 10552 while (*s == ' ') 10553 ++s; 10554 10555 if (*s != '-') 10556 reg2 = reg1; 10557 else 10558 { 10559 ++s; 10560 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) 10561 || reg2 < reg1) 10562 { 10563 as_bad (_("can't parse register list")); 10564 break; 10565 } 10566 } 10567 10568 while (reg1 <= reg2) 10569 { 10570 if (reg1 >= 4 && reg1 <= 7) 10571 { 10572 if (!seen_framesz) 10573 /* args $a0-$a3 */ 10574 args |= 1 << (reg1 - 4); 10575 else 10576 /* statics $a0-$a3 */ 10577 statics |= 1 << (reg1 - 4); 10578 } 10579 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) 10580 { 10581 /* $s0-$s8 */ 10582 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); 10583 } 10584 else if (reg1 == 31) 10585 { 10586 /* Add $ra to insn. */ 10587 opcode |= 0x40; 10588 } 10589 else 10590 { 10591 as_bad (_("unexpected register in list")); 10592 break; 10593 } 10594 if (++reg1 == 24) 10595 reg1 = 30; 10596 } 10597 } 10598 10599 /* Encode args/statics combination. */ 10600 if (args & statics) 10601 as_bad (_("arg/static registers overlap")); 10602 else if (args == 0xf) 10603 /* All $a0-$a3 are args. */ 10604 opcode |= MIPS16_ALL_ARGS << 16; 10605 else if (statics == 0xf) 10606 /* All $a0-$a3 are statics. */ 10607 opcode |= MIPS16_ALL_STATICS << 16; 10608 else 10609 { 10610 int narg = 0, nstat = 0; 10611 10612 /* Count arg registers. */ 10613 while (args & 0x1) 10614 { 10615 args >>= 1; 10616 narg++; 10617 } 10618 if (args != 0) 10619 as_bad (_("invalid arg register list")); 10620 10621 /* Count static registers. */ 10622 while (statics & 0x8) 10623 { 10624 statics = (statics << 1) & 0xf; 10625 nstat++; 10626 } 10627 if (statics != 0) 10628 as_bad (_("invalid static register list")); 10629 10630 /* Encode args/statics. */ 10631 opcode |= ((narg << 2) | nstat) << 16; 10632 } 10633 10634 /* Encode $s0/$s1. */ 10635 if (sregs & (1 << 0)) /* $s0 */ 10636 opcode |= 0x20; 10637 if (sregs & (1 << 1)) /* $s1 */ 10638 opcode |= 0x10; 10639 sregs >>= 2; 10640 10641 if (sregs != 0) 10642 { 10643 /* Count regs $s2-$s8. */ 10644 int nsreg = 0; 10645 while (sregs & 1) 10646 { 10647 sregs >>= 1; 10648 nsreg++; 10649 } 10650 if (sregs != 0) 10651 as_bad (_("invalid static register list")); 10652 /* Encode $s2-$s8. */ 10653 opcode |= nsreg << 24; 10654 } 10655 10656 /* Encode frame size. */ 10657 if (!seen_framesz) 10658 as_bad (_("missing frame size")); 10659 else if ((framesz & 7) != 0 || framesz < 0 10660 || framesz > 0xff * 8) 10661 as_bad (_("invalid frame size")); 10662 else if (framesz != 128 || (opcode >> 16) != 0) 10663 { 10664 framesz /= 8; 10665 opcode |= (((framesz & 0xf0) << 16) 10666 | (framesz & 0x0f)); 10667 } 10668 10669 /* Finally build the instruction. */ 10670 if ((opcode >> 16) != 0 || framesz == 0) 10671 { 10672 ip->use_extend = TRUE; 10673 ip->extend = opcode >> 16; 10674 } 10675 ip->insn_opcode |= opcode & 0x7f; 10676 } 10677 continue; 10678 10679 case 'e': /* extend code */ 10680 my_getExpression (&imm_expr, s); 10681 check_absolute_expr (ip, &imm_expr); 10682 if ((unsigned long) imm_expr.X_add_number > 0x7ff) 10683 { 10684 as_warn (_("Invalid value for `%s' (%lu)"), 10685 ip->insn_mo->name, 10686 (unsigned long) imm_expr.X_add_number); 10687 imm_expr.X_add_number &= 0x7ff; 10688 } 10689 ip->insn_opcode |= imm_expr.X_add_number; 10690 imm_expr.X_op = O_absent; 10691 s = expr_end; 10692 continue; 10693 10694 default: 10695 internalError (); 10696 } 10697 break; 10698 } 10699 10700 /* Args don't match. */ 10701 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && 10702 strcmp (insn->name, insn[1].name) == 0) 10703 { 10704 ++insn; 10705 s = argsstart; 10706 continue; 10707 } 10708 10709 insn_error = _("illegal operands"); 10710 10711 return; 10712 } 10713} 10714 10715/* This structure holds information we know about a mips16 immediate 10716 argument type. */ 10717 10718struct mips16_immed_operand 10719{ 10720 /* The type code used in the argument string in the opcode table. */ 10721 int type; 10722 /* The number of bits in the short form of the opcode. */ 10723 int nbits; 10724 /* The number of bits in the extended form of the opcode. */ 10725 int extbits; 10726 /* The amount by which the short form is shifted when it is used; 10727 for example, the sw instruction has a shift count of 2. */ 10728 int shift; 10729 /* The amount by which the short form is shifted when it is stored 10730 into the instruction code. */ 10731 int op_shift; 10732 /* Non-zero if the short form is unsigned. */ 10733 int unsp; 10734 /* Non-zero if the extended form is unsigned. */ 10735 int extu; 10736 /* Non-zero if the value is PC relative. */ 10737 int pcrel; 10738}; 10739 10740/* The mips16 immediate operand types. */ 10741 10742static const struct mips16_immed_operand mips16_immed_operands[] = 10743{ 10744 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, 10745 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, 10746 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, 10747 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, 10748 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, 10749 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, 10750 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, 10751 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, 10752 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, 10753 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, 10754 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, 10755 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, 10756 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, 10757 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, 10758 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, 10759 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, 10760 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, 10761 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, 10762 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, 10763 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, 10764 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } 10765}; 10766 10767#define MIPS16_NUM_IMMED \ 10768 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) 10769 10770/* Handle a mips16 instruction with an immediate value. This or's the 10771 small immediate value into *INSN. It sets *USE_EXTEND to indicate 10772 whether an extended value is needed; if one is needed, it sets 10773 *EXTEND to the value. The argument type is TYPE. The value is VAL. 10774 If SMALL is true, an unextended opcode was explicitly requested. 10775 If EXT is true, an extended opcode was explicitly requested. If 10776 WARN is true, warn if EXT does not match reality. */ 10777 10778static void 10779mips16_immed (char *file, unsigned int line, int type, offsetT val, 10780 bfd_boolean warn, bfd_boolean small, bfd_boolean ext, 10781 unsigned long *insn, bfd_boolean *use_extend, 10782 unsigned short *extend) 10783{ 10784 const struct mips16_immed_operand *op; 10785 int mintiny, maxtiny; 10786 bfd_boolean needext; 10787 10788 op = mips16_immed_operands; 10789 while (op->type != type) 10790 { 10791 ++op; 10792 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); 10793 } 10794 10795 if (op->unsp) 10796 { 10797 if (type == '<' || type == '>' || type == '[' || type == ']') 10798 { 10799 mintiny = 1; 10800 maxtiny = 1 << op->nbits; 10801 } 10802 else 10803 { 10804 mintiny = 0; 10805 maxtiny = (1 << op->nbits) - 1; 10806 } 10807 } 10808 else 10809 { 10810 mintiny = - (1 << (op->nbits - 1)); 10811 maxtiny = (1 << (op->nbits - 1)) - 1; 10812 } 10813 10814 /* Branch offsets have an implicit 0 in the lowest bit. */ 10815 if (type == 'p' || type == 'q') 10816 val /= 2; 10817 10818 if ((val & ((1 << op->shift) - 1)) != 0 10819 || val < (mintiny << op->shift) 10820 || val > (maxtiny << op->shift)) 10821 needext = TRUE; 10822 else 10823 needext = FALSE; 10824 10825 if (warn && ext && ! needext) 10826 as_warn_where (file, line, 10827 _("extended operand requested but not required")); 10828 if (small && needext) 10829 as_bad_where (file, line, _("invalid unextended operand value")); 10830 10831 if (small || (! ext && ! needext)) 10832 { 10833 int insnval; 10834 10835 *use_extend = FALSE; 10836 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); 10837 insnval <<= op->op_shift; 10838 *insn |= insnval; 10839 } 10840 else 10841 { 10842 long minext, maxext; 10843 int extval; 10844 10845 if (op->extu) 10846 { 10847 minext = 0; 10848 maxext = (1 << op->extbits) - 1; 10849 } 10850 else 10851 { 10852 minext = - (1 << (op->extbits - 1)); 10853 maxext = (1 << (op->extbits - 1)) - 1; 10854 } 10855 if (val < minext || val > maxext) 10856 as_bad_where (file, line, 10857 _("operand value out of range for instruction")); 10858 10859 *use_extend = TRUE; 10860 if (op->extbits == 16) 10861 { 10862 extval = ((val >> 11) & 0x1f) | (val & 0x7e0); 10863 val &= 0x1f; 10864 } 10865 else if (op->extbits == 15) 10866 { 10867 extval = ((val >> 11) & 0xf) | (val & 0x7f0); 10868 val &= 0xf; 10869 } 10870 else 10871 { 10872 extval = ((val & 0x1f) << 6) | (val & 0x20); 10873 val = 0; 10874 } 10875 10876 *extend = (unsigned short) extval; 10877 *insn |= val; 10878 } 10879} 10880 10881struct percent_op_match 10882{ 10883 const char *str; 10884 bfd_reloc_code_real_type reloc; 10885}; 10886 10887static const struct percent_op_match mips_percent_op[] = 10888{ 10889 {"%lo", BFD_RELOC_LO16}, 10890#ifdef OBJ_ELF 10891 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, 10892 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, 10893 {"%call16", BFD_RELOC_MIPS_CALL16}, 10894 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, 10895 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, 10896 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, 10897 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, 10898 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, 10899 {"%got", BFD_RELOC_MIPS_GOT16}, 10900 {"%gp_rel", BFD_RELOC_GPREL16}, 10901 {"%half", BFD_RELOC_16}, 10902 {"%highest", BFD_RELOC_MIPS_HIGHEST}, 10903 {"%higher", BFD_RELOC_MIPS_HIGHER}, 10904 {"%neg", BFD_RELOC_MIPS_SUB}, 10905 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, 10906 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, 10907 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, 10908 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, 10909 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, 10910 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, 10911 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, 10912#endif 10913 {"%hi", BFD_RELOC_HI16_S} 10914}; 10915 10916static const struct percent_op_match mips16_percent_op[] = 10917{ 10918 {"%lo", BFD_RELOC_MIPS16_LO16}, 10919 {"%gprel", BFD_RELOC_MIPS16_GPREL}, 10920 {"%hi", BFD_RELOC_MIPS16_HI16_S} 10921}; 10922 10923 10924/* Return true if *STR points to a relocation operator. When returning true, 10925 move *STR over the operator and store its relocation code in *RELOC. 10926 Leave both *STR and *RELOC alone when returning false. */ 10927 10928static bfd_boolean 10929parse_relocation (char **str, bfd_reloc_code_real_type *reloc) 10930{ 10931 const struct percent_op_match *percent_op; 10932 size_t limit, i; 10933 10934 if (mips_opts.mips16) 10935 { 10936 percent_op = mips16_percent_op; 10937 limit = ARRAY_SIZE (mips16_percent_op); 10938 } 10939 else 10940 { 10941 percent_op = mips_percent_op; 10942 limit = ARRAY_SIZE (mips_percent_op); 10943 } 10944 10945 for (i = 0; i < limit; i++) 10946 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) 10947 { 10948 int len = strlen (percent_op[i].str); 10949 10950 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') 10951 continue; 10952 10953 *str += strlen (percent_op[i].str); 10954 *reloc = percent_op[i].reloc; 10955 10956 /* Check whether the output BFD supports this relocation. 10957 If not, issue an error and fall back on something safe. */ 10958 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) 10959 { 10960 as_bad ("relocation %s isn't supported by the current ABI", 10961 percent_op[i].str); 10962 *reloc = BFD_RELOC_UNUSED; 10963 } 10964 return TRUE; 10965 } 10966 return FALSE; 10967} 10968 10969 10970/* Parse string STR as a 16-bit relocatable operand. Store the 10971 expression in *EP and the relocations in the array starting 10972 at RELOC. Return the number of relocation operators used. 10973 10974 On exit, EXPR_END points to the first character after the expression. */ 10975 10976static size_t 10977my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, 10978 char *str) 10979{ 10980 bfd_reloc_code_real_type reversed_reloc[3]; 10981 size_t reloc_index, i; 10982 int crux_depth, str_depth; 10983 char *crux; 10984 10985 /* Search for the start of the main expression, recoding relocations 10986 in REVERSED_RELOC. End the loop with CRUX pointing to the start 10987 of the main expression and with CRUX_DEPTH containing the number 10988 of open brackets at that point. */ 10989 reloc_index = -1; 10990 str_depth = 0; 10991 do 10992 { 10993 reloc_index++; 10994 crux = str; 10995 crux_depth = str_depth; 10996 10997 /* Skip over whitespace and brackets, keeping count of the number 10998 of brackets. */ 10999 while (*str == ' ' || *str == '\t' || *str == '(') 11000 if (*str++ == '(') 11001 str_depth++; 11002 } 11003 while (*str == '%' 11004 && reloc_index < (HAVE_NEWABI ? 3 : 1) 11005 && parse_relocation (&str, &reversed_reloc[reloc_index])); 11006 11007 my_getExpression (ep, crux); 11008 str = expr_end; 11009 11010 /* Match every open bracket. */ 11011 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) 11012 if (*str++ == ')') 11013 crux_depth--; 11014 11015 if (crux_depth > 0) 11016 as_bad ("unclosed '('"); 11017 11018 expr_end = str; 11019 11020 if (reloc_index != 0) 11021 { 11022 prev_reloc_op_frag = frag_now; 11023 for (i = 0; i < reloc_index; i++) 11024 reloc[i] = reversed_reloc[reloc_index - 1 - i]; 11025 } 11026 11027 return reloc_index; 11028} 11029 11030static void 11031my_getExpression (expressionS *ep, char *str) 11032{ 11033 char *save_in; 11034 valueT val; 11035 11036 save_in = input_line_pointer; 11037 input_line_pointer = str; 11038 expression (ep); 11039 expr_end = input_line_pointer; 11040 input_line_pointer = save_in; 11041 11042 /* If we are in mips16 mode, and this is an expression based on `.', 11043 then we bump the value of the symbol by 1 since that is how other 11044 text symbols are handled. We don't bother to handle complex 11045 expressions, just `.' plus or minus a constant. */ 11046 if (mips_opts.mips16 11047 && ep->X_op == O_symbol 11048 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 11049 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg 11050 && symbol_get_frag (ep->X_add_symbol) == frag_now 11051 && symbol_constant_p (ep->X_add_symbol) 11052 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) 11053 S_SET_VALUE (ep->X_add_symbol, val + 1); 11054} 11055 11056/* Turn a string in input_line_pointer into a floating point constant 11057 of type TYPE, and store the appropriate bytes in *LITP. The number 11058 of LITTLENUMS emitted is stored in *SIZEP. An error message is 11059 returned, or NULL on OK. */ 11060 11061char * 11062md_atof (int type, char *litP, int *sizeP) 11063{ 11064 int prec; 11065 LITTLENUM_TYPE words[4]; 11066 char *t; 11067 int i; 11068 11069 switch (type) 11070 { 11071 case 'f': 11072 prec = 2; 11073 break; 11074 11075 case 'd': 11076 prec = 4; 11077 break; 11078 11079 default: 11080 *sizeP = 0; 11081 return _("bad call to md_atof"); 11082 } 11083 11084 t = atof_ieee (input_line_pointer, type, words); 11085 if (t) 11086 input_line_pointer = t; 11087 11088 *sizeP = prec * 2; 11089 11090 if (! target_big_endian) 11091 { 11092 for (i = prec - 1; i >= 0; i--) 11093 { 11094 md_number_to_chars (litP, words[i], 2); 11095 litP += 2; 11096 } 11097 } 11098 else 11099 { 11100 for (i = 0; i < prec; i++) 11101 { 11102 md_number_to_chars (litP, words[i], 2); 11103 litP += 2; 11104 } 11105 } 11106 11107 return NULL; 11108} 11109 11110void 11111md_number_to_chars (char *buf, valueT val, int n) 11112{ 11113 if (target_big_endian) 11114 number_to_chars_bigendian (buf, val, n); 11115 else 11116 number_to_chars_littleendian (buf, val, n); 11117} 11118 11119#ifdef OBJ_ELF 11120static int support_64bit_objects(void) 11121{ 11122 const char **list, **l; 11123 int yes; 11124 11125 list = bfd_target_list (); 11126 for (l = list; *l != NULL; l++) 11127#ifdef TE_TMIPS 11128 /* This is traditional mips */ 11129 if (strcmp (*l, "elf64-tradbigmips") == 0 11130 || strcmp (*l, "elf64-tradlittlemips") == 0) 11131#else 11132 if (strcmp (*l, "elf64-bigmips") == 0 11133 || strcmp (*l, "elf64-littlemips") == 0) 11134#endif 11135 break; 11136 yes = (*l != NULL); 11137 free (list); 11138 return yes; 11139} 11140#endif /* OBJ_ELF */ 11141 11142const char *md_shortopts = "O::g::G:"; 11143 11144struct option md_longopts[] = 11145{ 11146 /* Options which specify architecture. */ 11147#define OPTION_ARCH_BASE (OPTION_MD_BASE) 11148#define OPTION_MARCH (OPTION_ARCH_BASE + 0) 11149 {"march", required_argument, NULL, OPTION_MARCH}, 11150#define OPTION_MTUNE (OPTION_ARCH_BASE + 1) 11151 {"mtune", required_argument, NULL, OPTION_MTUNE}, 11152#define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) 11153 {"mips0", no_argument, NULL, OPTION_MIPS1}, 11154 {"mips1", no_argument, NULL, OPTION_MIPS1}, 11155#define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) 11156 {"mips2", no_argument, NULL, OPTION_MIPS2}, 11157#define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) 11158 {"mips3", no_argument, NULL, OPTION_MIPS3}, 11159#define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) 11160 {"mips4", no_argument, NULL, OPTION_MIPS4}, 11161#define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) 11162 {"mips5", no_argument, NULL, OPTION_MIPS5}, 11163#define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) 11164 {"mips32", no_argument, NULL, OPTION_MIPS32}, 11165#define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) 11166 {"mips64", no_argument, NULL, OPTION_MIPS64}, 11167#define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) 11168 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, 11169#define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) 11170 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, 11171 11172 /* Options which specify Application Specific Extensions (ASEs). */ 11173#define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) 11174#define OPTION_MIPS16 (OPTION_ASE_BASE + 0) 11175 {"mips16", no_argument, NULL, OPTION_MIPS16}, 11176#define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) 11177 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, 11178#define OPTION_MIPS3D (OPTION_ASE_BASE + 2) 11179 {"mips3d", no_argument, NULL, OPTION_MIPS3D}, 11180#define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) 11181 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, 11182#define OPTION_MDMX (OPTION_ASE_BASE + 4) 11183 {"mdmx", no_argument, NULL, OPTION_MDMX}, 11184#define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) 11185 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, 11186#define OPTION_DSP (OPTION_ASE_BASE + 6) 11187 {"mdsp", no_argument, NULL, OPTION_DSP}, 11188#define OPTION_NO_DSP (OPTION_ASE_BASE + 7) 11189 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, 11190#define OPTION_MT (OPTION_ASE_BASE + 8) 11191 {"mmt", no_argument, NULL, OPTION_MT}, 11192#define OPTION_NO_MT (OPTION_ASE_BASE + 9) 11193 {"mno-mt", no_argument, NULL, OPTION_NO_MT}, 11194#define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10) 11195 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, 11196#define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11) 11197 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, 11198#define OPTION_DSPR2 (OPTION_ASE_BASE + 12) 11199 {"mdspr2", no_argument, NULL, OPTION_DSPR2}, 11200#define OPTION_NO_DSPR2 (OPTION_ASE_BASE + 13) 11201 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, 11202 11203 /* Old-style architecture options. Don't add more of these. */ 11204#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 14) 11205#define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) 11206 {"m4650", no_argument, NULL, OPTION_M4650}, 11207#define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) 11208 {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, 11209#define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) 11210 {"m4010", no_argument, NULL, OPTION_M4010}, 11211#define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) 11212 {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, 11213#define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) 11214 {"m4100", no_argument, NULL, OPTION_M4100}, 11215#define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) 11216 {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, 11217#define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) 11218 {"m3900", no_argument, NULL, OPTION_M3900}, 11219#define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) 11220 {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, 11221 11222 /* Options which enable bug fixes. */ 11223#define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) 11224#define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) 11225 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, 11226#define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) 11227 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, 11228 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, 11229#define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) 11230#define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) 11231 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, 11232 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, 11233#define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4) 11234#define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5) 11235 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, 11236 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, 11237 11238 /* Miscellaneous options. */ 11239#define OPTION_MISC_BASE (OPTION_FIX_BASE + 6) 11240#define OPTION_TRAP (OPTION_MISC_BASE + 0) 11241 {"trap", no_argument, NULL, OPTION_TRAP}, 11242 {"no-break", no_argument, NULL, OPTION_TRAP}, 11243#define OPTION_BREAK (OPTION_MISC_BASE + 1) 11244 {"break", no_argument, NULL, OPTION_BREAK}, 11245 {"no-trap", no_argument, NULL, OPTION_BREAK}, 11246#define OPTION_EB (OPTION_MISC_BASE + 2) 11247 {"EB", no_argument, NULL, OPTION_EB}, 11248#define OPTION_EL (OPTION_MISC_BASE + 3) 11249 {"EL", no_argument, NULL, OPTION_EL}, 11250#define OPTION_FP32 (OPTION_MISC_BASE + 4) 11251 {"mfp32", no_argument, NULL, OPTION_FP32}, 11252#define OPTION_GP32 (OPTION_MISC_BASE + 5) 11253 {"mgp32", no_argument, NULL, OPTION_GP32}, 11254#define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) 11255 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, 11256#define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) 11257 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, 11258#define OPTION_FP64 (OPTION_MISC_BASE + 8) 11259 {"mfp64", no_argument, NULL, OPTION_FP64}, 11260#define OPTION_GP64 (OPTION_MISC_BASE + 9) 11261 {"mgp64", no_argument, NULL, OPTION_GP64}, 11262#define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) 11263#define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) 11264 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, 11265 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, 11266#define OPTION_MSHARED (OPTION_MISC_BASE + 12) 11267#define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) 11268 {"mshared", no_argument, NULL, OPTION_MSHARED}, 11269 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, 11270#define OPTION_MSYM32 (OPTION_MISC_BASE + 14) 11271#define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15) 11272 {"msym32", no_argument, NULL, OPTION_MSYM32}, 11273 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, 11274 11275 /* ELF-specific options. */ 11276#ifdef OBJ_ELF 11277#define OPTION_ELF_BASE (OPTION_MISC_BASE + 16) 11278#define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) 11279 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, 11280 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, 11281#define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) 11282 {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, 11283#define OPTION_XGOT (OPTION_ELF_BASE + 2) 11284 {"xgot", no_argument, NULL, OPTION_XGOT}, 11285#define OPTION_MABI (OPTION_ELF_BASE + 3) 11286 {"mabi", required_argument, NULL, OPTION_MABI}, 11287#define OPTION_32 (OPTION_ELF_BASE + 4) 11288 {"32", no_argument, NULL, OPTION_32}, 11289#define OPTION_N32 (OPTION_ELF_BASE + 5) 11290 {"n32", no_argument, NULL, OPTION_N32}, 11291#define OPTION_64 (OPTION_ELF_BASE + 6) 11292 {"64", no_argument, NULL, OPTION_64}, 11293#define OPTION_MDEBUG (OPTION_ELF_BASE + 7) 11294 {"mdebug", no_argument, NULL, OPTION_MDEBUG}, 11295#define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) 11296 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, 11297#define OPTION_PDR (OPTION_ELF_BASE + 9) 11298 {"mpdr", no_argument, NULL, OPTION_PDR}, 11299#define OPTION_NO_PDR (OPTION_ELF_BASE + 10) 11300 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, 11301#define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11) 11302 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, 11303#endif /* OBJ_ELF */ 11304 11305#define OPTION_MOCTEON_UNSUPPORTED (OPTION_MISC_BASE + 28) 11306#define OPTION_NO_MOCTEON_UNSUPPORTED (OPTION_MISC_BASE + 29) 11307 {"mocteon-unsupported", no_argument, NULL, OPTION_MOCTEON_UNSUPPORTED}, 11308 {"mno-octeon-unsupported", no_argument, NULL, OPTION_NO_MOCTEON_UNSUPPORTED}, 11309 11310#define OPTION_MOCTEON_USEUN (OPTION_MISC_BASE + 30) 11311#define OPTION_NO_MOCTEON_USEUN (OPTION_MISC_BASE + 31) 11312 {"mocteon-useun", no_argument, NULL, OPTION_MOCTEON_USEUN}, 11313 {"mno-octeon-useun", no_argument, NULL, OPTION_NO_MOCTEON_USEUN}, 11314 11315 {NULL, no_argument, NULL, 0} 11316}; 11317size_t md_longopts_size = sizeof (md_longopts); 11318 11319/* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to 11320 NEW_VALUE. Warn if another value was already specified. Note: 11321 we have to defer parsing the -march and -mtune arguments in order 11322 to handle 'from-abi' correctly, since the ABI might be specified 11323 in a later argument. */ 11324 11325static void 11326mips_set_option_string (const char **string_ptr, const char *new_value) 11327{ 11328 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) 11329 as_warn (_("A different %s was already specified, is now %s"), 11330 string_ptr == &mips_arch_string ? "-march" : "-mtune", 11331 new_value); 11332 11333 *string_ptr = new_value; 11334} 11335 11336int 11337md_parse_option (int c, char *arg) 11338{ 11339 switch (c) 11340 { 11341 case OPTION_CONSTRUCT_FLOATS: 11342 mips_disable_float_construction = 0; 11343 break; 11344 11345 case OPTION_NO_CONSTRUCT_FLOATS: 11346 mips_disable_float_construction = 1; 11347 break; 11348 11349 case OPTION_TRAP: 11350 mips_trap = 1; 11351 break; 11352 11353 case OPTION_BREAK: 11354 mips_trap = 0; 11355 break; 11356 11357 case OPTION_EB: 11358 target_big_endian = 1; 11359 break; 11360 11361 case OPTION_EL: 11362 target_big_endian = 0; 11363 break; 11364 11365 case OPTION_MOCTEON_UNSUPPORTED: 11366 octeon_error_on_unsupported = 1; 11367 break; 11368 11369 case OPTION_NO_MOCTEON_UNSUPPORTED: 11370 octeon_error_on_unsupported = 0; 11371 break; 11372 11373 case OPTION_MOCTEON_USEUN: 11374 octeon_use_unalign = 1; 11375 break; 11376 11377 case OPTION_NO_MOCTEON_USEUN: 11378 octeon_use_unalign = 0; 11379 break; 11380 11381 case 'O': 11382 if (arg && arg[0] == '0') 11383 mips_optimize = 1; 11384 else 11385 mips_optimize = 2; 11386 break; 11387 11388 case 'g': 11389 if (arg == NULL) 11390 mips_debug = 2; 11391 else 11392 mips_debug = atoi (arg); 11393 break; 11394 11395 case OPTION_MIPS1: 11396 file_mips_isa = ISA_MIPS1; 11397 break; 11398 11399 case OPTION_MIPS2: 11400 file_mips_isa = ISA_MIPS2; 11401 break; 11402 11403 case OPTION_MIPS3: 11404 file_mips_isa = ISA_MIPS3; 11405 break; 11406 11407 case OPTION_MIPS4: 11408 file_mips_isa = ISA_MIPS4; 11409 break; 11410 11411 case OPTION_MIPS5: 11412 file_mips_isa = ISA_MIPS5; 11413 break; 11414 11415 case OPTION_MIPS32: 11416 file_mips_isa = ISA_MIPS32; 11417 break; 11418 11419 case OPTION_MIPS32R2: 11420 file_mips_isa = ISA_MIPS32R2; 11421 break; 11422 11423 case OPTION_MIPS64R2: 11424 file_mips_isa = ISA_MIPS64R2; 11425 break; 11426 11427 case OPTION_MIPS64: 11428 file_mips_isa = ISA_MIPS64; 11429 break; 11430 11431 case OPTION_MTUNE: 11432 mips_set_option_string (&mips_tune_string, arg); 11433 break; 11434 11435 case OPTION_MARCH: 11436 mips_set_option_string (&mips_arch_string, arg); 11437 break; 11438 11439 case OPTION_M4650: 11440 mips_set_option_string (&mips_arch_string, "4650"); 11441 mips_set_option_string (&mips_tune_string, "4650"); 11442 break; 11443 11444 case OPTION_NO_M4650: 11445 break; 11446 11447 case OPTION_M4010: 11448 mips_set_option_string (&mips_arch_string, "4010"); 11449 mips_set_option_string (&mips_tune_string, "4010"); 11450 break; 11451 11452 case OPTION_NO_M4010: 11453 break; 11454 11455 case OPTION_M4100: 11456 mips_set_option_string (&mips_arch_string, "4100"); 11457 mips_set_option_string (&mips_tune_string, "4100"); 11458 break; 11459 11460 case OPTION_NO_M4100: 11461 break; 11462 11463 case OPTION_M3900: 11464 mips_set_option_string (&mips_arch_string, "3900"); 11465 mips_set_option_string (&mips_tune_string, "3900"); 11466 break; 11467 11468 case OPTION_NO_M3900: 11469 break; 11470 11471 case OPTION_MDMX: 11472 mips_opts.ase_mdmx = 1; 11473 break; 11474 11475 case OPTION_NO_MDMX: 11476 mips_opts.ase_mdmx = 0; 11477 break; 11478 11479 case OPTION_DSP: 11480 mips_opts.ase_dsp = 1; 11481 mips_opts.ase_dspr2 = 0; 11482 break; 11483 11484 case OPTION_NO_DSP: 11485 mips_opts.ase_dsp = 0; 11486 mips_opts.ase_dspr2 = 0; 11487 break; 11488 11489 case OPTION_DSPR2: 11490 mips_opts.ase_dspr2 = 1; 11491 mips_opts.ase_dsp = 1; 11492 break; 11493 11494 case OPTION_NO_DSPR2: 11495 mips_opts.ase_dspr2 = 0; 11496 mips_opts.ase_dsp = 0; 11497 break; 11498 11499 case OPTION_MT: 11500 mips_opts.ase_mt = 1; 11501 break; 11502 11503 case OPTION_NO_MT: 11504 mips_opts.ase_mt = 0; 11505 break; 11506 11507 case OPTION_MIPS16: 11508 mips_opts.mips16 = 1; 11509 mips_no_prev_insn (); 11510 break; 11511 11512 case OPTION_NO_MIPS16: 11513 mips_opts.mips16 = 0; 11514 mips_no_prev_insn (); 11515 break; 11516 11517 case OPTION_MIPS3D: 11518 mips_opts.ase_mips3d = 1; 11519 break; 11520 11521 case OPTION_NO_MIPS3D: 11522 mips_opts.ase_mips3d = 0; 11523 break; 11524 11525 case OPTION_SMARTMIPS: 11526 mips_opts.ase_smartmips = 1; 11527 break; 11528 11529 case OPTION_NO_SMARTMIPS: 11530 mips_opts.ase_smartmips = 0; 11531 break; 11532 11533 case OPTION_FIX_VR4120: 11534 mips_fix_vr4120 = 1; 11535 break; 11536 11537 case OPTION_NO_FIX_VR4120: 11538 mips_fix_vr4120 = 0; 11539 break; 11540 11541 case OPTION_FIX_VR4130: 11542 mips_fix_vr4130 = 1; 11543 break; 11544 11545 case OPTION_NO_FIX_VR4130: 11546 mips_fix_vr4130 = 0; 11547 break; 11548 11549 case OPTION_RELAX_BRANCH: 11550 mips_relax_branch = 1; 11551 break; 11552 11553 case OPTION_NO_RELAX_BRANCH: 11554 mips_relax_branch = 0; 11555 break; 11556 11557 case OPTION_MSHARED: 11558 mips_in_shared = TRUE; 11559 break; 11560 11561 case OPTION_MNO_SHARED: 11562 mips_in_shared = FALSE; 11563 break; 11564 11565 case OPTION_MSYM32: 11566 mips_opts.sym32 = TRUE; 11567 break; 11568 11569 case OPTION_MNO_SYM32: 11570 mips_opts.sym32 = FALSE; 11571 break; 11572 11573#ifdef OBJ_ELF 11574 /* When generating ELF code, we permit -KPIC and -call_shared to 11575 select SVR4_PIC, and -non_shared to select no PIC. This is 11576 intended to be compatible with Irix 5. */ 11577 case OPTION_CALL_SHARED: 11578 if (!IS_ELF) 11579 { 11580 as_bad (_("-call_shared is supported only for ELF format")); 11581 return 0; 11582 } 11583 mips_pic = SVR4_PIC; 11584 mips_abicalls = TRUE; 11585 break; 11586 11587 case OPTION_NON_SHARED: 11588 if (!IS_ELF) 11589 { 11590 as_bad (_("-non_shared is supported only for ELF format")); 11591 return 0; 11592 } 11593 mips_pic = NO_PIC; 11594 mips_abicalls = FALSE; 11595 break; 11596 11597 /* The -xgot option tells the assembler to use 32 bit offsets 11598 when accessing the got in SVR4_PIC mode. It is for Irix 11599 compatibility. */ 11600 case OPTION_XGOT: 11601 mips_big_got = 1; 11602 break; 11603#endif /* OBJ_ELF */ 11604 11605 case 'G': 11606 g_switch_value = atoi (arg); 11607 g_switch_seen = 1; 11608 break; 11609 11610#ifdef OBJ_ELF 11611 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 11612 and -mabi=64. */ 11613 case OPTION_32: 11614 if (!IS_ELF) 11615 { 11616 as_bad (_("-32 is supported for ELF format only")); 11617 return 0; 11618 } 11619 mips_abi = O32_ABI; 11620 break; 11621 11622 case OPTION_N32: 11623 if (!IS_ELF) 11624 { 11625 as_bad (_("-n32 is supported for ELF format only")); 11626 return 0; 11627 } 11628 mips_abi = N32_ABI; 11629 break; 11630 11631 case OPTION_64: 11632 if (!IS_ELF) 11633 { 11634 as_bad (_("-64 is supported for ELF format only")); 11635 return 0; 11636 } 11637 mips_abi = N64_ABI; 11638 if (!support_64bit_objects()) 11639 as_fatal (_("No compiled in support for 64 bit object file format")); 11640 break; 11641#endif /* OBJ_ELF */ 11642 11643 case OPTION_GP32: 11644 file_mips_gp32 = 1; 11645 break; 11646 11647 case OPTION_GP64: 11648 file_mips_gp32 = 0; 11649 break; 11650 11651 case OPTION_FP32: 11652 file_mips_fp32 = 1; 11653 break; 11654 11655 case OPTION_FP64: 11656 file_mips_fp32 = 0; 11657 break; 11658 11659#ifdef OBJ_ELF 11660 case OPTION_MABI: 11661 if (!IS_ELF) 11662 { 11663 as_bad (_("-mabi is supported for ELF format only")); 11664 return 0; 11665 } 11666 if (strcmp (arg, "32") == 0) 11667 mips_abi = O32_ABI; 11668 else if (strcmp (arg, "o64") == 0) 11669 mips_abi = O64_ABI; 11670 else if (strcmp (arg, "n32") == 0) 11671 mips_abi = N32_ABI; 11672 else if (strcmp (arg, "64") == 0) 11673 { 11674 mips_abi = N64_ABI; 11675 if (! support_64bit_objects()) 11676 as_fatal (_("No compiled in support for 64 bit object file " 11677 "format")); 11678 } 11679 else if (strcmp (arg, "eabi") == 0) 11680 mips_abi = EABI_ABI; 11681 else 11682 { 11683 as_fatal (_("invalid abi -mabi=%s"), arg); 11684 return 0; 11685 } 11686 break; 11687#endif /* OBJ_ELF */ 11688 11689 case OPTION_M7000_HILO_FIX: 11690 mips_7000_hilo_fix = TRUE; 11691 break; 11692 11693 case OPTION_MNO_7000_HILO_FIX: 11694 mips_7000_hilo_fix = FALSE; 11695 break; 11696 11697#ifdef OBJ_ELF 11698 case OPTION_MDEBUG: 11699 mips_flag_mdebug = TRUE; 11700 break; 11701 11702 case OPTION_NO_MDEBUG: 11703 mips_flag_mdebug = FALSE; 11704 break; 11705 11706 case OPTION_PDR: 11707 mips_flag_pdr = TRUE; 11708 break; 11709 11710 case OPTION_NO_PDR: 11711 mips_flag_pdr = FALSE; 11712 break; 11713 11714 case OPTION_MVXWORKS_PIC: 11715 mips_pic = VXWORKS_PIC; 11716 break; 11717#endif /* OBJ_ELF */ 11718 11719 default: 11720 return 0; 11721 } 11722 11723 return 1; 11724} 11725 11726/* Set up globals to generate code for the ISA or processor 11727 described by INFO. */ 11728 11729static void 11730mips_set_architecture (const struct mips_cpu_info *info) 11731{ 11732 if (info != 0) 11733 { 11734 file_mips_arch = info->cpu; 11735 mips_opts.arch = info->cpu; 11736 mips_opts.isa = info->isa; 11737 } 11738} 11739 11740 11741/* Likewise for tuning. */ 11742 11743static void 11744mips_set_tune (const struct mips_cpu_info *info) 11745{ 11746 if (info != 0) 11747 mips_tune = info->cpu; 11748} 11749 11750 11751void 11752mips_after_parse_args (void) 11753{ 11754 const struct mips_cpu_info *arch_info = 0; 11755 const struct mips_cpu_info *tune_info = 0; 11756 11757 /* GP relative stuff not working for PE */ 11758 if (strncmp (TARGET_OS, "pe", 2) == 0) 11759 { 11760 if (g_switch_seen && g_switch_value != 0) 11761 as_bad (_("-G not supported in this configuration.")); 11762 g_switch_value = 0; 11763 } 11764 11765 if (mips_abi == NO_ABI) 11766 mips_abi = MIPS_DEFAULT_ABI; 11767 11768 /* The following code determines the architecture and register size. 11769 Similar code was added to GCC 3.3 (see override_options() in 11770 config/mips/mips.c). The GAS and GCC code should be kept in sync 11771 as much as possible. */ 11772 11773 if (mips_arch_string != 0) 11774 arch_info = mips_parse_cpu ("-march", mips_arch_string); 11775 11776 if (file_mips_isa != ISA_UNKNOWN) 11777 { 11778 /* Handle -mipsN. At this point, file_mips_isa contains the 11779 ISA level specified by -mipsN, while arch_info->isa contains 11780 the -march selection (if any). */ 11781 if (arch_info != 0) 11782 { 11783 /* -march takes precedence over -mipsN, since it is more descriptive. 11784 There's no harm in specifying both as long as the ISA levels 11785 are the same. */ 11786 if (file_mips_isa != arch_info->isa) 11787 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), 11788 mips_cpu_info_from_isa (file_mips_isa)->name, 11789 mips_cpu_info_from_isa (arch_info->isa)->name); 11790 } 11791 else 11792 arch_info = mips_cpu_info_from_isa (file_mips_isa); 11793 } 11794 11795 if (arch_info == 0) 11796 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); 11797 11798 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) 11799 as_bad ("-march=%s is not compatible with the selected ABI", 11800 arch_info->name); 11801 11802 mips_set_architecture (arch_info); 11803 11804 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ 11805 if (mips_tune_string != 0) 11806 tune_info = mips_parse_cpu ("-mtune", mips_tune_string); 11807 11808 if (tune_info == 0) 11809 mips_set_tune (arch_info); 11810 else 11811 mips_set_tune (tune_info); 11812 11813 if (file_mips_gp32 >= 0) 11814 { 11815 /* The user specified the size of the integer registers. Make sure 11816 it agrees with the ABI and ISA. */ 11817 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) 11818 as_bad (_("-mgp64 used with a 32-bit processor")); 11819 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) 11820 as_bad (_("-mgp32 used with a 64-bit ABI")); 11821 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) 11822 as_bad (_("-mgp64 used with a 32-bit ABI")); 11823 } 11824 else 11825 { 11826 /* Infer the integer register size from the ABI and processor. 11827 Restrict ourselves to 32-bit registers if that's all the 11828 processor has, or if the ABI cannot handle 64-bit registers. */ 11829 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) 11830 || !ISA_HAS_64BIT_REGS (mips_opts.isa)); 11831 } 11832 11833 switch (file_mips_fp32) 11834 { 11835 default: 11836 case -1: 11837 /* No user specified float register size. 11838 ??? GAS treats single-float processors as though they had 64-bit 11839 float registers (although it complains when double-precision 11840 instructions are used). As things stand, saying they have 32-bit 11841 registers would lead to spurious "register must be even" messages. 11842 So here we assume float registers are never smaller than the 11843 integer ones. */ 11844 if (file_mips_gp32 == 0) 11845 /* 64-bit integer registers implies 64-bit float registers. */ 11846 file_mips_fp32 = 0; 11847 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) 11848 && ISA_HAS_64BIT_FPRS (mips_opts.isa)) 11849 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ 11850 file_mips_fp32 = 0; 11851 else 11852 /* 32-bit float registers. */ 11853 file_mips_fp32 = 1; 11854 break; 11855 11856 /* The user specified the size of the float registers. Check if it 11857 agrees with the ABI and ISA. */ 11858 case 0: 11859 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) 11860 as_bad (_("-mfp64 used with a 32-bit fpu")); 11861 else if (ABI_NEEDS_32BIT_REGS (mips_abi) 11862 && !ISA_HAS_MXHC1 (mips_opts.isa)) 11863 as_warn (_("-mfp64 used with a 32-bit ABI")); 11864 break; 11865 case 1: 11866 if (ABI_NEEDS_64BIT_REGS (mips_abi)) 11867 as_warn (_("-mfp32 used with a 64-bit ABI")); 11868 break; 11869 } 11870 11871 /* End of GCC-shared inference code. */ 11872 11873 /* This flag is set when we have a 64-bit capable CPU but use only 11874 32-bit wide registers. Note that EABI does not use it. */ 11875 if (ISA_HAS_64BIT_REGS (mips_opts.isa) 11876 && ((mips_abi == NO_ABI && file_mips_gp32 == 1) 11877 || mips_abi == O32_ABI)) 11878 mips_32bitmode = 1; 11879 11880 if (mips_opts.isa == ISA_MIPS1 && mips_trap) 11881 as_bad (_("trap exception not supported at ISA 1")); 11882 11883 /* If the selected architecture includes support for ASEs, enable 11884 generation of code for them. */ 11885 if (mips_opts.mips16 == -1) 11886 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; 11887 if (mips_opts.ase_mips3d == -1) 11888 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) 11889 && file_mips_fp32 == 0) ? 1 : 0; 11890 if (mips_opts.ase_mips3d && file_mips_fp32 == 1) 11891 as_bad (_("-mfp32 used with -mips3d")); 11892 11893 if (mips_opts.ase_mdmx == -1) 11894 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) 11895 && file_mips_fp32 == 0) ? 1 : 0; 11896 if (mips_opts.ase_mdmx && file_mips_fp32 == 1) 11897 as_bad (_("-mfp32 used with -mdmx")); 11898 11899 if (mips_opts.ase_smartmips == -1) 11900 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; 11901 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) 11902 as_warn ("%s ISA does not support SmartMIPS", 11903 mips_cpu_info_from_isa (mips_opts.isa)->name); 11904 11905 if (mips_opts.ase_dsp == -1) 11906 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; 11907 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) 11908 as_warn ("%s ISA does not support DSP ASE", 11909 mips_cpu_info_from_isa (mips_opts.isa)->name); 11910 11911 if (mips_opts.ase_dspr2 == -1) 11912 { 11913 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; 11914 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; 11915 } 11916 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) 11917 as_warn ("%s ISA does not support DSP R2 ASE", 11918 mips_cpu_info_from_isa (mips_opts.isa)->name); 11919 11920 if (mips_opts.ase_mt == -1) 11921 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; 11922 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) 11923 as_warn ("%s ISA does not support MT ASE", 11924 mips_cpu_info_from_isa (mips_opts.isa)->name); 11925 11926 file_mips_isa = mips_opts.isa; 11927 file_ase_mips16 = mips_opts.mips16; 11928 file_ase_mips3d = mips_opts.ase_mips3d; 11929 file_ase_mdmx = mips_opts.ase_mdmx; 11930 file_ase_smartmips = mips_opts.ase_smartmips; 11931 file_ase_dsp = mips_opts.ase_dsp; 11932 file_ase_dspr2 = mips_opts.ase_dspr2; 11933 file_ase_mt = mips_opts.ase_mt; 11934 mips_opts.gp32 = file_mips_gp32; 11935 mips_opts.fp32 = file_mips_fp32; 11936 11937 if (mips_flag_mdebug < 0) 11938 { 11939#ifdef OBJ_MAYBE_ECOFF 11940 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) 11941 mips_flag_mdebug = 1; 11942 else 11943#endif /* OBJ_MAYBE_ECOFF */ 11944 mips_flag_mdebug = 0; 11945 } 11946} 11947 11948void 11949mips_init_after_args (void) 11950{ 11951 /* initialize opcodes */ 11952 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; 11953 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; 11954} 11955 11956long 11957md_pcrel_from (fixS *fixP) 11958{ 11959 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; 11960 switch (fixP->fx_r_type) 11961 { 11962 case BFD_RELOC_16_PCREL_S2: 11963 case BFD_RELOC_MIPS_JMP: 11964 /* Return the address of the delay slot. */ 11965 return addr + 4; 11966 default: 11967 /* We have no relocation type for PC relative MIPS16 instructions. */ 11968 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) 11969 as_bad_where (fixP->fx_file, fixP->fx_line, 11970 _("PC relative MIPS16 instruction references a different section")); 11971 return addr; 11972 } 11973} 11974 11975/* This is called before the symbol table is processed. In order to 11976 work with gcc when using mips-tfile, we must keep all local labels. 11977 However, in other cases, we want to discard them. If we were 11978 called with -g, but we didn't see any debugging information, it may 11979 mean that gcc is smuggling debugging information through to 11980 mips-tfile, in which case we must generate all local labels. */ 11981 11982void 11983mips_frob_file_before_adjust (void) 11984{ 11985#ifndef NO_ECOFF_DEBUGGING 11986 if (ECOFF_DEBUGGING 11987 && mips_debug != 0 11988 && ! ecoff_debugging_seen) 11989 flag_keep_locals = 1; 11990#endif 11991} 11992 11993/* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede 11994 the corresponding LO16 reloc. This is called before md_apply_fix and 11995 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit 11996 relocation operators. 11997 11998 For our purposes, a %lo() expression matches a %got() or %hi() 11999 expression if: 12000 12001 (a) it refers to the same symbol; and 12002 (b) the offset applied in the %lo() expression is no lower than 12003 the offset applied in the %got() or %hi(). 12004 12005 (b) allows us to cope with code like: 12006 12007 lui $4,%hi(foo) 12008 lh $4,%lo(foo+2)($4) 12009 12010 ...which is legal on RELA targets, and has a well-defined behaviour 12011 if the user knows that adding 2 to "foo" will not induce a carry to 12012 the high 16 bits. 12013 12014 When several %lo()s match a particular %got() or %hi(), we use the 12015 following rules to distinguish them: 12016 12017 (1) %lo()s with smaller offsets are a better match than %lo()s with 12018 higher offsets. 12019 12020 (2) %lo()s with no matching %got() or %hi() are better than those 12021 that already have a matching %got() or %hi(). 12022 12023 (3) later %lo()s are better than earlier %lo()s. 12024 12025 These rules are applied in order. 12026 12027 (1) means, among other things, that %lo()s with identical offsets are 12028 chosen if they exist. 12029 12030 (2) means that we won't associate several high-part relocations with 12031 the same low-part relocation unless there's no alternative. Having 12032 several high parts for the same low part is a GNU extension; this rule 12033 allows careful users to avoid it. 12034 12035 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, 12036 with the last high-part relocation being at the front of the list. 12037 It therefore makes sense to choose the last matching low-part 12038 relocation, all other things being equal. It's also easier 12039 to code that way. */ 12040 12041void 12042mips_frob_file (void) 12043{ 12044 struct mips_hi_fixup *l; 12045 12046 for (l = mips_hi_fixup_list; l != NULL; l = l->next) 12047 { 12048 segment_info_type *seginfo; 12049 bfd_boolean matched_lo_p; 12050 fixS **hi_pos, **lo_pos, **pos; 12051 12052 assert (reloc_needs_lo_p (l->fixp->fx_r_type)); 12053 12054 /* If a GOT16 relocation turns out to be against a global symbol, 12055 there isn't supposed to be a matching LO. */ 12056 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 12057 && !pic_need_relax (l->fixp->fx_addsy, l->seg)) 12058 continue; 12059 12060 /* Check quickly whether the next fixup happens to be a matching %lo. */ 12061 if (fixup_has_matching_lo_p (l->fixp)) 12062 continue; 12063 12064 seginfo = seg_info (l->seg); 12065 12066 /* Set HI_POS to the position of this relocation in the chain. 12067 Set LO_POS to the position of the chosen low-part relocation. 12068 MATCHED_LO_P is true on entry to the loop if *POS is a low-part 12069 relocation that matches an immediately-preceding high-part 12070 relocation. */ 12071 hi_pos = NULL; 12072 lo_pos = NULL; 12073 matched_lo_p = FALSE; 12074 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) 12075 { 12076 if (*pos == l->fixp) 12077 hi_pos = pos; 12078 12079 if (((*pos)->fx_r_type == BFD_RELOC_LO16 12080 || (*pos)->fx_r_type == BFD_RELOC_MIPS16_LO16) 12081 && (*pos)->fx_addsy == l->fixp->fx_addsy 12082 && (*pos)->fx_offset >= l->fixp->fx_offset 12083 && (lo_pos == NULL 12084 || (*pos)->fx_offset < (*lo_pos)->fx_offset 12085 || (!matched_lo_p 12086 && (*pos)->fx_offset == (*lo_pos)->fx_offset))) 12087 lo_pos = pos; 12088 12089 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) 12090 && fixup_has_matching_lo_p (*pos)); 12091 } 12092 12093 /* If we found a match, remove the high-part relocation from its 12094 current position and insert it before the low-part relocation. 12095 Make the offsets match so that fixup_has_matching_lo_p() 12096 will return true. 12097 12098 We don't warn about unmatched high-part relocations since some 12099 versions of gcc have been known to emit dead "lui ...%hi(...)" 12100 instructions. */ 12101 if (lo_pos != NULL) 12102 { 12103 l->fixp->fx_offset = (*lo_pos)->fx_offset; 12104 if (l->fixp->fx_next != *lo_pos) 12105 { 12106 *hi_pos = l->fixp->fx_next; 12107 l->fixp->fx_next = *lo_pos; 12108 *lo_pos = l->fixp; 12109 } 12110 } 12111 } 12112} 12113 12114/* We may have combined relocations without symbols in the N32/N64 ABI. 12115 We have to prevent gas from dropping them. */ 12116 12117int 12118mips_force_relocation (fixS *fixp) 12119{ 12120 if (generic_force_reloc (fixp)) 12121 return 1; 12122 12123 if (HAVE_NEWABI 12124 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr 12125 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB 12126 || fixp->fx_r_type == BFD_RELOC_HI16_S 12127 || fixp->fx_r_type == BFD_RELOC_LO16)) 12128 return 1; 12129 12130 return 0; 12131} 12132 12133/* Apply a fixup to the object file. */ 12134 12135void 12136md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 12137{ 12138 bfd_byte *buf; 12139 long insn; 12140 reloc_howto_type *howto; 12141 12142 /* We ignore generic BFD relocations we don't know about. */ 12143 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); 12144 if (! howto) 12145 return; 12146 12147 assert (fixP->fx_size == 4 12148 || fixP->fx_r_type == BFD_RELOC_16 12149 || fixP->fx_r_type == BFD_RELOC_64 12150 || fixP->fx_r_type == BFD_RELOC_CTOR 12151 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB 12152 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 12153 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY 12154 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); 12155 12156 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); 12157 12158 assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2); 12159 12160 /* Don't treat parts of a composite relocation as done. There are two 12161 reasons for this: 12162 12163 (1) The second and third parts will be against 0 (RSS_UNDEF) but 12164 should nevertheless be emitted if the first part is. 12165 12166 (2) In normal usage, composite relocations are never assembly-time 12167 constants. The easiest way of dealing with the pathological 12168 exceptions is to generate a relocation against STN_UNDEF and 12169 leave everything up to the linker. */ 12170 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) 12171 fixP->fx_done = 1; 12172 12173 switch (fixP->fx_r_type) 12174 { 12175 case BFD_RELOC_MIPS_TLS_GD: 12176 case BFD_RELOC_MIPS_TLS_LDM: 12177 case BFD_RELOC_MIPS_TLS_DTPREL32: 12178 case BFD_RELOC_MIPS_TLS_DTPREL64: 12179 case BFD_RELOC_MIPS_TLS_DTPREL_HI16: 12180 case BFD_RELOC_MIPS_TLS_DTPREL_LO16: 12181 case BFD_RELOC_MIPS_TLS_GOTTPREL: 12182 case BFD_RELOC_MIPS_TLS_TPREL_HI16: 12183 case BFD_RELOC_MIPS_TLS_TPREL_LO16: 12184 S_SET_THREAD_LOCAL (fixP->fx_addsy); 12185 /* fall through */ 12186 12187 case BFD_RELOC_MIPS_JMP: 12188 case BFD_RELOC_MIPS_SHIFT5: 12189 case BFD_RELOC_MIPS_SHIFT6: 12190 case BFD_RELOC_MIPS_GOT_DISP: 12191 case BFD_RELOC_MIPS_GOT_PAGE: 12192 case BFD_RELOC_MIPS_GOT_OFST: 12193 case BFD_RELOC_MIPS_SUB: 12194 case BFD_RELOC_MIPS_INSERT_A: 12195 case BFD_RELOC_MIPS_INSERT_B: 12196 case BFD_RELOC_MIPS_DELETE: 12197 case BFD_RELOC_MIPS_HIGHEST: 12198 case BFD_RELOC_MIPS_HIGHER: 12199 case BFD_RELOC_MIPS_SCN_DISP: 12200 case BFD_RELOC_MIPS_REL16: 12201 case BFD_RELOC_MIPS_RELGOT: 12202 case BFD_RELOC_MIPS_JALR: 12203 case BFD_RELOC_HI16: 12204 case BFD_RELOC_HI16_S: 12205 case BFD_RELOC_GPREL16: 12206 case BFD_RELOC_MIPS_LITERAL: 12207 case BFD_RELOC_MIPS_CALL16: 12208 case BFD_RELOC_MIPS_GOT16: 12209 case BFD_RELOC_GPREL32: 12210 case BFD_RELOC_MIPS_GOT_HI16: 12211 case BFD_RELOC_MIPS_GOT_LO16: 12212 case BFD_RELOC_MIPS_CALL_HI16: 12213 case BFD_RELOC_MIPS_CALL_LO16: 12214 case BFD_RELOC_MIPS16_GPREL: 12215 case BFD_RELOC_MIPS16_HI16: 12216 case BFD_RELOC_MIPS16_HI16_S: 12217 case BFD_RELOC_MIPS16_JMP: 12218 /* Nothing needed to do. The value comes from the reloc entry. */ 12219 break; 12220 12221 case BFD_RELOC_64: 12222 /* This is handled like BFD_RELOC_32, but we output a sign 12223 extended value if we are only 32 bits. */ 12224 if (fixP->fx_done) 12225 { 12226 if (8 <= sizeof (valueT)) 12227 md_number_to_chars ((char *) buf, *valP, 8); 12228 else 12229 { 12230 valueT hiv; 12231 12232 if ((*valP & 0x80000000) != 0) 12233 hiv = 0xffffffff; 12234 else 12235 hiv = 0; 12236 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), 12237 *valP, 4); 12238 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), 12239 hiv, 4); 12240 } 12241 } 12242 break; 12243 12244 case BFD_RELOC_RVA: 12245 case BFD_RELOC_32: 12246 case BFD_RELOC_16: 12247 /* If we are deleting this reloc entry, we must fill in the 12248 value now. This can happen if we have a .word which is not 12249 resolved when it appears but is later defined. */ 12250 if (fixP->fx_done) 12251 md_number_to_chars ((char *) buf, *valP, fixP->fx_size); 12252 break; 12253 12254 case BFD_RELOC_LO16: 12255 case BFD_RELOC_MIPS16_LO16: 12256 /* FIXME: Now that embedded-PIC is gone, some of this code/comment 12257 may be safe to remove, but if so it's not obvious. */ 12258 /* When handling an embedded PIC switch statement, we can wind 12259 up deleting a LO16 reloc. See the 'o' case in mips_ip. */ 12260 if (fixP->fx_done) 12261 { 12262 if (*valP + 0x8000 > 0xffff) 12263 as_bad_where (fixP->fx_file, fixP->fx_line, 12264 _("relocation overflow")); 12265 if (target_big_endian) 12266 buf += 2; 12267 md_number_to_chars ((char *) buf, *valP, 2); 12268 } 12269 break; 12270 12271 case BFD_RELOC_16_PCREL_S2: 12272 if ((*valP & 0x3) != 0) 12273 as_bad_where (fixP->fx_file, fixP->fx_line, 12274 _("Branch to misaligned address (%lx)"), (long) *valP); 12275 12276 /* We need to save the bits in the instruction since fixup_segment() 12277 might be deleting the relocation entry (i.e., a branch within 12278 the current segment). */ 12279 if (! fixP->fx_done) 12280 break; 12281 12282 /* Update old instruction data. */ 12283 if (target_big_endian) 12284 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; 12285 else 12286 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 12287 12288 if (*valP + 0x20000 <= 0x3ffff) 12289 { 12290 insn |= (*valP >> 2) & 0xffff; 12291 md_number_to_chars ((char *) buf, insn, 4); 12292 } 12293 else if (mips_pic == NO_PIC 12294 && fixP->fx_done 12295 && fixP->fx_frag->fr_address >= text_section->vma 12296 && (fixP->fx_frag->fr_address 12297 < text_section->vma + bfd_get_section_size (text_section)) 12298 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ 12299 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ 12300 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ 12301 { 12302 /* The branch offset is too large. If this is an 12303 unconditional branch, and we are not generating PIC code, 12304 we can convert it to an absolute jump instruction. */ 12305 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ 12306 insn = 0x0c000000; /* jal */ 12307 else 12308 insn = 0x08000000; /* j */ 12309 fixP->fx_r_type = BFD_RELOC_MIPS_JMP; 12310 fixP->fx_done = 0; 12311 fixP->fx_addsy = section_symbol (text_section); 12312 *valP += md_pcrel_from (fixP); 12313 md_number_to_chars ((char *) buf, insn, 4); 12314 } 12315 else 12316 { 12317 /* If we got here, we have branch-relaxation disabled, 12318 and there's nothing we can do to fix this instruction 12319 without turning it into a longer sequence. */ 12320 as_bad_where (fixP->fx_file, fixP->fx_line, 12321 _("Branch out of range")); 12322 } 12323 break; 12324 12325 case BFD_RELOC_VTABLE_INHERIT: 12326 fixP->fx_done = 0; 12327 if (fixP->fx_addsy 12328 && !S_IS_DEFINED (fixP->fx_addsy) 12329 && !S_IS_WEAK (fixP->fx_addsy)) 12330 S_SET_WEAK (fixP->fx_addsy); 12331 break; 12332 12333 case BFD_RELOC_VTABLE_ENTRY: 12334 fixP->fx_done = 0; 12335 break; 12336 12337 default: 12338 internalError (); 12339 } 12340 12341 /* Remember value for tc_gen_reloc. */ 12342 fixP->fx_addnumber = *valP; 12343} 12344 12345static symbolS * 12346get_symbol (void) 12347{ 12348 int c; 12349 char *name; 12350 symbolS *p; 12351 12352 name = input_line_pointer; 12353 c = get_symbol_end (); 12354 p = (symbolS *) symbol_find_or_make (name); 12355 *input_line_pointer = c; 12356 return p; 12357} 12358 12359/* Align the current frag to a given power of two. The MIPS assembler 12360 also automatically adjusts any preceding label. */ 12361 12362static void 12363mips_align (int to, int fill, symbolS *label) 12364{ 12365 mips_emit_delays (); 12366 frag_align (to, fill, 0); 12367 record_alignment (now_seg, to); 12368 if (label != NULL) 12369 { 12370 assert (S_GET_SEGMENT (label) == now_seg); 12371 symbol_set_frag (label, frag_now); 12372 S_SET_VALUE (label, (valueT) frag_now_fix ()); 12373 } 12374} 12375 12376/* Align to a given power of two. .align 0 turns off the automatic 12377 alignment used by the data creating pseudo-ops. */ 12378 12379static void 12380s_align (int x ATTRIBUTE_UNUSED) 12381{ 12382 int temp; 12383 long temp_fill; 12384 long max_alignment = 15; 12385 12386 /* o Note that the assembler pulls down any immediately preceding label 12387 to the aligned address. 12388 o It's not documented but auto alignment is reinstated by 12389 a .align pseudo instruction. 12390 o Note also that after auto alignment is turned off the mips assembler 12391 issues an error on attempt to assemble an improperly aligned data item. 12392 We don't. */ 12393 12394 temp = get_absolute_expression (); 12395 if (temp > max_alignment) 12396 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); 12397 else if (temp < 0) 12398 { 12399 as_warn (_("Alignment negative: 0 assumed.")); 12400 temp = 0; 12401 } 12402 if (*input_line_pointer == ',') 12403 { 12404 ++input_line_pointer; 12405 temp_fill = get_absolute_expression (); 12406 } 12407 else 12408 temp_fill = 0; 12409 if (temp) 12410 { 12411 segment_info_type *si = seg_info (now_seg); 12412 struct insn_label_list *l = si->label_list; 12413 /* Auto alignment should be switched on by next section change. */ 12414 auto_align = 1; 12415 mips_align (temp, (int) temp_fill, l != NULL ? l->label : NULL); 12416 } 12417 else 12418 { 12419 auto_align = 0; 12420 } 12421 12422 demand_empty_rest_of_line (); 12423} 12424 12425static void 12426s_change_sec (int sec) 12427{ 12428 segT seg; 12429 12430#ifdef OBJ_ELF 12431 /* The ELF backend needs to know that we are changing sections, so 12432 that .previous works correctly. We could do something like check 12433 for an obj_section_change_hook macro, but that might be confusing 12434 as it would not be appropriate to use it in the section changing 12435 functions in read.c, since obj-elf.c intercepts those. FIXME: 12436 This should be cleaner, somehow. */ 12437 if (IS_ELF) 12438 obj_elf_section_change_hook (); 12439#endif 12440 12441 mips_emit_delays (); 12442 switch (sec) 12443 { 12444 case 't': 12445 s_text (0); 12446 break; 12447 case 'd': 12448 s_data (0); 12449 break; 12450 case 'b': 12451 subseg_set (bss_section, (subsegT) get_absolute_expression ()); 12452 demand_empty_rest_of_line (); 12453 break; 12454 12455 case 'r': 12456 seg = subseg_new (RDATA_SECTION_NAME, 12457 (subsegT) get_absolute_expression ()); 12458 if (IS_ELF) 12459 { 12460 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD 12461 | SEC_READONLY | SEC_RELOC 12462 | SEC_DATA)); 12463 if (strcmp (TARGET_OS, "elf") != 0) 12464 record_alignment (seg, 4); 12465 } 12466 demand_empty_rest_of_line (); 12467 break; 12468 12469 case 's': 12470 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); 12471 if (IS_ELF) 12472 { 12473 bfd_set_section_flags (stdoutput, seg, 12474 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); 12475 if (strcmp (TARGET_OS, "elf") != 0) 12476 record_alignment (seg, 4); 12477 } 12478 demand_empty_rest_of_line (); 12479 break; 12480 } 12481 12482 auto_align = 1; 12483} 12484 12485void 12486s_change_section (int ignore ATTRIBUTE_UNUSED) 12487{ 12488#ifdef OBJ_ELF 12489 char *section_name; 12490 char c; 12491 char next_c = 0; 12492 int section_type; 12493 int section_flag; 12494 int section_entry_size; 12495 int section_alignment; 12496 12497 if (!IS_ELF) 12498 return; 12499 12500 section_name = input_line_pointer; 12501 c = get_symbol_end (); 12502 if (c) 12503 next_c = *(input_line_pointer + 1); 12504 12505 /* Do we have .section Name<,"flags">? */ 12506 if (c != ',' || (c == ',' && next_c == '"')) 12507 { 12508 /* just after name is now '\0'. */ 12509 *input_line_pointer = c; 12510 input_line_pointer = section_name; 12511 obj_elf_section (ignore); 12512 return; 12513 } 12514 input_line_pointer++; 12515 12516 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ 12517 if (c == ',') 12518 section_type = get_absolute_expression (); 12519 else 12520 section_type = 0; 12521 if (*input_line_pointer++ == ',') 12522 section_flag = get_absolute_expression (); 12523 else 12524 section_flag = 0; 12525 if (*input_line_pointer++ == ',') 12526 section_entry_size = get_absolute_expression (); 12527 else 12528 section_entry_size = 0; 12529 if (*input_line_pointer++ == ',') 12530 section_alignment = get_absolute_expression (); 12531 else 12532 section_alignment = 0; 12533 12534 section_name = xstrdup (section_name); 12535 12536 /* When using the generic form of .section (as implemented by obj-elf.c), 12537 there's no way to set the section type to SHT_MIPS_DWARF. Users have 12538 traditionally had to fall back on the more common @progbits instead. 12539 12540 There's nothing really harmful in this, since bfd will correct 12541 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it 12542 means that, for backwards compatibility, the special_section entries 12543 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. 12544 12545 Even so, we shouldn't force users of the MIPS .section syntax to 12546 incorrectly label the sections as SHT_PROGBITS. The best compromise 12547 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the 12548 generic type-checking code. */ 12549 if (section_type == SHT_MIPS_DWARF) 12550 section_type = SHT_PROGBITS; 12551 12552 obj_elf_change_section (section_name, section_type, section_flag, 12553 section_entry_size, 0, 0, 0); 12554 12555 if (now_seg->name != section_name) 12556 free (section_name); 12557#endif /* OBJ_ELF */ 12558} 12559 12560void 12561mips_enable_auto_align (void) 12562{ 12563 auto_align = 1; 12564} 12565 12566static void 12567s_cons (int log_size) 12568{ 12569 segment_info_type *si = seg_info (now_seg); 12570 struct insn_label_list *l = si->label_list; 12571 symbolS *label; 12572 12573 label = l != NULL ? l->label : NULL; 12574 mips_emit_delays (); 12575 if (log_size > 0 && auto_align) 12576 mips_align (log_size, 0, label); 12577 mips_clear_insn_labels (); 12578 cons (1 << log_size); 12579} 12580 12581static void 12582s_float_cons (int type) 12583{ 12584 segment_info_type *si = seg_info (now_seg); 12585 struct insn_label_list *l = si->label_list; 12586 symbolS *label; 12587 12588 label = l != NULL ? l->label : NULL; 12589 12590 mips_emit_delays (); 12591 12592 if (auto_align) 12593 { 12594 if (type == 'd') 12595 mips_align (3, 0, label); 12596 else 12597 mips_align (2, 0, label); 12598 } 12599 12600 mips_clear_insn_labels (); 12601 12602 float_cons (type); 12603} 12604 12605/* Handle .globl. We need to override it because on Irix 5 you are 12606 permitted to say 12607 .globl foo .text 12608 where foo is an undefined symbol, to mean that foo should be 12609 considered to be the address of a function. */ 12610 12611static void 12612s_mips_globl (int x ATTRIBUTE_UNUSED) 12613{ 12614 char *name; 12615 int c; 12616 symbolS *symbolP; 12617 flagword flag; 12618 12619 do 12620 { 12621 name = input_line_pointer; 12622 c = get_symbol_end (); 12623 symbolP = symbol_find_or_make (name); 12624 S_SET_EXTERNAL (symbolP); 12625 12626 *input_line_pointer = c; 12627 SKIP_WHITESPACE (); 12628 12629 /* On Irix 5, every global symbol that is not explicitly labelled as 12630 being a function is apparently labelled as being an object. */ 12631 flag = BSF_OBJECT; 12632 12633 if (!is_end_of_line[(unsigned char) *input_line_pointer] 12634 && (*input_line_pointer != ',')) 12635 { 12636 char *secname; 12637 asection *sec; 12638 12639 secname = input_line_pointer; 12640 c = get_symbol_end (); 12641 sec = bfd_get_section_by_name (stdoutput, secname); 12642 if (sec == NULL) 12643 as_bad (_("%s: no such section"), secname); 12644 *input_line_pointer = c; 12645 12646 if (sec != NULL && (sec->flags & SEC_CODE) != 0) 12647 flag = BSF_FUNCTION; 12648 } 12649 12650 symbol_get_bfdsym (symbolP)->flags |= flag; 12651 12652 c = *input_line_pointer; 12653 if (c == ',') 12654 { 12655 input_line_pointer++; 12656 SKIP_WHITESPACE (); 12657 if (is_end_of_line[(unsigned char) *input_line_pointer]) 12658 c = '\n'; 12659 } 12660 } 12661 while (c == ','); 12662 12663 demand_empty_rest_of_line (); 12664} 12665 12666static void 12667s_option (int x ATTRIBUTE_UNUSED) 12668{ 12669 char *opt; 12670 char c; 12671 12672 opt = input_line_pointer; 12673 c = get_symbol_end (); 12674 12675 if (*opt == 'O') 12676 { 12677 /* FIXME: What does this mean? */ 12678 } 12679 else if (strncmp (opt, "pic", 3) == 0) 12680 { 12681 int i; 12682 12683 i = atoi (opt + 3); 12684 if (i == 0) 12685 mips_pic = NO_PIC; 12686 else if (i == 2) 12687 { 12688 mips_pic = SVR4_PIC; 12689 mips_abicalls = TRUE; 12690 } 12691 else 12692 as_bad (_(".option pic%d not supported"), i); 12693 12694 if (mips_pic == SVR4_PIC) 12695 { 12696 if (g_switch_seen && g_switch_value != 0) 12697 as_warn (_("-G may not be used with SVR4 PIC code")); 12698 g_switch_value = 0; 12699 bfd_set_gp_size (stdoutput, 0); 12700 } 12701 } 12702 else 12703 as_warn (_("Unrecognized option \"%s\""), opt); 12704 12705 *input_line_pointer = c; 12706 demand_empty_rest_of_line (); 12707} 12708 12709/* This structure is used to hold a stack of .set values. */ 12710 12711struct mips_option_stack 12712{ 12713 struct mips_option_stack *next; 12714 struct mips_set_options options; 12715}; 12716 12717static struct mips_option_stack *mips_opts_stack; 12718 12719/* Handle the .set pseudo-op. */ 12720 12721static void 12722s_mipsset (int x ATTRIBUTE_UNUSED) 12723{ 12724 char *name = input_line_pointer, ch; 12725 12726 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 12727 ++input_line_pointer; 12728 ch = *input_line_pointer; 12729 *input_line_pointer = '\0'; 12730 12731 if (strcmp (name, "reorder") == 0) 12732 { 12733 if (mips_opts.noreorder) 12734 end_noreorder (); 12735 } 12736 else if (strcmp (name, "noreorder") == 0) 12737 { 12738 if (!mips_opts.noreorder) 12739 start_noreorder (); 12740 } 12741 else if (strcmp (name, "at") == 0) 12742 { 12743 mips_opts.noat = 0; 12744 } 12745 else if (strcmp (name, "noat") == 0) 12746 { 12747 mips_opts.noat = 1; 12748 } 12749 else if (strcmp (name, "macro") == 0) 12750 { 12751 mips_opts.warn_about_macros = 0; 12752 } 12753 else if (strcmp (name, "nomacro") == 0) 12754 { 12755 if (mips_opts.noreorder == 0) 12756 as_bad (_("`noreorder' must be set before `nomacro'")); 12757 mips_opts.warn_about_macros = 1; 12758 } 12759 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) 12760 { 12761 mips_opts.nomove = 0; 12762 } 12763 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) 12764 { 12765 mips_opts.nomove = 1; 12766 } 12767 else if (strcmp (name, "bopt") == 0) 12768 { 12769 mips_opts.nobopt = 0; 12770 } 12771 else if (strcmp (name, "nobopt") == 0) 12772 { 12773 mips_opts.nobopt = 1; 12774 } 12775 else if (strcmp (name, "gp=default") == 0) 12776 mips_opts.gp32 = file_mips_gp32; 12777 else if (strcmp (name, "gp=32") == 0) 12778 mips_opts.gp32 = 1; 12779 else if (strcmp (name, "gp=64") == 0) 12780 { 12781 if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) 12782 as_warn ("%s isa does not support 64-bit registers", 12783 mips_cpu_info_from_isa (mips_opts.isa)->name); 12784 mips_opts.gp32 = 0; 12785 } 12786 else if (strcmp (name, "fp=default") == 0) 12787 mips_opts.fp32 = file_mips_fp32; 12788 else if (strcmp (name, "fp=32") == 0) 12789 mips_opts.fp32 = 1; 12790 else if (strcmp (name, "fp=64") == 0) 12791 { 12792 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) 12793 as_warn ("%s isa does not support 64-bit floating point registers", 12794 mips_cpu_info_from_isa (mips_opts.isa)->name); 12795 mips_opts.fp32 = 0; 12796 } 12797 else if (strcmp (name, "mips16") == 0 12798 || strcmp (name, "MIPS-16") == 0) 12799 mips_opts.mips16 = 1; 12800 else if (strcmp (name, "nomips16") == 0 12801 || strcmp (name, "noMIPS-16") == 0) 12802 mips_opts.mips16 = 0; 12803 else if (strcmp (name, "smartmips") == 0) 12804 { 12805 if (!ISA_SUPPORTS_SMARTMIPS) 12806 as_warn ("%s ISA does not support SmartMIPS ASE", 12807 mips_cpu_info_from_isa (mips_opts.isa)->name); 12808 mips_opts.ase_smartmips = 1; 12809 } 12810 else if (strcmp (name, "nosmartmips") == 0) 12811 mips_opts.ase_smartmips = 0; 12812 else if (strcmp (name, "mips3d") == 0) 12813 mips_opts.ase_mips3d = 1; 12814 else if (strcmp (name, "nomips3d") == 0) 12815 mips_opts.ase_mips3d = 0; 12816 else if (strcmp (name, "mdmx") == 0) 12817 mips_opts.ase_mdmx = 1; 12818 else if (strcmp (name, "nomdmx") == 0) 12819 mips_opts.ase_mdmx = 0; 12820 else if (strcmp (name, "dsp") == 0) 12821 { 12822 if (!ISA_SUPPORTS_DSP_ASE) 12823 as_warn ("%s ISA does not support DSP ASE", 12824 mips_cpu_info_from_isa (mips_opts.isa)->name); 12825 mips_opts.ase_dsp = 1; 12826 mips_opts.ase_dspr2 = 0; 12827 } 12828 else if (strcmp (name, "nodsp") == 0) 12829 { 12830 mips_opts.ase_dsp = 0; 12831 mips_opts.ase_dspr2 = 0; 12832 } 12833 else if (strcmp (name, "dspr2") == 0) 12834 { 12835 if (!ISA_SUPPORTS_DSPR2_ASE) 12836 as_warn ("%s ISA does not support DSP R2 ASE", 12837 mips_cpu_info_from_isa (mips_opts.isa)->name); 12838 mips_opts.ase_dspr2 = 1; 12839 mips_opts.ase_dsp = 1; 12840 } 12841 else if (strcmp (name, "nodspr2") == 0) 12842 { 12843 mips_opts.ase_dspr2 = 0; 12844 mips_opts.ase_dsp = 0; 12845 } 12846 else if (strcmp (name, "mt") == 0) 12847 { 12848 if (!ISA_SUPPORTS_MT_ASE) 12849 as_warn ("%s ISA does not support MT ASE", 12850 mips_cpu_info_from_isa (mips_opts.isa)->name); 12851 mips_opts.ase_mt = 1; 12852 } 12853 else if (strcmp (name, "nomt") == 0) 12854 mips_opts.ase_mt = 0; 12855 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) 12856 { 12857 int reset = 0; 12858 12859 /* Permit the user to change the ISA and architecture on the fly. 12860 Needless to say, misuse can cause serious problems. */ 12861 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) 12862 { 12863 reset = 1; 12864 mips_opts.isa = file_mips_isa; 12865 mips_opts.arch = file_mips_arch; 12866 } 12867 else if (strncmp (name, "arch=", 5) == 0) 12868 { 12869 const struct mips_cpu_info *p; 12870 12871 p = mips_parse_cpu("internal use", name + 5); 12872 if (!p) 12873 as_bad (_("unknown architecture %s"), name + 5); 12874 else 12875 { 12876 mips_opts.arch = p->cpu; 12877 mips_opts.isa = p->isa; 12878 } 12879 } 12880 else if (strncmp (name, "mips", 4) == 0) 12881 { 12882 const struct mips_cpu_info *p; 12883 12884 p = mips_parse_cpu("internal use", name); 12885 if (!p) 12886 as_bad (_("unknown ISA level %s"), name + 4); 12887 else 12888 { 12889 mips_opts.arch = p->cpu; 12890 mips_opts.isa = p->isa; 12891 } 12892 } 12893 else 12894 as_bad (_("unknown ISA or architecture %s"), name); 12895 12896 switch (mips_opts.isa) 12897 { 12898 case 0: 12899 break; 12900 case ISA_MIPS1: 12901 case ISA_MIPS2: 12902 case ISA_MIPS32: 12903 case ISA_MIPS32R2: 12904 mips_opts.gp32 = 1; 12905 mips_opts.fp32 = 1; 12906 break; 12907 case ISA_MIPS3: 12908 case ISA_MIPS4: 12909 case ISA_MIPS5: 12910 case ISA_MIPS64: 12911 case ISA_MIPS64R2: 12912 mips_opts.gp32 = 0; 12913 mips_opts.fp32 = 0; 12914 break; 12915 default: 12916 as_bad (_("unknown ISA level %s"), name + 4); 12917 break; 12918 } 12919 if (reset) 12920 { 12921 mips_opts.gp32 = file_mips_gp32; 12922 mips_opts.fp32 = file_mips_fp32; 12923 } 12924 } 12925 else if (strcmp (name, "autoextend") == 0) 12926 mips_opts.noautoextend = 0; 12927 else if (strcmp (name, "noautoextend") == 0) 12928 mips_opts.noautoextend = 1; 12929 else if (strcmp (name, "push") == 0) 12930 { 12931 struct mips_option_stack *s; 12932 12933 s = (struct mips_option_stack *) xmalloc (sizeof *s); 12934 s->next = mips_opts_stack; 12935 s->options = mips_opts; 12936 mips_opts_stack = s; 12937 } 12938 else if (strcmp (name, "pop") == 0) 12939 { 12940 struct mips_option_stack *s; 12941 12942 s = mips_opts_stack; 12943 if (s == NULL) 12944 as_bad (_(".set pop with no .set push")); 12945 else 12946 { 12947 /* If we're changing the reorder mode we need to handle 12948 delay slots correctly. */ 12949 if (s->options.noreorder && ! mips_opts.noreorder) 12950 start_noreorder (); 12951 else if (! s->options.noreorder && mips_opts.noreorder) 12952 end_noreorder (); 12953 12954 mips_opts = s->options; 12955 mips_opts_stack = s->next; 12956 free (s); 12957 } 12958 } 12959 else if (strcmp (name, "sym32") == 0) 12960 mips_opts.sym32 = TRUE; 12961 else if (strcmp (name, "nosym32") == 0) 12962 mips_opts.sym32 = FALSE; 12963 else if (strchr (name, ',')) 12964 { 12965 /* Generic ".set" directive; use the generic handler. */ 12966 *input_line_pointer = ch; 12967 input_line_pointer = name; 12968 s_set (0); 12969 return; 12970 } 12971 else 12972 { 12973 as_warn (_("Tried to set unrecognized symbol: %s\n"), name); 12974 } 12975 *input_line_pointer = ch; 12976 demand_empty_rest_of_line (); 12977} 12978 12979/* Handle the .abicalls pseudo-op. I believe this is equivalent to 12980 .option pic2. It means to generate SVR4 PIC calls. */ 12981 12982static void 12983s_abicalls (int ignore ATTRIBUTE_UNUSED) 12984{ 12985 mips_pic = SVR4_PIC; 12986 mips_abicalls = TRUE; 12987 12988 if (g_switch_seen && g_switch_value != 0) 12989 as_warn (_("-G may not be used with SVR4 PIC code")); 12990 g_switch_value = 0; 12991 12992 bfd_set_gp_size (stdoutput, 0); 12993 demand_empty_rest_of_line (); 12994} 12995 12996/* Handle the .cpload pseudo-op. This is used when generating SVR4 12997 PIC code. It sets the $gp register for the function based on the 12998 function address, which is in the register named in the argument. 12999 This uses a relocation against _gp_disp, which is handled specially 13000 by the linker. The result is: 13001 lui $gp,%hi(_gp_disp) 13002 addiu $gp,$gp,%lo(_gp_disp) 13003 addu $gp,$gp,.cpload argument 13004 The .cpload argument is normally $25 == $t9. 13005 13006 The -mno-shared option changes this to: 13007 lui $gp,%hi(__gnu_local_gp) 13008 addiu $gp,$gp,%lo(__gnu_local_gp) 13009 and the argument is ignored. This saves an instruction, but the 13010 resulting code is not position independent; it uses an absolute 13011 address for __gnu_local_gp. Thus code assembled with -mno-shared 13012 can go into an ordinary executable, but not into a shared library. */ 13013 13014static void 13015s_cpload (int ignore ATTRIBUTE_UNUSED) 13016{ 13017 expressionS ex; 13018 int reg; 13019 int in_shared; 13020 13021 /* If we are not generating SVR4 PIC code, or if this is NewABI code, 13022 .cpload is ignored. */ 13023 if (mips_pic != SVR4_PIC || HAVE_NEWABI) 13024 { 13025 s_ignore (0); 13026 return; 13027 } 13028 13029 /* .cpload should be in a .set noreorder section. */ 13030 if (mips_opts.noreorder == 0) 13031 as_warn (_(".cpload not in noreorder section")); 13032 13033 reg = tc_get_register (0); 13034 13035 /* If we need to produce a 64-bit address, we are better off using 13036 the default instruction sequence. */ 13037 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; 13038 13039 ex.X_op = O_symbol; 13040 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : 13041 "__gnu_local_gp"); 13042 ex.X_op_symbol = NULL; 13043 ex.X_add_number = 0; 13044 13045 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ 13046 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; 13047 13048 macro_start (); 13049 macro_build_lui (&ex, mips_gp_register); 13050 macro_build (&ex, "addiu", "t,r,j", mips_gp_register, 13051 mips_gp_register, BFD_RELOC_LO16); 13052 if (in_shared) 13053 macro_build (NULL, "addu", "d,v,t", mips_gp_register, 13054 mips_gp_register, reg); 13055 macro_end (); 13056 13057 demand_empty_rest_of_line (); 13058} 13059 13060/* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: 13061 .cpsetup $reg1, offset|$reg2, label 13062 13063 If offset is given, this results in: 13064 sd $gp, offset($sp) 13065 lui $gp, %hi(%neg(%gp_rel(label))) 13066 addiu $gp, $gp, %lo(%neg(%gp_rel(label))) 13067 daddu $gp, $gp, $reg1 13068 13069 If $reg2 is given, this results in: 13070 daddu $reg2, $gp, $0 13071 lui $gp, %hi(%neg(%gp_rel(label))) 13072 addiu $gp, $gp, %lo(%neg(%gp_rel(label))) 13073 daddu $gp, $gp, $reg1 13074 $reg1 is normally $25 == $t9. 13075 13076 The -mno-shared option replaces the last three instructions with 13077 lui $gp,%hi(_gp) 13078 addiu $gp,$gp,%lo(_gp) */ 13079 13080static void 13081s_cpsetup (int ignore ATTRIBUTE_UNUSED) 13082{ 13083 expressionS ex_off; 13084 expressionS ex_sym; 13085 int reg1; 13086 13087 /* If we are not generating SVR4 PIC code, .cpsetup is ignored. 13088 We also need NewABI support. */ 13089 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 13090 { 13091 s_ignore (0); 13092 return; 13093 } 13094 13095 reg1 = tc_get_register (0); 13096 SKIP_WHITESPACE (); 13097 if (*input_line_pointer != ',') 13098 { 13099 as_bad (_("missing argument separator ',' for .cpsetup")); 13100 return; 13101 } 13102 else 13103 ++input_line_pointer; 13104 SKIP_WHITESPACE (); 13105 if (*input_line_pointer == '$') 13106 { 13107 mips_cpreturn_register = tc_get_register (0); 13108 mips_cpreturn_offset = -1; 13109 } 13110 else 13111 { 13112 mips_cpreturn_offset = get_absolute_expression (); 13113 mips_cpreturn_register = -1; 13114 } 13115 SKIP_WHITESPACE (); 13116 if (*input_line_pointer != ',') 13117 { 13118 as_bad (_("missing argument separator ',' for .cpsetup")); 13119 return; 13120 } 13121 else 13122 ++input_line_pointer; 13123 SKIP_WHITESPACE (); 13124 expression (&ex_sym); 13125 13126 macro_start (); 13127 if (mips_cpreturn_register == -1) 13128 { 13129 ex_off.X_op = O_constant; 13130 ex_off.X_add_symbol = NULL; 13131 ex_off.X_op_symbol = NULL; 13132 ex_off.X_add_number = mips_cpreturn_offset; 13133 13134 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, 13135 BFD_RELOC_LO16, SP); 13136 } 13137 else 13138 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, 13139 mips_gp_register, 0); 13140 13141 if (mips_in_shared || HAVE_64BIT_SYMBOLS) 13142 { 13143 macro_build (&ex_sym, "lui", "t,u", mips_gp_register, 13144 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, 13145 BFD_RELOC_HI16_S); 13146 13147 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, 13148 mips_gp_register, -1, BFD_RELOC_GPREL16, 13149 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); 13150 13151 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, 13152 mips_gp_register, reg1); 13153 } 13154 else 13155 { 13156 expressionS ex; 13157 13158 ex.X_op = O_symbol; 13159 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); 13160 ex.X_op_symbol = NULL; 13161 ex.X_add_number = 0; 13162 13163 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ 13164 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; 13165 13166 macro_build_lui (&ex, mips_gp_register); 13167 macro_build (&ex, "addiu", "t,r,j", mips_gp_register, 13168 mips_gp_register, BFD_RELOC_LO16); 13169 } 13170 13171 macro_end (); 13172 13173 demand_empty_rest_of_line (); 13174} 13175 13176static void 13177s_cplocal (int ignore ATTRIBUTE_UNUSED) 13178{ 13179 /* If we are not generating SVR4 PIC code, or if this is not NewABI code, 13180 .cplocal is ignored. */ 13181 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 13182 { 13183 s_ignore (0); 13184 return; 13185 } 13186 13187 mips_gp_register = tc_get_register (0); 13188 demand_empty_rest_of_line (); 13189} 13190 13191/* Handle the .cprestore pseudo-op. This stores $gp into a given 13192 offset from $sp. The offset is remembered, and after making a PIC 13193 call $gp is restored from that location. */ 13194 13195static void 13196s_cprestore (int ignore ATTRIBUTE_UNUSED) 13197{ 13198 expressionS ex; 13199 13200 /* If we are not generating SVR4 PIC code, or if this is NewABI code, 13201 .cprestore is ignored. */ 13202 if (mips_pic != SVR4_PIC || HAVE_NEWABI) 13203 { 13204 s_ignore (0); 13205 return; 13206 } 13207 13208 mips_cprestore_offset = get_absolute_expression (); 13209 mips_cprestore_valid = 1; 13210 13211 ex.X_op = O_constant; 13212 ex.X_add_symbol = NULL; 13213 ex.X_op_symbol = NULL; 13214 ex.X_add_number = mips_cprestore_offset; 13215 13216 macro_start (); 13217 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, 13218 SP, HAVE_64BIT_ADDRESSES); 13219 macro_end (); 13220 13221 demand_empty_rest_of_line (); 13222} 13223 13224/* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset 13225 was given in the preceding .cpsetup, it results in: 13226 ld $gp, offset($sp) 13227 13228 If a register $reg2 was given there, it results in: 13229 daddu $gp, $reg2, $0 */ 13230 13231static void 13232s_cpreturn (int ignore ATTRIBUTE_UNUSED) 13233{ 13234 expressionS ex; 13235 13236 /* If we are not generating SVR4 PIC code, .cpreturn is ignored. 13237 We also need NewABI support. */ 13238 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 13239 { 13240 s_ignore (0); 13241 return; 13242 } 13243 13244 macro_start (); 13245 if (mips_cpreturn_register == -1) 13246 { 13247 ex.X_op = O_constant; 13248 ex.X_add_symbol = NULL; 13249 ex.X_op_symbol = NULL; 13250 ex.X_add_number = mips_cpreturn_offset; 13251 13252 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); 13253 } 13254 else 13255 macro_build (NULL, "daddu", "d,v,t", mips_gp_register, 13256 mips_cpreturn_register, 0); 13257 macro_end (); 13258 13259 demand_empty_rest_of_line (); 13260} 13261 13262/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate 13263 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for 13264 use in DWARF debug information. */ 13265 13266static void 13267s_dtprel_internal (size_t bytes) 13268{ 13269 expressionS ex; 13270 char *p; 13271 13272 expression (&ex); 13273 13274 if (ex.X_op != O_symbol) 13275 { 13276 as_bad (_("Unsupported use of %s"), (bytes == 8 13277 ? ".dtpreldword" 13278 : ".dtprelword")); 13279 ignore_rest_of_line (); 13280 } 13281 13282 p = frag_more (bytes); 13283 md_number_to_chars (p, 0, bytes); 13284 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, 13285 (bytes == 8 13286 ? BFD_RELOC_MIPS_TLS_DTPREL64 13287 : BFD_RELOC_MIPS_TLS_DTPREL32)); 13288 13289 demand_empty_rest_of_line (); 13290} 13291 13292/* Handle .dtprelword. */ 13293 13294static void 13295s_dtprelword (int ignore ATTRIBUTE_UNUSED) 13296{ 13297 s_dtprel_internal (4); 13298} 13299 13300/* Handle .dtpreldword. */ 13301 13302static void 13303s_dtpreldword (int ignore ATTRIBUTE_UNUSED) 13304{ 13305 s_dtprel_internal (8); 13306} 13307 13308/* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC 13309 code. It sets the offset to use in gp_rel relocations. */ 13310 13311static void 13312s_gpvalue (int ignore ATTRIBUTE_UNUSED) 13313{ 13314 /* If we are not generating SVR4 PIC code, .gpvalue is ignored. 13315 We also need NewABI support. */ 13316 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 13317 { 13318 s_ignore (0); 13319 return; 13320 } 13321 13322 mips_gprel_offset = get_absolute_expression (); 13323 13324 demand_empty_rest_of_line (); 13325} 13326 13327/* Handle the .gpword pseudo-op. This is used when generating PIC 13328 code. It generates a 32 bit GP relative reloc. */ 13329 13330static void 13331s_gpword (int ignore ATTRIBUTE_UNUSED) 13332{ 13333 segment_info_type *si; 13334 struct insn_label_list *l; 13335 symbolS *label; 13336 expressionS ex; 13337 char *p; 13338 13339 /* When not generating PIC code, this is treated as .word. */ 13340 if (mips_pic != SVR4_PIC) 13341 { 13342 s_cons (2); 13343 return; 13344 } 13345 13346 si = seg_info (now_seg); 13347 l = si->label_list; 13348 label = l != NULL ? l->label : NULL; 13349 mips_emit_delays (); 13350 if (auto_align) 13351 mips_align (2, 0, label); 13352 mips_clear_insn_labels (); 13353 13354 expression (&ex); 13355 13356 if (ex.X_op != O_symbol || ex.X_add_number != 0) 13357 { 13358 as_bad (_("Unsupported use of .gpword")); 13359 ignore_rest_of_line (); 13360 } 13361 13362 p = frag_more (4); 13363 md_number_to_chars (p, 0, 4); 13364 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, 13365 BFD_RELOC_GPREL32); 13366 13367 demand_empty_rest_of_line (); 13368} 13369 13370static void 13371s_gpdword (int ignore ATTRIBUTE_UNUSED) 13372{ 13373 segment_info_type *si; 13374 struct insn_label_list *l; 13375 symbolS *label; 13376 expressionS ex; 13377 char *p; 13378 13379 /* When not generating PIC code, this is treated as .dword. */ 13380 if (mips_pic != SVR4_PIC) 13381 { 13382 s_cons (3); 13383 return; 13384 } 13385 13386 si = seg_info (now_seg); 13387 l = si->label_list; 13388 label = l != NULL ? l->label : NULL; 13389 mips_emit_delays (); 13390 if (auto_align) 13391 mips_align (3, 0, label); 13392 mips_clear_insn_labels (); 13393 13394 expression (&ex); 13395 13396 if (ex.X_op != O_symbol || ex.X_add_number != 0) 13397 { 13398 as_bad (_("Unsupported use of .gpdword")); 13399 ignore_rest_of_line (); 13400 } 13401 13402 p = frag_more (8); 13403 md_number_to_chars (p, 0, 8); 13404 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, 13405 BFD_RELOC_GPREL32)->fx_tcbit = 1; 13406 13407 /* GPREL32 composed with 64 gives a 64-bit GP offset. */ 13408 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, 13409 FALSE, BFD_RELOC_64)->fx_tcbit = 1; 13410 13411 demand_empty_rest_of_line (); 13412} 13413 13414/* Handle the .cpadd pseudo-op. This is used when dealing with switch 13415 tables in SVR4 PIC code. */ 13416 13417static void 13418s_cpadd (int ignore ATTRIBUTE_UNUSED) 13419{ 13420 int reg; 13421 13422 /* This is ignored when not generating SVR4 PIC code. */ 13423 if (mips_pic != SVR4_PIC) 13424 { 13425 s_ignore (0); 13426 return; 13427 } 13428 13429 /* Add $gp to the register named as an argument. */ 13430 macro_start (); 13431 reg = tc_get_register (0); 13432 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); 13433 macro_end (); 13434 13435 demand_empty_rest_of_line (); 13436} 13437 13438/* Handle the .insn pseudo-op. This marks instruction labels in 13439 mips16 mode. This permits the linker to handle them specially, 13440 such as generating jalx instructions when needed. We also make 13441 them odd for the duration of the assembly, in order to generate the 13442 right sort of code. We will make them even in the adjust_symtab 13443 routine, while leaving them marked. This is convenient for the 13444 debugger and the disassembler. The linker knows to make them odd 13445 again. */ 13446 13447static void 13448s_insn (int ignore ATTRIBUTE_UNUSED) 13449{ 13450 mips16_mark_labels (); 13451 13452 demand_empty_rest_of_line (); 13453} 13454 13455/* Handle a .stabn directive. We need these in order to mark a label 13456 as being a mips16 text label correctly. Sometimes the compiler 13457 will emit a label, followed by a .stabn, and then switch sections. 13458 If the label and .stabn are in mips16 mode, then the label is 13459 really a mips16 text label. */ 13460 13461static void 13462s_mips_stab (int type) 13463{ 13464 if (type == 'n') 13465 mips16_mark_labels (); 13466 13467 s_stab (type); 13468} 13469 13470/* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ 13471 13472static void 13473s_mips_weakext (int ignore ATTRIBUTE_UNUSED) 13474{ 13475 char *name; 13476 int c; 13477 symbolS *symbolP; 13478 expressionS exp; 13479 13480 name = input_line_pointer; 13481 c = get_symbol_end (); 13482 symbolP = symbol_find_or_make (name); 13483 S_SET_WEAK (symbolP); 13484 *input_line_pointer = c; 13485 13486 SKIP_WHITESPACE (); 13487 13488 if (! is_end_of_line[(unsigned char) *input_line_pointer]) 13489 { 13490 if (S_IS_DEFINED (symbolP)) 13491 { 13492 as_bad ("ignoring attempt to redefine symbol %s", 13493 S_GET_NAME (symbolP)); 13494 ignore_rest_of_line (); 13495 return; 13496 } 13497 13498 if (*input_line_pointer == ',') 13499 { 13500 ++input_line_pointer; 13501 SKIP_WHITESPACE (); 13502 } 13503 13504 expression (&exp); 13505 if (exp.X_op != O_symbol) 13506 { 13507 as_bad ("bad .weakext directive"); 13508 ignore_rest_of_line (); 13509 return; 13510 } 13511 symbol_set_value_expression (symbolP, &exp); 13512 } 13513 13514 demand_empty_rest_of_line (); 13515} 13516 13517/* Parse a register string into a number. Called from the ECOFF code 13518 to parse .frame. The argument is non-zero if this is the frame 13519 register, so that we can record it in mips_frame_reg. */ 13520 13521int 13522tc_get_register (int frame) 13523{ 13524 unsigned int reg; 13525 13526 SKIP_WHITESPACE (); 13527 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) 13528 reg = 0; 13529 if (frame) 13530 { 13531 mips_frame_reg = reg != 0 ? reg : SP; 13532 mips_frame_reg_valid = 1; 13533 mips_cprestore_valid = 0; 13534 } 13535 return reg; 13536} 13537 13538valueT 13539md_section_align (asection *seg, valueT addr) 13540{ 13541 int align = bfd_get_section_alignment (stdoutput, seg); 13542 13543 if (IS_ELF) 13544 { 13545 /* We don't need to align ELF sections to the full alignment. 13546 However, Irix 5 may prefer that we align them at least to a 16 13547 byte boundary. We don't bother to align the sections if we 13548 are targeted for an embedded system. */ 13549 if (strcmp (TARGET_OS, "elf") == 0) 13550 return addr; 13551 if (align > 4) 13552 align = 4; 13553 } 13554 13555 return ((addr + (1 << align) - 1) & (-1 << align)); 13556} 13557 13558/* Utility routine, called from above as well. If called while the 13559 input file is still being read, it's only an approximation. (For 13560 example, a symbol may later become defined which appeared to be 13561 undefined earlier.) */ 13562 13563static int 13564nopic_need_relax (symbolS *sym, int before_relaxing) 13565{ 13566 if (sym == 0) 13567 return 0; 13568 13569 if (g_switch_value > 0) 13570 { 13571 const char *symname; 13572 int change; 13573 13574 /* Find out whether this symbol can be referenced off the $gp 13575 register. It can be if it is smaller than the -G size or if 13576 it is in the .sdata or .sbss section. Certain symbols can 13577 not be referenced off the $gp, although it appears as though 13578 they can. */ 13579 symname = S_GET_NAME (sym); 13580 if (symname != (const char *) NULL 13581 && (strcmp (symname, "eprol") == 0 13582 || strcmp (symname, "etext") == 0 13583 || strcmp (symname, "_gp") == 0 13584 || strcmp (symname, "edata") == 0 13585 || strcmp (symname, "_fbss") == 0 13586 || strcmp (symname, "_fdata") == 0 13587 || strcmp (symname, "_ftext") == 0 13588 || strcmp (symname, "end") == 0 13589 || strcmp (symname, "_gp_disp") == 0)) 13590 change = 1; 13591 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) 13592 && (0 13593#ifndef NO_ECOFF_DEBUGGING 13594 || (symbol_get_obj (sym)->ecoff_extern_size != 0 13595 && (symbol_get_obj (sym)->ecoff_extern_size 13596 <= g_switch_value)) 13597#endif 13598 /* We must defer this decision until after the whole 13599 file has been read, since there might be a .extern 13600 after the first use of this symbol. */ 13601 || (before_relaxing 13602#ifndef NO_ECOFF_DEBUGGING 13603 && symbol_get_obj (sym)->ecoff_extern_size == 0 13604#endif 13605 && S_GET_VALUE (sym) == 0) 13606 || (S_GET_VALUE (sym) != 0 13607 && S_GET_VALUE (sym) <= g_switch_value))) 13608 change = 0; 13609 else 13610 { 13611 const char *segname; 13612 13613 segname = segment_name (S_GET_SEGMENT (sym)); 13614 assert (strcmp (segname, ".lit8") != 0 13615 && strcmp (segname, ".lit4") != 0); 13616 change = (strcmp (segname, ".sdata") != 0 13617 && strcmp (segname, ".sbss") != 0 13618 && strncmp (segname, ".sdata.", 7) != 0 13619 && strncmp (segname, ".sbss.", 6) != 0 13620 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 13621 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); 13622 } 13623 return change; 13624 } 13625 else 13626 /* We are not optimizing for the $gp register. */ 13627 return 1; 13628} 13629 13630 13631/* Return true if the given symbol should be considered local for SVR4 PIC. */ 13632 13633static bfd_boolean 13634pic_need_relax (symbolS *sym, asection *segtype) 13635{ 13636 asection *symsec; 13637 13638 /* Handle the case of a symbol equated to another symbol. */ 13639 while (symbol_equated_reloc_p (sym)) 13640 { 13641 symbolS *n; 13642 13643 /* It's possible to get a loop here in a badly written program. */ 13644 n = symbol_get_value_expression (sym)->X_add_symbol; 13645 if (n == sym) 13646 break; 13647 sym = n; 13648 } 13649 13650 if (symbol_section_p (sym)) 13651 return TRUE; 13652 13653 symsec = S_GET_SEGMENT (sym); 13654 13655 /* This must duplicate the test in adjust_reloc_syms. */ 13656 return (symsec != &bfd_und_section 13657 && symsec != &bfd_abs_section 13658 && !bfd_is_com_section (symsec) 13659 && !s_is_linkonce (sym, segtype) 13660#ifdef OBJ_ELF 13661 /* A global or weak symbol is treated as external. */ 13662 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) 13663#endif 13664 ); 13665} 13666 13667 13668/* Given a mips16 variant frag FRAGP, return non-zero if it needs an 13669 extended opcode. SEC is the section the frag is in. */ 13670 13671static int 13672mips16_extended_frag (fragS *fragp, asection *sec, long stretch) 13673{ 13674 int type; 13675 const struct mips16_immed_operand *op; 13676 offsetT val; 13677 int mintiny, maxtiny; 13678 segT symsec; 13679 fragS *sym_frag; 13680 13681 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) 13682 return 0; 13683 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) 13684 return 1; 13685 13686 type = RELAX_MIPS16_TYPE (fragp->fr_subtype); 13687 op = mips16_immed_operands; 13688 while (op->type != type) 13689 { 13690 ++op; 13691 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); 13692 } 13693 13694 if (op->unsp) 13695 { 13696 if (type == '<' || type == '>' || type == '[' || type == ']') 13697 { 13698 mintiny = 1; 13699 maxtiny = 1 << op->nbits; 13700 } 13701 else 13702 { 13703 mintiny = 0; 13704 maxtiny = (1 << op->nbits) - 1; 13705 } 13706 } 13707 else 13708 { 13709 mintiny = - (1 << (op->nbits - 1)); 13710 maxtiny = (1 << (op->nbits - 1)) - 1; 13711 } 13712 13713 sym_frag = symbol_get_frag (fragp->fr_symbol); 13714 val = S_GET_VALUE (fragp->fr_symbol); 13715 symsec = S_GET_SEGMENT (fragp->fr_symbol); 13716 13717 if (op->pcrel) 13718 { 13719 addressT addr; 13720 13721 /* We won't have the section when we are called from 13722 mips_relax_frag. However, we will always have been called 13723 from md_estimate_size_before_relax first. If this is a 13724 branch to a different section, we mark it as such. If SEC is 13725 NULL, and the frag is not marked, then it must be a branch to 13726 the same section. */ 13727 if (sec == NULL) 13728 { 13729 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) 13730 return 1; 13731 } 13732 else 13733 { 13734 /* Must have been called from md_estimate_size_before_relax. */ 13735 if (symsec != sec) 13736 { 13737 fragp->fr_subtype = 13738 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); 13739 13740 /* FIXME: We should support this, and let the linker 13741 catch branches and loads that are out of range. */ 13742 as_bad_where (fragp->fr_file, fragp->fr_line, 13743 _("unsupported PC relative reference to different section")); 13744 13745 return 1; 13746 } 13747 if (fragp != sym_frag && sym_frag->fr_address == 0) 13748 /* Assume non-extended on the first relaxation pass. 13749 The address we have calculated will be bogus if this is 13750 a forward branch to another frag, as the forward frag 13751 will have fr_address == 0. */ 13752 return 0; 13753 } 13754 13755 /* In this case, we know for sure that the symbol fragment is in 13756 the same section. If the relax_marker of the symbol fragment 13757 differs from the relax_marker of this fragment, we have not 13758 yet adjusted the symbol fragment fr_address. We want to add 13759 in STRETCH in order to get a better estimate of the address. 13760 This particularly matters because of the shift bits. */ 13761 if (stretch != 0 13762 && sym_frag->relax_marker != fragp->relax_marker) 13763 { 13764 fragS *f; 13765 13766 /* Adjust stretch for any alignment frag. Note that if have 13767 been expanding the earlier code, the symbol may be 13768 defined in what appears to be an earlier frag. FIXME: 13769 This doesn't handle the fr_subtype field, which specifies 13770 a maximum number of bytes to skip when doing an 13771 alignment. */ 13772 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) 13773 { 13774 if (f->fr_type == rs_align || f->fr_type == rs_align_code) 13775 { 13776 if (stretch < 0) 13777 stretch = - ((- stretch) 13778 & ~ ((1 << (int) f->fr_offset) - 1)); 13779 else 13780 stretch &= ~ ((1 << (int) f->fr_offset) - 1); 13781 if (stretch == 0) 13782 break; 13783 } 13784 } 13785 if (f != NULL) 13786 val += stretch; 13787 } 13788 13789 addr = fragp->fr_address + fragp->fr_fix; 13790 13791 /* The base address rules are complicated. The base address of 13792 a branch is the following instruction. The base address of a 13793 PC relative load or add is the instruction itself, but if it 13794 is in a delay slot (in which case it can not be extended) use 13795 the address of the instruction whose delay slot it is in. */ 13796 if (type == 'p' || type == 'q') 13797 { 13798 addr += 2; 13799 13800 /* If we are currently assuming that this frag should be 13801 extended, then, the current address is two bytes 13802 higher. */ 13803 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 13804 addr += 2; 13805 13806 /* Ignore the low bit in the target, since it will be set 13807 for a text label. */ 13808 if ((val & 1) != 0) 13809 --val; 13810 } 13811 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) 13812 addr -= 4; 13813 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) 13814 addr -= 2; 13815 13816 val -= addr & ~ ((1 << op->shift) - 1); 13817 13818 /* Branch offsets have an implicit 0 in the lowest bit. */ 13819 if (type == 'p' || type == 'q') 13820 val /= 2; 13821 13822 /* If any of the shifted bits are set, we must use an extended 13823 opcode. If the address depends on the size of this 13824 instruction, this can lead to a loop, so we arrange to always 13825 use an extended opcode. We only check this when we are in 13826 the main relaxation loop, when SEC is NULL. */ 13827 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) 13828 { 13829 fragp->fr_subtype = 13830 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); 13831 return 1; 13832 } 13833 13834 /* If we are about to mark a frag as extended because the value 13835 is precisely maxtiny + 1, then there is a chance of an 13836 infinite loop as in the following code: 13837 la $4,foo 13838 .skip 1020 13839 .align 2 13840 foo: 13841 In this case when the la is extended, foo is 0x3fc bytes 13842 away, so the la can be shrunk, but then foo is 0x400 away, so 13843 the la must be extended. To avoid this loop, we mark the 13844 frag as extended if it was small, and is about to become 13845 extended with a value of maxtiny + 1. */ 13846 if (val == ((maxtiny + 1) << op->shift) 13847 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) 13848 && sec == NULL) 13849 { 13850 fragp->fr_subtype = 13851 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); 13852 return 1; 13853 } 13854 } 13855 else if (symsec != absolute_section && sec != NULL) 13856 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); 13857 13858 if ((val & ((1 << op->shift) - 1)) != 0 13859 || val < (mintiny << op->shift) 13860 || val > (maxtiny << op->shift)) 13861 return 1; 13862 else 13863 return 0; 13864} 13865 13866/* Compute the length of a branch sequence, and adjust the 13867 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the 13868 worst-case length is computed, with UPDATE being used to indicate 13869 whether an unconditional (-1), branch-likely (+1) or regular (0) 13870 branch is to be computed. */ 13871static int 13872relaxed_branch_length (fragS *fragp, asection *sec, int update) 13873{ 13874 bfd_boolean toofar; 13875 int length; 13876 13877 if (fragp 13878 && S_IS_DEFINED (fragp->fr_symbol) 13879 && sec == S_GET_SEGMENT (fragp->fr_symbol)) 13880 { 13881 addressT addr; 13882 offsetT val; 13883 13884 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 13885 13886 addr = fragp->fr_address + fragp->fr_fix + 4; 13887 13888 val -= addr; 13889 13890 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); 13891 } 13892 else if (fragp) 13893 /* If the symbol is not defined or it's in a different segment, 13894 assume the user knows what's going on and emit a short 13895 branch. */ 13896 toofar = FALSE; 13897 else 13898 toofar = TRUE; 13899 13900 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) 13901 fragp->fr_subtype 13902 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), 13903 RELAX_BRANCH_LIKELY (fragp->fr_subtype), 13904 RELAX_BRANCH_LINK (fragp->fr_subtype), 13905 toofar); 13906 13907 length = 4; 13908 if (toofar) 13909 { 13910 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) 13911 length += 8; 13912 13913 if (mips_pic != NO_PIC) 13914 { 13915 /* Additional space for PIC loading of target address. */ 13916 length += 8; 13917 if (mips_opts.isa == ISA_MIPS1) 13918 /* Additional space for $at-stabilizing nop. */ 13919 length += 4; 13920 } 13921 13922 /* If branch is conditional. */ 13923 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) 13924 length += 8; 13925 } 13926 13927 return length; 13928} 13929 13930/* Estimate the size of a frag before relaxing. Unless this is the 13931 mips16, we are not really relaxing here, and the final size is 13932 encoded in the subtype information. For the mips16, we have to 13933 decide whether we are using an extended opcode or not. */ 13934 13935int 13936md_estimate_size_before_relax (fragS *fragp, asection *segtype) 13937{ 13938 int change; 13939 13940 if (RELAX_BRANCH_P (fragp->fr_subtype)) 13941 { 13942 13943 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); 13944 13945 return fragp->fr_var; 13946 } 13947 13948 if (RELAX_MIPS16_P (fragp->fr_subtype)) 13949 /* We don't want to modify the EXTENDED bit here; it might get us 13950 into infinite loops. We change it only in mips_relax_frag(). */ 13951 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); 13952 13953 if (mips_pic == NO_PIC) 13954 change = nopic_need_relax (fragp->fr_symbol, 0); 13955 else if (mips_pic == SVR4_PIC) 13956 change = pic_need_relax (fragp->fr_symbol, segtype); 13957 else if (mips_pic == VXWORKS_PIC) 13958 /* For vxworks, GOT16 relocations never have a corresponding LO16. */ 13959 change = 0; 13960 else 13961 abort (); 13962 13963 if (change) 13964 { 13965 fragp->fr_subtype |= RELAX_USE_SECOND; 13966 return -RELAX_FIRST (fragp->fr_subtype); 13967 } 13968 else 13969 return -RELAX_SECOND (fragp->fr_subtype); 13970} 13971 13972/* This is called to see whether a reloc against a defined symbol 13973 should be converted into a reloc against a section. */ 13974 13975int 13976mips_fix_adjustable (fixS *fixp) 13977{ 13978 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT 13979 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 13980 return 0; 13981 13982 if (fixp->fx_addsy == NULL) 13983 return 1; 13984 13985 /* If symbol SYM is in a mergeable section, relocations of the form 13986 SYM + 0 can usually be made section-relative. The mergeable data 13987 is then identified by the section offset rather than by the symbol. 13988 13989 However, if we're generating REL LO16 relocations, the offset is split 13990 between the LO16 and parterning high part relocation. The linker will 13991 need to recalculate the complete offset in order to correctly identify 13992 the merge data. 13993 13994 The linker has traditionally not looked for the parterning high part 13995 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be 13996 placed anywhere. Rather than break backwards compatibility by changing 13997 this, it seems better not to force the issue, and instead keep the 13998 original symbol. This will work with either linker behavior. */ 13999 if ((fixp->fx_r_type == BFD_RELOC_LO16 14000 || fixp->fx_r_type == BFD_RELOC_MIPS16_LO16 14001 || reloc_needs_lo_p (fixp->fx_r_type)) 14002 && HAVE_IN_PLACE_ADDENDS 14003 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) 14004 return 0; 14005 14006#ifdef OBJ_ELF 14007 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve 14008 to a floating-point stub. The same is true for non-R_MIPS16_26 14009 relocations against MIPS16 functions; in this case, the stub becomes 14010 the function's canonical address. 14011 14012 Floating-point stubs are stored in unique .mips16.call.* or 14013 .mips16.fn.* sections. If a stub T for function F is in section S, 14014 the first relocation in section S must be against F; this is how the 14015 linker determines the target function. All relocations that might 14016 resolve to T must also be against F. We therefore have the following 14017 restrictions, which are given in an intentionally-redundant way: 14018 14019 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 14020 symbols. 14021 14022 2. We cannot reduce a stub's relocations against non-MIPS16 symbols 14023 if that stub might be used. 14024 14025 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 14026 symbols. 14027 14028 4. We cannot reduce a stub's relocations against MIPS16 symbols if 14029 that stub might be used. 14030 14031 There is a further restriction: 14032 14033 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols 14034 on targets with in-place addends; the relocation field cannot 14035 encode the low bit. 14036 14037 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation 14038 against a MIPS16 symbol. 14039 14040 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 14041 relocation against some symbol R, no relocation against R may be 14042 reduced. (Note that this deals with (2) as well as (1) because 14043 relocations against global symbols will never be reduced on ELF 14044 targets.) This approach is a little simpler than trying to detect 14045 stub sections, and gives the "all or nothing" per-symbol consistency 14046 that we have for MIPS16 symbols. */ 14047 if (IS_ELF 14048 && fixp->fx_subsy == NULL 14049 && (S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 14050 || *symbol_get_tc (fixp->fx_addsy))) 14051 return 0; 14052#endif 14053 14054 return 1; 14055} 14056 14057/* Translate internal representation of relocation info to BFD target 14058 format. */ 14059 14060arelent ** 14061tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 14062{ 14063 static arelent *retval[4]; 14064 arelent *reloc; 14065 bfd_reloc_code_real_type code; 14066 14067 memset (retval, 0, sizeof(retval)); 14068 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); 14069 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 14070 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 14071 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 14072 14073 if (fixp->fx_pcrel) 14074 { 14075 assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2); 14076 14077 /* At this point, fx_addnumber is "symbol offset - pcrel address". 14078 Relocations want only the symbol offset. */ 14079 reloc->addend = fixp->fx_addnumber + reloc->address; 14080 if (!IS_ELF) 14081 { 14082 /* A gruesome hack which is a result of the gruesome gas 14083 reloc handling. What's worse, for COFF (as opposed to 14084 ECOFF), we might need yet another copy of reloc->address. 14085 See bfd_install_relocation. */ 14086 reloc->addend += reloc->address; 14087 } 14088 } 14089 else 14090 reloc->addend = fixp->fx_addnumber; 14091 14092 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable 14093 entry to be used in the relocation's section offset. */ 14094 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 14095 { 14096 reloc->address = reloc->addend; 14097 reloc->addend = 0; 14098 } 14099 14100 code = fixp->fx_r_type; 14101 14102 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 14103 if (reloc->howto == NULL) 14104 { 14105 as_bad_where (fixp->fx_file, fixp->fx_line, 14106 _("Can not represent %s relocation in this object file format"), 14107 bfd_get_reloc_code_name (code)); 14108 retval[0] = NULL; 14109 } 14110 14111 return retval; 14112} 14113 14114/* Relax a machine dependent frag. This returns the amount by which 14115 the current size of the frag should change. */ 14116 14117int 14118mips_relax_frag (asection *sec, fragS *fragp, long stretch) 14119{ 14120 if (RELAX_BRANCH_P (fragp->fr_subtype)) 14121 { 14122 offsetT old_var = fragp->fr_var; 14123 14124 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); 14125 14126 return fragp->fr_var - old_var; 14127 } 14128 14129 if (! RELAX_MIPS16_P (fragp->fr_subtype)) 14130 return 0; 14131 14132 if (mips16_extended_frag (fragp, NULL, stretch)) 14133 { 14134 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 14135 return 0; 14136 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); 14137 return 2; 14138 } 14139 else 14140 { 14141 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 14142 return 0; 14143 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); 14144 return -2; 14145 } 14146 14147 return 0; 14148} 14149 14150/* Convert a machine dependent frag. */ 14151 14152void 14153md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) 14154{ 14155 if (RELAX_BRANCH_P (fragp->fr_subtype)) 14156 { 14157 bfd_byte *buf; 14158 unsigned long insn; 14159 expressionS exp; 14160 fixS *fixp; 14161 14162 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; 14163 14164 if (target_big_endian) 14165 insn = bfd_getb32 (buf); 14166 else 14167 insn = bfd_getl32 (buf); 14168 14169 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) 14170 { 14171 /* We generate a fixup instead of applying it right now 14172 because, if there are linker relaxations, we're going to 14173 need the relocations. */ 14174 exp.X_op = O_symbol; 14175 exp.X_add_symbol = fragp->fr_symbol; 14176 exp.X_add_number = fragp->fr_offset; 14177 14178 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, 14179 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); 14180 fixp->fx_file = fragp->fr_file; 14181 fixp->fx_line = fragp->fr_line; 14182 14183 md_number_to_chars ((char *) buf, insn, 4); 14184 buf += 4; 14185 } 14186 else 14187 { 14188 int i; 14189 14190 as_warn_where (fragp->fr_file, fragp->fr_line, 14191 _("relaxed out-of-range branch into a jump")); 14192 14193 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) 14194 goto uncond; 14195 14196 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 14197 { 14198 /* Reverse the branch. */ 14199 switch ((insn >> 28) & 0xf) 14200 { 14201 case 4: 14202 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can 14203 have the condition reversed by tweaking a single 14204 bit, and their opcodes all have 0x4???????. */ 14205 assert ((insn & 0xf1000000) == 0x41000000); 14206 insn ^= 0x00010000; 14207 break; 14208 14209 case 0: 14210 /* bltz 0x04000000 bgez 0x04010000 14211 bltzal 0x04100000 bgezal 0x04110000 */ 14212 assert ((insn & 0xfc0e0000) == 0x04000000); 14213 insn ^= 0x00010000; 14214 break; 14215 14216 case 1: 14217 /* beq 0x10000000 bne 0x14000000 14218 blez 0x18000000 bgtz 0x1c000000 */ 14219 insn ^= 0x04000000; 14220 break; 14221 14222 default: 14223 abort (); 14224 } 14225 } 14226 14227 if (RELAX_BRANCH_LINK (fragp->fr_subtype)) 14228 { 14229 /* Clear the and-link bit. */ 14230 assert ((insn & 0xfc1c0000) == 0x04100000); 14231 14232 /* bltzal 0x04100000 bgezal 0x04110000 14233 bltzall 0x04120000 bgezall 0x04130000 */ 14234 insn &= ~0x00100000; 14235 } 14236 14237 /* Branch over the branch (if the branch was likely) or the 14238 full jump (not likely case). Compute the offset from the 14239 current instruction to branch to. */ 14240 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 14241 i = 16; 14242 else 14243 { 14244 /* How many bytes in instructions we've already emitted? */ 14245 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; 14246 /* How many bytes in instructions from here to the end? */ 14247 i = fragp->fr_var - i; 14248 } 14249 /* Convert to instruction count. */ 14250 i >>= 2; 14251 /* Branch counts from the next instruction. */ 14252 i--; 14253 insn |= i; 14254 /* Branch over the jump. */ 14255 md_number_to_chars ((char *) buf, insn, 4); 14256 buf += 4; 14257 14258 /* nop */ 14259 md_number_to_chars ((char *) buf, 0, 4); 14260 buf += 4; 14261 14262 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 14263 { 14264 /* beql $0, $0, 2f */ 14265 insn = 0x50000000; 14266 /* Compute the PC offset from the current instruction to 14267 the end of the variable frag. */ 14268 /* How many bytes in instructions we've already emitted? */ 14269 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; 14270 /* How many bytes in instructions from here to the end? */ 14271 i = fragp->fr_var - i; 14272 /* Convert to instruction count. */ 14273 i >>= 2; 14274 /* Don't decrement i, because we want to branch over the 14275 delay slot. */ 14276 14277 insn |= i; 14278 md_number_to_chars ((char *) buf, insn, 4); 14279 buf += 4; 14280 14281 md_number_to_chars ((char *) buf, 0, 4); 14282 buf += 4; 14283 } 14284 14285 uncond: 14286 if (mips_pic == NO_PIC) 14287 { 14288 /* j or jal. */ 14289 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) 14290 ? 0x0c000000 : 0x08000000); 14291 exp.X_op = O_symbol; 14292 exp.X_add_symbol = fragp->fr_symbol; 14293 exp.X_add_number = fragp->fr_offset; 14294 14295 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, 14296 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); 14297 fixp->fx_file = fragp->fr_file; 14298 fixp->fx_line = fragp->fr_line; 14299 14300 md_number_to_chars ((char *) buf, insn, 4); 14301 buf += 4; 14302 } 14303 else 14304 { 14305 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ 14306 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; 14307 exp.X_op = O_symbol; 14308 exp.X_add_symbol = fragp->fr_symbol; 14309 exp.X_add_number = fragp->fr_offset; 14310 14311 if (fragp->fr_offset) 14312 { 14313 exp.X_add_symbol = make_expr_symbol (&exp); 14314 exp.X_add_number = 0; 14315 } 14316 14317 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, 14318 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); 14319 fixp->fx_file = fragp->fr_file; 14320 fixp->fx_line = fragp->fr_line; 14321 14322 md_number_to_chars ((char *) buf, insn, 4); 14323 buf += 4; 14324 14325 if (mips_opts.isa == ISA_MIPS1) 14326 { 14327 /* nop */ 14328 md_number_to_chars ((char *) buf, 0, 4); 14329 buf += 4; 14330 } 14331 14332 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ 14333 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; 14334 14335 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, 14336 4, &exp, FALSE, BFD_RELOC_LO16); 14337 fixp->fx_file = fragp->fr_file; 14338 fixp->fx_line = fragp->fr_line; 14339 14340 md_number_to_chars ((char *) buf, insn, 4); 14341 buf += 4; 14342 14343 /* j(al)r $at. */ 14344 if (RELAX_BRANCH_LINK (fragp->fr_subtype)) 14345 insn = 0x0020f809; 14346 else 14347 insn = 0x00200008; 14348 14349 md_number_to_chars ((char *) buf, insn, 4); 14350 buf += 4; 14351 } 14352 } 14353 14354 assert (buf == (bfd_byte *)fragp->fr_literal 14355 + fragp->fr_fix + fragp->fr_var); 14356 14357 fragp->fr_fix += fragp->fr_var; 14358 14359 return; 14360 } 14361 14362 if (RELAX_MIPS16_P (fragp->fr_subtype)) 14363 { 14364 int type; 14365 const struct mips16_immed_operand *op; 14366 bfd_boolean small, ext; 14367 offsetT val; 14368 bfd_byte *buf; 14369 unsigned long insn; 14370 bfd_boolean use_extend; 14371 unsigned short extend; 14372 14373 type = RELAX_MIPS16_TYPE (fragp->fr_subtype); 14374 op = mips16_immed_operands; 14375 while (op->type != type) 14376 ++op; 14377 14378 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 14379 { 14380 small = FALSE; 14381 ext = TRUE; 14382 } 14383 else 14384 { 14385 small = TRUE; 14386 ext = FALSE; 14387 } 14388 14389 resolve_symbol_value (fragp->fr_symbol); 14390 val = S_GET_VALUE (fragp->fr_symbol); 14391 if (op->pcrel) 14392 { 14393 addressT addr; 14394 14395 addr = fragp->fr_address + fragp->fr_fix; 14396 14397 /* The rules for the base address of a PC relative reloc are 14398 complicated; see mips16_extended_frag. */ 14399 if (type == 'p' || type == 'q') 14400 { 14401 addr += 2; 14402 if (ext) 14403 addr += 2; 14404 /* Ignore the low bit in the target, since it will be 14405 set for a text label. */ 14406 if ((val & 1) != 0) 14407 --val; 14408 } 14409 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) 14410 addr -= 4; 14411 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) 14412 addr -= 2; 14413 14414 addr &= ~ (addressT) ((1 << op->shift) - 1); 14415 val -= addr; 14416 14417 /* Make sure the section winds up with the alignment we have 14418 assumed. */ 14419 if (op->shift > 0) 14420 record_alignment (asec, op->shift); 14421 } 14422 14423 if (ext 14424 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) 14425 || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) 14426 as_warn_where (fragp->fr_file, fragp->fr_line, 14427 _("extended instruction in delay slot")); 14428 14429 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); 14430 14431 if (target_big_endian) 14432 insn = bfd_getb16 (buf); 14433 else 14434 insn = bfd_getl16 (buf); 14435 14436 mips16_immed (fragp->fr_file, fragp->fr_line, type, val, 14437 RELAX_MIPS16_USER_EXT (fragp->fr_subtype), 14438 small, ext, &insn, &use_extend, &extend); 14439 14440 if (use_extend) 14441 { 14442 md_number_to_chars ((char *) buf, 0xf000 | extend, 2); 14443 fragp->fr_fix += 2; 14444 buf += 2; 14445 } 14446 14447 md_number_to_chars ((char *) buf, insn, 2); 14448 fragp->fr_fix += 2; 14449 buf += 2; 14450 } 14451 else 14452 { 14453 int first, second; 14454 fixS *fixp; 14455 14456 first = RELAX_FIRST (fragp->fr_subtype); 14457 second = RELAX_SECOND (fragp->fr_subtype); 14458 fixp = (fixS *) fragp->fr_opcode; 14459 14460 /* Possibly emit a warning if we've chosen the longer option. */ 14461 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) 14462 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) 14463 { 14464 const char *msg = macro_warning (fragp->fr_subtype); 14465 if (msg != 0) 14466 as_warn_where (fragp->fr_file, fragp->fr_line, msg); 14467 } 14468 14469 /* Go through all the fixups for the first sequence. Disable them 14470 (by marking them as done) if we're going to use the second 14471 sequence instead. */ 14472 while (fixp 14473 && fixp->fx_frag == fragp 14474 && fixp->fx_where < fragp->fr_fix - second) 14475 { 14476 if (fragp->fr_subtype & RELAX_USE_SECOND) 14477 fixp->fx_done = 1; 14478 fixp = fixp->fx_next; 14479 } 14480 14481 /* Go through the fixups for the second sequence. Disable them if 14482 we're going to use the first sequence, otherwise adjust their 14483 addresses to account for the relaxation. */ 14484 while (fixp && fixp->fx_frag == fragp) 14485 { 14486 if (fragp->fr_subtype & RELAX_USE_SECOND) 14487 fixp->fx_where -= first; 14488 else 14489 fixp->fx_done = 1; 14490 fixp = fixp->fx_next; 14491 } 14492 14493 /* Now modify the frag contents. */ 14494 if (fragp->fr_subtype & RELAX_USE_SECOND) 14495 { 14496 char *start; 14497 14498 start = fragp->fr_literal + fragp->fr_fix - first - second; 14499 memmove (start, start + first, second); 14500 fragp->fr_fix -= first; 14501 } 14502 else 14503 fragp->fr_fix -= second; 14504 } 14505} 14506 14507#ifdef OBJ_ELF 14508 14509/* This function is called after the relocs have been generated. 14510 We've been storing mips16 text labels as odd. Here we convert them 14511 back to even for the convenience of the debugger. */ 14512 14513void 14514mips_frob_file_after_relocs (void) 14515{ 14516 asymbol **syms; 14517 unsigned int count, i; 14518 14519 if (!IS_ELF) 14520 return; 14521 14522 syms = bfd_get_outsymbols (stdoutput); 14523 count = bfd_get_symcount (stdoutput); 14524 for (i = 0; i < count; i++, syms++) 14525 { 14526 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 14527 && ((*syms)->value & 1) != 0) 14528 { 14529 (*syms)->value &= ~1; 14530 /* If the symbol has an odd size, it was probably computed 14531 incorrectly, so adjust that as well. */ 14532 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) 14533 ++elf_symbol (*syms)->internal_elf_sym.st_size; 14534 } 14535 } 14536} 14537 14538#endif 14539 14540/* This function is called whenever a label is defined. It is used 14541 when handling branch delays; if a branch has a label, we assume we 14542 can not move it. */ 14543 14544void 14545mips_define_label (symbolS *sym) 14546{ 14547 segment_info_type *si = seg_info (now_seg); 14548 struct insn_label_list *l; 14549 14550 if (free_insn_labels == NULL) 14551 l = (struct insn_label_list *) xmalloc (sizeof *l); 14552 else 14553 { 14554 l = free_insn_labels; 14555 free_insn_labels = l->next; 14556 } 14557 14558 l->label = sym; 14559 l->next = si->label_list; 14560 si->label_list = l; 14561 14562#ifdef OBJ_ELF 14563 dwarf2_emit_label (sym); 14564#endif 14565} 14566 14567#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 14568 14569/* Some special processing for a MIPS ELF file. */ 14570 14571void 14572mips_elf_final_processing (void) 14573{ 14574 /* Write out the register information. */ 14575 if (mips_abi != N64_ABI) 14576 { 14577 Elf32_RegInfo s; 14578 14579 s.ri_gprmask = mips_gprmask; 14580 s.ri_cprmask[0] = mips_cprmask[0]; 14581 s.ri_cprmask[1] = mips_cprmask[1]; 14582 s.ri_cprmask[2] = mips_cprmask[2]; 14583 s.ri_cprmask[3] = mips_cprmask[3]; 14584 /* The gp_value field is set by the MIPS ELF backend. */ 14585 14586 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, 14587 ((Elf32_External_RegInfo *) 14588 mips_regmask_frag)); 14589 } 14590 else 14591 { 14592 Elf64_Internal_RegInfo s; 14593 14594 s.ri_gprmask = mips_gprmask; 14595 s.ri_pad = 0; 14596 s.ri_cprmask[0] = mips_cprmask[0]; 14597 s.ri_cprmask[1] = mips_cprmask[1]; 14598 s.ri_cprmask[2] = mips_cprmask[2]; 14599 s.ri_cprmask[3] = mips_cprmask[3]; 14600 /* The gp_value field is set by the MIPS ELF backend. */ 14601 14602 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, 14603 ((Elf64_External_RegInfo *) 14604 mips_regmask_frag)); 14605 } 14606 14607 /* Set the MIPS ELF flag bits. FIXME: There should probably be some 14608 sort of BFD interface for this. */ 14609 if (mips_any_noreorder) 14610 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; 14611 if (mips_pic != NO_PIC) 14612 { 14613 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; 14614 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; 14615 } 14616 if (mips_abicalls) 14617 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; 14618 14619 /* Set MIPS ELF flags for ASEs. */ 14620 /* We may need to define a new flag for DSP ASE, and set this flag when 14621 file_ase_dsp is true. */ 14622 /* Same for DSP R2. */ 14623 /* We may need to define a new flag for MT ASE, and set this flag when 14624 file_ase_mt is true. */ 14625 if (file_ase_mips16) 14626 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; 14627#if 0 /* XXX FIXME */ 14628 if (file_ase_mips3d) 14629 elf_elfheader (stdoutput)->e_flags |= ???; 14630#endif 14631 if (file_ase_mdmx) 14632 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; 14633 14634 /* Set the MIPS ELF ABI flags. */ 14635 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) 14636 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; 14637 else if (mips_abi == O64_ABI) 14638 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; 14639 else if (mips_abi == EABI_ABI) 14640 { 14641 if (!file_mips_gp32) 14642 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; 14643 else 14644 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; 14645 } 14646 else if (mips_abi == N32_ABI) 14647 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; 14648 14649 /* Nothing to do for N64_ABI. */ 14650 14651 if (mips_32bitmode) 14652 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; 14653 14654#if 0 /* XXX FIXME */ 14655 /* 32 bit code with 64 bit FP registers. */ 14656 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) 14657 elf_elfheader (stdoutput)->e_flags |= ???; 14658#endif 14659} 14660 14661#endif /* OBJ_ELF || OBJ_MAYBE_ELF */ 14662 14663typedef struct proc { 14664 symbolS *func_sym; 14665 symbolS *func_end_sym; 14666 unsigned long reg_mask; 14667 unsigned long reg_offset; 14668 unsigned long fpreg_mask; 14669 unsigned long fpreg_offset; 14670 unsigned long frame_offset; 14671 unsigned long frame_reg; 14672 unsigned long pc_reg; 14673} procS; 14674 14675static procS cur_proc; 14676static procS *cur_proc_ptr; 14677static int numprocs; 14678 14679/* Fill in an rs_align_code fragment. */ 14680 14681void 14682mips_handle_align (fragS *fragp) 14683{ 14684 if (fragp->fr_type != rs_align_code) 14685 return; 14686 14687 if (mips_opts.mips16) 14688 { 14689 static const unsigned char be_nop[] = { 0x65, 0x00 }; 14690 static const unsigned char le_nop[] = { 0x00, 0x65 }; 14691 14692 int bytes; 14693 char *p; 14694 14695 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 14696 p = fragp->fr_literal + fragp->fr_fix; 14697 14698 if (bytes & 1) 14699 { 14700 *p++ = 0; 14701 fragp->fr_fix++; 14702 } 14703 14704 memcpy (p, (target_big_endian ? be_nop : le_nop), 2); 14705 fragp->fr_var = 2; 14706 } 14707 14708 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ 14709} 14710 14711static void 14712md_obj_begin (void) 14713{ 14714} 14715 14716static void 14717md_obj_end (void) 14718{ 14719 /* Check for premature end, nesting errors, etc. */ 14720 if (cur_proc_ptr) 14721 as_warn (_("missing .end at end of assembly")); 14722} 14723 14724static long 14725get_number (void) 14726{ 14727 int negative = 0; 14728 long val = 0; 14729 14730 if (*input_line_pointer == '-') 14731 { 14732 ++input_line_pointer; 14733 negative = 1; 14734 } 14735 if (!ISDIGIT (*input_line_pointer)) 14736 as_bad (_("expected simple number")); 14737 if (input_line_pointer[0] == '0') 14738 { 14739 if (input_line_pointer[1] == 'x') 14740 { 14741 input_line_pointer += 2; 14742 while (ISXDIGIT (*input_line_pointer)) 14743 { 14744 val <<= 4; 14745 val |= hex_value (*input_line_pointer++); 14746 } 14747 return negative ? -val : val; 14748 } 14749 else 14750 { 14751 ++input_line_pointer; 14752 while (ISDIGIT (*input_line_pointer)) 14753 { 14754 val <<= 3; 14755 val |= *input_line_pointer++ - '0'; 14756 } 14757 return negative ? -val : val; 14758 } 14759 } 14760 if (!ISDIGIT (*input_line_pointer)) 14761 { 14762 printf (_(" *input_line_pointer == '%c' 0x%02x\n"), 14763 *input_line_pointer, *input_line_pointer); 14764 as_warn (_("invalid number")); 14765 return -1; 14766 } 14767 while (ISDIGIT (*input_line_pointer)) 14768 { 14769 val *= 10; 14770 val += *input_line_pointer++ - '0'; 14771 } 14772 return negative ? -val : val; 14773} 14774 14775/* The .file directive; just like the usual .file directive, but there 14776 is an initial number which is the ECOFF file index. In the non-ECOFF 14777 case .file implies DWARF-2. */ 14778 14779static void 14780s_mips_file (int x ATTRIBUTE_UNUSED) 14781{ 14782 static int first_file_directive = 0; 14783 14784 if (ECOFF_DEBUGGING) 14785 { 14786 get_number (); 14787 s_app_file (0); 14788 } 14789 else 14790 { 14791 char *filename; 14792 14793 filename = dwarf2_directive_file (0); 14794 14795 /* Versions of GCC up to 3.1 start files with a ".file" 14796 directive even for stabs output. Make sure that this 14797 ".file" is handled. Note that you need a version of GCC 14798 after 3.1 in order to support DWARF-2 on MIPS. */ 14799 if (filename != NULL && ! first_file_directive) 14800 { 14801 (void) new_logical_line (filename, -1); 14802 s_app_file_string (filename, 0); 14803 } 14804 first_file_directive = 1; 14805 } 14806} 14807 14808/* The .loc directive, implying DWARF-2. */ 14809 14810static void 14811s_mips_loc (int x ATTRIBUTE_UNUSED) 14812{ 14813 if (!ECOFF_DEBUGGING) 14814 dwarf2_directive_loc (0); 14815} 14816 14817/* The .end directive. */ 14818 14819static void 14820s_mips_end (int x ATTRIBUTE_UNUSED) 14821{ 14822 symbolS *p; 14823 14824 /* Following functions need their own .frame and .cprestore directives. */ 14825 mips_frame_reg_valid = 0; 14826 mips_cprestore_valid = 0; 14827 14828 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 14829 { 14830 p = get_symbol (); 14831 demand_empty_rest_of_line (); 14832 } 14833 else 14834 p = NULL; 14835 14836 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) 14837 as_warn (_(".end not in text section")); 14838 14839 if (!cur_proc_ptr) 14840 { 14841 as_warn (_(".end directive without a preceding .ent directive.")); 14842 demand_empty_rest_of_line (); 14843 return; 14844 } 14845 14846 if (p != NULL) 14847 { 14848 assert (S_GET_NAME (p)); 14849 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) 14850 as_warn (_(".end symbol does not match .ent symbol.")); 14851 14852 if (debug_type == DEBUG_STABS) 14853 stabs_generate_asm_endfunc (S_GET_NAME (p), 14854 S_GET_NAME (p)); 14855 } 14856 else 14857 as_warn (_(".end directive missing or unknown symbol")); 14858 14859#ifdef OBJ_ELF 14860 /* Create an expression to calculate the size of the function. */ 14861 if (p && cur_proc_ptr) 14862 { 14863 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); 14864 expressionS *exp = xmalloc (sizeof (expressionS)); 14865 14866 obj->size = exp; 14867 exp->X_op = O_subtract; 14868 exp->X_add_symbol = symbol_temp_new_now (); 14869 exp->X_op_symbol = p; 14870 exp->X_add_number = 0; 14871 14872 cur_proc_ptr->func_end_sym = exp->X_add_symbol; 14873 } 14874 14875 /* Generate a .pdr section. */ 14876 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) 14877 { 14878 segT saved_seg = now_seg; 14879 subsegT saved_subseg = now_subseg; 14880 valueT dot; 14881 expressionS exp; 14882 char *fragp; 14883 14884 dot = frag_now_fix (); 14885 14886#ifdef md_flush_pending_output 14887 md_flush_pending_output (); 14888#endif 14889 14890 assert (pdr_seg); 14891 subseg_set (pdr_seg, 0); 14892 14893 /* Write the symbol. */ 14894 exp.X_op = O_symbol; 14895 exp.X_add_symbol = p; 14896 exp.X_add_number = 0; 14897 emit_expr (&exp, 4); 14898 14899 fragp = frag_more (7 * 4); 14900 14901 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); 14902 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); 14903 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); 14904 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); 14905 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); 14906 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); 14907 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); 14908 14909 subseg_set (saved_seg, saved_subseg); 14910 } 14911#endif /* OBJ_ELF */ 14912 14913 cur_proc_ptr = NULL; 14914} 14915 14916/* The .aent and .ent directives. */ 14917 14918static void 14919s_mips_ent (int aent) 14920{ 14921 symbolS *symbolP; 14922 14923 symbolP = get_symbol (); 14924 if (*input_line_pointer == ',') 14925 ++input_line_pointer; 14926 SKIP_WHITESPACE (); 14927 if (ISDIGIT (*input_line_pointer) 14928 || *input_line_pointer == '-') 14929 get_number (); 14930 14931 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) 14932 as_warn (_(".ent or .aent not in text section.")); 14933 14934 if (!aent && cur_proc_ptr) 14935 as_warn (_("missing .end")); 14936 14937 if (!aent) 14938 { 14939 /* This function needs its own .frame and .cprestore directives. */ 14940 mips_frame_reg_valid = 0; 14941 mips_cprestore_valid = 0; 14942 14943 cur_proc_ptr = &cur_proc; 14944 memset (cur_proc_ptr, '\0', sizeof (procS)); 14945 14946 cur_proc_ptr->func_sym = symbolP; 14947 14948 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; 14949 14950 ++numprocs; 14951 14952 if (debug_type == DEBUG_STABS) 14953 stabs_generate_asm_func (S_GET_NAME (symbolP), 14954 S_GET_NAME (symbolP)); 14955 } 14956 14957 demand_empty_rest_of_line (); 14958} 14959 14960/* The .frame directive. If the mdebug section is present (IRIX 5 native) 14961 then ecoff.c (ecoff_directive_frame) is used. For embedded targets, 14962 s_mips_frame is used so that we can set the PDR information correctly. 14963 We can't use the ecoff routines because they make reference to the ecoff 14964 symbol table (in the mdebug section). */ 14965 14966static void 14967s_mips_frame (int ignore ATTRIBUTE_UNUSED) 14968{ 14969#ifdef OBJ_ELF 14970 if (IS_ELF && !ECOFF_DEBUGGING) 14971 { 14972 long val; 14973 14974 if (cur_proc_ptr == (procS *) NULL) 14975 { 14976 as_warn (_(".frame outside of .ent")); 14977 demand_empty_rest_of_line (); 14978 return; 14979 } 14980 14981 cur_proc_ptr->frame_reg = tc_get_register (1); 14982 14983 SKIP_WHITESPACE (); 14984 if (*input_line_pointer++ != ',' 14985 || get_absolute_expression_and_terminator (&val) != ',') 14986 { 14987 as_warn (_("Bad .frame directive")); 14988 --input_line_pointer; 14989 demand_empty_rest_of_line (); 14990 return; 14991 } 14992 14993 cur_proc_ptr->frame_offset = val; 14994 cur_proc_ptr->pc_reg = tc_get_register (0); 14995 14996 demand_empty_rest_of_line (); 14997 } 14998 else 14999#endif /* OBJ_ELF */ 15000 s_ignore (ignore); 15001} 15002 15003/* The .fmask and .mask directives. If the mdebug section is present 15004 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For 15005 embedded targets, s_mips_mask is used so that we can set the PDR 15006 information correctly. We can't use the ecoff routines because they 15007 make reference to the ecoff symbol table (in the mdebug section). */ 15008 15009static void 15010s_mips_mask (int reg_type) 15011{ 15012#ifdef OBJ_ELF 15013 if (IS_ELF && !ECOFF_DEBUGGING) 15014 { 15015 long mask, off; 15016 15017 if (cur_proc_ptr == (procS *) NULL) 15018 { 15019 as_warn (_(".mask/.fmask outside of .ent")); 15020 demand_empty_rest_of_line (); 15021 return; 15022 } 15023 15024 if (get_absolute_expression_and_terminator (&mask) != ',') 15025 { 15026 as_warn (_("Bad .mask/.fmask directive")); 15027 --input_line_pointer; 15028 demand_empty_rest_of_line (); 15029 return; 15030 } 15031 15032 off = get_absolute_expression (); 15033 15034 if (reg_type == 'F') 15035 { 15036 cur_proc_ptr->fpreg_mask = mask; 15037 cur_proc_ptr->fpreg_offset = off; 15038 } 15039 else 15040 { 15041 cur_proc_ptr->reg_mask = mask; 15042 cur_proc_ptr->reg_offset = off; 15043 } 15044 15045 demand_empty_rest_of_line (); 15046 } 15047 else 15048#endif /* OBJ_ELF */ 15049 s_ignore (reg_type); 15050} 15051 15052/* A table describing all the processors gas knows about. Names are 15053 matched in the order listed. 15054 15055 To ease comparison, please keep this table in the same order as 15056 gcc's mips_cpu_info_table[]. */ 15057static const struct mips_cpu_info mips_cpu_info_table[] = 15058{ 15059 /* Entries for generic ISAs */ 15060 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, 15061 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, 15062 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, 15063 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, 15064 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, 15065 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, 15066 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, 15067 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, 15068 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, 15069 15070 /* MIPS I */ 15071 { "r3000", 0, ISA_MIPS1, CPU_R3000 }, 15072 { "r2000", 0, ISA_MIPS1, CPU_R3000 }, 15073 { "r3900", 0, ISA_MIPS1, CPU_R3900 }, 15074 15075 /* MIPS II */ 15076 { "r6000", 0, ISA_MIPS2, CPU_R6000 }, 15077 15078 /* MIPS III */ 15079 { "r4000", 0, ISA_MIPS3, CPU_R4000 }, 15080 { "r4010", 0, ISA_MIPS2, CPU_R4010 }, 15081 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, 15082 { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, 15083 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, 15084 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, 15085 { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, 15086 { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, 15087 { "r4400", 0, ISA_MIPS3, CPU_R4400 }, 15088 { "r4600", 0, ISA_MIPS3, CPU_R4600 }, 15089 { "orion", 0, ISA_MIPS3, CPU_R4600 }, 15090 { "r4650", 0, ISA_MIPS3, CPU_R4650 }, 15091 15092 /* MIPS IV */ 15093 { "r8000", 0, ISA_MIPS4, CPU_R8000 }, 15094 { "r10000", 0, ISA_MIPS4, CPU_R10000 }, 15095 { "r12000", 0, ISA_MIPS4, CPU_R12000 }, 15096 { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, 15097 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, 15098 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, 15099 { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, 15100 { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, 15101 { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, 15102 { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, 15103 { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, 15104 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, 15105 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, 15106 15107 /* MIPS 32 */ 15108 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, 15109 { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, 15110 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, 15111 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, 15112 15113 /* MIPS 32 Release 2 */ 15114 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 15115 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 15116 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 15117 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, 15118 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 15119 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 15120 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 15121 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 15122 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 15123 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ 15124 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 15125 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 15126 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 15127 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ 15128 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, 15129 ISA_MIPS32R2, CPU_MIPS32R2 }, 15130 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, 15131 ISA_MIPS32R2, CPU_MIPS32R2 }, 15132 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, 15133 ISA_MIPS32R2, CPU_MIPS32R2 }, 15134 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ 15135 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, 15136 ISA_MIPS32R2, CPU_MIPS32R2 }, 15137 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, 15138 ISA_MIPS32R2, CPU_MIPS32R2 }, 15139 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, 15140 ISA_MIPS32R2, CPU_MIPS32R2 }, 15141 15142 /* MIPS 64 */ 15143 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, 15144 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, 15145 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, 15146 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, 15147 15148 /* MIPS 64 Release 2 */ 15149 15150 /* Broadcom SB-1 CPU core */ 15151 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, 15152 ISA_MIPS64, CPU_SB1 }, 15153 /* Broadcom SB-1A CPU core */ 15154 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, 15155 ISA_MIPS64, CPU_SB1 }, 15156 15157 /* Cavium Networks Octeon CPU core */ 15158 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, 15159 15160 /* End marker */ 15161 { NULL, 0, 0, 0 } 15162}; 15163 15164 15165/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL 15166 with a final "000" replaced by "k". Ignore case. 15167 15168 Note: this function is shared between GCC and GAS. */ 15169 15170static bfd_boolean 15171mips_strict_matching_cpu_name_p (const char *canonical, const char *given) 15172{ 15173 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) 15174 given++, canonical++; 15175 15176 return ((*given == 0 && *canonical == 0) 15177 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); 15178} 15179 15180 15181/* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied 15182 CPU name. We've traditionally allowed a lot of variation here. 15183 15184 Note: this function is shared between GCC and GAS. */ 15185 15186static bfd_boolean 15187mips_matching_cpu_name_p (const char *canonical, const char *given) 15188{ 15189 /* First see if the name matches exactly, or with a final "000" 15190 turned into "k". */ 15191 if (mips_strict_matching_cpu_name_p (canonical, given)) 15192 return TRUE; 15193 15194 /* If not, try comparing based on numerical designation alone. 15195 See if GIVEN is an unadorned number, or 'r' followed by a number. */ 15196 if (TOLOWER (*given) == 'r') 15197 given++; 15198 if (!ISDIGIT (*given)) 15199 return FALSE; 15200 15201 /* Skip over some well-known prefixes in the canonical name, 15202 hoping to find a number there too. */ 15203 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') 15204 canonical += 2; 15205 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') 15206 canonical += 2; 15207 else if (TOLOWER (canonical[0]) == 'r') 15208 canonical += 1; 15209 15210 return mips_strict_matching_cpu_name_p (canonical, given); 15211} 15212 15213 15214/* Parse an option that takes the name of a processor as its argument. 15215 OPTION is the name of the option and CPU_STRING is the argument. 15216 Return the corresponding processor enumeration if the CPU_STRING is 15217 recognized, otherwise report an error and return null. 15218 15219 A similar function exists in GCC. */ 15220 15221static const struct mips_cpu_info * 15222mips_parse_cpu (const char *option, const char *cpu_string) 15223{ 15224 const struct mips_cpu_info *p; 15225 15226 /* 'from-abi' selects the most compatible architecture for the given 15227 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the 15228 EABIs, we have to decide whether we're using the 32-bit or 64-bit 15229 version. Look first at the -mgp options, if given, otherwise base 15230 the choice on MIPS_DEFAULT_64BIT. 15231 15232 Treat NO_ABI like the EABIs. One reason to do this is that the 15233 plain 'mips' and 'mips64' configs have 'from-abi' as their default 15234 architecture. This code picks MIPS I for 'mips' and MIPS III for 15235 'mips64', just as we did in the days before 'from-abi'. */ 15236 if (strcasecmp (cpu_string, "from-abi") == 0) 15237 { 15238 if (ABI_NEEDS_32BIT_REGS (mips_abi)) 15239 return mips_cpu_info_from_isa (ISA_MIPS1); 15240 15241 if (ABI_NEEDS_64BIT_REGS (mips_abi)) 15242 return mips_cpu_info_from_isa (ISA_MIPS3); 15243 15244 if (file_mips_gp32 >= 0) 15245 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); 15246 15247 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT 15248 ? ISA_MIPS3 15249 : ISA_MIPS1); 15250 } 15251 15252 /* 'default' has traditionally been a no-op. Probably not very useful. */ 15253 if (strcasecmp (cpu_string, "default") == 0) 15254 return 0; 15255 15256 for (p = mips_cpu_info_table; p->name != 0; p++) 15257 if (mips_matching_cpu_name_p (p->name, cpu_string)) 15258 return p; 15259 15260 as_bad ("Bad value (%s) for %s", cpu_string, option); 15261 return 0; 15262} 15263 15264/* Return the canonical processor information for ISA (a member of the 15265 ISA_MIPS* enumeration). */ 15266 15267static const struct mips_cpu_info * 15268mips_cpu_info_from_isa (int isa) 15269{ 15270 int i; 15271 15272 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 15273 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) 15274 && isa == mips_cpu_info_table[i].isa) 15275 return (&mips_cpu_info_table[i]); 15276 15277 return NULL; 15278} 15279 15280static const struct mips_cpu_info * 15281mips_cpu_info_from_arch (int arch) 15282{ 15283 int i; 15284 15285 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 15286 if (arch == mips_cpu_info_table[i].cpu) 15287 return (&mips_cpu_info_table[i]); 15288 15289 return NULL; 15290} 15291 15292static void 15293show (FILE *stream, const char *string, int *col_p, int *first_p) 15294{ 15295 if (*first_p) 15296 { 15297 fprintf (stream, "%24s", ""); 15298 *col_p = 24; 15299 } 15300 else 15301 { 15302 fprintf (stream, ", "); 15303 *col_p += 2; 15304 } 15305 15306 if (*col_p + strlen (string) > 72) 15307 { 15308 fprintf (stream, "\n%24s", ""); 15309 *col_p = 24; 15310 } 15311 15312 fprintf (stream, "%s", string); 15313 *col_p += strlen (string); 15314 15315 *first_p = 0; 15316} 15317 15318void 15319md_show_usage (FILE *stream) 15320{ 15321 int column, first; 15322 size_t i; 15323 15324 fprintf (stream, _("\ 15325MIPS options:\n\ 15326-EB generate big endian output\n\ 15327-EL generate little endian output\n\ 15328-g, -g2 do not remove unneeded NOPs or swap branches\n\ 15329-G NUM allow referencing objects up to NUM bytes\n\ 15330 implicitly with the gp register [default 8]\n")); 15331 fprintf (stream, _("\ 15332-mips1 generate MIPS ISA I instructions\n\ 15333-mips2 generate MIPS ISA II instructions\n\ 15334-mips3 generate MIPS ISA III instructions\n\ 15335-mips4 generate MIPS ISA IV instructions\n\ 15336-mips5 generate MIPS ISA V instructions\n\ 15337-mips32 generate MIPS32 ISA instructions\n\ 15338-mips32r2 generate MIPS32 release 2 ISA instructions\n\ 15339-mips64 generate MIPS64 ISA instructions\n\ 15340-mips64r2 generate MIPS64 release 2 ISA instructions\n\ 15341-march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); 15342 15343 first = 1; 15344 15345 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 15346 show (stream, mips_cpu_info_table[i].name, &column, &first); 15347 show (stream, "from-abi", &column, &first); 15348 fputc ('\n', stream); 15349 15350 fprintf (stream, _("\ 15351-mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ 15352-no-mCPU don't generate code specific to CPU.\n\ 15353 For -mCPU and -no-mCPU, CPU must be one of:\n")); 15354 15355 first = 1; 15356 15357 show (stream, "3900", &column, &first); 15358 show (stream, "4010", &column, &first); 15359 show (stream, "4100", &column, &first); 15360 show (stream, "4650", &column, &first); 15361 fputc ('\n', stream); 15362 15363 fprintf (stream, _("\ 15364-mips16 generate mips16 instructions\n\ 15365-no-mips16 do not generate mips16 instructions\n")); 15366 fprintf (stream, _("\ 15367-msmartmips generate smartmips instructions\n\ 15368-mno-smartmips do not generate smartmips instructions\n")); 15369 fprintf (stream, _("\ 15370-mdsp generate DSP instructions\n\ 15371-mno-dsp do not generate DSP instructions\n")); 15372 fprintf (stream, _("\ 15373-mdspr2 generate DSP R2 instructions\n\ 15374-mno-dspr2 do not generate DSP R2 instructions\n")); 15375 fprintf (stream, _("\ 15376-mmt generate MT instructions\n\ 15377-mno-mt do not generate MT instructions\n")); 15378 fprintf (stream, _("\ 15379-mfix-vr4120 work around certain VR4120 errata\n\ 15380-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ 15381-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ 15382-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ 15383-msym32 assume all symbols have 32-bit values\n\ 15384-O0 remove unneeded NOPs, do not swap branches\n\ 15385-O remove unneeded NOPs and swap branches\n\ 15386--[no-]construct-floats [dis]allow floating point values to be constructed\n\ 15387--trap, --no-break trap exception on div by 0 and mult overflow\n\ 15388--break, --no-trap break exception on div by 0 and mult overflow\n")); 15389#ifdef OBJ_ELF 15390 fprintf (stream, _("\ 15391-KPIC, -call_shared generate SVR4 position independent code\n\ 15392-mvxworks-pic generate VxWorks position independent code\n\ 15393-non_shared do not generate position independent code\n\ 15394-xgot assume a 32 bit GOT\n\ 15395-mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ 15396-mshared, -mno-shared disable/enable .cpload optimization for\n\ 15397 position dependent (non shared) code\n\ 15398-mabi=ABI create ABI conformant object file for:\n")); 15399 15400 first = 1; 15401 15402 show (stream, "32", &column, &first); 15403 show (stream, "o64", &column, &first); 15404 show (stream, "n32", &column, &first); 15405 show (stream, "64", &column, &first); 15406 show (stream, "eabi", &column, &first); 15407 15408 fputc ('\n', stream); 15409 15410 fprintf (stream, _("\ 15411-32 create o32 ABI object file (default)\n\ 15412-n32 create n32 ABI object file\n\ 15413-64 create 64 ABI object file\n")); 15414#endif 15415 fprintf (stream, _("\ 15416-mocteon-unsupported error on unsupported Octeon instructions\n\ 15417-mno-octeon-unsupported do not error on unsupported Octeon instructions\n")); 15418 fprintf (stream, _("\ 15419-mocteon-useun generate Octeon unaligned load/store instructions\n\ 15420-mno-octeon-useun generate MIPS unaligned load/store instructions\n")); 15421} 15422 15423int 15424mips_dwarf2_addr_size (void) 15425{ 15426 if (HAVE_64BIT_SYMBOLS) 15427 return 8; 15428 else 15429 return 4; 15430} 15431 15432/* Standard calling conventions leave the CFA at SP on entry. */ 15433void 15434mips_cfi_frame_initial_instructions (void) 15435{ 15436 cfi_add_CFA_def_cfa_register (SP); 15437} 15438 15439int 15440tc_mips_regname_to_dw2regnum (char *regname) 15441{ 15442 unsigned int regnum = -1; 15443 unsigned int reg; 15444 15445 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) 15446 regnum = reg; 15447 15448 return regnum; 15449} 15450