tc-i386.c revision 261307
1/* tc-i386.c -- Assemble code for the Intel 80386 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 4 Free Software Foundation, Inc. 5 6 This file is part of GAS, the GNU Assembler. 7 8 GAS is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2, or (at your option) 11 any later version. 12 13 GAS is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GAS; see the file COPYING. If not, write to the Free 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 21 02110-1301, USA. */ 22 23/* Intel 80386 machine specific gas. 24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu). 25 x86_64 support by Jan Hubicka (jh@suse.cz) 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz) 27 Bugs & suggestions are completely welcome. This is free software. 28 Please help us make it better. */ 29 30#include "as.h" 31#include "safe-ctype.h" 32#include "subsegs.h" 33#include "dwarf2dbg.h" 34#include "dw2gencfi.h" 35#include "elf/x86-64.h" 36 37#ifndef REGISTER_WARNINGS 38#define REGISTER_WARNINGS 1 39#endif 40 41#ifndef INFER_ADDR_PREFIX 42#define INFER_ADDR_PREFIX 1 43#endif 44 45#ifndef SCALE1_WHEN_NO_INDEX 46/* Specifying a scale factor besides 1 when there is no index is 47 futile. eg. `mov (%ebx,2),%al' does exactly the same as 48 `mov (%ebx),%al'. To slavishly follow what the programmer 49 specified, set SCALE1_WHEN_NO_INDEX to 0. */ 50#define SCALE1_WHEN_NO_INDEX 1 51#endif 52 53#ifndef DEFAULT_ARCH 54#define DEFAULT_ARCH "i386" 55#endif 56 57#ifndef INLINE 58#if __GNUC__ >= 2 59#define INLINE __inline__ 60#else 61#define INLINE 62#endif 63#endif 64 65static void set_code_flag (int); 66static void set_16bit_gcc_code_flag (int); 67static void set_intel_syntax (int); 68static void set_cpu_arch (int); 69#ifdef TE_PE 70static void pe_directive_secrel (int); 71#endif 72static void signed_cons (int); 73static char *output_invalid (int c); 74static int i386_operand (char *); 75static int i386_intel_operand (char *, int); 76static const reg_entry *parse_register (char *, char **); 77static char *parse_insn (char *, char *); 78static char *parse_operands (char *, const char *); 79static void swap_operands (void); 80static void swap_2_operands (int, int); 81static void optimize_imm (void); 82static void optimize_disp (void); 83static int match_template (void); 84static int check_string (void); 85static int process_suffix (void); 86static int check_byte_reg (void); 87static int check_long_reg (void); 88static int check_qword_reg (void); 89static int check_word_reg (void); 90static int finalize_imm (void); 91static int process_operands (void); 92static const seg_entry *build_modrm_byte (void); 93static void output_insn (void); 94static void output_imm (fragS *, offsetT); 95static void output_disp (fragS *, offsetT); 96#ifndef I386COFF 97static void s_bss (int); 98#endif 99#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 100static void handle_large_common (int small ATTRIBUTE_UNUSED); 101#endif 102 103static const char *default_arch = DEFAULT_ARCH; 104 105/* 'md_assemble ()' gathers together information and puts it into a 106 i386_insn. */ 107 108union i386_op 109 { 110 expressionS *disps; 111 expressionS *imms; 112 const reg_entry *regs; 113 }; 114 115struct _i386_insn 116 { 117 /* TM holds the template for the insn were currently assembling. */ 118 template tm; 119 120 /* SUFFIX holds the instruction mnemonic suffix if given. 121 (e.g. 'l' for 'movl') */ 122 char suffix; 123 124 /* OPERANDS gives the number of given operands. */ 125 unsigned int operands; 126 127 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number 128 of given register, displacement, memory operands and immediate 129 operands. */ 130 unsigned int reg_operands, disp_operands, mem_operands, imm_operands; 131 132 /* TYPES [i] is the type (see above #defines) which tells us how to 133 use OP[i] for the corresponding operand. */ 134 unsigned int types[MAX_OPERANDS]; 135 136 /* Displacement expression, immediate expression, or register for each 137 operand. */ 138 union i386_op op[MAX_OPERANDS]; 139 140 /* Flags for operands. */ 141 unsigned int flags[MAX_OPERANDS]; 142#define Operand_PCrel 1 143 144 /* Relocation type for operand */ 145 enum bfd_reloc_code_real reloc[MAX_OPERANDS]; 146 147 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode 148 the base index byte below. */ 149 const reg_entry *base_reg; 150 const reg_entry *index_reg; 151 unsigned int log2_scale_factor; 152 153 /* SEG gives the seg_entries of this insn. They are zero unless 154 explicit segment overrides are given. */ 155 const seg_entry *seg[2]; 156 157 /* PREFIX holds all the given prefix opcodes (usually null). 158 PREFIXES is the number of prefix opcodes. */ 159 unsigned int prefixes; 160 unsigned char prefix[MAX_PREFIXES]; 161 162 /* RM and SIB are the modrm byte and the sib byte where the 163 addressing modes of this insn are encoded. */ 164 165 modrm_byte rm; 166 rex_byte rex; 167 sib_byte sib; 168 }; 169 170typedef struct _i386_insn i386_insn; 171 172/* List of chars besides those in app.c:symbol_chars that can start an 173 operand. Used to prevent the scrubber eating vital white-space. */ 174const char extra_symbol_chars[] = "*%-([" 175#ifdef LEX_AT 176 "@" 177#endif 178#ifdef LEX_QM 179 "?" 180#endif 181 ; 182 183#if (defined (TE_I386AIX) \ 184 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ 185 && !defined (TE_GNU) \ 186 && !defined (TE_LINUX) \ 187 && !defined (TE_NETWARE) \ 188 && !defined (TE_FreeBSD) \ 189 && !defined (TE_NetBSD))) 190/* This array holds the chars that always start a comment. If the 191 pre-processor is disabled, these aren't very useful. The option 192 --divide will remove '/' from this list. */ 193const char *i386_comment_chars = "#/"; 194#define SVR4_COMMENT_CHARS 1 195#define PREFIX_SEPARATOR '\\' 196 197#else 198const char *i386_comment_chars = "#"; 199#define PREFIX_SEPARATOR '/' 200#endif 201 202/* This array holds the chars that only start a comment at the beginning of 203 a line. If the line seems to have the form '# 123 filename' 204 .line and .file directives will appear in the pre-processed output. 205 Note that input_file.c hand checks for '#' at the beginning of the 206 first line of the input file. This is because the compiler outputs 207 #NO_APP at the beginning of its output. 208 Also note that comments started like this one will always work if 209 '/' isn't otherwise defined. */ 210const char line_comment_chars[] = "#/"; 211 212const char line_separator_chars[] = ";"; 213 214/* Chars that can be used to separate mant from exp in floating point 215 nums. */ 216const char EXP_CHARS[] = "eE"; 217 218/* Chars that mean this number is a floating point constant 219 As in 0f12.456 220 or 0d1.2345e12. */ 221const char FLT_CHARS[] = "fFdDxX"; 222 223/* Tables for lexical analysis. */ 224static char mnemonic_chars[256]; 225static char register_chars[256]; 226static char operand_chars[256]; 227static char identifier_chars[256]; 228static char digit_chars[256]; 229 230/* Lexical macros. */ 231#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) 232#define is_operand_char(x) (operand_chars[(unsigned char) x]) 233#define is_register_char(x) (register_chars[(unsigned char) x]) 234#define is_space_char(x) ((x) == ' ') 235#define is_identifier_char(x) (identifier_chars[(unsigned char) x]) 236#define is_digit_char(x) (digit_chars[(unsigned char) x]) 237 238/* All non-digit non-letter characters that may occur in an operand. */ 239static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; 240 241/* md_assemble() always leaves the strings it's passed unaltered. To 242 effect this we maintain a stack of saved characters that we've smashed 243 with '\0's (indicating end of strings for various sub-fields of the 244 assembler instruction). */ 245static char save_stack[32]; 246static char *save_stack_p; 247#define END_STRING_AND_SAVE(s) \ 248 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) 249#define RESTORE_END_STRING(s) \ 250 do { *(s) = *--save_stack_p; } while (0) 251 252/* The instruction we're assembling. */ 253static i386_insn i; 254 255/* Possible templates for current insn. */ 256static const templates *current_templates; 257 258/* Per instruction expressionS buffers: max displacements & immediates. */ 259static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; 260static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; 261 262/* Current operand we are working on. */ 263static int this_operand; 264 265/* We support four different modes. FLAG_CODE variable is used to distinguish 266 these. */ 267 268enum flag_code { 269 CODE_32BIT, 270 CODE_16BIT, 271 CODE_64BIT }; 272#define NUM_FLAG_CODE ((int) CODE_64BIT + 1) 273 274static enum flag_code flag_code; 275static unsigned int object_64bit; 276static int use_rela_relocations = 0; 277 278/* The names used to print error messages. */ 279static const char *flag_code_names[] = 280 { 281 "32", 282 "16", 283 "64" 284 }; 285 286/* 1 for intel syntax, 287 0 if att syntax. */ 288static int intel_syntax = 0; 289 290/* 1 if register prefix % not required. */ 291static int allow_naked_reg = 0; 292 293/* Register prefix used for error message. */ 294static const char *register_prefix = "%"; 295 296/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, 297 leave, push, and pop instructions so that gcc has the same stack 298 frame as in 32 bit mode. */ 299static char stackop_size = '\0'; 300 301/* Non-zero to optimize code alignment. */ 302int optimize_align_code = 1; 303 304/* Non-zero to quieten some warnings. */ 305static int quiet_warnings = 0; 306 307/* CPU name. */ 308static const char *cpu_arch_name = NULL; 309static const char *cpu_sub_arch_name = NULL; 310 311/* CPU feature flags. */ 312static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64; 313 314/* If we have selected a cpu we are generating instructions for. */ 315static int cpu_arch_tune_set = 0; 316 317/* Cpu we are generating instructions for. */ 318static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; 319 320/* CPU feature flags of cpu we are generating instructions for. */ 321static unsigned int cpu_arch_tune_flags = 0; 322 323/* CPU instruction set architecture used. */ 324static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; 325 326/* CPU feature flags of instruction set architecture used. */ 327static unsigned int cpu_arch_isa_flags = 0; 328 329/* If set, conditional jumps are not automatically promoted to handle 330 larger than a byte offset. */ 331static unsigned int no_cond_jump_promotion = 0; 332 333/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ 334static symbolS *GOT_symbol; 335 336/* The dwarf2 return column, adjusted for 32 or 64 bit. */ 337unsigned int x86_dwarf2_return_column; 338 339/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ 340int x86_cie_data_alignment; 341 342/* Interface to relax_segment. 343 There are 3 major relax states for 386 jump insns because the 344 different types of jumps add different sizes to frags when we're 345 figuring out what sort of jump to choose to reach a given label. */ 346 347/* Types. */ 348#define UNCOND_JUMP 0 349#define COND_JUMP 1 350#define COND_JUMP86 2 351 352/* Sizes. */ 353#define CODE16 1 354#define SMALL 0 355#define SMALL16 (SMALL | CODE16) 356#define BIG 2 357#define BIG16 (BIG | CODE16) 358 359#ifndef INLINE 360#ifdef __GNUC__ 361#define INLINE __inline__ 362#else 363#define INLINE 364#endif 365#endif 366 367#define ENCODE_RELAX_STATE(type, size) \ 368 ((relax_substateT) (((type) << 2) | (size))) 369#define TYPE_FROM_RELAX_STATE(s) \ 370 ((s) >> 2) 371#define DISP_SIZE_FROM_RELAX_STATE(s) \ 372 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) 373 374/* This table is used by relax_frag to promote short jumps to long 375 ones where necessary. SMALL (short) jumps may be promoted to BIG 376 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We 377 don't allow a short jump in a 32 bit code segment to be promoted to 378 a 16 bit offset jump because it's slower (requires data size 379 prefix), and doesn't work, unless the destination is in the bottom 380 64k of the code segment (The top 16 bits of eip are zeroed). */ 381 382const relax_typeS md_relax_table[] = 383{ 384 /* The fields are: 385 1) most positive reach of this state, 386 2) most negative reach of this state, 387 3) how many bytes this mode will have in the variable part of the frag 388 4) which index into the table to try if we can't fit into this one. */ 389 390 /* UNCOND_JUMP states. */ 391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, 392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, 393 /* dword jmp adds 4 bytes to frag: 394 0 extra opcode bytes, 4 displacement bytes. */ 395 {0, 0, 4, 0}, 396 /* word jmp adds 2 byte2 to frag: 397 0 extra opcode bytes, 2 displacement bytes. */ 398 {0, 0, 2, 0}, 399 400 /* COND_JUMP states. */ 401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, 402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, 403 /* dword conditionals adds 5 bytes to frag: 404 1 extra opcode byte, 4 displacement bytes. */ 405 {0, 0, 5, 0}, 406 /* word conditionals add 3 bytes to frag: 407 1 extra opcode byte, 2 displacement bytes. */ 408 {0, 0, 3, 0}, 409 410 /* COND_JUMP86 states. */ 411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, 412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, 413 /* dword conditionals adds 5 bytes to frag: 414 1 extra opcode byte, 4 displacement bytes. */ 415 {0, 0, 5, 0}, 416 /* word conditionals add 4 bytes to frag: 417 1 displacement byte and a 3 byte long branch insn. */ 418 {0, 0, 4, 0} 419}; 420 421static const arch_entry cpu_arch[] = 422{ 423 {"generic32", PROCESSOR_GENERIC32, 424 Cpu186|Cpu286|Cpu386}, 425 {"generic64", PROCESSOR_GENERIC64, 426 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX 427 |CpuMMX2|CpuSSE|CpuSSE2}, 428 {"i8086", PROCESSOR_UNKNOWN, 429 0}, 430 {"i186", PROCESSOR_UNKNOWN, 431 Cpu186}, 432 {"i286", PROCESSOR_UNKNOWN, 433 Cpu186|Cpu286}, 434 {"i386", PROCESSOR_GENERIC32, 435 Cpu186|Cpu286|Cpu386}, 436 {"i486", PROCESSOR_I486, 437 Cpu186|Cpu286|Cpu386|Cpu486}, 438 {"i586", PROCESSOR_PENTIUM, 439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586}, 440 {"i686", PROCESSOR_PENTIUMPRO, 441 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686}, 442 {"pentium", PROCESSOR_PENTIUM, 443 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586}, 444 {"pentiumpro",PROCESSOR_PENTIUMPRO, 445 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686}, 446 {"pentiumii", PROCESSOR_PENTIUMPRO, 447 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX}, 448 {"pentiumiii",PROCESSOR_PENTIUMPRO, 449 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE}, 450 {"pentium4", PROCESSOR_PENTIUM4, 451 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX 452 |CpuMMX2|CpuSSE|CpuSSE2}, 453 {"prescott", PROCESSOR_NOCONA, 454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX 455 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3}, 456 {"nocona", PROCESSOR_NOCONA, 457 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX 458 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3}, 459 {"yonah", PROCESSOR_CORE, 460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX 461 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3}, 462 {"core", PROCESSOR_CORE, 463 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX 464 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3}, 465 {"merom", PROCESSOR_CORE2, 466 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX 467 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3}, 468 {"core2", PROCESSOR_CORE2, 469 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX 470 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3}, 471 {"k6", PROCESSOR_K6, 472 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX}, 473 {"k6_2", PROCESSOR_K6, 474 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow}, 475 {"athlon", PROCESSOR_ATHLON, 476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6 477 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA}, 478 {"sledgehammer", PROCESSOR_K8, 479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6 480 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2}, 481 {"opteron", PROCESSOR_K8, 482 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6 483 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2}, 484 {"k8", PROCESSOR_K8, 485 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6 486 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2}, 487 {"amdfam10", PROCESSOR_AMDFAM10, 488 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer 489 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a 490 |CpuABM}, 491 {".mmx", PROCESSOR_UNKNOWN, 492 CpuMMX}, 493 {".sse", PROCESSOR_UNKNOWN, 494 CpuMMX|CpuMMX2|CpuSSE}, 495 {".sse2", PROCESSOR_UNKNOWN, 496 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2}, 497 {".sse3", PROCESSOR_UNKNOWN, 498 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3}, 499 {".ssse3", PROCESSOR_UNKNOWN, 500 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3}, 501 {".sse4.1", PROCESSOR_UNKNOWN, 502 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1}, 503 {".sse4.2", PROCESSOR_UNKNOWN, 504 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4}, 505 {".sse4", PROCESSOR_UNKNOWN, 506 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4}, 507 {".3dnow", PROCESSOR_UNKNOWN, 508 CpuMMX|Cpu3dnow}, 509 {".3dnowa", PROCESSOR_UNKNOWN, 510 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA}, 511 {".padlock", PROCESSOR_UNKNOWN, 512 CpuPadLock}, 513 {".pacifica", PROCESSOR_UNKNOWN, 514 CpuSVME}, 515 {".svme", PROCESSOR_UNKNOWN, 516 CpuSVME}, 517 {".sse4a", PROCESSOR_UNKNOWN, 518 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a}, 519 {".abm", PROCESSOR_UNKNOWN, 520 CpuABM}, 521 {".xsave", PROCESSOR_UNKNOWN, 522 CpuXSAVE} 523}; 524 525const pseudo_typeS md_pseudo_table[] = 526{ 527#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) 528 {"align", s_align_bytes, 0}, 529#else 530 {"align", s_align_ptwo, 0}, 531#endif 532 {"arch", set_cpu_arch, 0}, 533#ifndef I386COFF 534 {"bss", s_bss, 0}, 535#endif 536 {"ffloat", float_cons, 'f'}, 537 {"dfloat", float_cons, 'd'}, 538 {"tfloat", float_cons, 'x'}, 539 {"value", cons, 2}, 540 {"slong", signed_cons, 4}, 541 {"noopt", s_ignore, 0}, 542 {"optim", s_ignore, 0}, 543 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, 544 {"code16", set_code_flag, CODE_16BIT}, 545 {"code32", set_code_flag, CODE_32BIT}, 546 {"code64", set_code_flag, CODE_64BIT}, 547 {"intel_syntax", set_intel_syntax, 1}, 548 {"att_syntax", set_intel_syntax, 0}, 549#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 550 {"largecomm", handle_large_common, 0}, 551#else 552 {"file", (void (*) (int)) dwarf2_directive_file, 0}, 553 {"loc", dwarf2_directive_loc, 0}, 554 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, 555#endif 556#ifdef TE_PE 557 {"secrel32", pe_directive_secrel, 0}, 558#endif 559 {0, 0, 0} 560}; 561 562/* For interface with expression (). */ 563extern char *input_line_pointer; 564 565/* Hash table for instruction mnemonic lookup. */ 566static struct hash_control *op_hash; 567 568/* Hash table for register lookup. */ 569static struct hash_control *reg_hash; 570 571void 572i386_align_code (fragS *fragP, int count) 573{ 574 /* Various efficient no-op patterns for aligning code labels. 575 Note: Don't try to assemble the instructions in the comments. 576 0L and 0w are not legal. */ 577 static const char f32_1[] = 578 {0x90}; /* nop */ 579 static const char f32_2[] = 580 {0x66,0x90}; /* xchg %ax,%ax */ 581 static const char f32_3[] = 582 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ 583 static const char f32_4[] = 584 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ 585 static const char f32_5[] = 586 {0x90, /* nop */ 587 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ 588 static const char f32_6[] = 589 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ 590 static const char f32_7[] = 591 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ 592 static const char f32_8[] = 593 {0x90, /* nop */ 594 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ 595 static const char f32_9[] = 596 {0x89,0xf6, /* movl %esi,%esi */ 597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 598 static const char f32_10[] = 599 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ 600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 601 static const char f32_11[] = 602 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ 603 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 604 static const char f32_12[] = 605 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ 606 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ 607 static const char f32_13[] = 608 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ 609 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 610 static const char f32_14[] = 611 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ 612 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 613 static const char f32_15[] = 614 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ 615 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; 616 static const char f16_3[] = 617 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ 618 static const char f16_4[] = 619 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ 620 static const char f16_5[] = 621 {0x90, /* nop */ 622 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ 623 static const char f16_6[] = 624 {0x89,0xf6, /* mov %si,%si */ 625 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 626 static const char f16_7[] = 627 {0x8d,0x74,0x00, /* lea 0(%si),%si */ 628 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 629 static const char f16_8[] = 630 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ 631 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 632 static const char *const f32_patt[] = { 633 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, 634 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 635 }; 636 static const char *const f16_patt[] = { 637 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8, 638 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 639 }; 640 /* nopl (%[re]ax) */ 641 static const char alt_3[] = 642 {0x0f,0x1f,0x00}; 643 /* nopl 0(%[re]ax) */ 644 static const char alt_4[] = 645 {0x0f,0x1f,0x40,0x00}; 646 /* nopl 0(%[re]ax,%[re]ax,1) */ 647 static const char alt_5[] = 648 {0x0f,0x1f,0x44,0x00,0x00}; 649 /* nopw 0(%[re]ax,%[re]ax,1) */ 650 static const char alt_6[] = 651 {0x66,0x0f,0x1f,0x44,0x00,0x00}; 652 /* nopl 0L(%[re]ax) */ 653 static const char alt_7[] = 654 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; 655 /* nopl 0L(%[re]ax,%[re]ax,1) */ 656 static const char alt_8[] = 657 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 658 /* nopw 0L(%[re]ax,%[re]ax,1) */ 659 static const char alt_9[] = 660 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 661 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ 662 static const char alt_10[] = 663 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 664 /* data16 665 nopw %cs:0L(%[re]ax,%[re]ax,1) */ 666 static const char alt_long_11[] = 667 {0x66, 668 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 669 /* data16 670 data16 671 nopw %cs:0L(%[re]ax,%[re]ax,1) */ 672 static const char alt_long_12[] = 673 {0x66, 674 0x66, 675 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 676 /* data16 677 data16 678 data16 679 nopw %cs:0L(%[re]ax,%[re]ax,1) */ 680 static const char alt_long_13[] = 681 {0x66, 682 0x66, 683 0x66, 684 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 685 /* data16 686 data16 687 data16 688 data16 689 nopw %cs:0L(%[re]ax,%[re]ax,1) */ 690 static const char alt_long_14[] = 691 {0x66, 692 0x66, 693 0x66, 694 0x66, 695 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 696 /* data16 697 data16 698 data16 699 data16 700 data16 701 nopw %cs:0L(%[re]ax,%[re]ax,1) */ 702 static const char alt_long_15[] = 703 {0x66, 704 0x66, 705 0x66, 706 0x66, 707 0x66, 708 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 709 /* nopl 0(%[re]ax,%[re]ax,1) 710 nopw 0(%[re]ax,%[re]ax,1) */ 711 static const char alt_short_11[] = 712 {0x0f,0x1f,0x44,0x00,0x00, 713 0x66,0x0f,0x1f,0x44,0x00,0x00}; 714 /* nopw 0(%[re]ax,%[re]ax,1) 715 nopw 0(%[re]ax,%[re]ax,1) */ 716 static const char alt_short_12[] = 717 {0x66,0x0f,0x1f,0x44,0x00,0x00, 718 0x66,0x0f,0x1f,0x44,0x00,0x00}; 719 /* nopw 0(%[re]ax,%[re]ax,1) 720 nopl 0L(%[re]ax) */ 721 static const char alt_short_13[] = 722 {0x66,0x0f,0x1f,0x44,0x00,0x00, 723 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; 724 /* nopl 0L(%[re]ax) 725 nopl 0L(%[re]ax) */ 726 static const char alt_short_14[] = 727 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, 728 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; 729 /* nopl 0L(%[re]ax) 730 nopl 0L(%[re]ax,%[re]ax,1) */ 731 static const char alt_short_15[] = 732 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, 733 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 734 static const char *const alt_short_patt[] = { 735 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, 736 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13, 737 alt_short_14, alt_short_15 738 }; 739 static const char *const alt_long_patt[] = { 740 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, 741 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13, 742 alt_long_14, alt_long_15 743 }; 744 745 if (count <= 0 || count > 15) 746 return; 747 748 /* We need to decide which NOP sequence to use for 32bit and 749 64bit. When -mtune= is used: 750 751 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32, 752 f32_patt will be used. 753 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 754 0x66 prefix will be used. 755 3. For PROCESSOR_CORE2, alt_long_patt will be used. 756 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA, 757 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON 758 and PROCESSOR_GENERIC64, alt_short_patt will be used. 759 760 When -mtune= isn't used, alt_short_patt will be used if 761 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used. 762 763 When -march= or .arch is used, we can't use anything beyond 764 cpu_arch_isa_flags. */ 765 766 if (flag_code == CODE_16BIT) 767 { 768 memcpy (fragP->fr_literal + fragP->fr_fix, 769 f16_patt[count - 1], count); 770 if (count > 8) 771 /* Adjust jump offset. */ 772 fragP->fr_literal[fragP->fr_fix + 1] = count - 2; 773 } 774 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8) 775 { 776 int i; 777 int nnops = (count + 3) / 4; 778 int len = count / nnops; 779 int remains = count - nnops * len; 780 int pos = 0; 781 782 /* The recommended way to pad 64bit code is to use NOPs preceded 783 by maximally four 0x66 prefixes. Balance the size of nops. */ 784 for (i = 0; i < remains; i++) 785 { 786 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len); 787 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90; 788 pos += len + 1; 789 } 790 for (; i < nnops; i++) 791 { 792 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1); 793 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90; 794 pos += len; 795 } 796 } 797 else 798 { 799 const char *const *patt = NULL; 800 801 if (cpu_arch_isa == PROCESSOR_UNKNOWN) 802 { 803 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ 804 switch (cpu_arch_tune) 805 { 806 case PROCESSOR_UNKNOWN: 807 /* We use cpu_arch_isa_flags to check if we SHOULD 808 optimize for Cpu686. */ 809 if ((cpu_arch_isa_flags & Cpu686) != 0) 810 patt = alt_short_patt; 811 else 812 patt = f32_patt; 813 break; 814 case PROCESSOR_CORE2: 815 patt = alt_long_patt; 816 break; 817 case PROCESSOR_PENTIUMPRO: 818 case PROCESSOR_PENTIUM4: 819 case PROCESSOR_NOCONA: 820 case PROCESSOR_CORE: 821 case PROCESSOR_K6: 822 case PROCESSOR_ATHLON: 823 case PROCESSOR_K8: 824 case PROCESSOR_GENERIC64: 825 case PROCESSOR_AMDFAM10: 826 patt = alt_short_patt; 827 break; 828 case PROCESSOR_I486: 829 case PROCESSOR_PENTIUM: 830 case PROCESSOR_GENERIC32: 831 patt = f32_patt; 832 break; 833 } 834 } 835 else 836 { 837 switch (cpu_arch_tune) 838 { 839 case PROCESSOR_UNKNOWN: 840 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be 841 PROCESSOR_UNKNOWN. */ 842 abort (); 843 break; 844 845 case PROCESSOR_I486: 846 case PROCESSOR_PENTIUM: 847 case PROCESSOR_PENTIUMPRO: 848 case PROCESSOR_PENTIUM4: 849 case PROCESSOR_NOCONA: 850 case PROCESSOR_CORE: 851 case PROCESSOR_K6: 852 case PROCESSOR_ATHLON: 853 case PROCESSOR_K8: 854 case PROCESSOR_AMDFAM10: 855 case PROCESSOR_GENERIC32: 856 /* We use cpu_arch_isa_flags to check if we CAN optimize 857 for Cpu686. */ 858 if ((cpu_arch_isa_flags & Cpu686) != 0) 859 patt = alt_short_patt; 860 else 861 patt = f32_patt; 862 break; 863 case PROCESSOR_CORE2: 864 if ((cpu_arch_isa_flags & Cpu686) != 0) 865 patt = alt_long_patt; 866 else 867 patt = f32_patt; 868 break; 869 case PROCESSOR_GENERIC64: 870 patt = alt_short_patt; 871 break; 872 } 873 } 874 875 memcpy (fragP->fr_literal + fragP->fr_fix, 876 patt[count - 1], count); 877 } 878 fragP->fr_var = count; 879} 880 881static INLINE unsigned int 882mode_from_disp_size (unsigned int t) 883{ 884 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0; 885} 886 887static INLINE int 888fits_in_signed_byte (offsetT num) 889{ 890 return (num >= -128) && (num <= 127); 891} 892 893static INLINE int 894fits_in_unsigned_byte (offsetT num) 895{ 896 return (num & 0xff) == num; 897} 898 899static INLINE int 900fits_in_unsigned_word (offsetT num) 901{ 902 return (num & 0xffff) == num; 903} 904 905static INLINE int 906fits_in_signed_word (offsetT num) 907{ 908 return (-32768 <= num) && (num <= 32767); 909} 910 911static INLINE int 912fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED) 913{ 914#ifndef BFD64 915 return 1; 916#else 917 return (!(((offsetT) -1 << 31) & num) 918 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); 919#endif 920} /* fits_in_signed_long() */ 921 922static INLINE int 923fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED) 924{ 925#ifndef BFD64 926 return 1; 927#else 928 return (num & (((offsetT) 2 << 31) - 1)) == num; 929#endif 930} /* fits_in_unsigned_long() */ 931 932static unsigned int 933smallest_imm_type (offsetT num) 934{ 935 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64)) 936 { 937 /* This code is disabled on the 486 because all the Imm1 forms 938 in the opcode table are slower on the i486. They're the 939 versions with the implicitly specified single-position 940 displacement, which has another syntax if you really want to 941 use that form. */ 942 if (num == 1) 943 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64; 944 } 945 return (fits_in_signed_byte (num) 946 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64) 947 : fits_in_unsigned_byte (num) 948 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64) 949 : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) 950 ? (Imm16 | Imm32 | Imm32S | Imm64) 951 : fits_in_signed_long (num) 952 ? (Imm32 | Imm32S | Imm64) 953 : fits_in_unsigned_long (num) 954 ? (Imm32 | Imm64) 955 : Imm64); 956} 957 958static offsetT 959offset_in_range (offsetT val, int size) 960{ 961 addressT mask; 962 963 switch (size) 964 { 965 case 1: mask = ((addressT) 1 << 8) - 1; break; 966 case 2: mask = ((addressT) 1 << 16) - 1; break; 967 case 4: mask = ((addressT) 2 << 31) - 1; break; 968#ifdef BFD64 969 case 8: mask = ((addressT) 2 << 63) - 1; break; 970#endif 971 default: abort (); 972 } 973 974 /* If BFD64, sign extend val. */ 975 if (!use_rela_relocations) 976 if ((val & ~(((addressT) 2 << 31) - 1)) == 0) 977 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); 978 979 if ((val & ~mask) != 0 && (val & ~mask) != ~mask) 980 { 981 char buf1[40], buf2[40]; 982 983 sprint_value (buf1, val); 984 sprint_value (buf2, val & mask); 985 as_warn (_("%s shortened to %s"), buf1, buf2); 986 } 987 return val & mask; 988} 989 990/* Returns 0 if attempting to add a prefix where one from the same 991 class already exists, 1 if non rep/repne added, 2 if rep/repne 992 added. */ 993static int 994add_prefix (unsigned int prefix) 995{ 996 int ret = 1; 997 unsigned int q; 998 999 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 1000 && flag_code == CODE_64BIT) 1001 { 1002 if ((i.prefix[REX_PREFIX] & prefix & REX_W) 1003 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) 1004 && (prefix & (REX_R | REX_X | REX_B)))) 1005 ret = 0; 1006 q = REX_PREFIX; 1007 } 1008 else 1009 { 1010 switch (prefix) 1011 { 1012 default: 1013 abort (); 1014 1015 case CS_PREFIX_OPCODE: 1016 case DS_PREFIX_OPCODE: 1017 case ES_PREFIX_OPCODE: 1018 case FS_PREFIX_OPCODE: 1019 case GS_PREFIX_OPCODE: 1020 case SS_PREFIX_OPCODE: 1021 q = SEG_PREFIX; 1022 break; 1023 1024 case REPNE_PREFIX_OPCODE: 1025 case REPE_PREFIX_OPCODE: 1026 ret = 2; 1027 /* fall thru */ 1028 case LOCK_PREFIX_OPCODE: 1029 q = LOCKREP_PREFIX; 1030 break; 1031 1032 case FWAIT_OPCODE: 1033 q = WAIT_PREFIX; 1034 break; 1035 1036 case ADDR_PREFIX_OPCODE: 1037 q = ADDR_PREFIX; 1038 break; 1039 1040 case DATA_PREFIX_OPCODE: 1041 q = DATA_PREFIX; 1042 break; 1043 } 1044 if (i.prefix[q] != 0) 1045 ret = 0; 1046 } 1047 1048 if (ret) 1049 { 1050 if (!i.prefix[q]) 1051 ++i.prefixes; 1052 i.prefix[q] |= prefix; 1053 } 1054 else 1055 as_bad (_("same type of prefix used twice")); 1056 1057 return ret; 1058} 1059 1060static void 1061set_code_flag (int value) 1062{ 1063 flag_code = value; 1064 cpu_arch_flags &= ~(Cpu64 | CpuNo64); 1065 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); 1066 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer)) 1067 { 1068 as_bad (_("64bit mode not supported on this CPU.")); 1069 } 1070 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386)) 1071 { 1072 as_bad (_("32bit mode not supported on this CPU.")); 1073 } 1074 stackop_size = '\0'; 1075} 1076 1077static void 1078set_16bit_gcc_code_flag (int new_code_flag) 1079{ 1080 flag_code = new_code_flag; 1081 cpu_arch_flags &= ~(Cpu64 | CpuNo64); 1082 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); 1083 stackop_size = LONG_MNEM_SUFFIX; 1084} 1085 1086static void 1087set_intel_syntax (int syntax_flag) 1088{ 1089 /* Find out if register prefixing is specified. */ 1090 int ask_naked_reg = 0; 1091 1092 SKIP_WHITESPACE (); 1093 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 1094 { 1095 char *string = input_line_pointer; 1096 int e = get_symbol_end (); 1097 1098 if (strcmp (string, "prefix") == 0) 1099 ask_naked_reg = 1; 1100 else if (strcmp (string, "noprefix") == 0) 1101 ask_naked_reg = -1; 1102 else 1103 as_bad (_("bad argument to syntax directive.")); 1104 *input_line_pointer = e; 1105 } 1106 demand_empty_rest_of_line (); 1107 1108 intel_syntax = syntax_flag; 1109 1110 if (ask_naked_reg == 0) 1111 allow_naked_reg = (intel_syntax 1112 && (bfd_get_symbol_leading_char (stdoutput) != '\0')); 1113 else 1114 allow_naked_reg = (ask_naked_reg < 0); 1115 1116 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; 1117 identifier_chars['$'] = intel_syntax ? '$' : 0; 1118 register_prefix = allow_naked_reg ? "" : "%"; 1119} 1120 1121static void 1122set_cpu_arch (int dummy ATTRIBUTE_UNUSED) 1123{ 1124 SKIP_WHITESPACE (); 1125 1126 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 1127 { 1128 char *string = input_line_pointer; 1129 int e = get_symbol_end (); 1130 unsigned int i; 1131 1132 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) 1133 { 1134 if (strcmp (string, cpu_arch[i].name) == 0) 1135 { 1136 if (*string != '.') 1137 { 1138 cpu_arch_name = cpu_arch[i].name; 1139 cpu_sub_arch_name = NULL; 1140 cpu_arch_flags = (cpu_arch[i].flags 1141 | (flag_code == CODE_64BIT 1142 ? Cpu64 : CpuNo64)); 1143 cpu_arch_isa = cpu_arch[i].type; 1144 cpu_arch_isa_flags = cpu_arch[i].flags; 1145 if (!cpu_arch_tune_set) 1146 { 1147 cpu_arch_tune = cpu_arch_isa; 1148 cpu_arch_tune_flags = cpu_arch_isa_flags; 1149 } 1150 break; 1151 } 1152 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags) 1153 { 1154 cpu_sub_arch_name = cpu_arch[i].name; 1155 cpu_arch_flags |= cpu_arch[i].flags; 1156 } 1157 *input_line_pointer = e; 1158 demand_empty_rest_of_line (); 1159 return; 1160 } 1161 } 1162 if (i >= ARRAY_SIZE (cpu_arch)) 1163 as_bad (_("no such architecture: `%s'"), string); 1164 1165 *input_line_pointer = e; 1166 } 1167 else 1168 as_bad (_("missing cpu architecture")); 1169 1170 no_cond_jump_promotion = 0; 1171 if (*input_line_pointer == ',' 1172 && !is_end_of_line[(unsigned char) input_line_pointer[1]]) 1173 { 1174 char *string = ++input_line_pointer; 1175 int e = get_symbol_end (); 1176 1177 if (strcmp (string, "nojumps") == 0) 1178 no_cond_jump_promotion = 1; 1179 else if (strcmp (string, "jumps") == 0) 1180 ; 1181 else 1182 as_bad (_("no such architecture modifier: `%s'"), string); 1183 1184 *input_line_pointer = e; 1185 } 1186 1187 demand_empty_rest_of_line (); 1188} 1189 1190unsigned long 1191i386_mach () 1192{ 1193 if (!strcmp (default_arch, "x86_64")) 1194 return bfd_mach_x86_64; 1195 else if (!strcmp (default_arch, "i386")) 1196 return bfd_mach_i386_i386; 1197 else 1198 as_fatal (_("Unknown architecture")); 1199} 1200 1201void 1202md_begin () 1203{ 1204 const char *hash_err; 1205 1206 /* Initialize op_hash hash table. */ 1207 op_hash = hash_new (); 1208 1209 { 1210 const template *optab; 1211 templates *core_optab; 1212 1213 /* Setup for loop. */ 1214 optab = i386_optab; 1215 core_optab = (templates *) xmalloc (sizeof (templates)); 1216 core_optab->start = optab; 1217 1218 while (1) 1219 { 1220 ++optab; 1221 if (optab->name == NULL 1222 || strcmp (optab->name, (optab - 1)->name) != 0) 1223 { 1224 /* different name --> ship out current template list; 1225 add to hash table; & begin anew. */ 1226 core_optab->end = optab; 1227 hash_err = hash_insert (op_hash, 1228 (optab - 1)->name, 1229 (PTR) core_optab); 1230 if (hash_err) 1231 { 1232 as_fatal (_("Internal Error: Can't hash %s: %s"), 1233 (optab - 1)->name, 1234 hash_err); 1235 } 1236 if (optab->name == NULL) 1237 break; 1238 core_optab = (templates *) xmalloc (sizeof (templates)); 1239 core_optab->start = optab; 1240 } 1241 } 1242 } 1243 1244 /* Initialize reg_hash hash table. */ 1245 reg_hash = hash_new (); 1246 { 1247 const reg_entry *regtab; 1248 unsigned int regtab_size = i386_regtab_size; 1249 1250 for (regtab = i386_regtab; regtab_size--; regtab++) 1251 { 1252 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); 1253 if (hash_err) 1254 as_fatal (_("Internal Error: Can't hash %s: %s"), 1255 regtab->reg_name, 1256 hash_err); 1257 } 1258 } 1259 1260 /* Fill in lexical tables: mnemonic_chars, operand_chars. */ 1261 { 1262 int c; 1263 char *p; 1264 1265 for (c = 0; c < 256; c++) 1266 { 1267 if (ISDIGIT (c)) 1268 { 1269 digit_chars[c] = c; 1270 mnemonic_chars[c] = c; 1271 register_chars[c] = c; 1272 operand_chars[c] = c; 1273 } 1274 else if (ISLOWER (c)) 1275 { 1276 mnemonic_chars[c] = c; 1277 register_chars[c] = c; 1278 operand_chars[c] = c; 1279 } 1280 else if (ISUPPER (c)) 1281 { 1282 mnemonic_chars[c] = TOLOWER (c); 1283 register_chars[c] = mnemonic_chars[c]; 1284 operand_chars[c] = c; 1285 } 1286 1287 if (ISALPHA (c) || ISDIGIT (c)) 1288 identifier_chars[c] = c; 1289 else if (c >= 128) 1290 { 1291 identifier_chars[c] = c; 1292 operand_chars[c] = c; 1293 } 1294 } 1295 1296#ifdef LEX_AT 1297 identifier_chars['@'] = '@'; 1298#endif 1299#ifdef LEX_QM 1300 identifier_chars['?'] = '?'; 1301 operand_chars['?'] = '?'; 1302#endif 1303 digit_chars['-'] = '-'; 1304 mnemonic_chars['-'] = '-'; 1305 mnemonic_chars['.'] = '.'; 1306 identifier_chars['_'] = '_'; 1307 identifier_chars['.'] = '.'; 1308 1309 for (p = operand_special_chars; *p != '\0'; p++) 1310 operand_chars[(unsigned char) *p] = *p; 1311 } 1312 1313#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 1314 if (IS_ELF) 1315 { 1316 record_alignment (text_section, 2); 1317 record_alignment (data_section, 2); 1318 record_alignment (bss_section, 2); 1319 } 1320#endif 1321 1322 if (flag_code == CODE_64BIT) 1323 { 1324 x86_dwarf2_return_column = 16; 1325 x86_cie_data_alignment = -8; 1326 } 1327 else 1328 { 1329 x86_dwarf2_return_column = 8; 1330 x86_cie_data_alignment = -4; 1331 } 1332} 1333 1334void 1335i386_print_statistics (FILE *file) 1336{ 1337 hash_print_statistics (file, "i386 opcode", op_hash); 1338 hash_print_statistics (file, "i386 register", reg_hash); 1339} 1340 1341#ifdef DEBUG386 1342 1343/* Debugging routines for md_assemble. */ 1344static void pte (template *); 1345static void pt (unsigned int); 1346static void pe (expressionS *); 1347static void ps (symbolS *); 1348 1349static void 1350pi (char *line, i386_insn *x) 1351{ 1352 unsigned int i; 1353 1354 fprintf (stdout, "%s: template ", line); 1355 pte (&x->tm); 1356 fprintf (stdout, " address: base %s index %s scale %x\n", 1357 x->base_reg ? x->base_reg->reg_name : "none", 1358 x->index_reg ? x->index_reg->reg_name : "none", 1359 x->log2_scale_factor); 1360 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", 1361 x->rm.mode, x->rm.reg, x->rm.regmem); 1362 fprintf (stdout, " sib: base %x index %x scale %x\n", 1363 x->sib.base, x->sib.index, x->sib.scale); 1364 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", 1365 (x->rex & REX_W) != 0, 1366 (x->rex & REX_R) != 0, 1367 (x->rex & REX_X) != 0, 1368 (x->rex & REX_B) != 0); 1369 for (i = 0; i < x->operands; i++) 1370 { 1371 fprintf (stdout, " #%d: ", i + 1); 1372 pt (x->types[i]); 1373 fprintf (stdout, "\n"); 1374 if (x->types[i] 1375 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM)) 1376 fprintf (stdout, "%s\n", x->op[i].regs->reg_name); 1377 if (x->types[i] & Imm) 1378 pe (x->op[i].imms); 1379 if (x->types[i] & Disp) 1380 pe (x->op[i].disps); 1381 } 1382} 1383 1384static void 1385pte (template *t) 1386{ 1387 unsigned int i; 1388 fprintf (stdout, " %d operands ", t->operands); 1389 fprintf (stdout, "opcode %x ", t->base_opcode); 1390 if (t->extension_opcode != None) 1391 fprintf (stdout, "ext %x ", t->extension_opcode); 1392 if (t->opcode_modifier & D) 1393 fprintf (stdout, "D"); 1394 if (t->opcode_modifier & W) 1395 fprintf (stdout, "W"); 1396 fprintf (stdout, "\n"); 1397 for (i = 0; i < t->operands; i++) 1398 { 1399 fprintf (stdout, " #%d type ", i + 1); 1400 pt (t->operand_types[i]); 1401 fprintf (stdout, "\n"); 1402 } 1403} 1404 1405static void 1406pe (expressionS *e) 1407{ 1408 fprintf (stdout, " operation %d\n", e->X_op); 1409 fprintf (stdout, " add_number %ld (%lx)\n", 1410 (long) e->X_add_number, (long) e->X_add_number); 1411 if (e->X_add_symbol) 1412 { 1413 fprintf (stdout, " add_symbol "); 1414 ps (e->X_add_symbol); 1415 fprintf (stdout, "\n"); 1416 } 1417 if (e->X_op_symbol) 1418 { 1419 fprintf (stdout, " op_symbol "); 1420 ps (e->X_op_symbol); 1421 fprintf (stdout, "\n"); 1422 } 1423} 1424 1425static void 1426ps (symbolS *s) 1427{ 1428 fprintf (stdout, "%s type %s%s", 1429 S_GET_NAME (s), 1430 S_IS_EXTERNAL (s) ? "EXTERNAL " : "", 1431 segment_name (S_GET_SEGMENT (s))); 1432} 1433 1434static struct type_name 1435 { 1436 unsigned int mask; 1437 char *tname; 1438 } 1439const type_names[] = 1440{ 1441 { Reg8, "r8" }, 1442 { Reg16, "r16" }, 1443 { Reg32, "r32" }, 1444 { Reg64, "r64" }, 1445 { Imm8, "i8" }, 1446 { Imm8S, "i8s" }, 1447 { Imm16, "i16" }, 1448 { Imm32, "i32" }, 1449 { Imm32S, "i32s" }, 1450 { Imm64, "i64" }, 1451 { Imm1, "i1" }, 1452 { BaseIndex, "BaseIndex" }, 1453 { Disp8, "d8" }, 1454 { Disp16, "d16" }, 1455 { Disp32, "d32" }, 1456 { Disp32S, "d32s" }, 1457 { Disp64, "d64" }, 1458 { InOutPortReg, "InOutPortReg" }, 1459 { ShiftCount, "ShiftCount" }, 1460 { Control, "control reg" }, 1461 { Test, "test reg" }, 1462 { Debug, "debug reg" }, 1463 { FloatReg, "FReg" }, 1464 { FloatAcc, "FAcc" }, 1465 { SReg2, "SReg2" }, 1466 { SReg3, "SReg3" }, 1467 { Acc, "Acc" }, 1468 { JumpAbsolute, "Jump Absolute" }, 1469 { RegMMX, "rMMX" }, 1470 { RegXMM, "rXMM" }, 1471 { EsSeg, "es" }, 1472 { 0, "" } 1473}; 1474 1475static void 1476pt (t) 1477 unsigned int t; 1478{ 1479 const struct type_name *ty; 1480 1481 for (ty = type_names; ty->mask; ty++) 1482 if (t & ty->mask) 1483 fprintf (stdout, "%s, ", ty->tname); 1484 fflush (stdout); 1485} 1486 1487#endif /* DEBUG386 */ 1488 1489static bfd_reloc_code_real_type 1490reloc (unsigned int size, 1491 int pcrel, 1492 int sign, 1493 bfd_reloc_code_real_type other) 1494{ 1495 if (other != NO_RELOC) 1496 { 1497 reloc_howto_type *reloc; 1498 1499 if (size == 8) 1500 switch (other) 1501 { 1502 case BFD_RELOC_X86_64_GOT32: 1503 return BFD_RELOC_X86_64_GOT64; 1504 break; 1505 case BFD_RELOC_X86_64_PLTOFF64: 1506 return BFD_RELOC_X86_64_PLTOFF64; 1507 break; 1508 case BFD_RELOC_X86_64_GOTPC32: 1509 other = BFD_RELOC_X86_64_GOTPC64; 1510 break; 1511 case BFD_RELOC_X86_64_GOTPCREL: 1512 other = BFD_RELOC_X86_64_GOTPCREL64; 1513 break; 1514 case BFD_RELOC_X86_64_TPOFF32: 1515 other = BFD_RELOC_X86_64_TPOFF64; 1516 break; 1517 case BFD_RELOC_X86_64_DTPOFF32: 1518 other = BFD_RELOC_X86_64_DTPOFF64; 1519 break; 1520 default: 1521 break; 1522 } 1523 1524 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ 1525 if (size == 4 && flag_code != CODE_64BIT) 1526 sign = -1; 1527 1528 reloc = bfd_reloc_type_lookup (stdoutput, other); 1529 if (!reloc) 1530 as_bad (_("unknown relocation (%u)"), other); 1531 else if (size != bfd_get_reloc_size (reloc)) 1532 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), 1533 bfd_get_reloc_size (reloc), 1534 size); 1535 else if (pcrel && !reloc->pc_relative) 1536 as_bad (_("non-pc-relative relocation for pc-relative field")); 1537 else if ((reloc->complain_on_overflow == complain_overflow_signed 1538 && !sign) 1539 || (reloc->complain_on_overflow == complain_overflow_unsigned 1540 && sign > 0)) 1541 as_bad (_("relocated field and relocation type differ in signedness")); 1542 else 1543 return other; 1544 return NO_RELOC; 1545 } 1546 1547 if (pcrel) 1548 { 1549 if (!sign) 1550 as_bad (_("there are no unsigned pc-relative relocations")); 1551 switch (size) 1552 { 1553 case 1: return BFD_RELOC_8_PCREL; 1554 case 2: return BFD_RELOC_16_PCREL; 1555 case 4: return BFD_RELOC_32_PCREL; 1556 case 8: return BFD_RELOC_64_PCREL; 1557 } 1558 as_bad (_("cannot do %u byte pc-relative relocation"), size); 1559 } 1560 else 1561 { 1562 if (sign > 0) 1563 switch (size) 1564 { 1565 case 4: return BFD_RELOC_X86_64_32S; 1566 } 1567 else 1568 switch (size) 1569 { 1570 case 1: return BFD_RELOC_8; 1571 case 2: return BFD_RELOC_16; 1572 case 4: return BFD_RELOC_32; 1573 case 8: return BFD_RELOC_64; 1574 } 1575 as_bad (_("cannot do %s %u byte relocation"), 1576 sign > 0 ? "signed" : "unsigned", size); 1577 } 1578 1579 abort (); 1580 return BFD_RELOC_NONE; 1581} 1582 1583/* Here we decide which fixups can be adjusted to make them relative to 1584 the beginning of the section instead of the symbol. Basically we need 1585 to make sure that the dynamic relocations are done correctly, so in 1586 some cases we force the original symbol to be used. */ 1587 1588int 1589tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) 1590{ 1591#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 1592 if (!IS_ELF) 1593 return 1; 1594 1595 /* Don't adjust pc-relative references to merge sections in 64-bit 1596 mode. */ 1597 if (use_rela_relocations 1598 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 1599 && fixP->fx_pcrel) 1600 return 0; 1601 1602 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations 1603 and changed later by validate_fix. */ 1604 if (GOT_symbol && fixP->fx_subsy == GOT_symbol 1605 && fixP->fx_r_type == BFD_RELOC_32_PCREL) 1606 return 0; 1607 1608 /* adjust_reloc_syms doesn't know about the GOT. */ 1609 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF 1610 || fixP->fx_r_type == BFD_RELOC_386_PLT32 1611 || fixP->fx_r_type == BFD_RELOC_386_GOT32 1612 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD 1613 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM 1614 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 1615 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 1616 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE 1617 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE 1618 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 1619 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE 1620 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC 1621 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL 1622 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 1623 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 1624 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL 1625 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD 1626 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD 1627 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 1628 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 1629 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF 1630 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 1631 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 1632 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 1633 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC 1634 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL 1635 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 1636 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 1637 return 0; 1638#endif 1639 return 1; 1640} 1641 1642static int 1643intel_float_operand (const char *mnemonic) 1644{ 1645 /* Note that the value returned is meaningful only for opcodes with (memory) 1646 operands, hence the code here is free to improperly handle opcodes that 1647 have no operands (for better performance and smaller code). */ 1648 1649 if (mnemonic[0] != 'f') 1650 return 0; /* non-math */ 1651 1652 switch (mnemonic[1]) 1653 { 1654 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and 1655 the fs segment override prefix not currently handled because no 1656 call path can make opcodes without operands get here */ 1657 case 'i': 1658 return 2 /* integer op */; 1659 case 'l': 1660 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) 1661 return 3; /* fldcw/fldenv */ 1662 break; 1663 case 'n': 1664 if (mnemonic[2] != 'o' /* fnop */) 1665 return 3; /* non-waiting control op */ 1666 break; 1667 case 'r': 1668 if (mnemonic[2] == 's') 1669 return 3; /* frstor/frstpm */ 1670 break; 1671 case 's': 1672 if (mnemonic[2] == 'a') 1673 return 3; /* fsave */ 1674 if (mnemonic[2] == 't') 1675 { 1676 switch (mnemonic[3]) 1677 { 1678 case 'c': /* fstcw */ 1679 case 'd': /* fstdw */ 1680 case 'e': /* fstenv */ 1681 case 's': /* fsts[gw] */ 1682 return 3; 1683 } 1684 } 1685 break; 1686 case 'x': 1687 if (mnemonic[2] == 'r' || mnemonic[2] == 's') 1688 return 0; /* fxsave/fxrstor are not really math ops */ 1689 break; 1690 } 1691 1692 return 1; 1693} 1694 1695/* This is the guts of the machine-dependent assembler. LINE points to a 1696 machine dependent instruction. This function is supposed to emit 1697 the frags/bytes it assembles to. */ 1698 1699void 1700md_assemble (line) 1701 char *line; 1702{ 1703 int j; 1704 char mnemonic[MAX_MNEM_SIZE]; 1705 1706 /* Initialize globals. */ 1707 memset (&i, '\0', sizeof (i)); 1708 for (j = 0; j < MAX_OPERANDS; j++) 1709 i.reloc[j] = NO_RELOC; 1710 memset (disp_expressions, '\0', sizeof (disp_expressions)); 1711 memset (im_expressions, '\0', sizeof (im_expressions)); 1712 save_stack_p = save_stack; 1713 1714 /* First parse an instruction mnemonic & call i386_operand for the operands. 1715 We assume that the scrubber has arranged it so that line[0] is the valid 1716 start of a (possibly prefixed) mnemonic. */ 1717 1718 line = parse_insn (line, mnemonic); 1719 if (line == NULL) 1720 return; 1721 1722 line = parse_operands (line, mnemonic); 1723 if (line == NULL) 1724 return; 1725 1726 /* The order of the immediates should be reversed 1727 for 2 immediates extrq and insertq instructions */ 1728 if ((i.imm_operands == 2) 1729 && ((strcmp (mnemonic, "extrq") == 0) 1730 || (strcmp (mnemonic, "insertq") == 0))) 1731 { 1732 swap_2_operands (0, 1); 1733 /* "extrq" and insertq" are the only two instructions whose operands 1734 have to be reversed even though they have two immediate operands. 1735 */ 1736 if (intel_syntax) 1737 swap_operands (); 1738 } 1739 1740 /* Now we've parsed the mnemonic into a set of templates, and have the 1741 operands at hand. */ 1742 1743 /* All intel opcodes have reversed operands except for "bound" and 1744 "enter". We also don't reverse intersegment "jmp" and "call" 1745 instructions with 2 immediate operands so that the immediate segment 1746 precedes the offset, as it does when in AT&T mode. */ 1747 if (intel_syntax 1748 && i.operands > 1 1749 && (strcmp (mnemonic, "bound") != 0) 1750 && (strcmp (mnemonic, "invlpga") != 0) 1751 && !((i.types[0] & Imm) && (i.types[1] & Imm))) 1752 swap_operands (); 1753 1754 if (i.imm_operands) 1755 optimize_imm (); 1756 1757 /* Don't optimize displacement for movabs since it only takes 64bit 1758 displacement. */ 1759 if (i.disp_operands 1760 && (flag_code != CODE_64BIT 1761 || strcmp (mnemonic, "movabs") != 0)) 1762 optimize_disp (); 1763 1764 /* Next, we find a template that matches the given insn, 1765 making sure the overlap of the given operands types is consistent 1766 with the template operand types. */ 1767 1768 if (!match_template ()) 1769 return; 1770 1771 if (intel_syntax) 1772 { 1773 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ 1774 if (SYSV386_COMPAT 1775 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) 1776 i.tm.base_opcode ^= Opcode_FloatR; 1777 1778 /* Zap movzx and movsx suffix. The suffix may have been set from 1779 "word ptr" or "byte ptr" on the source operand, but we'll use 1780 the suffix later to choose the destination register. */ 1781 if ((i.tm.base_opcode & ~9) == 0x0fb6) 1782 { 1783 if (i.reg_operands < 2 1784 && !i.suffix 1785 && (~i.tm.opcode_modifier 1786 & (No_bSuf 1787 | No_wSuf 1788 | No_lSuf 1789 | No_sSuf 1790 | No_xSuf 1791 | No_qSuf))) 1792 as_bad (_("ambiguous operand size for `%s'"), i.tm.name); 1793 1794 i.suffix = 0; 1795 } 1796 } 1797 1798 if (i.tm.opcode_modifier & FWait) 1799 if (!add_prefix (FWAIT_OPCODE)) 1800 return; 1801 1802 /* Check string instruction segment overrides. */ 1803 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) 1804 { 1805 if (!check_string ()) 1806 return; 1807 } 1808 1809 if (!process_suffix ()) 1810 return; 1811 1812 /* Make still unresolved immediate matches conform to size of immediate 1813 given in i.suffix. */ 1814 if (!finalize_imm ()) 1815 return; 1816 1817 if (i.types[0] & Imm1) 1818 i.imm_operands = 0; /* kludge for shift insns. */ 1819 if (i.types[0] & ImplicitRegister) 1820 i.reg_operands--; 1821 if (i.types[1] & ImplicitRegister) 1822 i.reg_operands--; 1823 if (i.types[2] & ImplicitRegister) 1824 i.reg_operands--; 1825 1826 if (i.tm.opcode_modifier & ImmExt) 1827 { 1828 expressionS *exp; 1829 1830 if ((i.tm.cpu_flags & (CpuSSE3|CpuSMAP)) && i.operands > 0) 1831 { 1832 /* Streaming SIMD extensions 3 Instructions have the fixed 1833 operands with an opcode suffix which is coded in the same 1834 place as an 8-bit immediate field would be. Here we check 1835 those operands and remove them afterwards. */ 1836 unsigned int x; 1837 1838 for (x = 0; x < i.operands; x++) 1839 if (i.op[x].regs->reg_num != x) 1840 as_bad (_("can't use register '%s%s' as operand %d in '%s'."), 1841 register_prefix, 1842 i.op[x].regs->reg_name, 1843 x + 1, 1844 i.tm.name); 1845 i.operands = 0; 1846 } 1847 1848 /* These AMD 3DNow! and Intel Katmai New Instructions have an 1849 opcode suffix which is coded in the same place as an 8-bit 1850 immediate field would be. Here we fake an 8-bit immediate 1851 operand from the opcode suffix stored in tm.extension_opcode. */ 1852 1853 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); 1854 1855 exp = &im_expressions[i.imm_operands++]; 1856 i.op[i.operands].imms = exp; 1857 i.types[i.operands++] = Imm8; 1858 exp->X_op = O_constant; 1859 exp->X_add_number = i.tm.extension_opcode; 1860 i.tm.extension_opcode = None; 1861 } 1862 1863 /* For insns with operands there are more diddles to do to the opcode. */ 1864 if (i.operands) 1865 { 1866 if (!process_operands ()) 1867 return; 1868 } 1869 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) 1870 { 1871 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ 1872 as_warn (_("translating to `%sp'"), i.tm.name); 1873 } 1874 1875 /* Handle conversion of 'int $3' --> special int3 insn. */ 1876 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) 1877 { 1878 i.tm.base_opcode = INT3_OPCODE; 1879 i.imm_operands = 0; 1880 } 1881 1882 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) 1883 && i.op[0].disps->X_op == O_constant) 1884 { 1885 /* Convert "jmp constant" (and "call constant") to a jump (call) to 1886 the absolute address given by the constant. Since ix86 jumps and 1887 calls are pc relative, we need to generate a reloc. */ 1888 i.op[0].disps->X_add_symbol = &abs_symbol; 1889 i.op[0].disps->X_op = O_symbol; 1890 } 1891 1892 if ((i.tm.opcode_modifier & Rex64) != 0) 1893 i.rex |= REX_W; 1894 1895 /* For 8 bit registers we need an empty rex prefix. Also if the 1896 instruction already has a prefix, we need to convert old 1897 registers to new ones. */ 1898 1899 if (((i.types[0] & Reg8) != 0 1900 && (i.op[0].regs->reg_flags & RegRex64) != 0) 1901 || ((i.types[1] & Reg8) != 0 1902 && (i.op[1].regs->reg_flags & RegRex64) != 0) 1903 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0) 1904 && i.rex != 0)) 1905 { 1906 int x; 1907 1908 i.rex |= REX_OPCODE; 1909 for (x = 0; x < 2; x++) 1910 { 1911 /* Look for 8 bit operand that uses old registers. */ 1912 if ((i.types[x] & Reg8) != 0 1913 && (i.op[x].regs->reg_flags & RegRex64) == 0) 1914 { 1915 /* In case it is "hi" register, give up. */ 1916 if (i.op[x].regs->reg_num > 3) 1917 as_bad (_("can't encode register '%s%s' in an " 1918 "instruction requiring REX prefix."), 1919 register_prefix, i.op[x].regs->reg_name); 1920 1921 /* Otherwise it is equivalent to the extended register. 1922 Since the encoding doesn't change this is merely 1923 cosmetic cleanup for debug output. */ 1924 1925 i.op[x].regs = i.op[x].regs + 8; 1926 } 1927 } 1928 } 1929 1930 if (i.rex != 0) 1931 add_prefix (REX_OPCODE | i.rex); 1932 1933 /* We are ready to output the insn. */ 1934 output_insn (); 1935} 1936 1937static char * 1938parse_insn (char *line, char *mnemonic) 1939{ 1940 char *l = line; 1941 char *token_start = l; 1942 char *mnem_p; 1943 int supported; 1944 const template *t; 1945 1946 /* Non-zero if we found a prefix only acceptable with string insns. */ 1947 const char *expecting_string_instruction = NULL; 1948 1949 while (1) 1950 { 1951 mnem_p = mnemonic; 1952 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) 1953 { 1954 mnem_p++; 1955 if (mnem_p >= mnemonic + MAX_MNEM_SIZE) 1956 { 1957 as_bad (_("no such instruction: `%s'"), token_start); 1958 return NULL; 1959 } 1960 l++; 1961 } 1962 if (!is_space_char (*l) 1963 && *l != END_OF_INSN 1964 && (intel_syntax 1965 || (*l != PREFIX_SEPARATOR 1966 && *l != ','))) 1967 { 1968 as_bad (_("invalid character %s in mnemonic"), 1969 output_invalid (*l)); 1970 return NULL; 1971 } 1972 if (token_start == l) 1973 { 1974 if (!intel_syntax && *l == PREFIX_SEPARATOR) 1975 as_bad (_("expecting prefix; got nothing")); 1976 else 1977 as_bad (_("expecting mnemonic; got nothing")); 1978 return NULL; 1979 } 1980 1981 /* Look up instruction (or prefix) via hash table. */ 1982 current_templates = hash_find (op_hash, mnemonic); 1983 1984 if (*l != END_OF_INSN 1985 && (!is_space_char (*l) || l[1] != END_OF_INSN) 1986 && current_templates 1987 && (current_templates->start->opcode_modifier & IsPrefix)) 1988 { 1989 if (current_templates->start->cpu_flags 1990 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64)) 1991 { 1992 as_bad ((flag_code != CODE_64BIT 1993 ? _("`%s' is only supported in 64-bit mode") 1994 : _("`%s' is not supported in 64-bit mode")), 1995 current_templates->start->name); 1996 return NULL; 1997 } 1998 /* If we are in 16-bit mode, do not allow addr16 or data16. 1999 Similarly, in 32-bit mode, do not allow addr32 or data32. */ 2000 if ((current_templates->start->opcode_modifier & (Size16 | Size32)) 2001 && flag_code != CODE_64BIT 2002 && (((current_templates->start->opcode_modifier & Size32) != 0) 2003 ^ (flag_code == CODE_16BIT))) 2004 { 2005 as_bad (_("redundant %s prefix"), 2006 current_templates->start->name); 2007 return NULL; 2008 } 2009 /* Add prefix, checking for repeated prefixes. */ 2010 switch (add_prefix (current_templates->start->base_opcode)) 2011 { 2012 case 0: 2013 return NULL; 2014 case 2: 2015 expecting_string_instruction = current_templates->start->name; 2016 break; 2017 } 2018 /* Skip past PREFIX_SEPARATOR and reset token_start. */ 2019 token_start = ++l; 2020 } 2021 else 2022 break; 2023 } 2024 2025 if (!current_templates) 2026 { 2027 /* See if we can get a match by trimming off a suffix. */ 2028 switch (mnem_p[-1]) 2029 { 2030 case WORD_MNEM_SUFFIX: 2031 if (intel_syntax && (intel_float_operand (mnemonic) & 2)) 2032 i.suffix = SHORT_MNEM_SUFFIX; 2033 else 2034 case BYTE_MNEM_SUFFIX: 2035 case QWORD_MNEM_SUFFIX: 2036 i.suffix = mnem_p[-1]; 2037 mnem_p[-1] = '\0'; 2038 current_templates = hash_find (op_hash, mnemonic); 2039 break; 2040 case SHORT_MNEM_SUFFIX: 2041 case LONG_MNEM_SUFFIX: 2042 if (!intel_syntax) 2043 { 2044 i.suffix = mnem_p[-1]; 2045 mnem_p[-1] = '\0'; 2046 current_templates = hash_find (op_hash, mnemonic); 2047 } 2048 break; 2049 2050 /* Intel Syntax. */ 2051 case 'd': 2052 if (intel_syntax) 2053 { 2054 if (intel_float_operand (mnemonic) == 1) 2055 i.suffix = SHORT_MNEM_SUFFIX; 2056 else 2057 i.suffix = LONG_MNEM_SUFFIX; 2058 mnem_p[-1] = '\0'; 2059 current_templates = hash_find (op_hash, mnemonic); 2060 } 2061 break; 2062 } 2063 if (!current_templates) 2064 { 2065 as_bad (_("no such instruction: `%s'"), token_start); 2066 return NULL; 2067 } 2068 } 2069 2070 if (current_templates->start->opcode_modifier & (Jump | JumpByte)) 2071 { 2072 /* Check for a branch hint. We allow ",pt" and ",pn" for 2073 predict taken and predict not taken respectively. 2074 I'm not sure that branch hints actually do anything on loop 2075 and jcxz insns (JumpByte) for current Pentium4 chips. They 2076 may work in the future and it doesn't hurt to accept them 2077 now. */ 2078 if (l[0] == ',' && l[1] == 'p') 2079 { 2080 if (l[2] == 't') 2081 { 2082 if (!add_prefix (DS_PREFIX_OPCODE)) 2083 return NULL; 2084 l += 3; 2085 } 2086 else if (l[2] == 'n') 2087 { 2088 if (!add_prefix (CS_PREFIX_OPCODE)) 2089 return NULL; 2090 l += 3; 2091 } 2092 } 2093 } 2094 /* Any other comma loses. */ 2095 if (*l == ',') 2096 { 2097 as_bad (_("invalid character %s in mnemonic"), 2098 output_invalid (*l)); 2099 return NULL; 2100 } 2101 2102 /* Check if instruction is supported on specified architecture. */ 2103 supported = 0; 2104 for (t = current_templates->start; t < current_templates->end; ++t) 2105 { 2106 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64)) 2107 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))) 2108 supported |= 1; 2109 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64))) 2110 supported |= 2; 2111 } 2112 if (!(supported & 2)) 2113 { 2114 as_bad (flag_code == CODE_64BIT 2115 ? _("`%s' is not supported in 64-bit mode") 2116 : _("`%s' is only supported in 64-bit mode"), 2117 current_templates->start->name); 2118 return NULL; 2119 } 2120 if (!(supported & 1)) 2121 { 2122 as_warn (_("`%s' is not supported on `%s%s'"), 2123 current_templates->start->name, 2124 cpu_arch_name, 2125 cpu_sub_arch_name ? cpu_sub_arch_name : ""); 2126 } 2127 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT)) 2128 { 2129 as_warn (_("use .code16 to ensure correct addressing mode")); 2130 } 2131 2132 /* Check for rep/repne without a string instruction. */ 2133 if (expecting_string_instruction) 2134 { 2135 static templates override; 2136 2137 for (t = current_templates->start; t < current_templates->end; ++t) 2138 if (t->opcode_modifier & IsString) 2139 break; 2140 if (t >= current_templates->end) 2141 { 2142 as_bad (_("expecting string instruction after `%s'"), 2143 expecting_string_instruction); 2144 return NULL; 2145 } 2146 for (override.start = t; t < current_templates->end; ++t) 2147 if (!(t->opcode_modifier & IsString)) 2148 break; 2149 override.end = t; 2150 current_templates = &override; 2151 } 2152 2153 return l; 2154} 2155 2156static char * 2157parse_operands (char *l, const char *mnemonic) 2158{ 2159 char *token_start; 2160 2161 /* 1 if operand is pending after ','. */ 2162 unsigned int expecting_operand = 0; 2163 2164 /* Non-zero if operand parens not balanced. */ 2165 unsigned int paren_not_balanced; 2166 2167 while (*l != END_OF_INSN) 2168 { 2169 /* Skip optional white space before operand. */ 2170 if (is_space_char (*l)) 2171 ++l; 2172 if (!is_operand_char (*l) && *l != END_OF_INSN) 2173 { 2174 as_bad (_("invalid character %s before operand %d"), 2175 output_invalid (*l), 2176 i.operands + 1); 2177 return NULL; 2178 } 2179 token_start = l; /* after white space */ 2180 paren_not_balanced = 0; 2181 while (paren_not_balanced || *l != ',') 2182 { 2183 if (*l == END_OF_INSN) 2184 { 2185 if (paren_not_balanced) 2186 { 2187 if (!intel_syntax) 2188 as_bad (_("unbalanced parenthesis in operand %d."), 2189 i.operands + 1); 2190 else 2191 as_bad (_("unbalanced brackets in operand %d."), 2192 i.operands + 1); 2193 return NULL; 2194 } 2195 else 2196 break; /* we are done */ 2197 } 2198 else if (!is_operand_char (*l) && !is_space_char (*l)) 2199 { 2200 as_bad (_("invalid character %s in operand %d"), 2201 output_invalid (*l), 2202 i.operands + 1); 2203 return NULL; 2204 } 2205 if (!intel_syntax) 2206 { 2207 if (*l == '(') 2208 ++paren_not_balanced; 2209 if (*l == ')') 2210 --paren_not_balanced; 2211 } 2212 else 2213 { 2214 if (*l == '[') 2215 ++paren_not_balanced; 2216 if (*l == ']') 2217 --paren_not_balanced; 2218 } 2219 l++; 2220 } 2221 if (l != token_start) 2222 { /* Yes, we've read in another operand. */ 2223 unsigned int operand_ok; 2224 this_operand = i.operands++; 2225 if (i.operands > MAX_OPERANDS) 2226 { 2227 as_bad (_("spurious operands; (%d operands/instruction max)"), 2228 MAX_OPERANDS); 2229 return NULL; 2230 } 2231 /* Now parse operand adding info to 'i' as we go along. */ 2232 END_STRING_AND_SAVE (l); 2233 2234 if (intel_syntax) 2235 operand_ok = 2236 i386_intel_operand (token_start, 2237 intel_float_operand (mnemonic)); 2238 else 2239 operand_ok = i386_operand (token_start); 2240 2241 RESTORE_END_STRING (l); 2242 if (!operand_ok) 2243 return NULL; 2244 } 2245 else 2246 { 2247 if (expecting_operand) 2248 { 2249 expecting_operand_after_comma: 2250 as_bad (_("expecting operand after ','; got nothing")); 2251 return NULL; 2252 } 2253 if (*l == ',') 2254 { 2255 as_bad (_("expecting operand before ','; got nothing")); 2256 return NULL; 2257 } 2258 } 2259 2260 /* Now *l must be either ',' or END_OF_INSN. */ 2261 if (*l == ',') 2262 { 2263 if (*++l == END_OF_INSN) 2264 { 2265 /* Just skip it, if it's \n complain. */ 2266 goto expecting_operand_after_comma; 2267 } 2268 expecting_operand = 1; 2269 } 2270 } 2271 return l; 2272} 2273 2274static void 2275swap_2_operands (int xchg1, int xchg2) 2276{ 2277 union i386_op temp_op; 2278 unsigned int temp_type; 2279 enum bfd_reloc_code_real temp_reloc; 2280 2281 temp_type = i.types[xchg2]; 2282 i.types[xchg2] = i.types[xchg1]; 2283 i.types[xchg1] = temp_type; 2284 temp_op = i.op[xchg2]; 2285 i.op[xchg2] = i.op[xchg1]; 2286 i.op[xchg1] = temp_op; 2287 temp_reloc = i.reloc[xchg2]; 2288 i.reloc[xchg2] = i.reloc[xchg1]; 2289 i.reloc[xchg1] = temp_reloc; 2290} 2291 2292static void 2293swap_operands (void) 2294{ 2295 switch (i.operands) 2296 { 2297 case 4: 2298 swap_2_operands (1, i.operands - 2); 2299 case 3: 2300 case 2: 2301 swap_2_operands (0, i.operands - 1); 2302 break; 2303 default: 2304 abort (); 2305 } 2306 2307 if (i.mem_operands == 2) 2308 { 2309 const seg_entry *temp_seg; 2310 temp_seg = i.seg[0]; 2311 i.seg[0] = i.seg[1]; 2312 i.seg[1] = temp_seg; 2313 } 2314} 2315 2316/* Try to ensure constant immediates are represented in the smallest 2317 opcode possible. */ 2318static void 2319optimize_imm (void) 2320{ 2321 char guess_suffix = 0; 2322 int op; 2323 2324 if (i.suffix) 2325 guess_suffix = i.suffix; 2326 else if (i.reg_operands) 2327 { 2328 /* Figure out a suffix from the last register operand specified. 2329 We can't do this properly yet, ie. excluding InOutPortReg, 2330 but the following works for instructions with immediates. 2331 In any case, we can't set i.suffix yet. */ 2332 for (op = i.operands; --op >= 0;) 2333 if (i.types[op] & Reg) 2334 { 2335 if (i.types[op] & Reg8) 2336 guess_suffix = BYTE_MNEM_SUFFIX; 2337 else if (i.types[op] & Reg16) 2338 guess_suffix = WORD_MNEM_SUFFIX; 2339 else if (i.types[op] & Reg32) 2340 guess_suffix = LONG_MNEM_SUFFIX; 2341 else if (i.types[op] & Reg64) 2342 guess_suffix = QWORD_MNEM_SUFFIX; 2343 break; 2344 } 2345 } 2346 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) 2347 guess_suffix = WORD_MNEM_SUFFIX; 2348 2349 for (op = i.operands; --op >= 0;) 2350 if (i.types[op] & Imm) 2351 { 2352 switch (i.op[op].imms->X_op) 2353 { 2354 case O_constant: 2355 /* If a suffix is given, this operand may be shortened. */ 2356 switch (guess_suffix) 2357 { 2358 case LONG_MNEM_SUFFIX: 2359 i.types[op] |= Imm32 | Imm64; 2360 break; 2361 case WORD_MNEM_SUFFIX: 2362 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64; 2363 break; 2364 case BYTE_MNEM_SUFFIX: 2365 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64; 2366 break; 2367 } 2368 2369 /* If this operand is at most 16 bits, convert it 2370 to a signed 16 bit number before trying to see 2371 whether it will fit in an even smaller size. 2372 This allows a 16-bit operand such as $0xffe0 to 2373 be recognised as within Imm8S range. */ 2374 if ((i.types[op] & Imm16) 2375 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) 2376 { 2377 i.op[op].imms->X_add_number = 2378 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); 2379 } 2380 if ((i.types[op] & Imm32) 2381 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) 2382 == 0)) 2383 { 2384 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number 2385 ^ ((offsetT) 1 << 31)) 2386 - ((offsetT) 1 << 31)); 2387 } 2388 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number); 2389 2390 /* We must avoid matching of Imm32 templates when 64bit 2391 only immediate is available. */ 2392 if (guess_suffix == QWORD_MNEM_SUFFIX) 2393 i.types[op] &= ~Imm32; 2394 break; 2395 2396 case O_absent: 2397 case O_register: 2398 abort (); 2399 2400 /* Symbols and expressions. */ 2401 default: 2402 /* Convert symbolic operand to proper sizes for matching, but don't 2403 prevent matching a set of insns that only supports sizes other 2404 than those matching the insn suffix. */ 2405 { 2406 unsigned int mask, allowed = 0; 2407 const template *t; 2408 2409 for (t = current_templates->start; 2410 t < current_templates->end; 2411 ++t) 2412 allowed |= t->operand_types[op]; 2413 switch (guess_suffix) 2414 { 2415 case QWORD_MNEM_SUFFIX: 2416 mask = Imm64 | Imm32S; 2417 break; 2418 case LONG_MNEM_SUFFIX: 2419 mask = Imm32; 2420 break; 2421 case WORD_MNEM_SUFFIX: 2422 mask = Imm16; 2423 break; 2424 case BYTE_MNEM_SUFFIX: 2425 mask = Imm8; 2426 break; 2427 default: 2428 mask = 0; 2429 break; 2430 } 2431 if (mask & allowed) 2432 i.types[op] &= mask; 2433 } 2434 break; 2435 } 2436 } 2437} 2438 2439/* Try to use the smallest displacement type too. */ 2440static void 2441optimize_disp (void) 2442{ 2443 int op; 2444 2445 for (op = i.operands; --op >= 0;) 2446 if (i.types[op] & Disp) 2447 { 2448 if (i.op[op].disps->X_op == O_constant) 2449 { 2450 offsetT disp = i.op[op].disps->X_add_number; 2451 2452 if ((i.types[op] & Disp16) 2453 && (disp & ~(offsetT) 0xffff) == 0) 2454 { 2455 /* If this operand is at most 16 bits, convert 2456 to a signed 16 bit number and don't use 64bit 2457 displacement. */ 2458 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); 2459 i.types[op] &= ~Disp64; 2460 } 2461 if ((i.types[op] & Disp32) 2462 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0) 2463 { 2464 /* If this operand is at most 32 bits, convert 2465 to a signed 32 bit number and don't use 64bit 2466 displacement. */ 2467 disp &= (((offsetT) 2 << 31) - 1); 2468 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); 2469 i.types[op] &= ~Disp64; 2470 } 2471 if (!disp && (i.types[op] & BaseIndex)) 2472 { 2473 i.types[op] &= ~Disp; 2474 i.op[op].disps = 0; 2475 i.disp_operands--; 2476 } 2477 else if (flag_code == CODE_64BIT) 2478 { 2479 if (fits_in_signed_long (disp)) 2480 { 2481 i.types[op] &= ~Disp64; 2482 i.types[op] |= Disp32S; 2483 } 2484 if (fits_in_unsigned_long (disp)) 2485 i.types[op] |= Disp32; 2486 } 2487 if ((i.types[op] & (Disp32 | Disp32S | Disp16)) 2488 && fits_in_signed_byte (disp)) 2489 i.types[op] |= Disp8; 2490 } 2491 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL 2492 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) 2493 { 2494 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, 2495 i.op[op].disps, 0, i.reloc[op]); 2496 i.types[op] &= ~Disp; 2497 } 2498 else 2499 /* We only support 64bit displacement on constants. */ 2500 i.types[op] &= ~Disp64; 2501 } 2502} 2503 2504static int 2505match_template (void) 2506{ 2507 /* Points to template once we've found it. */ 2508 const template *t; 2509 unsigned int overlap0, overlap1, overlap2, overlap3; 2510 unsigned int found_reverse_match; 2511 int suffix_check; 2512 unsigned int operand_types [MAX_OPERANDS]; 2513 int addr_prefix_disp; 2514 unsigned int j; 2515 2516#if MAX_OPERANDS != 4 2517# error "MAX_OPERANDS must be 4." 2518#endif 2519 2520#define MATCH(overlap, given, template) \ 2521 ((overlap & ~JumpAbsolute) \ 2522 && (((given) & (BaseIndex | JumpAbsolute)) \ 2523 == ((overlap) & (BaseIndex | JumpAbsolute)))) 2524 2525 /* If given types r0 and r1 are registers they must be of the same type 2526 unless the expected operand type register overlap is null. 2527 Note that Acc in a template matches every size of reg. */ 2528#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ 2529 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \ 2530 || ((g0) & Reg) == ((g1) & Reg) \ 2531 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) 2532 2533 overlap0 = 0; 2534 overlap1 = 0; 2535 overlap2 = 0; 2536 overlap3 = 0; 2537 found_reverse_match = 0; 2538 for (j = 0; j < MAX_OPERANDS; j++) 2539 operand_types [j] = 0; 2540 addr_prefix_disp = -1; 2541 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX 2542 ? No_bSuf 2543 : (i.suffix == WORD_MNEM_SUFFIX 2544 ? No_wSuf 2545 : (i.suffix == SHORT_MNEM_SUFFIX 2546 ? No_sSuf 2547 : (i.suffix == LONG_MNEM_SUFFIX 2548 ? No_lSuf 2549 : (i.suffix == QWORD_MNEM_SUFFIX 2550 ? No_qSuf 2551 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX 2552 ? No_xSuf : 0)))))); 2553 2554 for (t = current_templates->start; t < current_templates->end; t++) 2555 { 2556 addr_prefix_disp = -1; 2557 2558 /* Must have right number of operands. */ 2559 if (i.operands != t->operands) 2560 continue; 2561 2562 /* Check the suffix, except for some instructions in intel mode. */ 2563 if ((t->opcode_modifier & suffix_check) 2564 && !(intel_syntax 2565 && (t->opcode_modifier & IgnoreSize))) 2566 continue; 2567 2568 for (j = 0; j < MAX_OPERANDS; j++) 2569 operand_types [j] = t->operand_types [j]; 2570 2571 /* In general, don't allow 64-bit operands in 32-bit mode. */ 2572 if (i.suffix == QWORD_MNEM_SUFFIX 2573 && flag_code != CODE_64BIT 2574 && (intel_syntax 2575 ? (!(t->opcode_modifier & IgnoreSize) 2576 && !intel_float_operand (t->name)) 2577 : intel_float_operand (t->name) != 2) 2578 && (!(operand_types[0] & (RegMMX | RegXMM)) 2579 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM))) 2580 && (t->base_opcode != 0x0fc7 2581 || t->extension_opcode != 1 /* cmpxchg8b */)) 2582 continue; 2583 2584 /* Do not verify operands when there are none. */ 2585 else if (!t->operands) 2586 { 2587 if (t->cpu_flags & ~cpu_arch_flags) 2588 continue; 2589 /* We've found a match; break out of loop. */ 2590 break; 2591 } 2592 2593 /* Address size prefix will turn Disp64/Disp32/Disp16 operand 2594 into Disp32/Disp16/Disp32 operand. */ 2595 if (i.prefix[ADDR_PREFIX] != 0) 2596 { 2597 unsigned int DispOn = 0, DispOff = 0; 2598 2599 switch (flag_code) 2600 { 2601 case CODE_16BIT: 2602 DispOn = Disp32; 2603 DispOff = Disp16; 2604 break; 2605 case CODE_32BIT: 2606 DispOn = Disp16; 2607 DispOff = Disp32; 2608 break; 2609 case CODE_64BIT: 2610 DispOn = Disp32; 2611 DispOff = Disp64; 2612 break; 2613 } 2614 2615 for (j = 0; j < MAX_OPERANDS; j++) 2616 { 2617 /* There should be only one Disp operand. */ 2618 if ((operand_types[j] & DispOff)) 2619 { 2620 addr_prefix_disp = j; 2621 operand_types[j] |= DispOn; 2622 operand_types[j] &= ~DispOff; 2623 break; 2624 } 2625 } 2626 } 2627 2628 overlap0 = i.types[0] & operand_types[0]; 2629 switch (t->operands) 2630 { 2631 case 1: 2632 if (!MATCH (overlap0, i.types[0], operand_types[0])) 2633 continue; 2634 break; 2635 case 2: 2636 /* xchg %eax, %eax is a special case. It is an aliase for nop 2637 only in 32bit mode and we can use opcode 0x90. In 64bit 2638 mode, we can't use 0x90 for xchg %eax, %eax since it should 2639 zero-extend %eax to %rax. */ 2640 if (flag_code == CODE_64BIT 2641 && t->base_opcode == 0x90 2642 && i.types [0] == (Acc | Reg32) 2643 && i.types [1] == (Acc | Reg32)) 2644 continue; 2645 case 3: 2646 case 4: 2647 overlap1 = i.types[1] & operand_types[1]; 2648 if (!MATCH (overlap0, i.types[0], operand_types[0]) 2649 || !MATCH (overlap1, i.types[1], operand_types[1]) 2650 /* monitor in SSE3 is a very special case. The first 2651 register and the second register may have different 2652 sizes. The same applies to crc32 in SSE4.2. */ 2653 || !((t->base_opcode == 0x0f01 2654 && t->extension_opcode == 0xc8) 2655 || t->base_opcode == 0xf20f38f1 2656 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], 2657 operand_types[0], 2658 overlap1, i.types[1], 2659 operand_types[1]))) 2660 { 2661 /* Check if other direction is valid ... */ 2662 if ((t->opcode_modifier & (D | FloatD)) == 0) 2663 continue; 2664 2665 /* Try reversing direction of operands. */ 2666 overlap0 = i.types[0] & operand_types[1]; 2667 overlap1 = i.types[1] & operand_types[0]; 2668 if (!MATCH (overlap0, i.types[0], operand_types[1]) 2669 || !MATCH (overlap1, i.types[1], operand_types[0]) 2670 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], 2671 operand_types[1], 2672 overlap1, i.types[1], 2673 operand_types[0])) 2674 { 2675 /* Does not match either direction. */ 2676 continue; 2677 } 2678 /* found_reverse_match holds which of D or FloatDR 2679 we've found. */ 2680 if ((t->opcode_modifier & D)) 2681 found_reverse_match = Opcode_D; 2682 else if ((t->opcode_modifier & FloatD)) 2683 found_reverse_match = Opcode_FloatD; 2684 else 2685 found_reverse_match = 0; 2686 if ((t->opcode_modifier & FloatR)) 2687 found_reverse_match |= Opcode_FloatR; 2688 } 2689 else 2690 { 2691 /* Found a forward 2 operand match here. */ 2692 switch (t->operands) 2693 { 2694 case 4: 2695 overlap3 = i.types[3] & operand_types[3]; 2696 case 3: 2697 overlap2 = i.types[2] & operand_types[2]; 2698 break; 2699 } 2700 2701 switch (t->operands) 2702 { 2703 case 4: 2704 if (!MATCH (overlap3, i.types[3], operand_types[3]) 2705 || !CONSISTENT_REGISTER_MATCH (overlap2, 2706 i.types[2], 2707 operand_types[2], 2708 overlap3, 2709 i.types[3], 2710 operand_types[3])) 2711 continue; 2712 case 3: 2713 /* Here we make use of the fact that there are no 2714 reverse match 3 operand instructions, and all 3 2715 operand instructions only need to be checked for 2716 register consistency between operands 2 and 3. */ 2717 if (!MATCH (overlap2, i.types[2], operand_types[2]) 2718 || !CONSISTENT_REGISTER_MATCH (overlap1, 2719 i.types[1], 2720 operand_types[1], 2721 overlap2, 2722 i.types[2], 2723 operand_types[2])) 2724 continue; 2725 break; 2726 } 2727 } 2728 /* Found either forward/reverse 2, 3 or 4 operand match here: 2729 slip through to break. */ 2730 } 2731 if (t->cpu_flags & ~cpu_arch_flags) 2732 { 2733 found_reverse_match = 0; 2734 continue; 2735 } 2736 /* We've found a match; break out of loop. */ 2737 break; 2738 } 2739 2740 if (t == current_templates->end) 2741 { 2742 /* We found no match. */ 2743 as_bad (_("suffix or operands invalid for `%s'"), 2744 current_templates->start->name); 2745 return 0; 2746 } 2747 2748 if (!quiet_warnings) 2749 { 2750 if (!intel_syntax 2751 && ((i.types[0] & JumpAbsolute) 2752 != (operand_types[0] & JumpAbsolute))) 2753 { 2754 as_warn (_("indirect %s without `*'"), t->name); 2755 } 2756 2757 if ((t->opcode_modifier & (IsPrefix | IgnoreSize)) 2758 == (IsPrefix | IgnoreSize)) 2759 { 2760 /* Warn them that a data or address size prefix doesn't 2761 affect assembly of the next line of code. */ 2762 as_warn (_("stand-alone `%s' prefix"), t->name); 2763 } 2764 } 2765 2766 /* Copy the template we found. */ 2767 i.tm = *t; 2768 2769 if (addr_prefix_disp != -1) 2770 i.tm.operand_types[addr_prefix_disp] 2771 = operand_types[addr_prefix_disp]; 2772 2773 if (found_reverse_match) 2774 { 2775 /* If we found a reverse match we must alter the opcode 2776 direction bit. found_reverse_match holds bits to change 2777 (different for int & float insns). */ 2778 2779 i.tm.base_opcode ^= found_reverse_match; 2780 2781 i.tm.operand_types[0] = operand_types[1]; 2782 i.tm.operand_types[1] = operand_types[0]; 2783 } 2784 2785 return 1; 2786} 2787 2788static int 2789check_string (void) 2790{ 2791 int mem_op = (i.types[0] & AnyMem) ? 0 : 1; 2792 if ((i.tm.operand_types[mem_op] & EsSeg) != 0) 2793 { 2794 if (i.seg[0] != NULL && i.seg[0] != &es) 2795 { 2796 as_bad (_("`%s' operand %d must use `%%es' segment"), 2797 i.tm.name, 2798 mem_op + 1); 2799 return 0; 2800 } 2801 /* There's only ever one segment override allowed per instruction. 2802 This instruction possibly has a legal segment override on the 2803 second operand, so copy the segment to where non-string 2804 instructions store it, allowing common code. */ 2805 i.seg[0] = i.seg[1]; 2806 } 2807 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) 2808 { 2809 if (i.seg[1] != NULL && i.seg[1] != &es) 2810 { 2811 as_bad (_("`%s' operand %d must use `%%es' segment"), 2812 i.tm.name, 2813 mem_op + 2); 2814 return 0; 2815 } 2816 } 2817 return 1; 2818} 2819 2820static int 2821process_suffix (void) 2822{ 2823 /* If matched instruction specifies an explicit instruction mnemonic 2824 suffix, use it. */ 2825 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64)) 2826 { 2827 if (i.tm.opcode_modifier & Size16) 2828 i.suffix = WORD_MNEM_SUFFIX; 2829 else if (i.tm.opcode_modifier & Size64) 2830 i.suffix = QWORD_MNEM_SUFFIX; 2831 else 2832 i.suffix = LONG_MNEM_SUFFIX; 2833 } 2834 else if (i.reg_operands) 2835 { 2836 /* If there's no instruction mnemonic suffix we try to invent one 2837 based on register operands. */ 2838 if (!i.suffix) 2839 { 2840 /* We take i.suffix from the last register operand specified, 2841 Destination register type is more significant than source 2842 register type. crc32 in SSE4.2 prefers source register 2843 type. */ 2844 if (i.tm.base_opcode == 0xf20f38f1) 2845 { 2846 if ((i.types[0] & Reg)) 2847 i.suffix = ((i.types[0] & Reg16) ? WORD_MNEM_SUFFIX : 2848 LONG_MNEM_SUFFIX); 2849 } 2850 else if (i.tm.base_opcode == 0xf20f38f0) 2851 { 2852 if ((i.types[0] & Reg8)) 2853 i.suffix = BYTE_MNEM_SUFFIX; 2854 } 2855 2856 if (!i.suffix) 2857 { 2858 int op; 2859 2860 if (i.tm.base_opcode == 0xf20f38f1 2861 || i.tm.base_opcode == 0xf20f38f0) 2862 { 2863 /* We have to know the operand size for crc32. */ 2864 as_bad (_("ambiguous memory operand size for `%s`"), 2865 i.tm.name); 2866 return 0; 2867 } 2868 2869 for (op = i.operands; --op >= 0;) 2870 if ((i.types[op] & Reg) 2871 && !(i.tm.operand_types[op] & InOutPortReg)) 2872 { 2873 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : 2874 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : 2875 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX : 2876 LONG_MNEM_SUFFIX); 2877 break; 2878 } 2879 } 2880 } 2881 else if (i.suffix == BYTE_MNEM_SUFFIX) 2882 { 2883 if (!check_byte_reg ()) 2884 return 0; 2885 } 2886 else if (i.suffix == LONG_MNEM_SUFFIX) 2887 { 2888 if (!check_long_reg ()) 2889 return 0; 2890 } 2891 else if (i.suffix == QWORD_MNEM_SUFFIX) 2892 { 2893 if (!check_qword_reg ()) 2894 return 0; 2895 } 2896 else if (i.suffix == WORD_MNEM_SUFFIX) 2897 { 2898 if (!check_word_reg ()) 2899 return 0; 2900 } 2901 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize)) 2902 /* Do nothing if the instruction is going to ignore the prefix. */ 2903 ; 2904 else 2905 abort (); 2906 } 2907 else if ((i.tm.opcode_modifier & DefaultSize) 2908 && !i.suffix 2909 /* exclude fldenv/frstor/fsave/fstenv */ 2910 && (i.tm.opcode_modifier & No_sSuf)) 2911 { 2912 i.suffix = stackop_size; 2913 } 2914 else if (intel_syntax 2915 && !i.suffix 2916 && ((i.tm.operand_types[0] & JumpAbsolute) 2917 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment)) 2918 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ 2919 && i.tm.extension_opcode <= 3))) 2920 { 2921 switch (flag_code) 2922 { 2923 case CODE_64BIT: 2924 if (!(i.tm.opcode_modifier & No_qSuf)) 2925 { 2926 i.suffix = QWORD_MNEM_SUFFIX; 2927 break; 2928 } 2929 case CODE_32BIT: 2930 if (!(i.tm.opcode_modifier & No_lSuf)) 2931 i.suffix = LONG_MNEM_SUFFIX; 2932 break; 2933 case CODE_16BIT: 2934 if (!(i.tm.opcode_modifier & No_wSuf)) 2935 i.suffix = WORD_MNEM_SUFFIX; 2936 break; 2937 } 2938 } 2939 2940 if (!i.suffix) 2941 { 2942 if (!intel_syntax) 2943 { 2944 if (i.tm.opcode_modifier & W) 2945 { 2946 as_bad (_("no instruction mnemonic suffix given and " 2947 "no register operands; can't size instruction")); 2948 return 0; 2949 } 2950 } 2951 else 2952 { 2953 unsigned int suffixes = (~i.tm.opcode_modifier 2954 & (No_bSuf 2955 | No_wSuf 2956 | No_lSuf 2957 | No_sSuf 2958 | No_xSuf 2959 | No_qSuf)); 2960 2961 if ((i.tm.opcode_modifier & W) 2962 || ((suffixes & (suffixes - 1)) 2963 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize)))) 2964 { 2965 as_bad (_("ambiguous operand size for `%s'"), i.tm.name); 2966 return 0; 2967 } 2968 } 2969 } 2970 2971 /* Change the opcode based on the operand size given by i.suffix; 2972 We don't need to change things for byte insns. */ 2973 2974 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) 2975 { 2976 /* It's not a byte, select word/dword operation. */ 2977 if (i.tm.opcode_modifier & W) 2978 { 2979 if (i.tm.opcode_modifier & ShortForm) 2980 i.tm.base_opcode |= 8; 2981 else 2982 i.tm.base_opcode |= 1; 2983 } 2984 2985 /* Now select between word & dword operations via the operand 2986 size prefix, except for instructions that will ignore this 2987 prefix anyway. */ 2988 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8) 2989 { 2990 /* monitor in SSE3 is a very special case. The default size 2991 of AX is the size of mode. The address size override 2992 prefix will change the size of AX. */ 2993 if (i.op->regs[0].reg_type & 2994 (flag_code == CODE_32BIT ? Reg16 : Reg32)) 2995 if (!add_prefix (ADDR_PREFIX_OPCODE)) 2996 return 0; 2997 } 2998 else if (i.suffix != QWORD_MNEM_SUFFIX 2999 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX 3000 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF)) 3001 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) 3002 || (flag_code == CODE_64BIT 3003 && (i.tm.opcode_modifier & JumpByte)))) 3004 { 3005 unsigned int prefix = DATA_PREFIX_OPCODE; 3006 3007 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ 3008 prefix = ADDR_PREFIX_OPCODE; 3009 3010 if (!add_prefix (prefix)) 3011 return 0; 3012 } 3013 3014 /* Set mode64 for an operand. */ 3015 if (i.suffix == QWORD_MNEM_SUFFIX 3016 && flag_code == CODE_64BIT 3017 && (i.tm.opcode_modifier & NoRex64) == 0) 3018 { 3019 /* Special case for xchg %rax,%rax. It is NOP and doesn't 3020 need rex64. */ 3021 if (i.operands != 2 3022 || i.types [0] != (Acc | Reg64) 3023 || i.types [1] != (Acc | Reg64) 3024 || i.tm.base_opcode != 0x90) 3025 i.rex |= REX_W; 3026 } 3027 3028 /* Size floating point instruction. */ 3029 if (i.suffix == LONG_MNEM_SUFFIX) 3030 if (i.tm.opcode_modifier & FloatMF) 3031 i.tm.base_opcode ^= 4; 3032 } 3033 3034 return 1; 3035} 3036 3037static int 3038check_byte_reg (void) 3039{ 3040 int op; 3041 3042 for (op = i.operands; --op >= 0;) 3043 { 3044 /* If this is an eight bit register, it's OK. If it's the 16 or 3045 32 bit version of an eight bit register, we will just use the 3046 low portion, and that's OK too. */ 3047 if (i.types[op] & Reg8) 3048 continue; 3049 3050 /* movzx and movsx should not generate this warning. */ 3051 if (intel_syntax 3052 && (i.tm.base_opcode == 0xfb7 3053 || i.tm.base_opcode == 0xfb6 3054 || i.tm.base_opcode == 0x63 3055 || i.tm.base_opcode == 0xfbe 3056 || i.tm.base_opcode == 0xfbf)) 3057 continue; 3058 3059 /* crc32 doesn't generate this warning. */ 3060 if (i.tm.base_opcode == 0xf20f38f0) 3061 continue; 3062 3063 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4) 3064 { 3065 /* Prohibit these changes in the 64bit mode, since the 3066 lowering is more complicated. */ 3067 if (flag_code == CODE_64BIT 3068 && (i.tm.operand_types[op] & InOutPortReg) == 0) 3069 { 3070 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), 3071 register_prefix, i.op[op].regs->reg_name, 3072 i.suffix); 3073 return 0; 3074 } 3075#if REGISTER_WARNINGS 3076 if (!quiet_warnings 3077 && (i.tm.operand_types[op] & InOutPortReg) == 0) 3078 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), 3079 register_prefix, 3080 (i.op[op].regs + (i.types[op] & Reg16 3081 ? REGNAM_AL - REGNAM_AX 3082 : REGNAM_AL - REGNAM_EAX))->reg_name, 3083 register_prefix, 3084 i.op[op].regs->reg_name, 3085 i.suffix); 3086#endif 3087 continue; 3088 } 3089 /* Any other register is bad. */ 3090 if (i.types[op] & (Reg | RegMMX | RegXMM 3091 | SReg2 | SReg3 3092 | Control | Debug | Test 3093 | FloatReg | FloatAcc)) 3094 { 3095 as_bad (_("`%s%s' not allowed with `%s%c'"), 3096 register_prefix, 3097 i.op[op].regs->reg_name, 3098 i.tm.name, 3099 i.suffix); 3100 return 0; 3101 } 3102 } 3103 return 1; 3104} 3105 3106static int 3107check_long_reg (void) 3108{ 3109 int op; 3110 3111 for (op = i.operands; --op >= 0;) 3112 /* Reject eight bit registers, except where the template requires 3113 them. (eg. movzb) */ 3114 if ((i.types[op] & Reg8) != 0 3115 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) 3116 { 3117 as_bad (_("`%s%s' not allowed with `%s%c'"), 3118 register_prefix, 3119 i.op[op].regs->reg_name, 3120 i.tm.name, 3121 i.suffix); 3122 return 0; 3123 } 3124 /* Warn if the e prefix on a general reg is missing. */ 3125 else if ((!quiet_warnings || flag_code == CODE_64BIT) 3126 && (i.types[op] & Reg16) != 0 3127 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) 3128 { 3129 /* Prohibit these changes in the 64bit mode, since the 3130 lowering is more complicated. */ 3131 if (flag_code == CODE_64BIT) 3132 { 3133 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), 3134 register_prefix, i.op[op].regs->reg_name, 3135 i.suffix); 3136 return 0; 3137 } 3138#if REGISTER_WARNINGS 3139 else 3140 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), 3141 register_prefix, 3142 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, 3143 register_prefix, 3144 i.op[op].regs->reg_name, 3145 i.suffix); 3146#endif 3147 } 3148 /* Warn if the r prefix on a general reg is missing. */ 3149 else if ((i.types[op] & Reg64) != 0 3150 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) 3151 { 3152 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), 3153 register_prefix, i.op[op].regs->reg_name, 3154 i.suffix); 3155 return 0; 3156 } 3157 return 1; 3158} 3159 3160static int 3161check_qword_reg (void) 3162{ 3163 int op; 3164 3165 for (op = i.operands; --op >= 0; ) 3166 /* Reject eight bit registers, except where the template requires 3167 them. (eg. movzb) */ 3168 if ((i.types[op] & Reg8) != 0 3169 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) 3170 { 3171 as_bad (_("`%s%s' not allowed with `%s%c'"), 3172 register_prefix, 3173 i.op[op].regs->reg_name, 3174 i.tm.name, 3175 i.suffix); 3176 return 0; 3177 } 3178 /* Warn if the e prefix on a general reg is missing. */ 3179 else if (((i.types[op] & Reg16) != 0 3180 || (i.types[op] & Reg32) != 0) 3181 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) 3182 { 3183 /* Prohibit these changes in the 64bit mode, since the 3184 lowering is more complicated. */ 3185 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), 3186 register_prefix, i.op[op].regs->reg_name, 3187 i.suffix); 3188 return 0; 3189 } 3190 return 1; 3191} 3192 3193static int 3194check_word_reg (void) 3195{ 3196 int op; 3197 for (op = i.operands; --op >= 0;) 3198 /* Reject eight bit registers, except where the template requires 3199 them. (eg. movzb) */ 3200 if ((i.types[op] & Reg8) != 0 3201 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) 3202 { 3203 as_bad (_("`%s%s' not allowed with `%s%c'"), 3204 register_prefix, 3205 i.op[op].regs->reg_name, 3206 i.tm.name, 3207 i.suffix); 3208 return 0; 3209 } 3210 /* Warn if the e prefix on a general reg is present. */ 3211 else if ((!quiet_warnings || flag_code == CODE_64BIT) 3212 && (i.types[op] & Reg32) != 0 3213 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0) 3214 { 3215 /* Prohibit these changes in the 64bit mode, since the 3216 lowering is more complicated. */ 3217 if (flag_code == CODE_64BIT) 3218 { 3219 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), 3220 register_prefix, i.op[op].regs->reg_name, 3221 i.suffix); 3222 return 0; 3223 } 3224 else 3225#if REGISTER_WARNINGS 3226 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), 3227 register_prefix, 3228 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, 3229 register_prefix, 3230 i.op[op].regs->reg_name, 3231 i.suffix); 3232#endif 3233 } 3234 return 1; 3235} 3236 3237static int 3238finalize_imm (void) 3239{ 3240 unsigned int overlap0, overlap1, overlap2; 3241 3242 overlap0 = i.types[0] & i.tm.operand_types[0]; 3243 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64)) 3244 && overlap0 != Imm8 && overlap0 != Imm8S 3245 && overlap0 != Imm16 && overlap0 != Imm32S 3246 && overlap0 != Imm32 && overlap0 != Imm64) 3247 { 3248 if (i.suffix) 3249 { 3250 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX 3251 ? Imm8 | Imm8S 3252 : (i.suffix == WORD_MNEM_SUFFIX 3253 ? Imm16 3254 : (i.suffix == QWORD_MNEM_SUFFIX 3255 ? Imm64 | Imm32S 3256 : Imm32))); 3257 } 3258 else if (overlap0 == (Imm16 | Imm32S | Imm32) 3259 || overlap0 == (Imm16 | Imm32) 3260 || overlap0 == (Imm16 | Imm32S)) 3261 { 3262 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0) 3263 ? Imm16 : Imm32S); 3264 } 3265 if (overlap0 != Imm8 && overlap0 != Imm8S 3266 && overlap0 != Imm16 && overlap0 != Imm32S 3267 && overlap0 != Imm32 && overlap0 != Imm64) 3268 { 3269 as_bad (_("no instruction mnemonic suffix given; " 3270 "can't determine immediate size")); 3271 return 0; 3272 } 3273 } 3274 i.types[0] = overlap0; 3275 3276 overlap1 = i.types[1] & i.tm.operand_types[1]; 3277 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64)) 3278 && overlap1 != Imm8 && overlap1 != Imm8S 3279 && overlap1 != Imm16 && overlap1 != Imm32S 3280 && overlap1 != Imm32 && overlap1 != Imm64) 3281 { 3282 if (i.suffix) 3283 { 3284 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX 3285 ? Imm8 | Imm8S 3286 : (i.suffix == WORD_MNEM_SUFFIX 3287 ? Imm16 3288 : (i.suffix == QWORD_MNEM_SUFFIX 3289 ? Imm64 | Imm32S 3290 : Imm32))); 3291 } 3292 else if (overlap1 == (Imm16 | Imm32 | Imm32S) 3293 || overlap1 == (Imm16 | Imm32) 3294 || overlap1 == (Imm16 | Imm32S)) 3295 { 3296 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0) 3297 ? Imm16 : Imm32S); 3298 } 3299 if (overlap1 != Imm8 && overlap1 != Imm8S 3300 && overlap1 != Imm16 && overlap1 != Imm32S 3301 && overlap1 != Imm32 && overlap1 != Imm64) 3302 { 3303 as_bad (_("no instruction mnemonic suffix given; " 3304 "can't determine immediate size %x %c"), 3305 overlap1, i.suffix); 3306 return 0; 3307 } 3308 } 3309 i.types[1] = overlap1; 3310 3311 overlap2 = i.types[2] & i.tm.operand_types[2]; 3312 assert ((overlap2 & Imm) == 0); 3313 i.types[2] = overlap2; 3314 3315 return 1; 3316} 3317 3318static int 3319process_operands (void) 3320{ 3321 /* Default segment register this instruction will use for memory 3322 accesses. 0 means unknown. This is only for optimizing out 3323 unnecessary segment overrides. */ 3324 const seg_entry *default_seg = 0; 3325 3326 /* The imul $imm, %reg instruction is converted into 3327 imul $imm, %reg, %reg, and the clr %reg instruction 3328 is converted into xor %reg, %reg. */ 3329 if (i.tm.opcode_modifier & RegKludge) 3330 { 3331 if ((i.tm.cpu_flags & CpuSSE4_1)) 3332 { 3333 /* The first operand in instruction blendvpd, blendvps and 3334 pblendvb in SSE4.1 is implicit and must be xmm0. */ 3335 assert (i.operands == 3 3336 && i.reg_operands >= 2 3337 && i.types[0] == RegXMM); 3338 if (i.op[0].regs->reg_num != 0) 3339 { 3340 if (intel_syntax) 3341 as_bad (_("the last operand of `%s' must be `%sxmm0'"), 3342 i.tm.name, register_prefix); 3343 else 3344 as_bad (_("the first operand of `%s' must be `%sxmm0'"), 3345 i.tm.name, register_prefix); 3346 return 0; 3347 } 3348 i.op[0] = i.op[1]; 3349 i.op[1] = i.op[2]; 3350 i.types[0] = i.types[1]; 3351 i.types[1] = i.types[2]; 3352 i.operands--; 3353 i.reg_operands--; 3354 3355 /* We need to adjust fields in i.tm since they are used by 3356 build_modrm_byte. */ 3357 i.tm.operand_types [0] = i.tm.operand_types [1]; 3358 i.tm.operand_types [1] = i.tm.operand_types [2]; 3359 i.tm.operands--; 3360 } 3361 else 3362 { 3363 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; 3364 /* Pretend we saw the extra register operand. */ 3365 assert (i.reg_operands == 1 3366 && i.op[first_reg_op + 1].regs == 0); 3367 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; 3368 i.types[first_reg_op + 1] = i.types[first_reg_op]; 3369 i.operands++; 3370 i.reg_operands++; 3371 } 3372 } 3373 3374 if (i.tm.opcode_modifier & ShortForm) 3375 { 3376 if (i.types[0] & (SReg2 | SReg3)) 3377 { 3378 if (i.tm.base_opcode == POP_SEG_SHORT 3379 && i.op[0].regs->reg_num == 1) 3380 { 3381 as_bad (_("you can't `pop %%cs'")); 3382 return 0; 3383 } 3384 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); 3385 if ((i.op[0].regs->reg_flags & RegRex) != 0) 3386 i.rex |= REX_B; 3387 } 3388 else 3389 { 3390 /* The register or float register operand is in operand 0 or 1. */ 3391 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; 3392 /* Register goes in low 3 bits of opcode. */ 3393 i.tm.base_opcode |= i.op[op].regs->reg_num; 3394 if ((i.op[op].regs->reg_flags & RegRex) != 0) 3395 i.rex |= REX_B; 3396 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) 3397 { 3398 /* Warn about some common errors, but press on regardless. 3399 The first case can be generated by gcc (<= 2.8.1). */ 3400 if (i.operands == 2) 3401 { 3402 /* Reversed arguments on faddp, fsubp, etc. */ 3403 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, 3404 register_prefix, i.op[1].regs->reg_name, 3405 register_prefix, i.op[0].regs->reg_name); 3406 } 3407 else 3408 { 3409 /* Extraneous `l' suffix on fp insn. */ 3410 as_warn (_("translating to `%s %s%s'"), i.tm.name, 3411 register_prefix, i.op[0].regs->reg_name); 3412 } 3413 } 3414 } 3415 } 3416 else if (i.tm.opcode_modifier & Modrm) 3417 { 3418 /* The opcode is completed (modulo i.tm.extension_opcode which 3419 must be put into the modrm byte). Now, we make the modrm and 3420 index base bytes based on all the info we've collected. */ 3421 3422 default_seg = build_modrm_byte (); 3423 } 3424 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) 3425 { 3426 default_seg = &ds; 3427 } 3428 else if ((i.tm.opcode_modifier & IsString) != 0) 3429 { 3430 /* For the string instructions that allow a segment override 3431 on one of their operands, the default segment is ds. */ 3432 default_seg = &ds; 3433 } 3434 3435 if ((i.tm.base_opcode == 0x8d /* lea */ 3436 || (i.tm.cpu_flags & CpuSVME)) 3437 && i.seg[0] && !quiet_warnings) 3438 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); 3439 3440 /* If a segment was explicitly specified, and the specified segment 3441 is not the default, use an opcode prefix to select it. If we 3442 never figured out what the default segment is, then default_seg 3443 will be zero at this point, and the specified segment prefix will 3444 always be used. */ 3445 if ((i.seg[0]) && (i.seg[0] != default_seg)) 3446 { 3447 if (!add_prefix (i.seg[0]->seg_prefix)) 3448 return 0; 3449 } 3450 return 1; 3451} 3452 3453static const seg_entry * 3454build_modrm_byte (void) 3455{ 3456 const seg_entry *default_seg = 0; 3457 3458 /* i.reg_operands MUST be the number of real register operands; 3459 implicit registers do not count. */ 3460 if (i.reg_operands == 2) 3461 { 3462 unsigned int source, dest; 3463 3464 switch (i.operands) 3465 { 3466 case 2: 3467 source = 0; 3468 break; 3469 case 3: 3470 /* When there are 3 operands, one of them may be immediate, 3471 which may be the first or the last operand. Otherwise, 3472 the first operand must be shift count register (cl). */ 3473 assert (i.imm_operands == 1 3474 || (i.imm_operands == 0 3475 && (i.types[0] & ShiftCount))); 3476 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0; 3477 break; 3478 case 4: 3479 /* When there are 4 operands, the first two must be immediate 3480 operands. The source operand will be the 3rd one. */ 3481 assert (i.imm_operands == 2 3482 && (i.types[0] & Imm) 3483 && (i.types[1] & Imm)); 3484 source = 2; 3485 break; 3486 default: 3487 abort (); 3488 } 3489 3490 dest = source + 1; 3491 3492 i.rm.mode = 3; 3493 /* One of the register operands will be encoded in the i.tm.reg 3494 field, the other in the combined i.tm.mode and i.tm.regmem 3495 fields. If no form of this instruction supports a memory 3496 destination operand, then we assume the source operand may 3497 sometimes be a memory operand and so we need to store the 3498 destination in the i.rm.reg field. */ 3499 if ((i.tm.operand_types[dest] & (AnyMem | RegMem)) == 0) 3500 { 3501 i.rm.reg = i.op[dest].regs->reg_num; 3502 i.rm.regmem = i.op[source].regs->reg_num; 3503 if ((i.op[dest].regs->reg_flags & RegRex) != 0) 3504 i.rex |= REX_R; 3505 if ((i.op[source].regs->reg_flags & RegRex) != 0) 3506 i.rex |= REX_B; 3507 } 3508 else 3509 { 3510 i.rm.reg = i.op[source].regs->reg_num; 3511 i.rm.regmem = i.op[dest].regs->reg_num; 3512 if ((i.op[dest].regs->reg_flags & RegRex) != 0) 3513 i.rex |= REX_B; 3514 if ((i.op[source].regs->reg_flags & RegRex) != 0) 3515 i.rex |= REX_R; 3516 } 3517 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) 3518 { 3519 if (!((i.types[0] | i.types[1]) & Control)) 3520 abort (); 3521 i.rex &= ~(REX_R | REX_B); 3522 add_prefix (LOCK_PREFIX_OPCODE); 3523 } 3524 } 3525 else 3526 { /* If it's not 2 reg operands... */ 3527 if (i.mem_operands) 3528 { 3529 unsigned int fake_zero_displacement = 0; 3530 unsigned int op; 3531 3532 for (op = 0; op < i.operands; op++) 3533 if ((i.types[op] & AnyMem)) 3534 break; 3535 assert (op < i.operands); 3536 3537 default_seg = &ds; 3538 3539 if (i.base_reg == 0) 3540 { 3541 i.rm.mode = 0; 3542 if (!i.disp_operands) 3543 fake_zero_displacement = 1; 3544 if (i.index_reg == 0) 3545 { 3546 /* Operand is just <disp> */ 3547 if (flag_code == CODE_64BIT) 3548 { 3549 /* 64bit mode overwrites the 32bit absolute 3550 addressing by RIP relative addressing and 3551 absolute addressing is encoded by one of the 3552 redundant SIB forms. */ 3553 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 3554 i.sib.base = NO_BASE_REGISTER; 3555 i.sib.index = NO_INDEX_REGISTER; 3556 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) 3557 ? Disp32S : Disp32); 3558 } 3559 else if ((flag_code == CODE_16BIT) 3560 ^ (i.prefix[ADDR_PREFIX] != 0)) 3561 { 3562 i.rm.regmem = NO_BASE_REGISTER_16; 3563 i.types[op] = Disp16; 3564 } 3565 else 3566 { 3567 i.rm.regmem = NO_BASE_REGISTER; 3568 i.types[op] = Disp32; 3569 } 3570 } 3571 else /* !i.base_reg && i.index_reg */ 3572 { 3573 i.sib.index = i.index_reg->reg_num; 3574 i.sib.base = NO_BASE_REGISTER; 3575 i.sib.scale = i.log2_scale_factor; 3576 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 3577 i.types[op] &= ~Disp; 3578 if (flag_code != CODE_64BIT) 3579 i.types[op] |= Disp32; /* Must be 32 bit */ 3580 else 3581 i.types[op] |= Disp32S; 3582 if ((i.index_reg->reg_flags & RegRex) != 0) 3583 i.rex |= REX_X; 3584 } 3585 } 3586 /* RIP addressing for 64bit mode. */ 3587 else if (i.base_reg->reg_type == BaseIndex) 3588 { 3589 i.rm.regmem = NO_BASE_REGISTER; 3590 i.types[op] &= ~ Disp; 3591 i.types[op] |= Disp32S; 3592 i.flags[op] |= Operand_PCrel; 3593 if (! i.disp_operands) 3594 fake_zero_displacement = 1; 3595 } 3596 else if (i.base_reg->reg_type & Reg16) 3597 { 3598 switch (i.base_reg->reg_num) 3599 { 3600 case 3: /* (%bx) */ 3601 if (i.index_reg == 0) 3602 i.rm.regmem = 7; 3603 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ 3604 i.rm.regmem = i.index_reg->reg_num - 6; 3605 break; 3606 case 5: /* (%bp) */ 3607 default_seg = &ss; 3608 if (i.index_reg == 0) 3609 { 3610 i.rm.regmem = 6; 3611 if ((i.types[op] & Disp) == 0) 3612 { 3613 /* fake (%bp) into 0(%bp) */ 3614 i.types[op] |= Disp8; 3615 fake_zero_displacement = 1; 3616 } 3617 } 3618 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ 3619 i.rm.regmem = i.index_reg->reg_num - 6 + 2; 3620 break; 3621 default: /* (%si) -> 4 or (%di) -> 5 */ 3622 i.rm.regmem = i.base_reg->reg_num - 6 + 4; 3623 } 3624 i.rm.mode = mode_from_disp_size (i.types[op]); 3625 } 3626 else /* i.base_reg and 32/64 bit mode */ 3627 { 3628 if (flag_code == CODE_64BIT 3629 && (i.types[op] & Disp)) 3630 i.types[op] = ((i.types[op] & Disp8) 3631 | (i.prefix[ADDR_PREFIX] == 0 3632 ? Disp32S : Disp32)); 3633 3634 i.rm.regmem = i.base_reg->reg_num; 3635 if ((i.base_reg->reg_flags & RegRex) != 0) 3636 i.rex |= REX_B; 3637 i.sib.base = i.base_reg->reg_num; 3638 /* x86-64 ignores REX prefix bit here to avoid decoder 3639 complications. */ 3640 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) 3641 { 3642 default_seg = &ss; 3643 if (i.disp_operands == 0) 3644 { 3645 fake_zero_displacement = 1; 3646 i.types[op] |= Disp8; 3647 } 3648 } 3649 else if (i.base_reg->reg_num == ESP_REG_NUM) 3650 { 3651 default_seg = &ss; 3652 } 3653 i.sib.scale = i.log2_scale_factor; 3654 if (i.index_reg == 0) 3655 { 3656 /* <disp>(%esp) becomes two byte modrm with no index 3657 register. We've already stored the code for esp 3658 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. 3659 Any base register besides %esp will not use the 3660 extra modrm byte. */ 3661 i.sib.index = NO_INDEX_REGISTER; 3662#if !SCALE1_WHEN_NO_INDEX 3663 /* Another case where we force the second modrm byte. */ 3664 if (i.log2_scale_factor) 3665 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 3666#endif 3667 } 3668 else 3669 { 3670 i.sib.index = i.index_reg->reg_num; 3671 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 3672 if ((i.index_reg->reg_flags & RegRex) != 0) 3673 i.rex |= REX_X; 3674 } 3675 3676 if (i.disp_operands 3677 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL 3678 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) 3679 i.rm.mode = 0; 3680 else 3681 i.rm.mode = mode_from_disp_size (i.types[op]); 3682 } 3683 3684 if (fake_zero_displacement) 3685 { 3686 /* Fakes a zero displacement assuming that i.types[op] 3687 holds the correct displacement size. */ 3688 expressionS *exp; 3689 3690 assert (i.op[op].disps == 0); 3691 exp = &disp_expressions[i.disp_operands++]; 3692 i.op[op].disps = exp; 3693 exp->X_op = O_constant; 3694 exp->X_add_number = 0; 3695 exp->X_add_symbol = (symbolS *) 0; 3696 exp->X_op_symbol = (symbolS *) 0; 3697 } 3698 } 3699 3700 /* Fill in i.rm.reg or i.rm.regmem field with register operand 3701 (if any) based on i.tm.extension_opcode. Again, we must be 3702 careful to make sure that segment/control/debug/test/MMX 3703 registers are coded into the i.rm.reg field. */ 3704 if (i.reg_operands) 3705 { 3706 unsigned int op; 3707 3708 for (op = 0; op < i.operands; op++) 3709 if ((i.types[op] & (Reg | RegMMX | RegXMM 3710 | SReg2 | SReg3 3711 | Control | Debug | Test))) 3712 break; 3713 assert (op < i.operands); 3714 3715 /* If there is an extension opcode to put here, the register 3716 number must be put into the regmem field. */ 3717 if (i.tm.extension_opcode != None) 3718 { 3719 i.rm.regmem = i.op[op].regs->reg_num; 3720 if ((i.op[op].regs->reg_flags & RegRex) != 0) 3721 i.rex |= REX_B; 3722 } 3723 else 3724 { 3725 i.rm.reg = i.op[op].regs->reg_num; 3726 if ((i.op[op].regs->reg_flags & RegRex) != 0) 3727 i.rex |= REX_R; 3728 } 3729 3730 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we 3731 must set it to 3 to indicate this is a register operand 3732 in the regmem field. */ 3733 if (!i.mem_operands) 3734 i.rm.mode = 3; 3735 } 3736 3737 /* Fill in i.rm.reg field with extension opcode (if any). */ 3738 if (i.tm.extension_opcode != None) 3739 i.rm.reg = i.tm.extension_opcode; 3740 } 3741 return default_seg; 3742} 3743 3744static void 3745output_branch (void) 3746{ 3747 char *p; 3748 int code16; 3749 int prefix; 3750 relax_substateT subtype; 3751 symbolS *sym; 3752 offsetT off; 3753 3754 code16 = 0; 3755 if (flag_code == CODE_16BIT) 3756 code16 = CODE16; 3757 3758 prefix = 0; 3759 if (i.prefix[DATA_PREFIX] != 0) 3760 { 3761 prefix = 1; 3762 i.prefixes -= 1; 3763 code16 ^= CODE16; 3764 } 3765 /* Pentium4 branch hints. */ 3766 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ 3767 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) 3768 { 3769 prefix++; 3770 i.prefixes--; 3771 } 3772 if (i.prefix[REX_PREFIX] != 0) 3773 { 3774 prefix++; 3775 i.prefixes--; 3776 } 3777 3778 if (i.prefixes != 0 && !intel_syntax) 3779 as_warn (_("skipping prefixes on this instruction")); 3780 3781 /* It's always a symbol; End frag & setup for relax. 3782 Make sure there is enough room in this frag for the largest 3783 instruction we may generate in md_convert_frag. This is 2 3784 bytes for the opcode and room for the prefix and largest 3785 displacement. */ 3786 frag_grow (prefix + 2 + 4); 3787 /* Prefix and 1 opcode byte go in fr_fix. */ 3788 p = frag_more (prefix + 1); 3789 if (i.prefix[DATA_PREFIX] != 0) 3790 *p++ = DATA_PREFIX_OPCODE; 3791 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE 3792 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) 3793 *p++ = i.prefix[SEG_PREFIX]; 3794 if (i.prefix[REX_PREFIX] != 0) 3795 *p++ = i.prefix[REX_PREFIX]; 3796 *p = i.tm.base_opcode; 3797 3798 if ((unsigned char) *p == JUMP_PC_RELATIVE) 3799 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL); 3800 else if ((cpu_arch_flags & Cpu386) != 0) 3801 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL); 3802 else 3803 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL); 3804 subtype |= code16; 3805 3806 sym = i.op[0].disps->X_add_symbol; 3807 off = i.op[0].disps->X_add_number; 3808 3809 if (i.op[0].disps->X_op != O_constant 3810 && i.op[0].disps->X_op != O_symbol) 3811 { 3812 /* Handle complex expressions. */ 3813 sym = make_expr_symbol (i.op[0].disps); 3814 off = 0; 3815 } 3816 3817 /* 1 possible extra opcode + 4 byte displacement go in var part. 3818 Pass reloc in fr_var. */ 3819 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); 3820} 3821 3822static void 3823output_jump (void) 3824{ 3825 char *p; 3826 int size; 3827 fixS *fixP; 3828 3829 if (i.tm.opcode_modifier & JumpByte) 3830 { 3831 /* This is a loop or jecxz type instruction. */ 3832 size = 1; 3833 if (i.prefix[ADDR_PREFIX] != 0) 3834 { 3835 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); 3836 i.prefixes -= 1; 3837 } 3838 /* Pentium4 branch hints. */ 3839 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ 3840 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) 3841 { 3842 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); 3843 i.prefixes--; 3844 } 3845 } 3846 else 3847 { 3848 int code16; 3849 3850 code16 = 0; 3851 if (flag_code == CODE_16BIT) 3852 code16 = CODE16; 3853 3854 if (i.prefix[DATA_PREFIX] != 0) 3855 { 3856 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); 3857 i.prefixes -= 1; 3858 code16 ^= CODE16; 3859 } 3860 3861 size = 4; 3862 if (code16) 3863 size = 2; 3864 } 3865 3866 if (i.prefix[REX_PREFIX] != 0) 3867 { 3868 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); 3869 i.prefixes -= 1; 3870 } 3871 3872 if (i.prefixes != 0 && !intel_syntax) 3873 as_warn (_("skipping prefixes on this instruction")); 3874 3875 p = frag_more (1 + size); 3876 *p++ = i.tm.base_opcode; 3877 3878 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, 3879 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); 3880 3881 /* All jumps handled here are signed, but don't use a signed limit 3882 check for 32 and 16 bit jumps as we want to allow wrap around at 3883 4G and 64k respectively. */ 3884 if (size == 1) 3885 fixP->fx_signed = 1; 3886} 3887 3888static void 3889output_interseg_jump (void) 3890{ 3891 char *p; 3892 int size; 3893 int prefix; 3894 int code16; 3895 3896 code16 = 0; 3897 if (flag_code == CODE_16BIT) 3898 code16 = CODE16; 3899 3900 prefix = 0; 3901 if (i.prefix[DATA_PREFIX] != 0) 3902 { 3903 prefix = 1; 3904 i.prefixes -= 1; 3905 code16 ^= CODE16; 3906 } 3907 if (i.prefix[REX_PREFIX] != 0) 3908 { 3909 prefix++; 3910 i.prefixes -= 1; 3911 } 3912 3913 size = 4; 3914 if (code16) 3915 size = 2; 3916 3917 if (i.prefixes != 0 && !intel_syntax) 3918 as_warn (_("skipping prefixes on this instruction")); 3919 3920 /* 1 opcode; 2 segment; offset */ 3921 p = frag_more (prefix + 1 + 2 + size); 3922 3923 if (i.prefix[DATA_PREFIX] != 0) 3924 *p++ = DATA_PREFIX_OPCODE; 3925 3926 if (i.prefix[REX_PREFIX] != 0) 3927 *p++ = i.prefix[REX_PREFIX]; 3928 3929 *p++ = i.tm.base_opcode; 3930 if (i.op[1].imms->X_op == O_constant) 3931 { 3932 offsetT n = i.op[1].imms->X_add_number; 3933 3934 if (size == 2 3935 && !fits_in_unsigned_word (n) 3936 && !fits_in_signed_word (n)) 3937 { 3938 as_bad (_("16-bit jump out of range")); 3939 return; 3940 } 3941 md_number_to_chars (p, n, size); 3942 } 3943 else 3944 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 3945 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); 3946 if (i.op[0].imms->X_op != O_constant) 3947 as_bad (_("can't handle non absolute segment in `%s'"), 3948 i.tm.name); 3949 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); 3950} 3951 3952static void 3953output_insn (void) 3954{ 3955 fragS *insn_start_frag; 3956 offsetT insn_start_off; 3957 3958 /* Tie dwarf2 debug info to the address at the start of the insn. 3959 We can't do this after the insn has been output as the current 3960 frag may have been closed off. eg. by frag_var. */ 3961 dwarf2_emit_insn (0); 3962 3963 insn_start_frag = frag_now; 3964 insn_start_off = frag_now_fix (); 3965 3966 /* Output jumps. */ 3967 if (i.tm.opcode_modifier & Jump) 3968 output_branch (); 3969 else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) 3970 output_jump (); 3971 else if (i.tm.opcode_modifier & JumpInterSegment) 3972 output_interseg_jump (); 3973 else 3974 { 3975 /* Output normal instructions here. */ 3976 char *p; 3977 unsigned char *q; 3978 unsigned int prefix; 3979 3980 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and 3981 SSE4 instructions have 3 bytes. We may use one more higher 3982 byte to specify a prefix the instruction requires. Exclude 3983 instructions which are in both SSE4 and ABM. */ 3984 if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4 | CpuAES | CpuPCLMUL)) != 0 3985 && (i.tm.cpu_flags & CpuABM) == 0) 3986 { 3987 if (i.tm.base_opcode & 0xff000000) 3988 { 3989 prefix = (i.tm.base_opcode >> 24) & 0xff; 3990 goto check_prefix; 3991 } 3992 } 3993 else if (i.tm.base_opcode == 0x660f3880 || i.tm.base_opcode == 0x660f3881 3994 || i.tm.base_opcode == 0x660f3882) 3995 { 3996 /* invept and invvpid are 3 byte instructions with a 3997 mandatory prefix. */ 3998 if (i.tm.base_opcode & 0xff000000) 3999 { 4000 prefix = (i.tm.base_opcode >> 24) & 0xff; 4001 add_prefix (prefix); 4002 } 4003 } 4004 else if ((i.tm.base_opcode & 0xff0000) != 0) 4005 { 4006 prefix = (i.tm.base_opcode >> 16) & 0xff; 4007 if ((i.tm.cpu_flags & CpuPadLock) != 0) 4008 { 4009 check_prefix: 4010 if (prefix != REPE_PREFIX_OPCODE 4011 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE) 4012 add_prefix (prefix); 4013 } 4014 else 4015 add_prefix (prefix); 4016 } 4017 4018 /* The prefix bytes. */ 4019 for (q = i.prefix; 4020 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); 4021 q++) 4022 { 4023 if (*q) 4024 { 4025 p = frag_more (1); 4026 md_number_to_chars (p, (valueT) *q, 1); 4027 } 4028 } 4029 4030 /* Now the opcode; be careful about word order here! */ 4031 if (fits_in_unsigned_byte (i.tm.base_opcode)) 4032 { 4033 FRAG_APPEND_1_CHAR (i.tm.base_opcode); 4034 } 4035 else 4036 { 4037 if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4 | CpuAES | CpuPCLMUL)) != 0 4038 && (i.tm.cpu_flags & CpuABM) == 0) 4039 { 4040 p = frag_more (3); 4041 *p++ = (i.tm.base_opcode >> 16) & 0xff; 4042 } 4043 else if (i.tm.base_opcode == 0x660f3880 || 4044 i.tm.base_opcode == 0x660f3881 || 4045 i.tm.base_opcode == 0x660f3882) 4046 { 4047 p = frag_more (3); 4048 *p++ = (i.tm.base_opcode >> 16) & 0xff; 4049 } 4050 else 4051 p = frag_more (2); 4052 4053 /* Put out high byte first: can't use md_number_to_chars! */ 4054 *p++ = (i.tm.base_opcode >> 8) & 0xff; 4055 *p = i.tm.base_opcode & 0xff; 4056 } 4057 4058 /* Now the modrm byte and sib byte (if present). */ 4059 if (i.tm.opcode_modifier & Modrm) 4060 { 4061 p = frag_more (1); 4062 md_number_to_chars (p, 4063 (valueT) (i.rm.regmem << 0 4064 | i.rm.reg << 3 4065 | i.rm.mode << 6), 4066 1); 4067 /* If i.rm.regmem == ESP (4) 4068 && i.rm.mode != (Register mode) 4069 && not 16 bit 4070 ==> need second modrm byte. */ 4071 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING 4072 && i.rm.mode != 3 4073 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) 4074 { 4075 p = frag_more (1); 4076 md_number_to_chars (p, 4077 (valueT) (i.sib.base << 0 4078 | i.sib.index << 3 4079 | i.sib.scale << 6), 4080 1); 4081 } 4082 } 4083 4084 if (i.disp_operands) 4085 output_disp (insn_start_frag, insn_start_off); 4086 4087 if (i.imm_operands) 4088 output_imm (insn_start_frag, insn_start_off); 4089 } 4090 4091#ifdef DEBUG386 4092 if (flag_debug) 4093 { 4094 pi ("" /*line*/, &i); 4095 } 4096#endif /* DEBUG386 */ 4097} 4098 4099/* Return the size of the displacement operand N. */ 4100 4101static int 4102disp_size (unsigned int n) 4103{ 4104 int size = 4; 4105 if (i.types[n] & (Disp8 | Disp16 | Disp64)) 4106 { 4107 size = 2; 4108 if (i.types[n] & Disp8) 4109 size = 1; 4110 if (i.types[n] & Disp64) 4111 size = 8; 4112 } 4113 return size; 4114} 4115 4116/* Return the size of the immediate operand N. */ 4117 4118static int 4119imm_size (unsigned int n) 4120{ 4121 int size = 4; 4122 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) 4123 { 4124 size = 2; 4125 if (i.types[n] & (Imm8 | Imm8S)) 4126 size = 1; 4127 if (i.types[n] & Imm64) 4128 size = 8; 4129 } 4130 return size; 4131} 4132 4133static void 4134output_disp (fragS *insn_start_frag, offsetT insn_start_off) 4135{ 4136 char *p; 4137 unsigned int n; 4138 4139 for (n = 0; n < i.operands; n++) 4140 { 4141 if (i.types[n] & Disp) 4142 { 4143 if (i.op[n].disps->X_op == O_constant) 4144 { 4145 int size = disp_size (n); 4146 offsetT val; 4147 4148 val = offset_in_range (i.op[n].disps->X_add_number, 4149 size); 4150 p = frag_more (size); 4151 md_number_to_chars (p, val, size); 4152 } 4153 else 4154 { 4155 enum bfd_reloc_code_real reloc_type; 4156 int size = disp_size (n); 4157 int sign = (i.types[n] & Disp32S) != 0; 4158 int pcrel = (i.flags[n] & Operand_PCrel) != 0; 4159 4160 /* We can't have 8 bit displacement here. */ 4161 assert ((i.types[n] & Disp8) == 0); 4162 4163 /* The PC relative address is computed relative 4164 to the instruction boundary, so in case immediate 4165 fields follows, we need to adjust the value. */ 4166 if (pcrel && i.imm_operands) 4167 { 4168 unsigned int n1; 4169 int sz = 0; 4170 4171 for (n1 = 0; n1 < i.operands; n1++) 4172 if (i.types[n1] & Imm) 4173 { 4174 /* Only one immediate is allowed for PC 4175 relative address. */ 4176 assert (sz == 0); 4177 sz = imm_size (n1); 4178 i.op[n].disps->X_add_number -= sz; 4179 } 4180 /* We should find the immediate. */ 4181 assert (sz != 0); 4182 } 4183 4184 p = frag_more (size); 4185 reloc_type = reloc (size, pcrel, sign, i.reloc[n]); 4186 if (GOT_symbol 4187 && GOT_symbol == i.op[n].disps->X_add_symbol 4188 && (((reloc_type == BFD_RELOC_32 4189 || reloc_type == BFD_RELOC_X86_64_32S 4190 || (reloc_type == BFD_RELOC_64 4191 && object_64bit)) 4192 && (i.op[n].disps->X_op == O_symbol 4193 || (i.op[n].disps->X_op == O_add 4194 && ((symbol_get_value_expression 4195 (i.op[n].disps->X_op_symbol)->X_op) 4196 == O_subtract)))) 4197 || reloc_type == BFD_RELOC_32_PCREL)) 4198 { 4199 offsetT add; 4200 4201 if (insn_start_frag == frag_now) 4202 add = (p - frag_now->fr_literal) - insn_start_off; 4203 else 4204 { 4205 fragS *fr; 4206 4207 add = insn_start_frag->fr_fix - insn_start_off; 4208 for (fr = insn_start_frag->fr_next; 4209 fr && fr != frag_now; fr = fr->fr_next) 4210 add += fr->fr_fix; 4211 add += p - frag_now->fr_literal; 4212 } 4213 4214 if (!object_64bit) 4215 { 4216 reloc_type = BFD_RELOC_386_GOTPC; 4217 i.op[n].imms->X_add_number += add; 4218 } 4219 else if (reloc_type == BFD_RELOC_64) 4220 reloc_type = BFD_RELOC_X86_64_GOTPC64; 4221 else 4222 /* Don't do the adjustment for x86-64, as there 4223 the pcrel addressing is relative to the _next_ 4224 insn, and that is taken care of in other code. */ 4225 reloc_type = BFD_RELOC_X86_64_GOTPC32; 4226 } 4227 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 4228 i.op[n].disps, pcrel, reloc_type); 4229 } 4230 } 4231 } 4232} 4233 4234static void 4235output_imm (fragS *insn_start_frag, offsetT insn_start_off) 4236{ 4237 char *p; 4238 unsigned int n; 4239 4240 for (n = 0; n < i.operands; n++) 4241 { 4242 if (i.types[n] & Imm) 4243 { 4244 if (i.op[n].imms->X_op == O_constant) 4245 { 4246 int size = imm_size (n); 4247 offsetT val; 4248 4249 val = offset_in_range (i.op[n].imms->X_add_number, 4250 size); 4251 p = frag_more (size); 4252 md_number_to_chars (p, val, size); 4253 } 4254 else 4255 { 4256 /* Not absolute_section. 4257 Need a 32-bit fixup (don't support 8bit 4258 non-absolute imms). Try to support other 4259 sizes ... */ 4260 enum bfd_reloc_code_real reloc_type; 4261 int size = imm_size (n); 4262 int sign; 4263 4264 if ((i.types[n] & (Imm32S)) 4265 && (i.suffix == QWORD_MNEM_SUFFIX 4266 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf)))) 4267 sign = 1; 4268 else 4269 sign = 0; 4270 4271 p = frag_more (size); 4272 reloc_type = reloc (size, 0, sign, i.reloc[n]); 4273 4274 /* This is tough to explain. We end up with this one if we 4275 * have operands that look like 4276 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to 4277 * obtain the absolute address of the GOT, and it is strongly 4278 * preferable from a performance point of view to avoid using 4279 * a runtime relocation for this. The actual sequence of 4280 * instructions often look something like: 4281 * 4282 * call .L66 4283 * .L66: 4284 * popl %ebx 4285 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx 4286 * 4287 * The call and pop essentially return the absolute address 4288 * of the label .L66 and store it in %ebx. The linker itself 4289 * will ultimately change the first operand of the addl so 4290 * that %ebx points to the GOT, but to keep things simple, the 4291 * .o file must have this operand set so that it generates not 4292 * the absolute address of .L66, but the absolute address of 4293 * itself. This allows the linker itself simply treat a GOTPC 4294 * relocation as asking for a pcrel offset to the GOT to be 4295 * added in, and the addend of the relocation is stored in the 4296 * operand field for the instruction itself. 4297 * 4298 * Our job here is to fix the operand so that it would add 4299 * the correct offset so that %ebx would point to itself. The 4300 * thing that is tricky is that .-.L66 will point to the 4301 * beginning of the instruction, so we need to further modify 4302 * the operand so that it will point to itself. There are 4303 * other cases where you have something like: 4304 * 4305 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] 4306 * 4307 * and here no correction would be required. Internally in 4308 * the assembler we treat operands of this form as not being 4309 * pcrel since the '.' is explicitly mentioned, and I wonder 4310 * whether it would simplify matters to do it this way. Who 4311 * knows. In earlier versions of the PIC patches, the 4312 * pcrel_adjust field was used to store the correction, but 4313 * since the expression is not pcrel, I felt it would be 4314 * confusing to do it this way. */ 4315 4316 if ((reloc_type == BFD_RELOC_32 4317 || reloc_type == BFD_RELOC_X86_64_32S 4318 || reloc_type == BFD_RELOC_64) 4319 && GOT_symbol 4320 && GOT_symbol == i.op[n].imms->X_add_symbol 4321 && (i.op[n].imms->X_op == O_symbol 4322 || (i.op[n].imms->X_op == O_add 4323 && ((symbol_get_value_expression 4324 (i.op[n].imms->X_op_symbol)->X_op) 4325 == O_subtract)))) 4326 { 4327 offsetT add; 4328 4329 if (insn_start_frag == frag_now) 4330 add = (p - frag_now->fr_literal) - insn_start_off; 4331 else 4332 { 4333 fragS *fr; 4334 4335 add = insn_start_frag->fr_fix - insn_start_off; 4336 for (fr = insn_start_frag->fr_next; 4337 fr && fr != frag_now; fr = fr->fr_next) 4338 add += fr->fr_fix; 4339 add += p - frag_now->fr_literal; 4340 } 4341 4342 if (!object_64bit) 4343 reloc_type = BFD_RELOC_386_GOTPC; 4344 else if (size == 4) 4345 reloc_type = BFD_RELOC_X86_64_GOTPC32; 4346 else if (size == 8) 4347 reloc_type = BFD_RELOC_X86_64_GOTPC64; 4348 i.op[n].imms->X_add_number += add; 4349 } 4350 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 4351 i.op[n].imms, 0, reloc_type); 4352 } 4353 } 4354 } 4355} 4356 4357/* x86_cons_fix_new is called via the expression parsing code when a 4358 reloc is needed. We use this hook to get the correct .got reloc. */ 4359static enum bfd_reloc_code_real got_reloc = NO_RELOC; 4360static int cons_sign = -1; 4361 4362void 4363x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, 4364 expressionS *exp) 4365{ 4366 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc); 4367 4368 got_reloc = NO_RELOC; 4369 4370#ifdef TE_PE 4371 if (exp->X_op == O_secrel) 4372 { 4373 exp->X_op = O_symbol; 4374 r = BFD_RELOC_32_SECREL; 4375 } 4376#endif 4377 4378 fix_new_exp (frag, off, len, exp, 0, r); 4379} 4380 4381#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT) 4382# define lex_got(reloc, adjust, types) NULL 4383#else 4384/* Parse operands of the form 4385 <symbol>@GOTOFF+<nnn> 4386 and similar .plt or .got references. 4387 4388 If we find one, set up the correct relocation in RELOC and copy the 4389 input string, minus the `@GOTOFF' into a malloc'd buffer for 4390 parsing by the calling routine. Return this buffer, and if ADJUST 4391 is non-null set it to the length of the string we removed from the 4392 input line. Otherwise return NULL. */ 4393static char * 4394lex_got (enum bfd_reloc_code_real *reloc, 4395 int *adjust, 4396 unsigned int *types) 4397{ 4398 /* Some of the relocations depend on the size of what field is to 4399 be relocated. But in our callers i386_immediate and i386_displacement 4400 we don't yet know the operand size (this will be set by insn 4401 matching). Hence we record the word32 relocation here, 4402 and adjust the reloc according to the real size in reloc(). */ 4403 static const struct { 4404 const char *str; 4405 const enum bfd_reloc_code_real rel[2]; 4406 const unsigned int types64; 4407 } gotrel[] = { 4408 { "PLTOFF", { 0, 4409 BFD_RELOC_X86_64_PLTOFF64 }, 4410 Imm64 }, 4411 { "PLT", { BFD_RELOC_386_PLT32, 4412 BFD_RELOC_X86_64_PLT32 }, 4413 Imm32 | Imm32S | Disp32 }, 4414 { "GOTPLT", { 0, 4415 BFD_RELOC_X86_64_GOTPLT64 }, 4416 Imm64 | Disp64 }, 4417 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 4418 BFD_RELOC_X86_64_GOTOFF64 }, 4419 Imm64 | Disp64 }, 4420 { "GOTPCREL", { 0, 4421 BFD_RELOC_X86_64_GOTPCREL }, 4422 Imm32 | Imm32S | Disp32 }, 4423 { "TLSGD", { BFD_RELOC_386_TLS_GD, 4424 BFD_RELOC_X86_64_TLSGD }, 4425 Imm32 | Imm32S | Disp32 }, 4426 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 4427 0 }, 4428 0 }, 4429 { "TLSLD", { 0, 4430 BFD_RELOC_X86_64_TLSLD }, 4431 Imm32 | Imm32S | Disp32 }, 4432 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 4433 BFD_RELOC_X86_64_GOTTPOFF }, 4434 Imm32 | Imm32S | Disp32 }, 4435 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 4436 BFD_RELOC_X86_64_TPOFF32 }, 4437 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 }, 4438 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 4439 0 }, 4440 0 }, 4441 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 4442 BFD_RELOC_X86_64_DTPOFF32 }, 4443 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 }, 4444 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 4445 0 }, 4446 0 }, 4447 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 4448 0 }, 4449 0 }, 4450 { "GOT", { BFD_RELOC_386_GOT32, 4451 BFD_RELOC_X86_64_GOT32 }, 4452 Imm32 | Imm32S | Disp32 | Imm64 }, 4453 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, 4454 BFD_RELOC_X86_64_GOTPC32_TLSDESC }, 4455 Imm32 | Imm32S | Disp32 }, 4456 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, 4457 BFD_RELOC_X86_64_TLSDESC_CALL }, 4458 Imm32 | Imm32S | Disp32 } 4459 }; 4460 char *cp; 4461 unsigned int j; 4462 4463 if (!IS_ELF) 4464 return NULL; 4465 4466 for (cp = input_line_pointer; *cp != '@'; cp++) 4467 if (is_end_of_line[(unsigned char) *cp]) 4468 return NULL; 4469 4470 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++) 4471 { 4472 int len; 4473 4474 len = strlen (gotrel[j].str); 4475 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) 4476 { 4477 if (gotrel[j].rel[object_64bit] != 0) 4478 { 4479 int first, second; 4480 char *tmpbuf, *past_reloc; 4481 4482 *reloc = gotrel[j].rel[object_64bit]; 4483 if (adjust) 4484 *adjust = len; 4485 4486 if (types) 4487 { 4488 if (flag_code != CODE_64BIT) 4489 *types = Imm32 | Disp32; 4490 else 4491 *types = gotrel[j].types64; 4492 } 4493 4494 if (GOT_symbol == NULL) 4495 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); 4496 4497 /* The length of the first part of our input line. */ 4498 first = cp - input_line_pointer; 4499 4500 /* The second part goes from after the reloc token until 4501 (and including) an end_of_line char. Don't use strlen 4502 here as the end_of_line char may not be a NUL. */ 4503 past_reloc = cp + 1 + len; 4504 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; ) 4505 ; 4506 second = cp - past_reloc; 4507 4508 /* Allocate and copy string. The trailing NUL shouldn't 4509 be necessary, but be safe. */ 4510 tmpbuf = xmalloc (first + second + 2); 4511 memcpy (tmpbuf, input_line_pointer, first); 4512 if (second != 0 && *past_reloc != ' ') 4513 /* Replace the relocation token with ' ', so that 4514 errors like foo@GOTOFF1 will be detected. */ 4515 tmpbuf[first++] = ' '; 4516 memcpy (tmpbuf + first, past_reloc, second); 4517 tmpbuf[first + second] = '\0'; 4518 return tmpbuf; 4519 } 4520 4521 as_bad (_("@%s reloc is not supported with %d-bit output format"), 4522 gotrel[j].str, 1 << (5 + object_64bit)); 4523 return NULL; 4524 } 4525 } 4526 4527 /* Might be a symbol version string. Don't as_bad here. */ 4528 return NULL; 4529} 4530 4531void 4532x86_cons (expressionS *exp, int size) 4533{ 4534 if (size == 4 || (object_64bit && size == 8)) 4535 { 4536 /* Handle @GOTOFF and the like in an expression. */ 4537 char *save; 4538 char *gotfree_input_line; 4539 int adjust; 4540 4541 save = input_line_pointer; 4542 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); 4543 if (gotfree_input_line) 4544 input_line_pointer = gotfree_input_line; 4545 4546 expression (exp); 4547 4548 if (gotfree_input_line) 4549 { 4550 /* expression () has merrily parsed up to the end of line, 4551 or a comma - in the wrong buffer. Transfer how far 4552 input_line_pointer has moved to the right buffer. */ 4553 input_line_pointer = (save 4554 + (input_line_pointer - gotfree_input_line) 4555 + adjust); 4556 free (gotfree_input_line); 4557 } 4558 } 4559 else 4560 expression (exp); 4561} 4562#endif 4563 4564static void signed_cons (int size) 4565{ 4566 if (flag_code == CODE_64BIT) 4567 cons_sign = 1; 4568 cons (size); 4569 cons_sign = -1; 4570} 4571 4572#ifdef TE_PE 4573static void 4574pe_directive_secrel (dummy) 4575 int dummy ATTRIBUTE_UNUSED; 4576{ 4577 expressionS exp; 4578 4579 do 4580 { 4581 expression (&exp); 4582 if (exp.X_op == O_symbol) 4583 exp.X_op = O_secrel; 4584 4585 emit_expr (&exp, 4); 4586 } 4587 while (*input_line_pointer++ == ','); 4588 4589 input_line_pointer--; 4590 demand_empty_rest_of_line (); 4591} 4592#endif 4593 4594static int 4595i386_immediate (char *imm_start) 4596{ 4597 char *save_input_line_pointer; 4598 char *gotfree_input_line; 4599 segT exp_seg = 0; 4600 expressionS *exp; 4601 unsigned int types = ~0U; 4602 4603 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) 4604 { 4605 as_bad (_("at most %d immediate operands are allowed"), 4606 MAX_IMMEDIATE_OPERANDS); 4607 return 0; 4608 } 4609 4610 exp = &im_expressions[i.imm_operands++]; 4611 i.op[this_operand].imms = exp; 4612 4613 if (is_space_char (*imm_start)) 4614 ++imm_start; 4615 4616 save_input_line_pointer = input_line_pointer; 4617 input_line_pointer = imm_start; 4618 4619 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); 4620 if (gotfree_input_line) 4621 input_line_pointer = gotfree_input_line; 4622 4623 exp_seg = expression (exp); 4624 4625 SKIP_WHITESPACE (); 4626 if (*input_line_pointer) 4627 as_bad (_("junk `%s' after expression"), input_line_pointer); 4628 4629 input_line_pointer = save_input_line_pointer; 4630 if (gotfree_input_line) 4631 free (gotfree_input_line); 4632 4633 if (exp->X_op == O_absent || exp->X_op == O_big) 4634 { 4635 /* Missing or bad expr becomes absolute 0. */ 4636 as_bad (_("missing or invalid immediate expression `%s' taken as 0"), 4637 imm_start); 4638 exp->X_op = O_constant; 4639 exp->X_add_number = 0; 4640 exp->X_add_symbol = (symbolS *) 0; 4641 exp->X_op_symbol = (symbolS *) 0; 4642 } 4643 else if (exp->X_op == O_constant) 4644 { 4645 /* Size it properly later. */ 4646 i.types[this_operand] |= Imm64; 4647 /* If BFD64, sign extend val. */ 4648 if (!use_rela_relocations 4649 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) 4650 exp->X_add_number 4651 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); 4652 } 4653#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 4654 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour 4655 && exp_seg != absolute_section 4656 && exp_seg != text_section 4657 && exp_seg != data_section 4658 && exp_seg != bss_section 4659 && exp_seg != undefined_section 4660 && !bfd_is_com_section (exp_seg)) 4661 { 4662 as_bad (_("unimplemented segment %s in operand"), exp_seg->name); 4663 return 0; 4664 } 4665#endif 4666 else if (!intel_syntax && exp->X_op == O_register) 4667 { 4668 as_bad (_("illegal immediate register operand %s"), imm_start); 4669 return 0; 4670 } 4671 else 4672 { 4673 /* This is an address. The size of the address will be 4674 determined later, depending on destination register, 4675 suffix, or the default for the section. */ 4676 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64; 4677 i.types[this_operand] &= types; 4678 } 4679 4680 return 1; 4681} 4682 4683static char * 4684i386_scale (char *scale) 4685{ 4686 offsetT val; 4687 char *save = input_line_pointer; 4688 4689 input_line_pointer = scale; 4690 val = get_absolute_expression (); 4691 4692 switch (val) 4693 { 4694 case 1: 4695 i.log2_scale_factor = 0; 4696 break; 4697 case 2: 4698 i.log2_scale_factor = 1; 4699 break; 4700 case 4: 4701 i.log2_scale_factor = 2; 4702 break; 4703 case 8: 4704 i.log2_scale_factor = 3; 4705 break; 4706 default: 4707 { 4708 char sep = *input_line_pointer; 4709 4710 *input_line_pointer = '\0'; 4711 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), 4712 scale); 4713 *input_line_pointer = sep; 4714 input_line_pointer = save; 4715 return NULL; 4716 } 4717 } 4718 if (i.log2_scale_factor != 0 && i.index_reg == 0) 4719 { 4720 as_warn (_("scale factor of %d without an index register"), 4721 1 << i.log2_scale_factor); 4722#if SCALE1_WHEN_NO_INDEX 4723 i.log2_scale_factor = 0; 4724#endif 4725 } 4726 scale = input_line_pointer; 4727 input_line_pointer = save; 4728 return scale; 4729} 4730 4731static int 4732i386_displacement (char *disp_start, char *disp_end) 4733{ 4734 expressionS *exp; 4735 segT exp_seg = 0; 4736 char *save_input_line_pointer; 4737 char *gotfree_input_line; 4738 int bigdisp, override; 4739 unsigned int types = Disp; 4740 4741 if (i.disp_operands == MAX_MEMORY_OPERANDS) 4742 { 4743 as_bad (_("at most %d displacement operands are allowed"), 4744 MAX_MEMORY_OPERANDS); 4745 return 0; 4746 } 4747 4748 if ((i.types[this_operand] & JumpAbsolute) 4749 || !(current_templates->start->opcode_modifier & (Jump | JumpDword))) 4750 { 4751 bigdisp = Disp32; 4752 override = (i.prefix[ADDR_PREFIX] != 0); 4753 } 4754 else 4755 { 4756 /* For PC-relative branches, the width of the displacement 4757 is dependent upon data size, not address size. */ 4758 bigdisp = 0; 4759 override = (i.prefix[DATA_PREFIX] != 0); 4760 } 4761 if (flag_code == CODE_64BIT) 4762 { 4763 if (!bigdisp) 4764 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX) 4765 ? Disp16 4766 : Disp32S | Disp32); 4767 else if (!override) 4768 bigdisp = Disp64 | Disp32S | Disp32; 4769 } 4770 else 4771 { 4772 if (!bigdisp) 4773 { 4774 if (!override) 4775 override = (i.suffix == (flag_code != CODE_16BIT 4776 ? WORD_MNEM_SUFFIX 4777 : LONG_MNEM_SUFFIX)); 4778 bigdisp = Disp32; 4779 } 4780 if ((flag_code == CODE_16BIT) ^ override) 4781 bigdisp = Disp16; 4782 } 4783 i.types[this_operand] |= bigdisp; 4784 4785 exp = &disp_expressions[i.disp_operands]; 4786 i.op[this_operand].disps = exp; 4787 i.disp_operands++; 4788 save_input_line_pointer = input_line_pointer; 4789 input_line_pointer = disp_start; 4790 END_STRING_AND_SAVE (disp_end); 4791 4792#ifndef GCC_ASM_O_HACK 4793#define GCC_ASM_O_HACK 0 4794#endif 4795#if GCC_ASM_O_HACK 4796 END_STRING_AND_SAVE (disp_end + 1); 4797 if ((i.types[this_operand] & BaseIndex) != 0 4798 && displacement_string_end[-1] == '+') 4799 { 4800 /* This hack is to avoid a warning when using the "o" 4801 constraint within gcc asm statements. 4802 For instance: 4803 4804 #define _set_tssldt_desc(n,addr,limit,type) \ 4805 __asm__ __volatile__ ( \ 4806 "movw %w2,%0\n\t" \ 4807 "movw %w1,2+%0\n\t" \ 4808 "rorl $16,%1\n\t" \ 4809 "movb %b1,4+%0\n\t" \ 4810 "movb %4,5+%0\n\t" \ 4811 "movb $0,6+%0\n\t" \ 4812 "movb %h1,7+%0\n\t" \ 4813 "rorl $16,%1" \ 4814 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) 4815 4816 This works great except that the output assembler ends 4817 up looking a bit weird if it turns out that there is 4818 no offset. You end up producing code that looks like: 4819 4820 #APP 4821 movw $235,(%eax) 4822 movw %dx,2+(%eax) 4823 rorl $16,%edx 4824 movb %dl,4+(%eax) 4825 movb $137,5+(%eax) 4826 movb $0,6+(%eax) 4827 movb %dh,7+(%eax) 4828 rorl $16,%edx 4829 #NO_APP 4830 4831 So here we provide the missing zero. */ 4832 4833 *displacement_string_end = '0'; 4834 } 4835#endif 4836 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); 4837 if (gotfree_input_line) 4838 input_line_pointer = gotfree_input_line; 4839 4840 exp_seg = expression (exp); 4841 4842 SKIP_WHITESPACE (); 4843 if (*input_line_pointer) 4844 as_bad (_("junk `%s' after expression"), input_line_pointer); 4845#if GCC_ASM_O_HACK 4846 RESTORE_END_STRING (disp_end + 1); 4847#endif 4848 RESTORE_END_STRING (disp_end); 4849 input_line_pointer = save_input_line_pointer; 4850 if (gotfree_input_line) 4851 free (gotfree_input_line); 4852 4853 /* We do this to make sure that the section symbol is in 4854 the symbol table. We will ultimately change the relocation 4855 to be relative to the beginning of the section. */ 4856 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF 4857 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL 4858 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) 4859 { 4860 if (exp->X_op != O_symbol) 4861 { 4862 as_bad (_("bad expression used with @%s"), 4863 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL 4864 ? "GOTPCREL" 4865 : "GOTOFF")); 4866 return 0; 4867 } 4868 4869 if (S_IS_LOCAL (exp->X_add_symbol) 4870 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) 4871 section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); 4872 exp->X_op = O_subtract; 4873 exp->X_op_symbol = GOT_symbol; 4874 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) 4875 i.reloc[this_operand] = BFD_RELOC_32_PCREL; 4876 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) 4877 i.reloc[this_operand] = BFD_RELOC_64; 4878 else 4879 i.reloc[this_operand] = BFD_RELOC_32; 4880 } 4881 4882 if (exp->X_op == O_absent || exp->X_op == O_big) 4883 { 4884 /* Missing or bad expr becomes absolute 0. */ 4885 as_bad (_("missing or invalid displacement expression `%s' taken as 0"), 4886 disp_start); 4887 exp->X_op = O_constant; 4888 exp->X_add_number = 0; 4889 exp->X_add_symbol = (symbolS *) 0; 4890 exp->X_op_symbol = (symbolS *) 0; 4891 } 4892 4893#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 4894 if (exp->X_op != O_constant 4895 && OUTPUT_FLAVOR == bfd_target_aout_flavour 4896 && exp_seg != absolute_section 4897 && exp_seg != text_section 4898 && exp_seg != data_section 4899 && exp_seg != bss_section 4900 && exp_seg != undefined_section 4901 && !bfd_is_com_section (exp_seg)) 4902 { 4903 as_bad (_("unimplemented segment %s in operand"), exp_seg->name); 4904 return 0; 4905 } 4906#endif 4907 4908 if (!(i.types[this_operand] & ~Disp)) 4909 i.types[this_operand] &= types; 4910 4911 return 1; 4912} 4913 4914/* Make sure the memory operand we've been dealt is valid. 4915 Return 1 on success, 0 on a failure. */ 4916 4917static int 4918i386_index_check (const char *operand_string) 4919{ 4920 int ok; 4921#if INFER_ADDR_PREFIX 4922 int fudged = 0; 4923 4924 tryprefix: 4925#endif 4926 ok = 1; 4927 if ((current_templates->start->cpu_flags & CpuSVME) 4928 && current_templates->end[-1].operand_types[0] == AnyMem) 4929 { 4930 /* Memory operands of SVME insns are special in that they only allow 4931 rAX as their memory address and ignore any segment override. */ 4932 unsigned RegXX; 4933 4934 /* SKINIT is even more restrictive: it always requires EAX. */ 4935 if (strcmp (current_templates->start->name, "skinit") == 0) 4936 RegXX = Reg32; 4937 else if (flag_code == CODE_64BIT) 4938 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32; 4939 else 4940 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0) 4941 ? Reg16 4942 : Reg32); 4943 if (!i.base_reg 4944 || !(i.base_reg->reg_type & Acc) 4945 || !(i.base_reg->reg_type & RegXX) 4946 || i.index_reg 4947 || (i.types[0] & Disp)) 4948 ok = 0; 4949 } 4950 else if (flag_code == CODE_64BIT) 4951 { 4952 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32); 4953 4954 if ((i.base_reg 4955 && ((i.base_reg->reg_type & RegXX) == 0) 4956 && (i.base_reg->reg_type != BaseIndex 4957 || i.index_reg)) 4958 || (i.index_reg 4959 && ((i.index_reg->reg_type & (RegXX | BaseIndex)) 4960 != (RegXX | BaseIndex)))) 4961 ok = 0; 4962 } 4963 else 4964 { 4965 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) 4966 { 4967 /* 16bit checks. */ 4968 if ((i.base_reg 4969 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex)) 4970 != (Reg16 | BaseIndex))) 4971 || (i.index_reg 4972 && (((i.index_reg->reg_type & (Reg16 | BaseIndex)) 4973 != (Reg16 | BaseIndex)) 4974 || !(i.base_reg 4975 && i.base_reg->reg_num < 6 4976 && i.index_reg->reg_num >= 6 4977 && i.log2_scale_factor == 0)))) 4978 ok = 0; 4979 } 4980 else 4981 { 4982 /* 32bit checks. */ 4983 if ((i.base_reg 4984 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32) 4985 || (i.index_reg 4986 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex)) 4987 != (Reg32 | BaseIndex)))) 4988 ok = 0; 4989 } 4990 } 4991 if (!ok) 4992 { 4993#if INFER_ADDR_PREFIX 4994 if (i.prefix[ADDR_PREFIX] == 0) 4995 { 4996 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; 4997 i.prefixes += 1; 4998 /* Change the size of any displacement too. At most one of 4999 Disp16 or Disp32 is set. 5000 FIXME. There doesn't seem to be any real need for separate 5001 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. 5002 Removing them would probably clean up the code quite a lot. */ 5003 if (flag_code != CODE_64BIT 5004 && (i.types[this_operand] & (Disp16 | Disp32))) 5005 i.types[this_operand] ^= (Disp16 | Disp32); 5006 fudged = 1; 5007 goto tryprefix; 5008 } 5009 if (fudged) 5010 as_bad (_("`%s' is not a valid base/index expression"), 5011 operand_string); 5012 else 5013#endif 5014 as_bad (_("`%s' is not a valid %s bit base/index expression"), 5015 operand_string, 5016 flag_code_names[flag_code]); 5017 } 5018 return ok; 5019} 5020 5021/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero 5022 on error. */ 5023 5024static int 5025i386_operand (char *operand_string) 5026{ 5027 const reg_entry *r; 5028 char *end_op; 5029 char *op_string = operand_string; 5030 5031 if (is_space_char (*op_string)) 5032 ++op_string; 5033 5034 /* We check for an absolute prefix (differentiating, 5035 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ 5036 if (*op_string == ABSOLUTE_PREFIX) 5037 { 5038 ++op_string; 5039 if (is_space_char (*op_string)) 5040 ++op_string; 5041 i.types[this_operand] |= JumpAbsolute; 5042 } 5043 5044 /* Check if operand is a register. */ 5045 if ((r = parse_register (op_string, &end_op)) != NULL) 5046 { 5047 /* Check for a segment override by searching for ':' after a 5048 segment register. */ 5049 op_string = end_op; 5050 if (is_space_char (*op_string)) 5051 ++op_string; 5052 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) 5053 { 5054 switch (r->reg_num) 5055 { 5056 case 0: 5057 i.seg[i.mem_operands] = &es; 5058 break; 5059 case 1: 5060 i.seg[i.mem_operands] = &cs; 5061 break; 5062 case 2: 5063 i.seg[i.mem_operands] = &ss; 5064 break; 5065 case 3: 5066 i.seg[i.mem_operands] = &ds; 5067 break; 5068 case 4: 5069 i.seg[i.mem_operands] = &fs; 5070 break; 5071 case 5: 5072 i.seg[i.mem_operands] = &gs; 5073 break; 5074 } 5075 5076 /* Skip the ':' and whitespace. */ 5077 ++op_string; 5078 if (is_space_char (*op_string)) 5079 ++op_string; 5080 5081 if (!is_digit_char (*op_string) 5082 && !is_identifier_char (*op_string) 5083 && *op_string != '(' 5084 && *op_string != ABSOLUTE_PREFIX) 5085 { 5086 as_bad (_("bad memory operand `%s'"), op_string); 5087 return 0; 5088 } 5089 /* Handle case of %es:*foo. */ 5090 if (*op_string == ABSOLUTE_PREFIX) 5091 { 5092 ++op_string; 5093 if (is_space_char (*op_string)) 5094 ++op_string; 5095 i.types[this_operand] |= JumpAbsolute; 5096 } 5097 goto do_memory_reference; 5098 } 5099 if (*op_string) 5100 { 5101 as_bad (_("junk `%s' after register"), op_string); 5102 return 0; 5103 } 5104 i.types[this_operand] |= r->reg_type & ~BaseIndex; 5105 i.op[this_operand].regs = r; 5106 i.reg_operands++; 5107 } 5108 else if (*op_string == REGISTER_PREFIX) 5109 { 5110 as_bad (_("bad register name `%s'"), op_string); 5111 return 0; 5112 } 5113 else if (*op_string == IMMEDIATE_PREFIX) 5114 { 5115 ++op_string; 5116 if (i.types[this_operand] & JumpAbsolute) 5117 { 5118 as_bad (_("immediate operand illegal with absolute jump")); 5119 return 0; 5120 } 5121 if (!i386_immediate (op_string)) 5122 return 0; 5123 } 5124 else if (is_digit_char (*op_string) 5125 || is_identifier_char (*op_string) 5126 || *op_string == '(') 5127 { 5128 /* This is a memory reference of some sort. */ 5129 char *base_string; 5130 5131 /* Start and end of displacement string expression (if found). */ 5132 char *displacement_string_start; 5133 char *displacement_string_end; 5134 5135 do_memory_reference: 5136 if ((i.mem_operands == 1 5137 && (current_templates->start->opcode_modifier & IsString) == 0) 5138 || i.mem_operands == 2) 5139 { 5140 as_bad (_("too many memory references for `%s'"), 5141 current_templates->start->name); 5142 return 0; 5143 } 5144 5145 /* Check for base index form. We detect the base index form by 5146 looking for an ')' at the end of the operand, searching 5147 for the '(' matching it, and finding a REGISTER_PREFIX or ',' 5148 after the '('. */ 5149 base_string = op_string + strlen (op_string); 5150 5151 --base_string; 5152 if (is_space_char (*base_string)) 5153 --base_string; 5154 5155 /* If we only have a displacement, set-up for it to be parsed later. */ 5156 displacement_string_start = op_string; 5157 displacement_string_end = base_string + 1; 5158 5159 if (*base_string == ')') 5160 { 5161 char *temp_string; 5162 unsigned int parens_balanced = 1; 5163 /* We've already checked that the number of left & right ()'s are 5164 equal, so this loop will not be infinite. */ 5165 do 5166 { 5167 base_string--; 5168 if (*base_string == ')') 5169 parens_balanced++; 5170 if (*base_string == '(') 5171 parens_balanced--; 5172 } 5173 while (parens_balanced); 5174 5175 temp_string = base_string; 5176 5177 /* Skip past '(' and whitespace. */ 5178 ++base_string; 5179 if (is_space_char (*base_string)) 5180 ++base_string; 5181 5182 if (*base_string == ',' 5183 || ((i.base_reg = parse_register (base_string, &end_op)) 5184 != NULL)) 5185 { 5186 displacement_string_end = temp_string; 5187 5188 i.types[this_operand] |= BaseIndex; 5189 5190 if (i.base_reg) 5191 { 5192 base_string = end_op; 5193 if (is_space_char (*base_string)) 5194 ++base_string; 5195 } 5196 5197 /* There may be an index reg or scale factor here. */ 5198 if (*base_string == ',') 5199 { 5200 ++base_string; 5201 if (is_space_char (*base_string)) 5202 ++base_string; 5203 5204 if ((i.index_reg = parse_register (base_string, &end_op)) 5205 != NULL) 5206 { 5207 base_string = end_op; 5208 if (is_space_char (*base_string)) 5209 ++base_string; 5210 if (*base_string == ',') 5211 { 5212 ++base_string; 5213 if (is_space_char (*base_string)) 5214 ++base_string; 5215 } 5216 else if (*base_string != ')') 5217 { 5218 as_bad (_("expecting `,' or `)' " 5219 "after index register in `%s'"), 5220 operand_string); 5221 return 0; 5222 } 5223 } 5224 else if (*base_string == REGISTER_PREFIX) 5225 { 5226 as_bad (_("bad register name `%s'"), base_string); 5227 return 0; 5228 } 5229 5230 /* Check for scale factor. */ 5231 if (*base_string != ')') 5232 { 5233 char *end_scale = i386_scale (base_string); 5234 5235 if (!end_scale) 5236 return 0; 5237 5238 base_string = end_scale; 5239 if (is_space_char (*base_string)) 5240 ++base_string; 5241 if (*base_string != ')') 5242 { 5243 as_bad (_("expecting `)' " 5244 "after scale factor in `%s'"), 5245 operand_string); 5246 return 0; 5247 } 5248 } 5249 else if (!i.index_reg) 5250 { 5251 as_bad (_("expecting index register or scale factor " 5252 "after `,'; got '%c'"), 5253 *base_string); 5254 return 0; 5255 } 5256 } 5257 else if (*base_string != ')') 5258 { 5259 as_bad (_("expecting `,' or `)' " 5260 "after base register in `%s'"), 5261 operand_string); 5262 return 0; 5263 } 5264 } 5265 else if (*base_string == REGISTER_PREFIX) 5266 { 5267 as_bad (_("bad register name `%s'"), base_string); 5268 return 0; 5269 } 5270 } 5271 5272 /* If there's an expression beginning the operand, parse it, 5273 assuming displacement_string_start and 5274 displacement_string_end are meaningful. */ 5275 if (displacement_string_start != displacement_string_end) 5276 { 5277 if (!i386_displacement (displacement_string_start, 5278 displacement_string_end)) 5279 return 0; 5280 } 5281 5282 /* Special case for (%dx) while doing input/output op. */ 5283 if (i.base_reg 5284 && i.base_reg->reg_type == (Reg16 | InOutPortReg) 5285 && i.index_reg == 0 5286 && i.log2_scale_factor == 0 5287 && i.seg[i.mem_operands] == 0 5288 && (i.types[this_operand] & Disp) == 0) 5289 { 5290 i.types[this_operand] = InOutPortReg; 5291 return 1; 5292 } 5293 5294 if (i386_index_check (operand_string) == 0) 5295 return 0; 5296 i.mem_operands++; 5297 } 5298 else 5299 { 5300 /* It's not a memory operand; argh! */ 5301 as_bad (_("invalid char %s beginning operand %d `%s'"), 5302 output_invalid (*op_string), 5303 this_operand + 1, 5304 op_string); 5305 return 0; 5306 } 5307 return 1; /* Normal return. */ 5308} 5309 5310/* md_estimate_size_before_relax() 5311 5312 Called just before relax() for rs_machine_dependent frags. The x86 5313 assembler uses these frags to handle variable size jump 5314 instructions. 5315 5316 Any symbol that is now undefined will not become defined. 5317 Return the correct fr_subtype in the frag. 5318 Return the initial "guess for variable size of frag" to caller. 5319 The guess is actually the growth beyond the fixed part. Whatever 5320 we do to grow the fixed or variable part contributes to our 5321 returned value. */ 5322 5323int 5324md_estimate_size_before_relax (fragP, segment) 5325 fragS *fragP; 5326 segT segment; 5327{ 5328 /* We've already got fragP->fr_subtype right; all we have to do is 5329 check for un-relaxable symbols. On an ELF system, we can't relax 5330 an externally visible symbol, because it may be overridden by a 5331 shared library. */ 5332 if (S_GET_SEGMENT (fragP->fr_symbol) != segment 5333#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5334 || (IS_ELF 5335 && (S_IS_EXTERNAL (fragP->fr_symbol) 5336 || S_IS_WEAK (fragP->fr_symbol))) 5337#endif 5338 ) 5339 { 5340 /* Symbol is undefined in this segment, or we need to keep a 5341 reloc so that weak symbols can be overridden. */ 5342 int size = (fragP->fr_subtype & CODE16) ? 2 : 4; 5343 enum bfd_reloc_code_real reloc_type; 5344 unsigned char *opcode; 5345 int old_fr_fix; 5346 5347 if (fragP->fr_var != NO_RELOC) 5348 reloc_type = fragP->fr_var; 5349 else if (size == 2) 5350 reloc_type = BFD_RELOC_16_PCREL; 5351 else 5352 reloc_type = BFD_RELOC_32_PCREL; 5353 5354 old_fr_fix = fragP->fr_fix; 5355 opcode = (unsigned char *) fragP->fr_opcode; 5356 5357 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) 5358 { 5359 case UNCOND_JUMP: 5360 /* Make jmp (0xeb) a (d)word displacement jump. */ 5361 opcode[0] = 0xe9; 5362 fragP->fr_fix += size; 5363 fix_new (fragP, old_fr_fix, size, 5364 fragP->fr_symbol, 5365 fragP->fr_offset, 1, 5366 reloc_type); 5367 break; 5368 5369 case COND_JUMP86: 5370 if (size == 2 5371 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) 5372 { 5373 /* Negate the condition, and branch past an 5374 unconditional jump. */ 5375 opcode[0] ^= 1; 5376 opcode[1] = 3; 5377 /* Insert an unconditional jump. */ 5378 opcode[2] = 0xe9; 5379 /* We added two extra opcode bytes, and have a two byte 5380 offset. */ 5381 fragP->fr_fix += 2 + 2; 5382 fix_new (fragP, old_fr_fix + 2, 2, 5383 fragP->fr_symbol, 5384 fragP->fr_offset, 1, 5385 reloc_type); 5386 break; 5387 } 5388 /* Fall through. */ 5389 5390 case COND_JUMP: 5391 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) 5392 { 5393 fixS *fixP; 5394 5395 fragP->fr_fix += 1; 5396 fixP = fix_new (fragP, old_fr_fix, 1, 5397 fragP->fr_symbol, 5398 fragP->fr_offset, 1, 5399 BFD_RELOC_8_PCREL); 5400 fixP->fx_signed = 1; 5401 break; 5402 } 5403 5404 /* This changes the byte-displacement jump 0x7N 5405 to the (d)word-displacement jump 0x0f,0x8N. */ 5406 opcode[1] = opcode[0] + 0x10; 5407 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 5408 /* We've added an opcode byte. */ 5409 fragP->fr_fix += 1 + size; 5410 fix_new (fragP, old_fr_fix + 1, size, 5411 fragP->fr_symbol, 5412 fragP->fr_offset, 1, 5413 reloc_type); 5414 break; 5415 5416 default: 5417 BAD_CASE (fragP->fr_subtype); 5418 break; 5419 } 5420 frag_wane (fragP); 5421 return fragP->fr_fix - old_fr_fix; 5422 } 5423 5424 /* Guess size depending on current relax state. Initially the relax 5425 state will correspond to a short jump and we return 1, because 5426 the variable part of the frag (the branch offset) is one byte 5427 long. However, we can relax a section more than once and in that 5428 case we must either set fr_subtype back to the unrelaxed state, 5429 or return the value for the appropriate branch. */ 5430 return md_relax_table[fragP->fr_subtype].rlx_length; 5431} 5432 5433/* Called after relax() is finished. 5434 5435 In: Address of frag. 5436 fr_type == rs_machine_dependent. 5437 fr_subtype is what the address relaxed to. 5438 5439 Out: Any fixSs and constants are set up. 5440 Caller will turn frag into a ".space 0". */ 5441 5442void 5443md_convert_frag (abfd, sec, fragP) 5444 bfd *abfd ATTRIBUTE_UNUSED; 5445 segT sec ATTRIBUTE_UNUSED; 5446 fragS *fragP; 5447{ 5448 unsigned char *opcode; 5449 unsigned char *where_to_put_displacement = NULL; 5450 offsetT target_address; 5451 offsetT opcode_address; 5452 unsigned int extension = 0; 5453 offsetT displacement_from_opcode_start; 5454 5455 opcode = (unsigned char *) fragP->fr_opcode; 5456 5457 /* Address we want to reach in file space. */ 5458 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; 5459 5460 /* Address opcode resides at in file space. */ 5461 opcode_address = fragP->fr_address + fragP->fr_fix; 5462 5463 /* Displacement from opcode start to fill into instruction. */ 5464 displacement_from_opcode_start = target_address - opcode_address; 5465 5466 if ((fragP->fr_subtype & BIG) == 0) 5467 { 5468 /* Don't have to change opcode. */ 5469 extension = 1; /* 1 opcode + 1 displacement */ 5470 where_to_put_displacement = &opcode[1]; 5471 } 5472 else 5473 { 5474 if (no_cond_jump_promotion 5475 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) 5476 as_warn_where (fragP->fr_file, fragP->fr_line, 5477 _("long jump required")); 5478 5479 switch (fragP->fr_subtype) 5480 { 5481 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): 5482 extension = 4; /* 1 opcode + 4 displacement */ 5483 opcode[0] = 0xe9; 5484 where_to_put_displacement = &opcode[1]; 5485 break; 5486 5487 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): 5488 extension = 2; /* 1 opcode + 2 displacement */ 5489 opcode[0] = 0xe9; 5490 where_to_put_displacement = &opcode[1]; 5491 break; 5492 5493 case ENCODE_RELAX_STATE (COND_JUMP, BIG): 5494 case ENCODE_RELAX_STATE (COND_JUMP86, BIG): 5495 extension = 5; /* 2 opcode + 4 displacement */ 5496 opcode[1] = opcode[0] + 0x10; 5497 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 5498 where_to_put_displacement = &opcode[2]; 5499 break; 5500 5501 case ENCODE_RELAX_STATE (COND_JUMP, BIG16): 5502 extension = 3; /* 2 opcode + 2 displacement */ 5503 opcode[1] = opcode[0] + 0x10; 5504 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 5505 where_to_put_displacement = &opcode[2]; 5506 break; 5507 5508 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): 5509 extension = 4; 5510 opcode[0] ^= 1; 5511 opcode[1] = 3; 5512 opcode[2] = 0xe9; 5513 where_to_put_displacement = &opcode[3]; 5514 break; 5515 5516 default: 5517 BAD_CASE (fragP->fr_subtype); 5518 break; 5519 } 5520 } 5521 5522 /* If size if less then four we are sure that the operand fits, 5523 but if it's 4, then it could be that the displacement is larger 5524 then -/+ 2GB. */ 5525 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 5526 && object_64bit 5527 && ((addressT) (displacement_from_opcode_start - extension 5528 + ((addressT) 1 << 31)) 5529 > (((addressT) 2 << 31) - 1))) 5530 { 5531 as_bad_where (fragP->fr_file, fragP->fr_line, 5532 _("jump target out of range")); 5533 /* Make us emit 0. */ 5534 displacement_from_opcode_start = extension; 5535 } 5536 /* Now put displacement after opcode. */ 5537 md_number_to_chars ((char *) where_to_put_displacement, 5538 (valueT) (displacement_from_opcode_start - extension), 5539 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); 5540 fragP->fr_fix += extension; 5541} 5542 5543/* Size of byte displacement jmp. */ 5544int md_short_jump_size = 2; 5545 5546/* Size of dword displacement jmp. */ 5547int md_long_jump_size = 5; 5548 5549void 5550md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) 5551 char *ptr; 5552 addressT from_addr, to_addr; 5553 fragS *frag ATTRIBUTE_UNUSED; 5554 symbolS *to_symbol ATTRIBUTE_UNUSED; 5555{ 5556 offsetT offset; 5557 5558 offset = to_addr - (from_addr + 2); 5559 /* Opcode for byte-disp jump. */ 5560 md_number_to_chars (ptr, (valueT) 0xeb, 1); 5561 md_number_to_chars (ptr + 1, (valueT) offset, 1); 5562} 5563 5564void 5565md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) 5566 char *ptr; 5567 addressT from_addr, to_addr; 5568 fragS *frag ATTRIBUTE_UNUSED; 5569 symbolS *to_symbol ATTRIBUTE_UNUSED; 5570{ 5571 offsetT offset; 5572 5573 offset = to_addr - (from_addr + 5); 5574 md_number_to_chars (ptr, (valueT) 0xe9, 1); 5575 md_number_to_chars (ptr + 1, (valueT) offset, 4); 5576} 5577 5578/* Apply a fixup (fixS) to segment data, once it has been determined 5579 by our caller that we have all the info we need to fix it up. 5580 5581 On the 386, immediates, displacements, and data pointers are all in 5582 the same (little-endian) format, so we don't need to care about which 5583 we are handling. */ 5584 5585void 5586md_apply_fix (fixP, valP, seg) 5587 /* The fix we're to put in. */ 5588 fixS *fixP; 5589 /* Pointer to the value of the bits. */ 5590 valueT *valP; 5591 /* Segment fix is from. */ 5592 segT seg ATTRIBUTE_UNUSED; 5593{ 5594 char *p = fixP->fx_where + fixP->fx_frag->fr_literal; 5595 valueT value = *valP; 5596 5597#if !defined (TE_Mach) 5598 if (fixP->fx_pcrel) 5599 { 5600 switch (fixP->fx_r_type) 5601 { 5602 default: 5603 break; 5604 5605 case BFD_RELOC_64: 5606 fixP->fx_r_type = BFD_RELOC_64_PCREL; 5607 break; 5608 case BFD_RELOC_32: 5609 case BFD_RELOC_X86_64_32S: 5610 fixP->fx_r_type = BFD_RELOC_32_PCREL; 5611 break; 5612 case BFD_RELOC_16: 5613 fixP->fx_r_type = BFD_RELOC_16_PCREL; 5614 break; 5615 case BFD_RELOC_8: 5616 fixP->fx_r_type = BFD_RELOC_8_PCREL; 5617 break; 5618 } 5619 } 5620 5621 if (fixP->fx_addsy != NULL 5622 && (fixP->fx_r_type == BFD_RELOC_32_PCREL 5623 || fixP->fx_r_type == BFD_RELOC_64_PCREL 5624 || fixP->fx_r_type == BFD_RELOC_16_PCREL 5625 || fixP->fx_r_type == BFD_RELOC_8_PCREL) 5626 && !use_rela_relocations) 5627 { 5628 /* This is a hack. There should be a better way to handle this. 5629 This covers for the fact that bfd_install_relocation will 5630 subtract the current location (for partial_inplace, PC relative 5631 relocations); see more below. */ 5632#ifndef OBJ_AOUT 5633 if (IS_ELF 5634#ifdef TE_PE 5635 || OUTPUT_FLAVOR == bfd_target_coff_flavour 5636#endif 5637 ) 5638 value += fixP->fx_where + fixP->fx_frag->fr_address; 5639#endif 5640#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5641 if (IS_ELF) 5642 { 5643 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); 5644 5645 if ((sym_seg == seg 5646 || (symbol_section_p (fixP->fx_addsy) 5647 && sym_seg != absolute_section)) 5648 && !generic_force_reloc (fixP)) 5649 { 5650 /* Yes, we add the values in twice. This is because 5651 bfd_install_relocation subtracts them out again. I think 5652 bfd_install_relocation is broken, but I don't dare change 5653 it. FIXME. */ 5654 value += fixP->fx_where + fixP->fx_frag->fr_address; 5655 } 5656 } 5657#endif 5658#if defined (OBJ_COFF) && defined (TE_PE) 5659 /* For some reason, the PE format does not store a 5660 section address offset for a PC relative symbol. */ 5661 if (S_GET_SEGMENT (fixP->fx_addsy) != seg 5662 || S_IS_WEAK (fixP->fx_addsy)) 5663 value += md_pcrel_from (fixP); 5664#endif 5665 } 5666 5667 /* Fix a few things - the dynamic linker expects certain values here, 5668 and we must not disappoint it. */ 5669#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5670 if (IS_ELF && fixP->fx_addsy) 5671 switch (fixP->fx_r_type) 5672 { 5673 case BFD_RELOC_386_PLT32: 5674 case BFD_RELOC_X86_64_PLT32: 5675 /* Make the jump instruction point to the address of the operand. At 5676 runtime we merely add the offset to the actual PLT entry. */ 5677 value = -4; 5678 break; 5679 5680 case BFD_RELOC_386_TLS_GD: 5681 case BFD_RELOC_386_TLS_LDM: 5682 case BFD_RELOC_386_TLS_IE_32: 5683 case BFD_RELOC_386_TLS_IE: 5684 case BFD_RELOC_386_TLS_GOTIE: 5685 case BFD_RELOC_386_TLS_GOTDESC: 5686 case BFD_RELOC_X86_64_TLSGD: 5687 case BFD_RELOC_X86_64_TLSLD: 5688 case BFD_RELOC_X86_64_GOTTPOFF: 5689 case BFD_RELOC_X86_64_GOTPC32_TLSDESC: 5690 value = 0; /* Fully resolved at runtime. No addend. */ 5691 /* Fallthrough */ 5692 case BFD_RELOC_386_TLS_LE: 5693 case BFD_RELOC_386_TLS_LDO_32: 5694 case BFD_RELOC_386_TLS_LE_32: 5695 case BFD_RELOC_X86_64_DTPOFF32: 5696 case BFD_RELOC_X86_64_DTPOFF64: 5697 case BFD_RELOC_X86_64_TPOFF32: 5698 case BFD_RELOC_X86_64_TPOFF64: 5699 S_SET_THREAD_LOCAL (fixP->fx_addsy); 5700 break; 5701 5702 case BFD_RELOC_386_TLS_DESC_CALL: 5703 case BFD_RELOC_X86_64_TLSDESC_CALL: 5704 value = 0; /* Fully resolved at runtime. No addend. */ 5705 S_SET_THREAD_LOCAL (fixP->fx_addsy); 5706 fixP->fx_done = 0; 5707 return; 5708 5709 case BFD_RELOC_386_GOT32: 5710 case BFD_RELOC_X86_64_GOT32: 5711 value = 0; /* Fully resolved at runtime. No addend. */ 5712 break; 5713 5714 case BFD_RELOC_VTABLE_INHERIT: 5715 case BFD_RELOC_VTABLE_ENTRY: 5716 fixP->fx_done = 0; 5717 return; 5718 5719 default: 5720 break; 5721 } 5722#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ 5723 *valP = value; 5724#endif /* !defined (TE_Mach) */ 5725 5726 /* Are we finished with this relocation now? */ 5727 if (fixP->fx_addsy == NULL) 5728 fixP->fx_done = 1; 5729 else if (use_rela_relocations) 5730 { 5731 fixP->fx_no_overflow = 1; 5732 /* Remember value for tc_gen_reloc. */ 5733 fixP->fx_addnumber = value; 5734 value = 0; 5735 } 5736 5737 md_number_to_chars (p, value, fixP->fx_size); 5738} 5739 5740#define MAX_LITTLENUMS 6 5741 5742/* Turn the string pointed to by litP into a floating point constant 5743 of type TYPE, and emit the appropriate bytes. The number of 5744 LITTLENUMS emitted is stored in *SIZEP. An error message is 5745 returned, or NULL on OK. */ 5746 5747char * 5748md_atof (type, litP, sizeP) 5749 int type; 5750 char *litP; 5751 int *sizeP; 5752{ 5753 int prec; 5754 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 5755 LITTLENUM_TYPE *wordP; 5756 char *t; 5757 5758 switch (type) 5759 { 5760 case 'f': 5761 case 'F': 5762 prec = 2; 5763 break; 5764 5765 case 'd': 5766 case 'D': 5767 prec = 4; 5768 break; 5769 5770 case 'x': 5771 case 'X': 5772 prec = 5; 5773 break; 5774 5775 default: 5776 *sizeP = 0; 5777 return _("Bad call to md_atof ()"); 5778 } 5779 t = atof_ieee (input_line_pointer, type, words); 5780 if (t) 5781 input_line_pointer = t; 5782 5783 *sizeP = prec * sizeof (LITTLENUM_TYPE); 5784 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with 5785 the bigendian 386. */ 5786 for (wordP = words + prec - 1; prec--;) 5787 { 5788 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); 5789 litP += sizeof (LITTLENUM_TYPE); 5790 } 5791 return 0; 5792} 5793 5794static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; 5795 5796static char * 5797output_invalid (int c) 5798{ 5799 if (ISPRINT (c)) 5800 snprintf (output_invalid_buf, sizeof (output_invalid_buf), 5801 "'%c'", c); 5802 else 5803 snprintf (output_invalid_buf, sizeof (output_invalid_buf), 5804 "(0x%x)", (unsigned char) c); 5805 return output_invalid_buf; 5806} 5807 5808/* REG_STRING starts *before* REGISTER_PREFIX. */ 5809 5810static const reg_entry * 5811parse_real_register (char *reg_string, char **end_op) 5812{ 5813 char *s = reg_string; 5814 char *p; 5815 char reg_name_given[MAX_REG_NAME_SIZE + 1]; 5816 const reg_entry *r; 5817 5818 /* Skip possible REGISTER_PREFIX and possible whitespace. */ 5819 if (*s == REGISTER_PREFIX) 5820 ++s; 5821 5822 if (is_space_char (*s)) 5823 ++s; 5824 5825 p = reg_name_given; 5826 while ((*p++ = register_chars[(unsigned char) *s]) != '\0') 5827 { 5828 if (p >= reg_name_given + MAX_REG_NAME_SIZE) 5829 return (const reg_entry *) NULL; 5830 s++; 5831 } 5832 5833 /* For naked regs, make sure that we are not dealing with an identifier. 5834 This prevents confusing an identifier like `eax_var' with register 5835 `eax'. */ 5836 if (allow_naked_reg && identifier_chars[(unsigned char) *s]) 5837 return (const reg_entry *) NULL; 5838 5839 *end_op = s; 5840 5841 r = (const reg_entry *) hash_find (reg_hash, reg_name_given); 5842 5843 /* Handle floating point regs, allowing spaces in the (i) part. */ 5844 if (r == i386_regtab /* %st is first entry of table */) 5845 { 5846 if (is_space_char (*s)) 5847 ++s; 5848 if (*s == '(') 5849 { 5850 ++s; 5851 if (is_space_char (*s)) 5852 ++s; 5853 if (*s >= '0' && *s <= '7') 5854 { 5855 int fpr = *s - '0'; 5856 ++s; 5857 if (is_space_char (*s)) 5858 ++s; 5859 if (*s == ')') 5860 { 5861 *end_op = s + 1; 5862 r = hash_find (reg_hash, "st(0)"); 5863 know (r); 5864 return r + fpr; 5865 } 5866 } 5867 /* We have "%st(" then garbage. */ 5868 return (const reg_entry *) NULL; 5869 } 5870 } 5871 5872 if (r != NULL 5873 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0 5874 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer)) 5875 && flag_code != CODE_64BIT) 5876 return (const reg_entry *) NULL; 5877 5878 return r; 5879} 5880 5881/* REG_STRING starts *before* REGISTER_PREFIX. */ 5882 5883static const reg_entry * 5884parse_register (char *reg_string, char **end_op) 5885{ 5886 const reg_entry *r; 5887 5888 if (*reg_string == REGISTER_PREFIX || allow_naked_reg) 5889 r = parse_real_register (reg_string, end_op); 5890 else 5891 r = NULL; 5892 if (!r) 5893 { 5894 char *save = input_line_pointer; 5895 char c; 5896 symbolS *symbolP; 5897 5898 input_line_pointer = reg_string; 5899 c = get_symbol_end (); 5900 symbolP = symbol_find (reg_string); 5901 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) 5902 { 5903 const expressionS *e = symbol_get_value_expression (symbolP); 5904 5905 know (e->X_op == O_register); 5906 know (e->X_add_number >= 0 5907 && (valueT) e->X_add_number < i386_regtab_size); 5908 r = i386_regtab + e->X_add_number; 5909 *end_op = input_line_pointer; 5910 } 5911 *input_line_pointer = c; 5912 input_line_pointer = save; 5913 } 5914 return r; 5915} 5916 5917int 5918i386_parse_name (char *name, expressionS *e, char *nextcharP) 5919{ 5920 const reg_entry *r; 5921 char *end = input_line_pointer; 5922 5923 *end = *nextcharP; 5924 r = parse_register (name, &input_line_pointer); 5925 if (r && end <= input_line_pointer) 5926 { 5927 *nextcharP = *input_line_pointer; 5928 *input_line_pointer = 0; 5929 e->X_op = O_register; 5930 e->X_add_number = r - i386_regtab; 5931 return 1; 5932 } 5933 input_line_pointer = end; 5934 *end = 0; 5935 return 0; 5936} 5937 5938void 5939md_operand (expressionS *e) 5940{ 5941 if (*input_line_pointer == REGISTER_PREFIX) 5942 { 5943 char *end; 5944 const reg_entry *r = parse_real_register (input_line_pointer, &end); 5945 5946 if (r) 5947 { 5948 e->X_op = O_register; 5949 e->X_add_number = r - i386_regtab; 5950 input_line_pointer = end; 5951 } 5952 } 5953} 5954 5955 5956#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5957const char *md_shortopts = "kVQ:sqn"; 5958#else 5959const char *md_shortopts = "qn"; 5960#endif 5961 5962#define OPTION_32 (OPTION_MD_BASE + 0) 5963#define OPTION_64 (OPTION_MD_BASE + 1) 5964#define OPTION_DIVIDE (OPTION_MD_BASE + 2) 5965#define OPTION_MARCH (OPTION_MD_BASE + 3) 5966#define OPTION_MTUNE (OPTION_MD_BASE + 4) 5967 5968struct option md_longopts[] = 5969{ 5970 {"32", no_argument, NULL, OPTION_32}, 5971#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) 5972 {"64", no_argument, NULL, OPTION_64}, 5973#endif 5974 {"divide", no_argument, NULL, OPTION_DIVIDE}, 5975 {"march", required_argument, NULL, OPTION_MARCH}, 5976 {"mtune", required_argument, NULL, OPTION_MTUNE}, 5977 {NULL, no_argument, NULL, 0} 5978}; 5979size_t md_longopts_size = sizeof (md_longopts); 5980 5981int 5982md_parse_option (int c, char *arg) 5983{ 5984 unsigned int i; 5985 5986 switch (c) 5987 { 5988 case 'n': 5989 optimize_align_code = 0; 5990 break; 5991 5992 case 'q': 5993 quiet_warnings = 1; 5994 break; 5995 5996#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5997 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section 5998 should be emitted or not. FIXME: Not implemented. */ 5999 case 'Q': 6000 break; 6001 6002 /* -V: SVR4 argument to print version ID. */ 6003 case 'V': 6004 print_version_id (); 6005 break; 6006 6007 /* -k: Ignore for FreeBSD compatibility. */ 6008 case 'k': 6009 break; 6010 6011 case 's': 6012 /* -s: On i386 Solaris, this tells the native assembler to use 6013 .stab instead of .stab.excl. We always use .stab anyhow. */ 6014 break; 6015#endif 6016#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) 6017 case OPTION_64: 6018 { 6019 const char **list, **l; 6020 6021 list = bfd_target_list (); 6022 for (l = list; *l != NULL; l++) 6023 if (CONST_STRNEQ (*l, "elf64-x86-64") 6024 || strcmp (*l, "coff-x86-64") == 0 6025 || strcmp (*l, "pe-x86-64") == 0 6026 || strcmp (*l, "pei-x86-64") == 0) 6027 { 6028 default_arch = "x86_64"; 6029 break; 6030 } 6031 if (*l == NULL) 6032 as_fatal (_("No compiled in support for x86_64")); 6033 free (list); 6034 } 6035 break; 6036#endif 6037 6038 case OPTION_32: 6039 default_arch = "i386"; 6040 break; 6041 6042 case OPTION_DIVIDE: 6043#ifdef SVR4_COMMENT_CHARS 6044 { 6045 char *n, *t; 6046 const char *s; 6047 6048 n = (char *) xmalloc (strlen (i386_comment_chars) + 1); 6049 t = n; 6050 for (s = i386_comment_chars; *s != '\0'; s++) 6051 if (*s != '/') 6052 *t++ = *s; 6053 *t = '\0'; 6054 i386_comment_chars = n; 6055 } 6056#endif 6057 break; 6058 6059 case OPTION_MARCH: 6060 if (*arg == '.') 6061 as_fatal (_("Invalid -march= option: `%s'"), arg); 6062 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) 6063 { 6064 if (strcmp (arg, cpu_arch [i].name) == 0) 6065 { 6066 cpu_arch_isa = cpu_arch[i].type; 6067 cpu_arch_isa_flags = cpu_arch[i].flags; 6068 if (!cpu_arch_tune_set) 6069 { 6070 cpu_arch_tune = cpu_arch_isa; 6071 cpu_arch_tune_flags = cpu_arch_isa_flags; 6072 } 6073 break; 6074 } 6075 } 6076 if (i >= ARRAY_SIZE (cpu_arch)) 6077 as_fatal (_("Invalid -march= option: `%s'"), arg); 6078 break; 6079 6080 case OPTION_MTUNE: 6081 if (*arg == '.') 6082 as_fatal (_("Invalid -mtune= option: `%s'"), arg); 6083 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) 6084 { 6085 if (strcmp (arg, cpu_arch [i].name) == 0) 6086 { 6087 cpu_arch_tune_set = 1; 6088 cpu_arch_tune = cpu_arch [i].type; 6089 cpu_arch_tune_flags = cpu_arch[i].flags; 6090 break; 6091 } 6092 } 6093 if (i >= ARRAY_SIZE (cpu_arch)) 6094 as_fatal (_("Invalid -mtune= option: `%s'"), arg); 6095 break; 6096 6097 default: 6098 return 0; 6099 } 6100 return 1; 6101} 6102 6103void 6104md_show_usage (stream) 6105 FILE *stream; 6106{ 6107#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 6108 fprintf (stream, _("\ 6109 -Q ignored\n\ 6110 -V print assembler version number\n\ 6111 -k ignored\n")); 6112#endif 6113 fprintf (stream, _("\ 6114 -n Do not optimize code alignment\n\ 6115 -q quieten some warnings\n")); 6116#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 6117 fprintf (stream, _("\ 6118 -s ignored\n")); 6119#endif 6120#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) 6121 fprintf (stream, _("\ 6122 --32/--64 generate 32bit/64bit code\n")); 6123#endif 6124#ifdef SVR4_COMMENT_CHARS 6125 fprintf (stream, _("\ 6126 --divide do not treat `/' as a comment character\n")); 6127#else 6128 fprintf (stream, _("\ 6129 --divide ignored\n")); 6130#endif 6131 fprintf (stream, _("\ 6132 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\ 6133 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\ 6134 core, core2, k6, athlon, k8, generic32, generic64\n")); 6135 6136} 6137 6138#if defined(TE_PEP) 6139const char * 6140x86_64_target_format (void) 6141{ 6142 if (strcmp (default_arch, "x86_64") == 0) 6143 { 6144 set_code_flag (CODE_64BIT); 6145 return COFF_TARGET_FORMAT; 6146 } 6147 else if (strcmp (default_arch, "i386") == 0) 6148 { 6149 set_code_flag (CODE_32BIT); 6150 return "coff-i386"; 6151 } 6152 6153 as_fatal (_("Unknown architecture")); 6154 return NULL; 6155} 6156#endif 6157 6158#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ 6159 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) 6160 6161/* Pick the target format to use. */ 6162 6163const char * 6164i386_target_format (void) 6165{ 6166 if (!strcmp (default_arch, "x86_64")) 6167 { 6168 set_code_flag (CODE_64BIT); 6169 if (cpu_arch_isa_flags == 0) 6170 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486 6171 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2 6172 |CpuSSE|CpuSSE2; 6173 if (cpu_arch_tune_flags == 0) 6174 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486 6175 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2 6176 |CpuSSE|CpuSSE2; 6177 } 6178 else if (!strcmp (default_arch, "i386")) 6179 { 6180 set_code_flag (CODE_32BIT); 6181 if (cpu_arch_isa_flags == 0) 6182 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386; 6183 if (cpu_arch_tune_flags == 0) 6184 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386; 6185 } 6186 else 6187 as_fatal (_("Unknown architecture")); 6188 switch (OUTPUT_FLAVOR) 6189 { 6190#ifdef OBJ_MAYBE_AOUT 6191 case bfd_target_aout_flavour: 6192 return AOUT_TARGET_FORMAT; 6193#endif 6194#ifdef OBJ_MAYBE_COFF 6195 case bfd_target_coff_flavour: 6196 return "coff-i386"; 6197#endif 6198#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) 6199 case bfd_target_elf_flavour: 6200 { 6201 if (flag_code == CODE_64BIT) 6202 { 6203 object_64bit = 1; 6204 use_rela_relocations = 1; 6205 } 6206 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT; 6207 } 6208#endif 6209 default: 6210 abort (); 6211 return NULL; 6212 } 6213} 6214 6215#endif /* OBJ_MAYBE_ more than one */ 6216 6217#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) 6218void 6219i386_elf_emit_arch_note (void) 6220{ 6221 if (IS_ELF && cpu_arch_name != NULL) 6222 { 6223 char *p; 6224 asection *seg = now_seg; 6225 subsegT subseg = now_subseg; 6226 Elf_Internal_Note i_note; 6227 Elf_External_Note e_note; 6228 asection *note_secp; 6229 int len; 6230 6231 /* Create the .note section. */ 6232 note_secp = subseg_new (".note", 0); 6233 bfd_set_section_flags (stdoutput, 6234 note_secp, 6235 SEC_HAS_CONTENTS | SEC_READONLY); 6236 6237 /* Process the arch string. */ 6238 len = strlen (cpu_arch_name); 6239 6240 i_note.namesz = len + 1; 6241 i_note.descsz = 0; 6242 i_note.type = NT_ARCH; 6243 p = frag_more (sizeof (e_note.namesz)); 6244 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); 6245 p = frag_more (sizeof (e_note.descsz)); 6246 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); 6247 p = frag_more (sizeof (e_note.type)); 6248 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); 6249 p = frag_more (len + 1); 6250 strcpy (p, cpu_arch_name); 6251 6252 frag_align (2, 0, 0); 6253 6254 subseg_set (seg, subseg); 6255 } 6256} 6257#endif 6258 6259symbolS * 6260md_undefined_symbol (name) 6261 char *name; 6262{ 6263 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] 6264 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] 6265 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] 6266 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) 6267 { 6268 if (!GOT_symbol) 6269 { 6270 if (symbol_find (name)) 6271 as_bad (_("GOT already in symbol table")); 6272 GOT_symbol = symbol_new (name, undefined_section, 6273 (valueT) 0, &zero_address_frag); 6274 }; 6275 return GOT_symbol; 6276 } 6277 return 0; 6278} 6279 6280/* Round up a section size to the appropriate boundary. */ 6281 6282valueT 6283md_section_align (segment, size) 6284 segT segment ATTRIBUTE_UNUSED; 6285 valueT size; 6286{ 6287#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 6288 if (OUTPUT_FLAVOR == bfd_target_aout_flavour) 6289 { 6290 /* For a.out, force the section size to be aligned. If we don't do 6291 this, BFD will align it for us, but it will not write out the 6292 final bytes of the section. This may be a bug in BFD, but it is 6293 easier to fix it here since that is how the other a.out targets 6294 work. */ 6295 int align; 6296 6297 align = bfd_get_section_alignment (stdoutput, segment); 6298 size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); 6299 } 6300#endif 6301 6302 return size; 6303} 6304 6305/* On the i386, PC-relative offsets are relative to the start of the 6306 next instruction. That is, the address of the offset, plus its 6307 size, since the offset is always the last part of the insn. */ 6308 6309long 6310md_pcrel_from (fixS *fixP) 6311{ 6312 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; 6313} 6314 6315#ifndef I386COFF 6316 6317static void 6318s_bss (int ignore ATTRIBUTE_UNUSED) 6319{ 6320 int temp; 6321 6322#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 6323 if (IS_ELF) 6324 obj_elf_section_change_hook (); 6325#endif 6326 temp = get_absolute_expression (); 6327 subseg_set (bss_section, (subsegT) temp); 6328 demand_empty_rest_of_line (); 6329} 6330 6331#endif 6332 6333void 6334i386_validate_fix (fixS *fixp) 6335{ 6336 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) 6337 { 6338 if (fixp->fx_r_type == BFD_RELOC_32_PCREL) 6339 { 6340 if (!object_64bit) 6341 abort (); 6342 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; 6343 } 6344 else 6345 { 6346 if (!object_64bit) 6347 fixp->fx_r_type = BFD_RELOC_386_GOTOFF; 6348 else 6349 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; 6350 } 6351 fixp->fx_subsy = 0; 6352 } 6353} 6354 6355arelent * 6356tc_gen_reloc (section, fixp) 6357 asection *section ATTRIBUTE_UNUSED; 6358 fixS *fixp; 6359{ 6360 arelent *rel; 6361 bfd_reloc_code_real_type code; 6362 6363 switch (fixp->fx_r_type) 6364 { 6365 case BFD_RELOC_X86_64_PLT32: 6366 case BFD_RELOC_X86_64_GOT32: 6367 case BFD_RELOC_X86_64_GOTPCREL: 6368 case BFD_RELOC_386_PLT32: 6369 case BFD_RELOC_386_GOT32: 6370 case BFD_RELOC_386_GOTOFF: 6371 case BFD_RELOC_386_GOTPC: 6372 case BFD_RELOC_386_TLS_GD: 6373 case BFD_RELOC_386_TLS_LDM: 6374 case BFD_RELOC_386_TLS_LDO_32: 6375 case BFD_RELOC_386_TLS_IE_32: 6376 case BFD_RELOC_386_TLS_IE: 6377 case BFD_RELOC_386_TLS_GOTIE: 6378 case BFD_RELOC_386_TLS_LE_32: 6379 case BFD_RELOC_386_TLS_LE: 6380 case BFD_RELOC_386_TLS_GOTDESC: 6381 case BFD_RELOC_386_TLS_DESC_CALL: 6382 case BFD_RELOC_X86_64_TLSGD: 6383 case BFD_RELOC_X86_64_TLSLD: 6384 case BFD_RELOC_X86_64_DTPOFF32: 6385 case BFD_RELOC_X86_64_DTPOFF64: 6386 case BFD_RELOC_X86_64_GOTTPOFF: 6387 case BFD_RELOC_X86_64_TPOFF32: 6388 case BFD_RELOC_X86_64_TPOFF64: 6389 case BFD_RELOC_X86_64_GOTOFF64: 6390 case BFD_RELOC_X86_64_GOTPC32: 6391 case BFD_RELOC_X86_64_GOT64: 6392 case BFD_RELOC_X86_64_GOTPCREL64: 6393 case BFD_RELOC_X86_64_GOTPC64: 6394 case BFD_RELOC_X86_64_GOTPLT64: 6395 case BFD_RELOC_X86_64_PLTOFF64: 6396 case BFD_RELOC_X86_64_GOTPC32_TLSDESC: 6397 case BFD_RELOC_X86_64_TLSDESC_CALL: 6398 case BFD_RELOC_RVA: 6399 case BFD_RELOC_VTABLE_ENTRY: 6400 case BFD_RELOC_VTABLE_INHERIT: 6401#ifdef TE_PE 6402 case BFD_RELOC_32_SECREL: 6403#endif 6404 code = fixp->fx_r_type; 6405 break; 6406 case BFD_RELOC_X86_64_32S: 6407 if (!fixp->fx_pcrel) 6408 { 6409 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ 6410 code = fixp->fx_r_type; 6411 break; 6412 } 6413 default: 6414 if (fixp->fx_pcrel) 6415 { 6416 switch (fixp->fx_size) 6417 { 6418 default: 6419 as_bad_where (fixp->fx_file, fixp->fx_line, 6420 _("can not do %d byte pc-relative relocation"), 6421 fixp->fx_size); 6422 code = BFD_RELOC_32_PCREL; 6423 break; 6424 case 1: code = BFD_RELOC_8_PCREL; break; 6425 case 2: code = BFD_RELOC_16_PCREL; break; 6426 case 4: code = BFD_RELOC_32_PCREL; break; 6427#ifdef BFD64 6428 case 8: code = BFD_RELOC_64_PCREL; break; 6429#endif 6430 } 6431 } 6432 else 6433 { 6434 switch (fixp->fx_size) 6435 { 6436 default: 6437 as_bad_where (fixp->fx_file, fixp->fx_line, 6438 _("can not do %d byte relocation"), 6439 fixp->fx_size); 6440 code = BFD_RELOC_32; 6441 break; 6442 case 1: code = BFD_RELOC_8; break; 6443 case 2: code = BFD_RELOC_16; break; 6444 case 4: code = BFD_RELOC_32; break; 6445#ifdef BFD64 6446 case 8: code = BFD_RELOC_64; break; 6447#endif 6448 } 6449 } 6450 break; 6451 } 6452 6453 if ((code == BFD_RELOC_32 6454 || code == BFD_RELOC_32_PCREL 6455 || code == BFD_RELOC_X86_64_32S) 6456 && GOT_symbol 6457 && fixp->fx_addsy == GOT_symbol) 6458 { 6459 if (!object_64bit) 6460 code = BFD_RELOC_386_GOTPC; 6461 else 6462 code = BFD_RELOC_X86_64_GOTPC32; 6463 } 6464 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) 6465 && GOT_symbol 6466 && fixp->fx_addsy == GOT_symbol) 6467 { 6468 code = BFD_RELOC_X86_64_GOTPC64; 6469 } 6470 6471 rel = (arelent *) xmalloc (sizeof (arelent)); 6472 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 6473 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 6474 6475 rel->address = fixp->fx_frag->fr_address + fixp->fx_where; 6476 6477 if (!use_rela_relocations) 6478 { 6479 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the 6480 vtable entry to be used in the relocation's section offset. */ 6481 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 6482 rel->address = fixp->fx_offset; 6483 6484 rel->addend = 0; 6485 } 6486 /* Use the rela in 64bit mode. */ 6487 else 6488 { 6489 if (!fixp->fx_pcrel) 6490 rel->addend = fixp->fx_offset; 6491 else 6492 switch (code) 6493 { 6494 case BFD_RELOC_X86_64_PLT32: 6495 case BFD_RELOC_X86_64_GOT32: 6496 case BFD_RELOC_X86_64_GOTPCREL: 6497 case BFD_RELOC_X86_64_TLSGD: 6498 case BFD_RELOC_X86_64_TLSLD: 6499 case BFD_RELOC_X86_64_GOTTPOFF: 6500 case BFD_RELOC_X86_64_GOTPC32_TLSDESC: 6501 case BFD_RELOC_X86_64_TLSDESC_CALL: 6502 rel->addend = fixp->fx_offset - fixp->fx_size; 6503 break; 6504 default: 6505 rel->addend = (section->vma 6506 - fixp->fx_size 6507 + fixp->fx_addnumber 6508 + md_pcrel_from (fixp)); 6509 break; 6510 } 6511 } 6512 6513 rel->howto = bfd_reloc_type_lookup (stdoutput, code); 6514 if (rel->howto == NULL) 6515 { 6516 as_bad_where (fixp->fx_file, fixp->fx_line, 6517 _("cannot represent relocation type %s"), 6518 bfd_get_reloc_code_name (code)); 6519 /* Set howto to a garbage value so that we can keep going. */ 6520 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); 6521 assert (rel->howto != NULL); 6522 } 6523 6524 return rel; 6525} 6526 6527 6528/* Parse operands using Intel syntax. This implements a recursive descent 6529 parser based on the BNF grammar published in Appendix B of the MASM 6.1 6530 Programmer's Guide. 6531 6532 FIXME: We do not recognize the full operand grammar defined in the MASM 6533 documentation. In particular, all the structure/union and 6534 high-level macro operands are missing. 6535 6536 Uppercase words are terminals, lower case words are non-terminals. 6537 Objects surrounded by double brackets '[[' ']]' are optional. Vertical 6538 bars '|' denote choices. Most grammar productions are implemented in 6539 functions called 'intel_<production>'. 6540 6541 Initial production is 'expr'. 6542 6543 addOp + | - 6544 6545 alpha [a-zA-Z] 6546 6547 binOp & | AND | \| | OR | ^ | XOR 6548 6549 byteRegister AL | AH | BL | BH | CL | CH | DL | DH 6550 6551 constant digits [[ radixOverride ]] 6552 6553 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD 6554 6555 digits decdigit 6556 | digits decdigit 6557 | digits hexdigit 6558 6559 decdigit [0-9] 6560 6561 e04 e04 addOp e05 6562 | e05 6563 6564 e05 e05 binOp e06 6565 | e06 6566 6567 e06 e06 mulOp e09 6568 | e09 6569 6570 e09 OFFSET e10 6571 | SHORT e10 6572 | + e10 6573 | - e10 6574 | ~ e10 6575 | NOT e10 6576 | e09 PTR e10 6577 | e09 : e10 6578 | e10 6579 6580 e10 e10 [ expr ] 6581 | e11 6582 6583 e11 ( expr ) 6584 | [ expr ] 6585 | constant 6586 | dataType 6587 | id 6588 | $ 6589 | register 6590 6591 => expr expr cmpOp e04 6592 | e04 6593 6594 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX 6595 | BP | EBP | SP | ESP | DI | EDI | SI | ESI 6596 6597 hexdigit a | b | c | d | e | f 6598 | A | B | C | D | E | F 6599 6600 id alpha 6601 | id alpha 6602 | id decdigit 6603 6604 mulOp * | / | % | MOD | << | SHL | >> | SHR 6605 6606 quote " | ' 6607 6608 register specialRegister 6609 | gpRegister 6610 | byteRegister 6611 6612 segmentRegister CS | DS | ES | FS | GS | SS 6613 6614 specialRegister CR0 | CR2 | CR3 | CR4 6615 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 6616 | TR3 | TR4 | TR5 | TR6 | TR7 6617 6618 We simplify the grammar in obvious places (e.g., register parsing is 6619 done by calling parse_register) and eliminate immediate left recursion 6620 to implement a recursive-descent parser. 6621 6622 expr e04 expr' 6623 6624 expr' cmpOp e04 expr' 6625 | Empty 6626 6627 e04 e05 e04' 6628 6629 e04' addOp e05 e04' 6630 | Empty 6631 6632 e05 e06 e05' 6633 6634 e05' binOp e06 e05' 6635 | Empty 6636 6637 e06 e09 e06' 6638 6639 e06' mulOp e09 e06' 6640 | Empty 6641 6642 e09 OFFSET e10 e09' 6643 | SHORT e10' 6644 | + e10' 6645 | - e10' 6646 | ~ e10' 6647 | NOT e10' 6648 | e10 e09' 6649 6650 e09' PTR e10 e09' 6651 | : e10 e09' 6652 | Empty 6653 6654 e10 e11 e10' 6655 6656 e10' [ expr ] e10' 6657 | Empty 6658 6659 e11 ( expr ) 6660 | [ expr ] 6661 | BYTE 6662 | WORD 6663 | DWORD 6664 | FWORD 6665 | QWORD 6666 | TBYTE 6667 | OWORD 6668 | XMMWORD 6669 | . 6670 | $ 6671 | register 6672 | id 6673 | constant */ 6674 6675/* Parsing structure for the intel syntax parser. Used to implement the 6676 semantic actions for the operand grammar. */ 6677struct intel_parser_s 6678 { 6679 char *op_string; /* The string being parsed. */ 6680 int got_a_float; /* Whether the operand is a float. */ 6681 int op_modifier; /* Operand modifier. */ 6682 int is_mem; /* 1 if operand is memory reference. */ 6683 int in_offset; /* >=1 if parsing operand of offset. */ 6684 int in_bracket; /* >=1 if parsing operand in brackets. */ 6685 const reg_entry *reg; /* Last register reference found. */ 6686 char *disp; /* Displacement string being built. */ 6687 char *next_operand; /* Resume point when splitting operands. */ 6688 }; 6689 6690static struct intel_parser_s intel_parser; 6691 6692/* Token structure for parsing intel syntax. */ 6693struct intel_token 6694 { 6695 int code; /* Token code. */ 6696 const reg_entry *reg; /* Register entry for register tokens. */ 6697 char *str; /* String representation. */ 6698 }; 6699 6700static struct intel_token cur_token, prev_token; 6701 6702/* Token codes for the intel parser. Since T_SHORT is already used 6703 by COFF, undefine it first to prevent a warning. */ 6704#define T_NIL -1 6705#define T_CONST 1 6706#define T_REG 2 6707#define T_BYTE 3 6708#define T_WORD 4 6709#define T_DWORD 5 6710#define T_FWORD 6 6711#define T_QWORD 7 6712#define T_TBYTE 8 6713#define T_XMMWORD 9 6714#undef T_SHORT 6715#define T_SHORT 10 6716#define T_OFFSET 11 6717#define T_PTR 12 6718#define T_ID 13 6719#define T_SHL 14 6720#define T_SHR 15 6721 6722/* Prototypes for intel parser functions. */ 6723static int intel_match_token (int); 6724static void intel_putback_token (void); 6725static void intel_get_token (void); 6726static int intel_expr (void); 6727static int intel_e04 (void); 6728static int intel_e05 (void); 6729static int intel_e06 (void); 6730static int intel_e09 (void); 6731static int intel_e10 (void); 6732static int intel_e11 (void); 6733 6734static int 6735i386_intel_operand (char *operand_string, int got_a_float) 6736{ 6737 int ret; 6738 char *p; 6739 6740 p = intel_parser.op_string = xstrdup (operand_string); 6741 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1); 6742 6743 for (;;) 6744 { 6745 /* Initialize token holders. */ 6746 cur_token.code = prev_token.code = T_NIL; 6747 cur_token.reg = prev_token.reg = NULL; 6748 cur_token.str = prev_token.str = NULL; 6749 6750 /* Initialize parser structure. */ 6751 intel_parser.got_a_float = got_a_float; 6752 intel_parser.op_modifier = 0; 6753 intel_parser.is_mem = 0; 6754 intel_parser.in_offset = 0; 6755 intel_parser.in_bracket = 0; 6756 intel_parser.reg = NULL; 6757 intel_parser.disp[0] = '\0'; 6758 intel_parser.next_operand = NULL; 6759 6760 /* Read the first token and start the parser. */ 6761 intel_get_token (); 6762 ret = intel_expr (); 6763 6764 if (!ret) 6765 break; 6766 6767 if (cur_token.code != T_NIL) 6768 { 6769 as_bad (_("invalid operand for '%s' ('%s' unexpected)"), 6770 current_templates->start->name, cur_token.str); 6771 ret = 0; 6772 } 6773 /* If we found a memory reference, hand it over to i386_displacement 6774 to fill in the rest of the operand fields. */ 6775 else if (intel_parser.is_mem) 6776 { 6777 if ((i.mem_operands == 1 6778 && (current_templates->start->opcode_modifier & IsString) == 0) 6779 || i.mem_operands == 2) 6780 { 6781 as_bad (_("too many memory references for '%s'"), 6782 current_templates->start->name); 6783 ret = 0; 6784 } 6785 else 6786 { 6787 char *s = intel_parser.disp; 6788 i.mem_operands++; 6789 6790 if (!quiet_warnings && intel_parser.is_mem < 0) 6791 /* See the comments in intel_bracket_expr. */ 6792 as_warn (_("Treating `%s' as memory reference"), operand_string); 6793 6794 /* Add the displacement expression. */ 6795 if (*s != '\0') 6796 ret = i386_displacement (s, s + strlen (s)); 6797 if (ret) 6798 { 6799 /* Swap base and index in 16-bit memory operands like 6800 [si+bx]. Since i386_index_check is also used in AT&T 6801 mode we have to do that here. */ 6802 if (i.base_reg 6803 && i.index_reg 6804 && (i.base_reg->reg_type & Reg16) 6805 && (i.index_reg->reg_type & Reg16) 6806 && i.base_reg->reg_num >= 6 6807 && i.index_reg->reg_num < 6) 6808 { 6809 const reg_entry *base = i.index_reg; 6810 6811 i.index_reg = i.base_reg; 6812 i.base_reg = base; 6813 } 6814 ret = i386_index_check (operand_string); 6815 } 6816 } 6817 } 6818 6819 /* Constant and OFFSET expressions are handled by i386_immediate. */ 6820 else if ((intel_parser.op_modifier & (1 << T_OFFSET)) 6821 || intel_parser.reg == NULL) 6822 ret = i386_immediate (intel_parser.disp); 6823 6824 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1) 6825 ret = 0; 6826 if (!ret || !intel_parser.next_operand) 6827 break; 6828 intel_parser.op_string = intel_parser.next_operand; 6829 this_operand = i.operands++; 6830 } 6831 6832 free (p); 6833 free (intel_parser.disp); 6834 6835 return ret; 6836} 6837 6838#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg) 6839 6840/* expr e04 expr' 6841 6842 expr' cmpOp e04 expr' 6843 | Empty */ 6844static int 6845intel_expr (void) 6846{ 6847 /* XXX Implement the comparison operators. */ 6848 return intel_e04 (); 6849} 6850 6851/* e04 e05 e04' 6852 6853 e04' addOp e05 e04' 6854 | Empty */ 6855static int 6856intel_e04 (void) 6857{ 6858 int nregs = -1; 6859 6860 for (;;) 6861 { 6862 if (!intel_e05()) 6863 return 0; 6864 6865 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) 6866 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */ 6867 6868 if (cur_token.code == '+') 6869 nregs = -1; 6870 else if (cur_token.code == '-') 6871 nregs = NUM_ADDRESS_REGS; 6872 else 6873 return 1; 6874 6875 strcat (intel_parser.disp, cur_token.str); 6876 intel_match_token (cur_token.code); 6877 } 6878} 6879 6880/* e05 e06 e05' 6881 6882 e05' binOp e06 e05' 6883 | Empty */ 6884static int 6885intel_e05 (void) 6886{ 6887 int nregs = ~NUM_ADDRESS_REGS; 6888 6889 for (;;) 6890 { 6891 if (!intel_e06()) 6892 return 0; 6893 6894 if (cur_token.code == '&' 6895 || cur_token.code == '|' 6896 || cur_token.code == '^') 6897 { 6898 char str[2]; 6899 6900 str[0] = cur_token.code; 6901 str[1] = 0; 6902 strcat (intel_parser.disp, str); 6903 } 6904 else 6905 break; 6906 6907 intel_match_token (cur_token.code); 6908 6909 if (nregs < 0) 6910 nregs = ~nregs; 6911 } 6912 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) 6913 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */ 6914 return 1; 6915} 6916 6917/* e06 e09 e06' 6918 6919 e06' mulOp e09 e06' 6920 | Empty */ 6921static int 6922intel_e06 (void) 6923{ 6924 int nregs = ~NUM_ADDRESS_REGS; 6925 6926 for (;;) 6927 { 6928 if (!intel_e09()) 6929 return 0; 6930 6931 if (cur_token.code == '*' 6932 || cur_token.code == '/' 6933 || cur_token.code == '%') 6934 { 6935 char str[2]; 6936 6937 str[0] = cur_token.code; 6938 str[1] = 0; 6939 strcat (intel_parser.disp, str); 6940 } 6941 else if (cur_token.code == T_SHL) 6942 strcat (intel_parser.disp, "<<"); 6943 else if (cur_token.code == T_SHR) 6944 strcat (intel_parser.disp, ">>"); 6945 else 6946 break; 6947 6948 intel_match_token (cur_token.code); 6949 6950 if (nregs < 0) 6951 nregs = ~nregs; 6952 } 6953 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) 6954 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */ 6955 return 1; 6956} 6957 6958/* e09 OFFSET e09 6959 | SHORT e09 6960 | + e09 6961 | - e09 6962 | ~ e09 6963 | NOT e09 6964 | e10 e09' 6965 6966 e09' PTR e10 e09' 6967 | : e10 e09' 6968 | Empty */ 6969static int 6970intel_e09 (void) 6971{ 6972 int nregs = ~NUM_ADDRESS_REGS; 6973 int in_offset = 0; 6974 6975 for (;;) 6976 { 6977 /* Don't consume constants here. */ 6978 if (cur_token.code == '+' || cur_token.code == '-') 6979 { 6980 /* Need to look one token ahead - if the next token 6981 is a constant, the current token is its sign. */ 6982 int next_code; 6983 6984 intel_match_token (cur_token.code); 6985 next_code = cur_token.code; 6986 intel_putback_token (); 6987 if (next_code == T_CONST) 6988 break; 6989 } 6990 6991 /* e09 OFFSET e09 */ 6992 if (cur_token.code == T_OFFSET) 6993 { 6994 if (!in_offset++) 6995 ++intel_parser.in_offset; 6996 } 6997 6998 /* e09 SHORT e09 */ 6999 else if (cur_token.code == T_SHORT) 7000 intel_parser.op_modifier |= 1 << T_SHORT; 7001 7002 /* e09 + e09 */ 7003 else if (cur_token.code == '+') 7004 strcat (intel_parser.disp, "+"); 7005 7006 /* e09 - e09 7007 | ~ e09 7008 | NOT e09 */ 7009 else if (cur_token.code == '-' || cur_token.code == '~') 7010 { 7011 char str[2]; 7012 7013 if (nregs < 0) 7014 nregs = ~nregs; 7015 str[0] = cur_token.code; 7016 str[1] = 0; 7017 strcat (intel_parser.disp, str); 7018 } 7019 7020 /* e09 e10 e09' */ 7021 else 7022 break; 7023 7024 intel_match_token (cur_token.code); 7025 } 7026 7027 for (;;) 7028 { 7029 if (!intel_e10 ()) 7030 return 0; 7031 7032 /* e09' PTR e10 e09' */ 7033 if (cur_token.code == T_PTR) 7034 { 7035 char suffix; 7036 7037 if (prev_token.code == T_BYTE) 7038 suffix = BYTE_MNEM_SUFFIX; 7039 7040 else if (prev_token.code == T_WORD) 7041 { 7042 if (current_templates->start->name[0] == 'l' 7043 && current_templates->start->name[2] == 's' 7044 && current_templates->start->name[3] == 0) 7045 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ 7046 else if (intel_parser.got_a_float == 2) /* "fi..." */ 7047 suffix = SHORT_MNEM_SUFFIX; 7048 else 7049 suffix = WORD_MNEM_SUFFIX; 7050 } 7051 7052 else if (prev_token.code == T_DWORD) 7053 { 7054 if (current_templates->start->name[0] == 'l' 7055 && current_templates->start->name[2] == 's' 7056 && current_templates->start->name[3] == 0) 7057 suffix = WORD_MNEM_SUFFIX; 7058 else if (flag_code == CODE_16BIT 7059 && (current_templates->start->opcode_modifier 7060 & (Jump | JumpDword))) 7061 suffix = LONG_DOUBLE_MNEM_SUFFIX; 7062 else if (intel_parser.got_a_float == 1) /* "f..." */ 7063 suffix = SHORT_MNEM_SUFFIX; 7064 else 7065 suffix = LONG_MNEM_SUFFIX; 7066 } 7067 7068 else if (prev_token.code == T_FWORD) 7069 { 7070 if (current_templates->start->name[0] == 'l' 7071 && current_templates->start->name[2] == 's' 7072 && current_templates->start->name[3] == 0) 7073 suffix = LONG_MNEM_SUFFIX; 7074 else if (!intel_parser.got_a_float) 7075 { 7076 if (flag_code == CODE_16BIT) 7077 add_prefix (DATA_PREFIX_OPCODE); 7078 suffix = LONG_DOUBLE_MNEM_SUFFIX; 7079 } 7080 else 7081 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ 7082 } 7083 7084 else if (prev_token.code == T_QWORD) 7085 { 7086 if (intel_parser.got_a_float == 1) /* "f..." */ 7087 suffix = LONG_MNEM_SUFFIX; 7088 else 7089 suffix = QWORD_MNEM_SUFFIX; 7090 } 7091 7092 else if (prev_token.code == T_TBYTE) 7093 { 7094 if (intel_parser.got_a_float == 1) 7095 suffix = LONG_DOUBLE_MNEM_SUFFIX; 7096 else 7097 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ 7098 } 7099 7100 else if (prev_token.code == T_XMMWORD) 7101 { 7102 /* XXX ignored for now, but accepted since gcc uses it */ 7103 suffix = 0; 7104 } 7105 7106 else 7107 { 7108 as_bad (_("Unknown operand modifier `%s'"), prev_token.str); 7109 return 0; 7110 } 7111 7112 /* Operands for jump/call using 'ptr' notation denote absolute 7113 addresses. */ 7114 if (current_templates->start->opcode_modifier & (Jump | JumpDword)) 7115 i.types[this_operand] |= JumpAbsolute; 7116 7117 if (current_templates->start->base_opcode == 0x8d /* lea */) 7118 ; 7119 else if (!i.suffix) 7120 i.suffix = suffix; 7121 else if (i.suffix != suffix) 7122 { 7123 as_bad (_("Conflicting operand modifiers")); 7124 return 0; 7125 } 7126 7127 } 7128 7129 /* e09' : e10 e09' */ 7130 else if (cur_token.code == ':') 7131 { 7132 if (prev_token.code != T_REG) 7133 { 7134 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a 7135 segment/group identifier (which we don't have), using comma 7136 as the operand separator there is even less consistent, since 7137 there all branches only have a single operand. */ 7138 if (this_operand != 0 7139 || intel_parser.in_offset 7140 || intel_parser.in_bracket 7141 || (!(current_templates->start->opcode_modifier 7142 & (Jump|JumpDword|JumpInterSegment)) 7143 && !(current_templates->start->operand_types[0] 7144 & JumpAbsolute))) 7145 return intel_match_token (T_NIL); 7146 /* Remember the start of the 2nd operand and terminate 1st 7147 operand here. 7148 XXX This isn't right, yet (when SSSS:OOOO is right operand of 7149 another expression), but it gets at least the simplest case 7150 (a plain number or symbol on the left side) right. */ 7151 intel_parser.next_operand = intel_parser.op_string; 7152 *--intel_parser.op_string = '\0'; 7153 return intel_match_token (':'); 7154 } 7155 } 7156 7157 /* e09' Empty */ 7158 else 7159 break; 7160 7161 intel_match_token (cur_token.code); 7162 7163 } 7164 7165 if (in_offset) 7166 { 7167 --intel_parser.in_offset; 7168 if (nregs < 0) 7169 nregs = ~nregs; 7170 if (NUM_ADDRESS_REGS > nregs) 7171 { 7172 as_bad (_("Invalid operand to `OFFSET'")); 7173 return 0; 7174 } 7175 intel_parser.op_modifier |= 1 << T_OFFSET; 7176 } 7177 7178 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) 7179 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */ 7180 return 1; 7181} 7182 7183static int 7184intel_bracket_expr (void) 7185{ 7186 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET); 7187 const char *start = intel_parser.op_string; 7188 int len; 7189 7190 if (i.op[this_operand].regs) 7191 return intel_match_token (T_NIL); 7192 7193 intel_match_token ('['); 7194 7195 /* Mark as a memory operand only if it's not already known to be an 7196 offset expression. If it's an offset expression, we need to keep 7197 the brace in. */ 7198 if (!intel_parser.in_offset) 7199 { 7200 ++intel_parser.in_bracket; 7201 7202 /* Operands for jump/call inside brackets denote absolute addresses. */ 7203 if (current_templates->start->opcode_modifier & (Jump | JumpDword)) 7204 i.types[this_operand] |= JumpAbsolute; 7205 7206 /* Unfortunately gas always diverged from MASM in a respect that can't 7207 be easily fixed without risking to break code sequences likely to be 7208 encountered (the testsuite even check for this): MASM doesn't consider 7209 an expression inside brackets unconditionally as a memory reference. 7210 When that is e.g. a constant, an offset expression, or the sum of the 7211 two, this is still taken as a constant load. gas, however, always 7212 treated these as memory references. As a compromise, we'll try to make 7213 offset expressions inside brackets work the MASM way (since that's 7214 less likely to be found in real world code), but make constants alone 7215 continue to work the traditional gas way. In either case, issue a 7216 warning. */ 7217 intel_parser.op_modifier &= ~was_offset; 7218 } 7219 else 7220 strcat (intel_parser.disp, "["); 7221 7222 /* Add a '+' to the displacement string if necessary. */ 7223 if (*intel_parser.disp != '\0' 7224 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') 7225 strcat (intel_parser.disp, "+"); 7226 7227 if (intel_expr () 7228 && (len = intel_parser.op_string - start - 1, 7229 intel_match_token (']'))) 7230 { 7231 /* Preserve brackets when the operand is an offset expression. */ 7232 if (intel_parser.in_offset) 7233 strcat (intel_parser.disp, "]"); 7234 else 7235 { 7236 --intel_parser.in_bracket; 7237 if (i.base_reg || i.index_reg) 7238 intel_parser.is_mem = 1; 7239 if (!intel_parser.is_mem) 7240 { 7241 if (!(intel_parser.op_modifier & (1 << T_OFFSET))) 7242 /* Defer the warning until all of the operand was parsed. */ 7243 intel_parser.is_mem = -1; 7244 else if (!quiet_warnings) 7245 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), 7246 len, start, len, start); 7247 } 7248 } 7249 intel_parser.op_modifier |= was_offset; 7250 7251 return 1; 7252 } 7253 return 0; 7254} 7255 7256/* e10 e11 e10' 7257 7258 e10' [ expr ] e10' 7259 | Empty */ 7260static int 7261intel_e10 (void) 7262{ 7263 if (!intel_e11 ()) 7264 return 0; 7265 7266 while (cur_token.code == '[') 7267 { 7268 if (!intel_bracket_expr ()) 7269 return 0; 7270 } 7271 7272 return 1; 7273} 7274 7275/* e11 ( expr ) 7276 | [ expr ] 7277 | BYTE 7278 | WORD 7279 | DWORD 7280 | FWORD 7281 | QWORD 7282 | TBYTE 7283 | OWORD 7284 | XMMWORD 7285 | $ 7286 | . 7287 | register 7288 | id 7289 | constant */ 7290static int 7291intel_e11 (void) 7292{ 7293 switch (cur_token.code) 7294 { 7295 /* e11 ( expr ) */ 7296 case '(': 7297 intel_match_token ('('); 7298 strcat (intel_parser.disp, "("); 7299 7300 if (intel_expr () && intel_match_token (')')) 7301 { 7302 strcat (intel_parser.disp, ")"); 7303 return 1; 7304 } 7305 return 0; 7306 7307 /* e11 [ expr ] */ 7308 case '[': 7309 return intel_bracket_expr (); 7310 7311 /* e11 $ 7312 | . */ 7313 case '.': 7314 strcat (intel_parser.disp, cur_token.str); 7315 intel_match_token (cur_token.code); 7316 7317 /* Mark as a memory operand only if it's not already known to be an 7318 offset expression. */ 7319 if (!intel_parser.in_offset) 7320 intel_parser.is_mem = 1; 7321 7322 return 1; 7323 7324 /* e11 register */ 7325 case T_REG: 7326 { 7327 const reg_entry *reg = intel_parser.reg = cur_token.reg; 7328 7329 intel_match_token (T_REG); 7330 7331 /* Check for segment change. */ 7332 if (cur_token.code == ':') 7333 { 7334 if (!(reg->reg_type & (SReg2 | SReg3))) 7335 { 7336 as_bad (_("`%s' is not a valid segment register"), 7337 reg->reg_name); 7338 return 0; 7339 } 7340 else if (i.seg[i.mem_operands]) 7341 as_warn (_("Extra segment override ignored")); 7342 else 7343 { 7344 if (!intel_parser.in_offset) 7345 intel_parser.is_mem = 1; 7346 switch (reg->reg_num) 7347 { 7348 case 0: 7349 i.seg[i.mem_operands] = &es; 7350 break; 7351 case 1: 7352 i.seg[i.mem_operands] = &cs; 7353 break; 7354 case 2: 7355 i.seg[i.mem_operands] = &ss; 7356 break; 7357 case 3: 7358 i.seg[i.mem_operands] = &ds; 7359 break; 7360 case 4: 7361 i.seg[i.mem_operands] = &fs; 7362 break; 7363 case 5: 7364 i.seg[i.mem_operands] = &gs; 7365 break; 7366 } 7367 } 7368 } 7369 7370 /* Not a segment register. Check for register scaling. */ 7371 else if (cur_token.code == '*') 7372 { 7373 if (!intel_parser.in_bracket) 7374 { 7375 as_bad (_("Register scaling only allowed in memory operands")); 7376 return 0; 7377 } 7378 7379 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */ 7380 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */ 7381 else if (i.index_reg) 7382 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */ 7383 7384 /* What follows must be a valid scale. */ 7385 intel_match_token ('*'); 7386 i.index_reg = reg; 7387 i.types[this_operand] |= BaseIndex; 7388 7389 /* Set the scale after setting the register (otherwise, 7390 i386_scale will complain) */ 7391 if (cur_token.code == '+' || cur_token.code == '-') 7392 { 7393 char *str, sign = cur_token.code; 7394 intel_match_token (cur_token.code); 7395 if (cur_token.code != T_CONST) 7396 { 7397 as_bad (_("Syntax error: Expecting a constant, got `%s'"), 7398 cur_token.str); 7399 return 0; 7400 } 7401 str = (char *) xmalloc (strlen (cur_token.str) + 2); 7402 strcpy (str + 1, cur_token.str); 7403 *str = sign; 7404 if (!i386_scale (str)) 7405 return 0; 7406 free (str); 7407 } 7408 else if (!i386_scale (cur_token.str)) 7409 return 0; 7410 intel_match_token (cur_token.code); 7411 } 7412 7413 /* No scaling. If this is a memory operand, the register is either a 7414 base register (first occurrence) or an index register (second 7415 occurrence). */ 7416 else if (intel_parser.in_bracket) 7417 { 7418 7419 if (!i.base_reg) 7420 i.base_reg = reg; 7421 else if (!i.index_reg) 7422 i.index_reg = reg; 7423 else 7424 { 7425 as_bad (_("Too many register references in memory operand")); 7426 return 0; 7427 } 7428 7429 i.types[this_operand] |= BaseIndex; 7430 } 7431 7432 /* It's neither base nor index. */ 7433 else if (!intel_parser.in_offset && !intel_parser.is_mem) 7434 { 7435 i.types[this_operand] |= reg->reg_type & ~BaseIndex; 7436 i.op[this_operand].regs = reg; 7437 i.reg_operands++; 7438 } 7439 else 7440 { 7441 as_bad (_("Invalid use of register")); 7442 return 0; 7443 } 7444 7445 /* Since registers are not part of the displacement string (except 7446 when we're parsing offset operands), we may need to remove any 7447 preceding '+' from the displacement string. */ 7448 if (*intel_parser.disp != '\0' 7449 && !intel_parser.in_offset) 7450 { 7451 char *s = intel_parser.disp; 7452 s += strlen (s) - 1; 7453 if (*s == '+') 7454 *s = '\0'; 7455 } 7456 7457 return 1; 7458 } 7459 7460 /* e11 BYTE 7461 | WORD 7462 | DWORD 7463 | FWORD 7464 | QWORD 7465 | TBYTE 7466 | OWORD 7467 | XMMWORD */ 7468 case T_BYTE: 7469 case T_WORD: 7470 case T_DWORD: 7471 case T_FWORD: 7472 case T_QWORD: 7473 case T_TBYTE: 7474 case T_XMMWORD: 7475 intel_match_token (cur_token.code); 7476 7477 if (cur_token.code == T_PTR) 7478 return 1; 7479 7480 /* It must have been an identifier. */ 7481 intel_putback_token (); 7482 cur_token.code = T_ID; 7483 /* FALLTHRU */ 7484 7485 /* e11 id 7486 | constant */ 7487 case T_ID: 7488 if (!intel_parser.in_offset && intel_parser.is_mem <= 0) 7489 { 7490 symbolS *symbolP; 7491 7492 /* The identifier represents a memory reference only if it's not 7493 preceded by an offset modifier and if it's not an equate. */ 7494 symbolP = symbol_find(cur_token.str); 7495 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section) 7496 intel_parser.is_mem = 1; 7497 } 7498 /* FALLTHRU */ 7499 7500 case T_CONST: 7501 case '-': 7502 case '+': 7503 { 7504 char *save_str, sign = 0; 7505 7506 /* Allow constants that start with `+' or `-'. */ 7507 if (cur_token.code == '-' || cur_token.code == '+') 7508 { 7509 sign = cur_token.code; 7510 intel_match_token (cur_token.code); 7511 if (cur_token.code != T_CONST) 7512 { 7513 as_bad (_("Syntax error: Expecting a constant, got `%s'"), 7514 cur_token.str); 7515 return 0; 7516 } 7517 } 7518 7519 save_str = (char *) xmalloc (strlen (cur_token.str) + 2); 7520 strcpy (save_str + !!sign, cur_token.str); 7521 if (sign) 7522 *save_str = sign; 7523 7524 /* Get the next token to check for register scaling. */ 7525 intel_match_token (cur_token.code); 7526 7527 /* Check if this constant is a scaling factor for an 7528 index register. */ 7529 if (cur_token.code == '*') 7530 { 7531 if (intel_match_token ('*') && cur_token.code == T_REG) 7532 { 7533 const reg_entry *reg = cur_token.reg; 7534 7535 if (!intel_parser.in_bracket) 7536 { 7537 as_bad (_("Register scaling only allowed " 7538 "in memory operands")); 7539 return 0; 7540 } 7541 7542 /* Disallow things like [1*si]. 7543 sp and esp are invalid as index. */ 7544 if (reg->reg_type & Reg16) 7545 reg = i386_regtab + REGNAM_AX + 4; 7546 else if (i.index_reg) 7547 reg = i386_regtab + REGNAM_EAX + 4; 7548 7549 /* The constant is followed by `* reg', so it must be 7550 a valid scale. */ 7551 i.index_reg = reg; 7552 i.types[this_operand] |= BaseIndex; 7553 7554 /* Set the scale after setting the register (otherwise, 7555 i386_scale will complain) */ 7556 if (!i386_scale (save_str)) 7557 return 0; 7558 intel_match_token (T_REG); 7559 7560 /* Since registers are not part of the displacement 7561 string, we may need to remove any preceding '+' from 7562 the displacement string. */ 7563 if (*intel_parser.disp != '\0') 7564 { 7565 char *s = intel_parser.disp; 7566 s += strlen (s) - 1; 7567 if (*s == '+') 7568 *s = '\0'; 7569 } 7570 7571 free (save_str); 7572 7573 return 1; 7574 } 7575 7576 /* The constant was not used for register scaling. Since we have 7577 already consumed the token following `*' we now need to put it 7578 back in the stream. */ 7579 intel_putback_token (); 7580 } 7581 7582 /* Add the constant to the displacement string. */ 7583 strcat (intel_parser.disp, save_str); 7584 free (save_str); 7585 7586 return 1; 7587 } 7588 } 7589 7590 as_bad (_("Unrecognized token '%s'"), cur_token.str); 7591 return 0; 7592} 7593 7594/* Match the given token against cur_token. If they match, read the next 7595 token from the operand string. */ 7596static int 7597intel_match_token (int code) 7598{ 7599 if (cur_token.code == code) 7600 { 7601 intel_get_token (); 7602 return 1; 7603 } 7604 else 7605 { 7606 as_bad (_("Unexpected token `%s'"), cur_token.str); 7607 return 0; 7608 } 7609} 7610 7611/* Read a new token from intel_parser.op_string and store it in cur_token. */ 7612static void 7613intel_get_token (void) 7614{ 7615 char *end_op; 7616 const reg_entry *reg; 7617 struct intel_token new_token; 7618 7619 new_token.code = T_NIL; 7620 new_token.reg = NULL; 7621 new_token.str = NULL; 7622 7623 /* Free the memory allocated to the previous token and move 7624 cur_token to prev_token. */ 7625 if (prev_token.str) 7626 free (prev_token.str); 7627 7628 prev_token = cur_token; 7629 7630 /* Skip whitespace. */ 7631 while (is_space_char (*intel_parser.op_string)) 7632 intel_parser.op_string++; 7633 7634 /* Return an empty token if we find nothing else on the line. */ 7635 if (*intel_parser.op_string == '\0') 7636 { 7637 cur_token = new_token; 7638 return; 7639 } 7640 7641 /* The new token cannot be larger than the remainder of the operand 7642 string. */ 7643 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1); 7644 new_token.str[0] = '\0'; 7645 7646 if (strchr ("0123456789", *intel_parser.op_string)) 7647 { 7648 char *p = new_token.str; 7649 char *q = intel_parser.op_string; 7650 new_token.code = T_CONST; 7651 7652 /* Allow any kind of identifier char to encompass floating point and 7653 hexadecimal numbers. */ 7654 while (is_identifier_char (*q)) 7655 *p++ = *q++; 7656 *p = '\0'; 7657 7658 /* Recognize special symbol names [0-9][bf]. */ 7659 if (strlen (intel_parser.op_string) == 2 7660 && (intel_parser.op_string[1] == 'b' 7661 || intel_parser.op_string[1] == 'f')) 7662 new_token.code = T_ID; 7663 } 7664 7665 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL) 7666 { 7667 size_t len = end_op - intel_parser.op_string; 7668 7669 new_token.code = T_REG; 7670 new_token.reg = reg; 7671 7672 memcpy (new_token.str, intel_parser.op_string, len); 7673 new_token.str[len] = '\0'; 7674 } 7675 7676 else if (is_identifier_char (*intel_parser.op_string)) 7677 { 7678 char *p = new_token.str; 7679 char *q = intel_parser.op_string; 7680 7681 /* A '.' or '$' followed by an identifier char is an identifier. 7682 Otherwise, it's operator '.' followed by an expression. */ 7683 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1))) 7684 { 7685 new_token.code = '.'; 7686 new_token.str[0] = '.'; 7687 new_token.str[1] = '\0'; 7688 } 7689 else 7690 { 7691 while (is_identifier_char (*q) || *q == '@') 7692 *p++ = *q++; 7693 *p = '\0'; 7694 7695 if (strcasecmp (new_token.str, "NOT") == 0) 7696 new_token.code = '~'; 7697 7698 else if (strcasecmp (new_token.str, "MOD") == 0) 7699 new_token.code = '%'; 7700 7701 else if (strcasecmp (new_token.str, "AND") == 0) 7702 new_token.code = '&'; 7703 7704 else if (strcasecmp (new_token.str, "OR") == 0) 7705 new_token.code = '|'; 7706 7707 else if (strcasecmp (new_token.str, "XOR") == 0) 7708 new_token.code = '^'; 7709 7710 else if (strcasecmp (new_token.str, "SHL") == 0) 7711 new_token.code = T_SHL; 7712 7713 else if (strcasecmp (new_token.str, "SHR") == 0) 7714 new_token.code = T_SHR; 7715 7716 else if (strcasecmp (new_token.str, "BYTE") == 0) 7717 new_token.code = T_BYTE; 7718 7719 else if (strcasecmp (new_token.str, "WORD") == 0) 7720 new_token.code = T_WORD; 7721 7722 else if (strcasecmp (new_token.str, "DWORD") == 0) 7723 new_token.code = T_DWORD; 7724 7725 else if (strcasecmp (new_token.str, "FWORD") == 0) 7726 new_token.code = T_FWORD; 7727 7728 else if (strcasecmp (new_token.str, "QWORD") == 0) 7729 new_token.code = T_QWORD; 7730 7731 else if (strcasecmp (new_token.str, "TBYTE") == 0 7732 /* XXX remove (gcc still uses it) */ 7733 || strcasecmp (new_token.str, "XWORD") == 0) 7734 new_token.code = T_TBYTE; 7735 7736 else if (strcasecmp (new_token.str, "XMMWORD") == 0 7737 || strcasecmp (new_token.str, "OWORD") == 0) 7738 new_token.code = T_XMMWORD; 7739 7740 else if (strcasecmp (new_token.str, "PTR") == 0) 7741 new_token.code = T_PTR; 7742 7743 else if (strcasecmp (new_token.str, "SHORT") == 0) 7744 new_token.code = T_SHORT; 7745 7746 else if (strcasecmp (new_token.str, "OFFSET") == 0) 7747 { 7748 new_token.code = T_OFFSET; 7749 7750 /* ??? This is not mentioned in the MASM grammar but gcc 7751 makes use of it with -mintel-syntax. OFFSET may be 7752 followed by FLAT: */ 7753 if (strncasecmp (q, " FLAT:", 6) == 0) 7754 strcat (new_token.str, " FLAT:"); 7755 } 7756 7757 /* ??? This is not mentioned in the MASM grammar. */ 7758 else if (strcasecmp (new_token.str, "FLAT") == 0) 7759 { 7760 new_token.code = T_OFFSET; 7761 if (*q == ':') 7762 strcat (new_token.str, ":"); 7763 else 7764 as_bad (_("`:' expected")); 7765 } 7766 7767 else 7768 new_token.code = T_ID; 7769 } 7770 } 7771 7772 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string)) 7773 { 7774 new_token.code = *intel_parser.op_string; 7775 new_token.str[0] = *intel_parser.op_string; 7776 new_token.str[1] = '\0'; 7777 } 7778 7779 else if (strchr ("<>", *intel_parser.op_string) 7780 && *intel_parser.op_string == *(intel_parser.op_string + 1)) 7781 { 7782 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR; 7783 new_token.str[0] = *intel_parser.op_string; 7784 new_token.str[1] = *intel_parser.op_string; 7785 new_token.str[2] = '\0'; 7786 } 7787 7788 else 7789 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string); 7790 7791 intel_parser.op_string += strlen (new_token.str); 7792 cur_token = new_token; 7793} 7794 7795/* Put cur_token back into the token stream and make cur_token point to 7796 prev_token. */ 7797static void 7798intel_putback_token (void) 7799{ 7800 if (cur_token.code != T_NIL) 7801 { 7802 intel_parser.op_string -= strlen (cur_token.str); 7803 free (cur_token.str); 7804 } 7805 cur_token = prev_token; 7806 7807 /* Forget prev_token. */ 7808 prev_token.code = T_NIL; 7809 prev_token.reg = NULL; 7810 prev_token.str = NULL; 7811} 7812 7813int 7814tc_x86_regname_to_dw2regnum (char *regname) 7815{ 7816 unsigned int regnum; 7817 unsigned int regnames_count; 7818 static const char *const regnames_32[] = 7819 { 7820 "eax", "ecx", "edx", "ebx", 7821 "esp", "ebp", "esi", "edi", 7822 "eip", "eflags", NULL, 7823 "st0", "st1", "st2", "st3", 7824 "st4", "st5", "st6", "st7", 7825 NULL, NULL, 7826 "xmm0", "xmm1", "xmm2", "xmm3", 7827 "xmm4", "xmm5", "xmm6", "xmm7", 7828 "mm0", "mm1", "mm2", "mm3", 7829 "mm4", "mm5", "mm6", "mm7", 7830 "fcw", "fsw", "mxcsr", 7831 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL, 7832 "tr", "ldtr" 7833 }; 7834 static const char *const regnames_64[] = 7835 { 7836 "rax", "rdx", "rcx", "rbx", 7837 "rsi", "rdi", "rbp", "rsp", 7838 "r8", "r9", "r10", "r11", 7839 "r12", "r13", "r14", "r15", 7840 "rip", 7841 "xmm0", "xmm1", "xmm2", "xmm3", 7842 "xmm4", "xmm5", "xmm6", "xmm7", 7843 "xmm8", "xmm9", "xmm10", "xmm11", 7844 "xmm12", "xmm13", "xmm14", "xmm15", 7845 "st0", "st1", "st2", "st3", 7846 "st4", "st5", "st6", "st7", 7847 "mm0", "mm1", "mm2", "mm3", 7848 "mm4", "mm5", "mm6", "mm7", 7849 "rflags", 7850 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL, 7851 "fs.base", "gs.base", NULL, NULL, 7852 "tr", "ldtr", 7853 "mxcsr", "fcw", "fsw" 7854 }; 7855 const char *const *regnames; 7856 7857 if (flag_code == CODE_64BIT) 7858 { 7859 regnames = regnames_64; 7860 regnames_count = ARRAY_SIZE (regnames_64); 7861 } 7862 else 7863 { 7864 regnames = regnames_32; 7865 regnames_count = ARRAY_SIZE (regnames_32); 7866 } 7867 7868 for (regnum = 0; regnum < regnames_count; regnum++) 7869 if (regnames[regnum] != NULL 7870 && strcmp (regname, regnames[regnum]) == 0) 7871 return regnum; 7872 7873 return -1; 7874} 7875 7876void 7877tc_x86_frame_initial_instructions (void) 7878{ 7879 static unsigned int sp_regno; 7880 7881 if (!sp_regno) 7882 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT 7883 ? "rsp" : "esp"); 7884 7885 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment); 7886 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); 7887} 7888 7889int 7890i386_elf_section_type (const char *str, size_t len) 7891{ 7892 if (flag_code == CODE_64BIT 7893 && len == sizeof ("unwind") - 1 7894 && strncmp (str, "unwind", 6) == 0) 7895 return SHT_X86_64_UNWIND; 7896 7897 return -1; 7898} 7899 7900#ifdef TE_PE 7901void 7902tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) 7903{ 7904 expressionS expr; 7905 7906 expr.X_op = O_secrel; 7907 expr.X_add_symbol = symbol; 7908 expr.X_add_number = 0; 7909 emit_expr (&expr, size); 7910} 7911#endif 7912 7913#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 7914/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ 7915 7916int 7917x86_64_section_letter (int letter, char **ptr_msg) 7918{ 7919 if (flag_code == CODE_64BIT) 7920 { 7921 if (letter == 'l') 7922 return SHF_X86_64_LARGE; 7923 7924 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string"); 7925 } 7926 else 7927 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string"); 7928 return -1; 7929} 7930 7931int 7932x86_64_section_word (char *str, size_t len) 7933{ 7934 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) 7935 return SHF_X86_64_LARGE; 7936 7937 return -1; 7938} 7939 7940static void 7941handle_large_common (int small ATTRIBUTE_UNUSED) 7942{ 7943 if (flag_code != CODE_64BIT) 7944 { 7945 s_comm_internal (0, elf_common_parse); 7946 as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); 7947 } 7948 else 7949 { 7950 static segT lbss_section; 7951 asection *saved_com_section_ptr = elf_com_section_ptr; 7952 asection *saved_bss_section = bss_section; 7953 7954 if (lbss_section == NULL) 7955 { 7956 flagword applicable; 7957 segT seg = now_seg; 7958 subsegT subseg = now_subseg; 7959 7960 /* The .lbss section is for local .largecomm symbols. */ 7961 lbss_section = subseg_new (".lbss", 0); 7962 applicable = bfd_applicable_section_flags (stdoutput); 7963 bfd_set_section_flags (stdoutput, lbss_section, 7964 applicable & SEC_ALLOC); 7965 seg_info (lbss_section)->bss = 1; 7966 7967 subseg_set (seg, subseg); 7968 } 7969 7970 elf_com_section_ptr = &_bfd_elf_large_com_section; 7971 bss_section = lbss_section; 7972 7973 s_comm_internal (0, elf_common_parse); 7974 7975 elf_com_section_ptr = saved_com_section_ptr; 7976 bss_section = saved_bss_section; 7977 } 7978} 7979#endif /* OBJ_ELF || OBJ_MAYBE_ELF */ 7980