tc-arm.c revision 301232
1/* tc-arm.c -- Assemble for the ARM 2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 3 2004, 2005, 2006 4 Free Software Foundation, Inc. 5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) 6 Modified by David Taylor (dtaylor@armltd.co.uk) 7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) 8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) 9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) 10 11 This file is part of GAS, the GNU Assembler. 12 13 GAS is free software; you can redistribute it and/or modify 14 it under the terms of the GNU General Public License as published by 15 the Free Software Foundation; either version 2, or (at your option) 16 any later version. 17 18 GAS is distributed in the hope that it will be useful, 19 but WITHOUT ANY WARRANTY; without even the implied warranty of 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 GNU General Public License for more details. 22 23 You should have received a copy of the GNU General Public License 24 along with GAS; see the file COPYING. If not, write to the Free 25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 26 02110-1301, USA. */ 27 28#include <limits.h> 29#include <stdarg.h> 30#define NO_RELOC 0 31#include "as.h" 32#include "safe-ctype.h" 33#include "subsegs.h" 34#include "obstack.h" 35 36#include "opcode/arm.h" 37 38#ifdef OBJ_ELF 39#include "elf/arm.h" 40#include "dw2gencfi.h" 41#endif 42 43#include "dwarf2dbg.h" 44 45#define WARN_DEPRECATED 1 46 47#ifdef OBJ_ELF 48/* Must be at least the size of the largest unwind opcode (currently two). */ 49#define ARM_OPCODE_CHUNK_SIZE 8 50 51/* This structure holds the unwinding state. */ 52 53static struct 54{ 55 symbolS * proc_start; 56 symbolS * table_entry; 57 symbolS * personality_routine; 58 int personality_index; 59 /* The segment containing the function. */ 60 segT saved_seg; 61 subsegT saved_subseg; 62 /* Opcodes generated from this function. */ 63 unsigned char * opcodes; 64 int opcode_count; 65 int opcode_alloc; 66 /* The number of bytes pushed to the stack. */ 67 offsetT frame_size; 68 /* We don't add stack adjustment opcodes immediately so that we can merge 69 multiple adjustments. We can also omit the final adjustment 70 when using a frame pointer. */ 71 offsetT pending_offset; 72 /* These two fields are set by both unwind_movsp and unwind_setfp. They 73 hold the reg+offset to use when restoring sp from a frame pointer. */ 74 offsetT fp_offset; 75 int fp_reg; 76 /* Nonzero if an unwind_setfp directive has been seen. */ 77 unsigned fp_used:1; 78 /* Nonzero if the last opcode restores sp from fp_reg. */ 79 unsigned sp_restored:1; 80} unwind; 81 82/* Bit N indicates that an R_ARM_NONE relocation has been output for 83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be 84 emitted only once per section, to save unnecessary bloat. */ 85static unsigned int marked_pr_dependency = 0; 86 87#endif /* OBJ_ELF */ 88 89/* Results from operand parsing worker functions. */ 90 91typedef enum 92{ 93 PARSE_OPERAND_SUCCESS, 94 PARSE_OPERAND_FAIL, 95 PARSE_OPERAND_FAIL_NO_BACKTRACK 96} parse_operand_result; 97 98enum arm_float_abi 99{ 100 ARM_FLOAT_ABI_HARD, 101 ARM_FLOAT_ABI_SOFTFP, 102 ARM_FLOAT_ABI_SOFT 103}; 104 105/* Types of processor to assemble for. */ 106#ifndef CPU_DEFAULT 107#if defined __XSCALE__ 108#define CPU_DEFAULT ARM_ARCH_XSCALE 109#else 110#if defined __thumb__ 111#define CPU_DEFAULT ARM_ARCH_V5T 112#endif 113#endif 114#endif 115 116#ifndef FPU_DEFAULT 117# ifdef TE_LINUX 118# define FPU_DEFAULT FPU_ARCH_FPA 119# elif defined (TE_NetBSD) 120# ifdef OBJ_ELF 121# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ 122# else 123 /* Legacy a.out format. */ 124# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ 125# endif 126# elif defined (TE_VXWORKS) 127# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ 128# else 129 /* For backwards compatibility, default to FPA. */ 130# define FPU_DEFAULT FPU_ARCH_FPA 131# endif 132#endif /* ifndef FPU_DEFAULT */ 133 134#define streq(a, b) (strcmp (a, b) == 0) 135 136static arm_feature_set cpu_variant; 137static arm_feature_set arm_arch_used; 138static arm_feature_set thumb_arch_used; 139 140/* Flags stored in private area of BFD structure. */ 141static int uses_apcs_26 = FALSE; 142static int atpcs = FALSE; 143static int support_interwork = FALSE; 144static int uses_apcs_float = FALSE; 145static int pic_code = FALSE; 146 147/* Variables that we set while parsing command-line options. Once all 148 options have been read we re-process these values to set the real 149 assembly flags. */ 150static const arm_feature_set *legacy_cpu = NULL; 151static const arm_feature_set *legacy_fpu = NULL; 152 153static const arm_feature_set *mcpu_cpu_opt = NULL; 154static const arm_feature_set *mcpu_fpu_opt = NULL; 155static const arm_feature_set *march_cpu_opt = NULL; 156static const arm_feature_set *march_fpu_opt = NULL; 157static const arm_feature_set *mfpu_opt = NULL; 158static const arm_feature_set *object_arch = NULL; 159 160/* Constants for known architecture features. */ 161static const arm_feature_set fpu_default = FPU_DEFAULT; 162static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; 163static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; 164static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; 165static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; 166static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; 167static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; 168static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; 169static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; 170 171#ifdef CPU_DEFAULT 172static const arm_feature_set cpu_default = CPU_DEFAULT; 173#endif 174 175static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); 176static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); 177static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); 178static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); 179static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); 180static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); 181static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); 182static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); 183static const arm_feature_set arm_ext_v4t_5 = 184 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); 185static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); 186static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); 187static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); 188static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); 189static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); 190static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); 191static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0); 192static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); 193static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); 194static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); 195static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); 196static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); 197static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); 198static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); 199 200static const arm_feature_set arm_arch_any = ARM_ANY; 201static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); 202static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; 203static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; 204 205static const arm_feature_set arm_cext_iwmmxt2 = 206 ARM_FEATURE (0, ARM_CEXT_IWMMXT2); 207static const arm_feature_set arm_cext_iwmmxt = 208 ARM_FEATURE (0, ARM_CEXT_IWMMXT); 209static const arm_feature_set arm_cext_xscale = 210 ARM_FEATURE (0, ARM_CEXT_XSCALE); 211static const arm_feature_set arm_cext_maverick = 212 ARM_FEATURE (0, ARM_CEXT_MAVERICK); 213static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); 214static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); 215static const arm_feature_set fpu_vfp_ext_v1xd = 216 ARM_FEATURE (0, FPU_VFP_EXT_V1xD); 217static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); 218static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); 219static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); 220static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); 221static const arm_feature_set fpu_vfp_v3_or_neon_ext = 222 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); 223 224static int mfloat_abi_opt = -1; 225/* Record user cpu selection for object attributes. */ 226static arm_feature_set selected_cpu = ARM_ARCH_NONE; 227/* Must be long enough to hold any of the names in arm_cpus. */ 228static char selected_cpu_name[16]; 229#ifdef OBJ_ELF 230# ifdef EABI_DEFAULT 231static int meabi_flags = EABI_DEFAULT; 232# else 233static int meabi_flags = EF_ARM_EABI_UNKNOWN; 234# endif 235 236bfd_boolean 237arm_is_eabi(void) 238{ 239 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); 240} 241#endif 242 243#ifdef OBJ_ELF 244/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ 245symbolS * GOT_symbol; 246#endif 247 248/* 0: assemble for ARM, 249 1: assemble for Thumb, 250 2: assemble for Thumb even though target CPU does not support thumb 251 instructions. */ 252static int thumb_mode = 0; 253 254/* If unified_syntax is true, we are processing the new unified 255 ARM/Thumb syntax. Important differences from the old ARM mode: 256 257 - Immediate operands do not require a # prefix. 258 - Conditional affixes always appear at the end of the 259 instruction. (For backward compatibility, those instructions 260 that formerly had them in the middle, continue to accept them 261 there.) 262 - The IT instruction may appear, and if it does is validated 263 against subsequent conditional affixes. It does not generate 264 machine code. 265 266 Important differences from the old Thumb mode: 267 268 - Immediate operands do not require a # prefix. 269 - Most of the V6T2 instructions are only available in unified mode. 270 - The .N and .W suffixes are recognized and honored (it is an error 271 if they cannot be honored). 272 - All instructions set the flags if and only if they have an 's' affix. 273 - Conditional affixes may be used. They are validated against 274 preceding IT instructions. Unlike ARM mode, you cannot use a 275 conditional affix except in the scope of an IT instruction. */ 276 277static bfd_boolean unified_syntax = FALSE; 278 279enum neon_el_type 280{ 281 NT_invtype, 282 NT_untyped, 283 NT_integer, 284 NT_float, 285 NT_poly, 286 NT_signed, 287 NT_unsigned 288}; 289 290struct neon_type_el 291{ 292 enum neon_el_type type; 293 unsigned size; 294}; 295 296#define NEON_MAX_TYPE_ELS 4 297 298struct neon_type 299{ 300 struct neon_type_el el[NEON_MAX_TYPE_ELS]; 301 unsigned elems; 302}; 303 304struct arm_it 305{ 306 const char * error; 307 unsigned long instruction; 308 int size; 309 int size_req; 310 int cond; 311 /* "uncond_value" is set to the value in place of the conditional field in 312 unconditional versions of the instruction, or -1 if nothing is 313 appropriate. */ 314 int uncond_value; 315 struct neon_type vectype; 316 /* Set to the opcode if the instruction needs relaxation. 317 Zero if the instruction is not relaxed. */ 318 unsigned long relax; 319 struct 320 { 321 bfd_reloc_code_real_type type; 322 expressionS exp; 323 int pc_rel; 324 } reloc; 325 326 struct 327 { 328 unsigned reg; 329 signed int imm; 330 struct neon_type_el vectype; 331 unsigned present : 1; /* Operand present. */ 332 unsigned isreg : 1; /* Operand was a register. */ 333 unsigned immisreg : 1; /* .imm field is a second register. */ 334 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ 335 unsigned immisalign : 1; /* Immediate is an alignment specifier. */ 336 unsigned immisfloat : 1; /* Immediate was parsed as a float. */ 337 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV 338 instructions. This allows us to disambiguate ARM <-> vector insns. */ 339 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ 340 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ 341 unsigned isquad : 1; /* Operand is Neon quad-precision register. */ 342 unsigned issingle : 1; /* Operand is VFP single-precision register. */ 343 unsigned hasreloc : 1; /* Operand has relocation suffix. */ 344 unsigned writeback : 1; /* Operand has trailing ! */ 345 unsigned preind : 1; /* Preindexed address. */ 346 unsigned postind : 1; /* Postindexed address. */ 347 unsigned negative : 1; /* Index register was negated. */ 348 unsigned shifted : 1; /* Shift applied to operation. */ 349 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ 350 } operands[6]; 351}; 352 353static struct arm_it inst; 354 355#define NUM_FLOAT_VALS 8 356 357const char * fp_const[] = 358{ 359 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 360}; 361 362/* Number of littlenums required to hold an extended precision number. */ 363#define MAX_LITTLENUMS 6 364 365LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; 366 367#define FAIL (-1) 368#define SUCCESS (0) 369 370#define SUFF_S 1 371#define SUFF_D 2 372#define SUFF_E 3 373#define SUFF_P 4 374 375#define CP_T_X 0x00008000 376#define CP_T_Y 0x00400000 377 378#define CONDS_BIT 0x00100000 379#define LOAD_BIT 0x00100000 380 381#define DOUBLE_LOAD_FLAG 0x00000001 382 383struct asm_cond 384{ 385 const char * template; 386 unsigned long value; 387}; 388 389#define COND_ALWAYS 0xE 390 391struct asm_psr 392{ 393 const char *template; 394 unsigned long field; 395}; 396 397struct asm_barrier_opt 398{ 399 const char *template; 400 unsigned long value; 401}; 402 403/* The bit that distinguishes CPSR and SPSR. */ 404#define SPSR_BIT (1 << 22) 405 406/* The individual PSR flag bits. */ 407#define PSR_c (1 << 16) 408#define PSR_x (1 << 17) 409#define PSR_s (1 << 18) 410#define PSR_f (1 << 19) 411 412struct reloc_entry 413{ 414 char *name; 415 bfd_reloc_code_real_type reloc; 416}; 417 418enum vfp_reg_pos 419{ 420 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, 421 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn 422}; 423 424enum vfp_ldstm_type 425{ 426 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX 427}; 428 429/* Bits for DEFINED field in neon_typed_alias. */ 430#define NTA_HASTYPE 1 431#define NTA_HASINDEX 2 432 433struct neon_typed_alias 434{ 435 unsigned char defined; 436 unsigned char index; 437 struct neon_type_el eltype; 438}; 439 440/* ARM register categories. This includes coprocessor numbers and various 441 architecture extensions' registers. */ 442enum arm_reg_type 443{ 444 REG_TYPE_RN, 445 REG_TYPE_CP, 446 REG_TYPE_CN, 447 REG_TYPE_FN, 448 REG_TYPE_VFS, 449 REG_TYPE_VFD, 450 REG_TYPE_NQ, 451 REG_TYPE_VFSD, 452 REG_TYPE_NDQ, 453 REG_TYPE_NSDQ, 454 REG_TYPE_VFC, 455 REG_TYPE_MVF, 456 REG_TYPE_MVD, 457 REG_TYPE_MVFX, 458 REG_TYPE_MVDX, 459 REG_TYPE_MVAX, 460 REG_TYPE_DSPSC, 461 REG_TYPE_MMXWR, 462 REG_TYPE_MMXWC, 463 REG_TYPE_MMXWCG, 464 REG_TYPE_XSCALE, 465}; 466 467/* Structure for a hash table entry for a register. 468 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra 469 information which states whether a vector type or index is specified (for a 470 register alias created with .dn or .qn). Otherwise NEON should be NULL. */ 471struct reg_entry 472{ 473 const char *name; 474 unsigned char number; 475 unsigned char type; 476 unsigned char builtin; 477 struct neon_typed_alias *neon; 478}; 479 480/* Diagnostics used when we don't get a register of the expected type. */ 481const char *const reg_expected_msgs[] = 482{ 483 N_("ARM register expected"), 484 N_("bad or missing co-processor number"), 485 N_("co-processor register expected"), 486 N_("FPA register expected"), 487 N_("VFP single precision register expected"), 488 N_("VFP/Neon double precision register expected"), 489 N_("Neon quad precision register expected"), 490 N_("VFP single or double precision register expected"), 491 N_("Neon double or quad precision register expected"), 492 N_("VFP single, double or Neon quad precision register expected"), 493 N_("VFP system register expected"), 494 N_("Maverick MVF register expected"), 495 N_("Maverick MVD register expected"), 496 N_("Maverick MVFX register expected"), 497 N_("Maverick MVDX register expected"), 498 N_("Maverick MVAX register expected"), 499 N_("Maverick DSPSC register expected"), 500 N_("iWMMXt data register expected"), 501 N_("iWMMXt control register expected"), 502 N_("iWMMXt scalar register expected"), 503 N_("XScale accumulator register expected"), 504}; 505 506/* Some well known registers that we refer to directly elsewhere. */ 507#define REG_SP 13 508#define REG_LR 14 509#define REG_PC 15 510 511/* ARM instructions take 4bytes in the object file, Thumb instructions 512 take 2: */ 513#define INSN_SIZE 4 514 515struct asm_opcode 516{ 517 /* Basic string to match. */ 518 const char *template; 519 520 /* Parameters to instruction. */ 521 unsigned char operands[8]; 522 523 /* Conditional tag - see opcode_lookup. */ 524 unsigned int tag : 4; 525 526 /* Basic instruction code. */ 527 unsigned int avalue : 28; 528 529 /* Thumb-format instruction code. */ 530 unsigned int tvalue; 531 532 /* Which architecture variant provides this instruction. */ 533 const arm_feature_set *avariant; 534 const arm_feature_set *tvariant; 535 536 /* Function to call to encode instruction in ARM format. */ 537 void (* aencode) (void); 538 539 /* Function to call to encode instruction in Thumb format. */ 540 void (* tencode) (void); 541}; 542 543/* Defines for various bits that we will want to toggle. */ 544#define INST_IMMEDIATE 0x02000000 545#define OFFSET_REG 0x02000000 546#define HWOFFSET_IMM 0x00400000 547#define SHIFT_BY_REG 0x00000010 548#define PRE_INDEX 0x01000000 549#define INDEX_UP 0x00800000 550#define WRITE_BACK 0x00200000 551#define LDM_TYPE_2_OR_3 0x00400000 552#define CPSI_MMOD 0x00020000 553 554#define LITERAL_MASK 0xf000f000 555#define OPCODE_MASK 0xfe1fffff 556#define V4_STR_BIT 0x00000020 557 558#define T2_SUBS_PC_LR 0xf3de8f00 559 560#define DATA_OP_SHIFT 21 561 562#define T2_OPCODE_MASK 0xfe1fffff 563#define T2_DATA_OP_SHIFT 21 564 565/* Codes to distinguish the arithmetic instructions. */ 566#define OPCODE_AND 0 567#define OPCODE_EOR 1 568#define OPCODE_SUB 2 569#define OPCODE_RSB 3 570#define OPCODE_ADD 4 571#define OPCODE_ADC 5 572#define OPCODE_SBC 6 573#define OPCODE_RSC 7 574#define OPCODE_TST 8 575#define OPCODE_TEQ 9 576#define OPCODE_CMP 10 577#define OPCODE_CMN 11 578#define OPCODE_ORR 12 579#define OPCODE_MOV 13 580#define OPCODE_BIC 14 581#define OPCODE_MVN 15 582 583#define T2_OPCODE_AND 0 584#define T2_OPCODE_BIC 1 585#define T2_OPCODE_ORR 2 586#define T2_OPCODE_ORN 3 587#define T2_OPCODE_EOR 4 588#define T2_OPCODE_ADD 8 589#define T2_OPCODE_ADC 10 590#define T2_OPCODE_SBC 11 591#define T2_OPCODE_SUB 13 592#define T2_OPCODE_RSB 14 593 594#define T_OPCODE_MUL 0x4340 595#define T_OPCODE_TST 0x4200 596#define T_OPCODE_CMN 0x42c0 597#define T_OPCODE_NEG 0x4240 598#define T_OPCODE_MVN 0x43c0 599 600#define T_OPCODE_ADD_R3 0x1800 601#define T_OPCODE_SUB_R3 0x1a00 602#define T_OPCODE_ADD_HI 0x4400 603#define T_OPCODE_ADD_ST 0xb000 604#define T_OPCODE_SUB_ST 0xb080 605#define T_OPCODE_ADD_SP 0xa800 606#define T_OPCODE_ADD_PC 0xa000 607#define T_OPCODE_ADD_I8 0x3000 608#define T_OPCODE_SUB_I8 0x3800 609#define T_OPCODE_ADD_I3 0x1c00 610#define T_OPCODE_SUB_I3 0x1e00 611 612#define T_OPCODE_ASR_R 0x4100 613#define T_OPCODE_LSL_R 0x4080 614#define T_OPCODE_LSR_R 0x40c0 615#define T_OPCODE_ROR_R 0x41c0 616#define T_OPCODE_ASR_I 0x1000 617#define T_OPCODE_LSL_I 0x0000 618#define T_OPCODE_LSR_I 0x0800 619 620#define T_OPCODE_MOV_I8 0x2000 621#define T_OPCODE_CMP_I8 0x2800 622#define T_OPCODE_CMP_LR 0x4280 623#define T_OPCODE_MOV_HR 0x4600 624#define T_OPCODE_CMP_HR 0x4500 625 626#define T_OPCODE_LDR_PC 0x4800 627#define T_OPCODE_LDR_SP 0x9800 628#define T_OPCODE_STR_SP 0x9000 629#define T_OPCODE_LDR_IW 0x6800 630#define T_OPCODE_STR_IW 0x6000 631#define T_OPCODE_LDR_IH 0x8800 632#define T_OPCODE_STR_IH 0x8000 633#define T_OPCODE_LDR_IB 0x7800 634#define T_OPCODE_STR_IB 0x7000 635#define T_OPCODE_LDR_RW 0x5800 636#define T_OPCODE_STR_RW 0x5000 637#define T_OPCODE_LDR_RH 0x5a00 638#define T_OPCODE_STR_RH 0x5200 639#define T_OPCODE_LDR_RB 0x5c00 640#define T_OPCODE_STR_RB 0x5400 641 642#define T_OPCODE_PUSH 0xb400 643#define T_OPCODE_POP 0xbc00 644 645#define T_OPCODE_BRANCH 0xe000 646 647#define THUMB_SIZE 2 /* Size of thumb instruction. */ 648#define THUMB_PP_PC_LR 0x0100 649#define THUMB_LOAD_BIT 0x0800 650#define THUMB2_LOAD_BIT 0x00100000 651 652#define BAD_ARGS _("bad arguments to instruction") 653#define BAD_PC _("r15 not allowed here") 654#define BAD_SP _("r13 not allowed here") 655#define BAD_COND _("instruction cannot be conditional") 656#define BAD_OVERLAP _("registers may not be the same") 657#define BAD_HIREG _("lo register required") 658#define BAD_THUMB32 _("instruction not supported in Thumb16 mode") 659#define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); 660#define BAD_BRANCH _("branch must be last instruction in IT block") 661#define BAD_NOT_IT _("instruction not allowed in IT block") 662#define BAD_FPU _("selected FPU does not support instruction") 663#define BAD_VMRS _("APSR_nzcv may only be used with fpscr") 664 665static struct hash_control *arm_ops_hsh; 666static struct hash_control *arm_cond_hsh; 667static struct hash_control *arm_shift_hsh; 668static struct hash_control *arm_psr_hsh; 669static struct hash_control *arm_v7m_psr_hsh; 670static struct hash_control *arm_reg_hsh; 671static struct hash_control *arm_reloc_hsh; 672static struct hash_control *arm_barrier_opt_hsh; 673 674/* Stuff needed to resolve the label ambiguity 675 As: 676 ... 677 label: <insn> 678 may differ from: 679 ... 680 label: 681 <insn> 682*/ 683 684symbolS * last_label_seen; 685static int label_is_thumb_function_name = FALSE; 686 687/* Literal pool structure. Held on a per-section 688 and per-sub-section basis. */ 689 690#define MAX_LITERAL_POOL_SIZE 1024 691typedef struct literal_pool 692{ 693 expressionS literals [MAX_LITERAL_POOL_SIZE]; 694 unsigned int next_free_entry; 695 unsigned int id; 696 symbolS * symbol; 697 segT section; 698 subsegT sub_section; 699 struct literal_pool * next; 700} literal_pool; 701 702/* Pointer to a linked list of literal pools. */ 703literal_pool * list_of_pools = NULL; 704 705/* State variables for IT block handling. */ 706static bfd_boolean current_it_mask = 0; 707static int current_cc; 708 709 710/* Pure syntax. */ 711 712/* This array holds the chars that always start a comment. If the 713 pre-processor is disabled, these aren't very useful. */ 714const char comment_chars[] = "@"; 715 716/* This array holds the chars that only start a comment at the beginning of 717 a line. If the line seems to have the form '# 123 filename' 718 .line and .file directives will appear in the pre-processed output. */ 719/* Note that input_file.c hand checks for '#' at the beginning of the 720 first line of the input file. This is because the compiler outputs 721 #NO_APP at the beginning of its output. */ 722/* Also note that comments like this one will always work. */ 723const char line_comment_chars[] = "#"; 724 725const char line_separator_chars[] = ";"; 726 727/* Chars that can be used to separate mant 728 from exp in floating point numbers. */ 729const char EXP_CHARS[] = "eE"; 730 731/* Chars that mean this number is a floating point constant. */ 732/* As in 0f12.456 */ 733/* or 0d1.2345e12 */ 734 735const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; 736 737/* Prefix characters that indicate the start of an immediate 738 value. */ 739#define is_immediate_prefix(C) ((C) == '#' || (C) == '$') 740 741/* Separator character handling. */ 742 743#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) 744 745static inline int 746skip_past_char (char ** str, char c) 747{ 748 if (**str == c) 749 { 750 (*str)++; 751 return SUCCESS; 752 } 753 else 754 return FAIL; 755} 756#define skip_past_comma(str) skip_past_char (str, ',') 757 758/* Arithmetic expressions (possibly involving symbols). */ 759 760/* Return TRUE if anything in the expression is a bignum. */ 761 762static int 763walk_no_bignums (symbolS * sp) 764{ 765 if (symbol_get_value_expression (sp)->X_op == O_big) 766 return 1; 767 768 if (symbol_get_value_expression (sp)->X_add_symbol) 769 { 770 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) 771 || (symbol_get_value_expression (sp)->X_op_symbol 772 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); 773 } 774 775 return 0; 776} 777 778static int in_my_get_expression = 0; 779 780/* Third argument to my_get_expression. */ 781#define GE_NO_PREFIX 0 782#define GE_IMM_PREFIX 1 783#define GE_OPT_PREFIX 2 784/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) 785 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ 786#define GE_OPT_PREFIX_BIG 3 787 788static int 789my_get_expression (expressionS * ep, char ** str, int prefix_mode) 790{ 791 char * save_in; 792 segT seg; 793 794 /* In unified syntax, all prefixes are optional. */ 795 if (unified_syntax) 796 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode 797 : GE_OPT_PREFIX; 798 799 switch (prefix_mode) 800 { 801 case GE_NO_PREFIX: break; 802 case GE_IMM_PREFIX: 803 if (!is_immediate_prefix (**str)) 804 { 805 inst.error = _("immediate expression requires a # prefix"); 806 return FAIL; 807 } 808 (*str)++; 809 break; 810 case GE_OPT_PREFIX: 811 case GE_OPT_PREFIX_BIG: 812 if (is_immediate_prefix (**str)) 813 (*str)++; 814 break; 815 default: abort (); 816 } 817 818 memset (ep, 0, sizeof (expressionS)); 819 820 save_in = input_line_pointer; 821 input_line_pointer = *str; 822 in_my_get_expression = 1; 823 seg = expression (ep); 824 in_my_get_expression = 0; 825 826 if (ep->X_op == O_illegal) 827 { 828 /* We found a bad expression in md_operand(). */ 829 *str = input_line_pointer; 830 input_line_pointer = save_in; 831 if (inst.error == NULL) 832 inst.error = _("bad expression"); 833 return 1; 834 } 835 836#ifdef OBJ_AOUT 837 if (seg != absolute_section 838 && seg != text_section 839 && seg != data_section 840 && seg != bss_section 841 && seg != undefined_section) 842 { 843 inst.error = _("bad segment"); 844 *str = input_line_pointer; 845 input_line_pointer = save_in; 846 return 1; 847 } 848#endif 849 850 /* Get rid of any bignums now, so that we don't generate an error for which 851 we can't establish a line number later on. Big numbers are never valid 852 in instructions, which is where this routine is always called. */ 853 if (prefix_mode != GE_OPT_PREFIX_BIG 854 && (ep->X_op == O_big 855 || (ep->X_add_symbol 856 && (walk_no_bignums (ep->X_add_symbol) 857 || (ep->X_op_symbol 858 && walk_no_bignums (ep->X_op_symbol)))))) 859 { 860 inst.error = _("invalid constant"); 861 *str = input_line_pointer; 862 input_line_pointer = save_in; 863 return 1; 864 } 865 866 *str = input_line_pointer; 867 input_line_pointer = save_in; 868 return 0; 869} 870 871/* Turn a string in input_line_pointer into a floating point constant 872 of type TYPE, and store the appropriate bytes in *LITP. The number 873 of LITTLENUMS emitted is stored in *SIZEP. An error message is 874 returned, or NULL on OK. 875 876 Note that fp constants aren't represent in the normal way on the ARM. 877 In big endian mode, things are as expected. However, in little endian 878 mode fp constants are big-endian word-wise, and little-endian byte-wise 879 within the words. For example, (double) 1.1 in big endian mode is 880 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is 881 the byte sequence 99 99 f1 3f 9a 99 99 99. 882 883 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ 884 885char * 886md_atof (int type, char * litP, int * sizeP) 887{ 888 int prec; 889 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 890 char *t; 891 int i; 892 893 switch (type) 894 { 895 case 'f': 896 case 'F': 897 case 's': 898 case 'S': 899 prec = 2; 900 break; 901 902 case 'd': 903 case 'D': 904 case 'r': 905 case 'R': 906 prec = 4; 907 break; 908 909 case 'x': 910 case 'X': 911 prec = 6; 912 break; 913 914 case 'p': 915 case 'P': 916 prec = 6; 917 break; 918 919 default: 920 *sizeP = 0; 921 return _("bad call to MD_ATOF()"); 922 } 923 924 t = atof_ieee (input_line_pointer, type, words); 925 if (t) 926 input_line_pointer = t; 927 *sizeP = prec * 2; 928 929 if (target_big_endian) 930 { 931 for (i = 0; i < prec; i++) 932 { 933 md_number_to_chars (litP, (valueT) words[i], 2); 934 litP += 2; 935 } 936 } 937 else 938 { 939 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) 940 for (i = prec - 1; i >= 0; i--) 941 { 942 md_number_to_chars (litP, (valueT) words[i], 2); 943 litP += 2; 944 } 945 else 946 /* For a 4 byte float the order of elements in `words' is 1 0. 947 For an 8 byte float the order is 1 0 3 2. */ 948 for (i = 0; i < prec; i += 2) 949 { 950 md_number_to_chars (litP, (valueT) words[i + 1], 2); 951 md_number_to_chars (litP + 2, (valueT) words[i], 2); 952 litP += 4; 953 } 954 } 955 956 return 0; 957} 958 959/* We handle all bad expressions here, so that we can report the faulty 960 instruction in the error message. */ 961void 962md_operand (expressionS * expr) 963{ 964 if (in_my_get_expression) 965 expr->X_op = O_illegal; 966} 967 968/* Immediate values. */ 969 970/* Generic immediate-value read function for use in directives. 971 Accepts anything that 'expression' can fold to a constant. 972 *val receives the number. */ 973#ifdef OBJ_ELF 974static int 975immediate_for_directive (int *val) 976{ 977 expressionS exp; 978 exp.X_op = O_illegal; 979 980 if (is_immediate_prefix (*input_line_pointer)) 981 { 982 input_line_pointer++; 983 expression (&exp); 984 } 985 986 if (exp.X_op != O_constant) 987 { 988 as_bad (_("expected #constant")); 989 ignore_rest_of_line (); 990 return FAIL; 991 } 992 *val = exp.X_add_number; 993 return SUCCESS; 994} 995#endif 996 997/* Register parsing. */ 998 999/* Generic register parser. CCP points to what should be the 1000 beginning of a register name. If it is indeed a valid register 1001 name, advance CCP over it and return the reg_entry structure; 1002 otherwise return NULL. Does not issue diagnostics. */ 1003 1004static struct reg_entry * 1005arm_reg_parse_multi (char **ccp) 1006{ 1007 char *start = *ccp; 1008 char *p; 1009 struct reg_entry *reg; 1010 1011#ifdef REGISTER_PREFIX 1012 if (*start != REGISTER_PREFIX) 1013 return NULL; 1014 start++; 1015#endif 1016#ifdef OPTIONAL_REGISTER_PREFIX 1017 if (*start == OPTIONAL_REGISTER_PREFIX) 1018 start++; 1019#endif 1020 1021 p = start; 1022 if (!ISALPHA (*p) || !is_name_beginner (*p)) 1023 return NULL; 1024 1025 do 1026 p++; 1027 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); 1028 1029 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); 1030 1031 if (!reg) 1032 return NULL; 1033 1034 *ccp = p; 1035 return reg; 1036} 1037 1038static int 1039arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, 1040 enum arm_reg_type type) 1041{ 1042 /* Alternative syntaxes are accepted for a few register classes. */ 1043 switch (type) 1044 { 1045 case REG_TYPE_MVF: 1046 case REG_TYPE_MVD: 1047 case REG_TYPE_MVFX: 1048 case REG_TYPE_MVDX: 1049 /* Generic coprocessor register names are allowed for these. */ 1050 if (reg && reg->type == REG_TYPE_CN) 1051 return reg->number; 1052 break; 1053 1054 case REG_TYPE_CP: 1055 /* For backward compatibility, a bare number is valid here. */ 1056 { 1057 unsigned long processor = strtoul (start, ccp, 10); 1058 if (*ccp != start && processor <= 15) 1059 return processor; 1060 } 1061 1062 case REG_TYPE_MMXWC: 1063 /* WC includes WCG. ??? I'm not sure this is true for all 1064 instructions that take WC registers. */ 1065 if (reg && reg->type == REG_TYPE_MMXWCG) 1066 return reg->number; 1067 break; 1068 1069 default: 1070 break; 1071 } 1072 1073 return FAIL; 1074} 1075 1076/* As arm_reg_parse_multi, but the register must be of type TYPE, and the 1077 return value is the register number or FAIL. */ 1078 1079static int 1080arm_reg_parse (char **ccp, enum arm_reg_type type) 1081{ 1082 char *start = *ccp; 1083 struct reg_entry *reg = arm_reg_parse_multi (ccp); 1084 int ret; 1085 1086 /* Do not allow a scalar (reg+index) to parse as a register. */ 1087 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) 1088 return FAIL; 1089 1090 if (reg && reg->type == type) 1091 return reg->number; 1092 1093 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) 1094 return ret; 1095 1096 *ccp = start; 1097 return FAIL; 1098} 1099 1100/* Parse a Neon type specifier. *STR should point at the leading '.' 1101 character. Does no verification at this stage that the type fits the opcode 1102 properly. E.g., 1103 1104 .i32.i32.s16 1105 .s32.f32 1106 .u16 1107 1108 Can all be legally parsed by this function. 1109 1110 Fills in neon_type struct pointer with parsed information, and updates STR 1111 to point after the parsed type specifier. Returns SUCCESS if this was a legal 1112 type, FAIL if not. */ 1113 1114static int 1115parse_neon_type (struct neon_type *type, char **str) 1116{ 1117 char *ptr = *str; 1118 1119 if (type) 1120 type->elems = 0; 1121 1122 while (type->elems < NEON_MAX_TYPE_ELS) 1123 { 1124 enum neon_el_type thistype = NT_untyped; 1125 unsigned thissize = -1u; 1126 1127 if (*ptr != '.') 1128 break; 1129 1130 ptr++; 1131 1132 /* Just a size without an explicit type. */ 1133 if (ISDIGIT (*ptr)) 1134 goto parsesize; 1135 1136 switch (TOLOWER (*ptr)) 1137 { 1138 case 'i': thistype = NT_integer; break; 1139 case 'f': thistype = NT_float; break; 1140 case 'p': thistype = NT_poly; break; 1141 case 's': thistype = NT_signed; break; 1142 case 'u': thistype = NT_unsigned; break; 1143 case 'd': 1144 thistype = NT_float; 1145 thissize = 64; 1146 ptr++; 1147 goto done; 1148 default: 1149 as_bad (_("unexpected character `%c' in type specifier"), *ptr); 1150 return FAIL; 1151 } 1152 1153 ptr++; 1154 1155 /* .f is an abbreviation for .f32. */ 1156 if (thistype == NT_float && !ISDIGIT (*ptr)) 1157 thissize = 32; 1158 else 1159 { 1160 parsesize: 1161 thissize = strtoul (ptr, &ptr, 10); 1162 1163 if (thissize != 8 && thissize != 16 && thissize != 32 1164 && thissize != 64) 1165 { 1166 as_bad (_("bad size %d in type specifier"), thissize); 1167 return FAIL; 1168 } 1169 } 1170 1171 done: 1172 if (type) 1173 { 1174 type->el[type->elems].type = thistype; 1175 type->el[type->elems].size = thissize; 1176 type->elems++; 1177 } 1178 } 1179 1180 /* Empty/missing type is not a successful parse. */ 1181 if (type->elems == 0) 1182 return FAIL; 1183 1184 *str = ptr; 1185 1186 return SUCCESS; 1187} 1188 1189/* Errors may be set multiple times during parsing or bit encoding 1190 (particularly in the Neon bits), but usually the earliest error which is set 1191 will be the most meaningful. Avoid overwriting it with later (cascading) 1192 errors by calling this function. */ 1193 1194static void 1195first_error (const char *err) 1196{ 1197 if (!inst.error) 1198 inst.error = err; 1199} 1200 1201/* Parse a single type, e.g. ".s32", leading period included. */ 1202static int 1203parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) 1204{ 1205 char *str = *ccp; 1206 struct neon_type optype; 1207 1208 if (*str == '.') 1209 { 1210 if (parse_neon_type (&optype, &str) == SUCCESS) 1211 { 1212 if (optype.elems == 1) 1213 *vectype = optype.el[0]; 1214 else 1215 { 1216 first_error (_("only one type should be specified for operand")); 1217 return FAIL; 1218 } 1219 } 1220 else 1221 { 1222 first_error (_("vector type expected")); 1223 return FAIL; 1224 } 1225 } 1226 else 1227 return FAIL; 1228 1229 *ccp = str; 1230 1231 return SUCCESS; 1232} 1233 1234/* Special meanings for indices (which have a range of 0-7), which will fit into 1235 a 4-bit integer. */ 1236 1237#define NEON_ALL_LANES 15 1238#define NEON_INTERLEAVE_LANES 14 1239 1240/* Parse either a register or a scalar, with an optional type. Return the 1241 register number, and optionally fill in the actual type of the register 1242 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and 1243 type/index information in *TYPEINFO. */ 1244 1245static int 1246parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, 1247 enum arm_reg_type *rtype, 1248 struct neon_typed_alias *typeinfo) 1249{ 1250 char *str = *ccp; 1251 struct reg_entry *reg = arm_reg_parse_multi (&str); 1252 struct neon_typed_alias atype; 1253 struct neon_type_el parsetype; 1254 1255 atype.defined = 0; 1256 atype.index = -1; 1257 atype.eltype.type = NT_invtype; 1258 atype.eltype.size = -1; 1259 1260 /* Try alternate syntax for some types of register. Note these are mutually 1261 exclusive with the Neon syntax extensions. */ 1262 if (reg == NULL) 1263 { 1264 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); 1265 if (altreg != FAIL) 1266 *ccp = str; 1267 if (typeinfo) 1268 *typeinfo = atype; 1269 return altreg; 1270 } 1271 1272 /* Undo polymorphism when a set of register types may be accepted. */ 1273 if ((type == REG_TYPE_NDQ 1274 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) 1275 || (type == REG_TYPE_VFSD 1276 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) 1277 || (type == REG_TYPE_NSDQ 1278 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD 1279 || reg->type == REG_TYPE_NQ)) 1280 || (type == REG_TYPE_MMXWC 1281 && (reg->type == REG_TYPE_MMXWCG))) 1282 type = reg->type; 1283 1284 if (type != reg->type) 1285 return FAIL; 1286 1287 if (reg->neon) 1288 atype = *reg->neon; 1289 1290 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) 1291 { 1292 if ((atype.defined & NTA_HASTYPE) != 0) 1293 { 1294 first_error (_("can't redefine type for operand")); 1295 return FAIL; 1296 } 1297 atype.defined |= NTA_HASTYPE; 1298 atype.eltype = parsetype; 1299 } 1300 1301 if (skip_past_char (&str, '[') == SUCCESS) 1302 { 1303 if (type != REG_TYPE_VFD) 1304 { 1305 first_error (_("only D registers may be indexed")); 1306 return FAIL; 1307 } 1308 1309 if ((atype.defined & NTA_HASINDEX) != 0) 1310 { 1311 first_error (_("can't change index for operand")); 1312 return FAIL; 1313 } 1314 1315 atype.defined |= NTA_HASINDEX; 1316 1317 if (skip_past_char (&str, ']') == SUCCESS) 1318 atype.index = NEON_ALL_LANES; 1319 else 1320 { 1321 expressionS exp; 1322 1323 my_get_expression (&exp, &str, GE_NO_PREFIX); 1324 1325 if (exp.X_op != O_constant) 1326 { 1327 first_error (_("constant expression required")); 1328 return FAIL; 1329 } 1330 1331 if (skip_past_char (&str, ']') == FAIL) 1332 return FAIL; 1333 1334 atype.index = exp.X_add_number; 1335 } 1336 } 1337 1338 if (typeinfo) 1339 *typeinfo = atype; 1340 1341 if (rtype) 1342 *rtype = type; 1343 1344 *ccp = str; 1345 1346 return reg->number; 1347} 1348 1349/* Like arm_reg_parse, but allow allow the following extra features: 1350 - If RTYPE is non-zero, return the (possibly restricted) type of the 1351 register (e.g. Neon double or quad reg when either has been requested). 1352 - If this is a Neon vector type with additional type information, fill 1353 in the struct pointed to by VECTYPE (if non-NULL). 1354 This function will fault on encountering a scalar. 1355*/ 1356 1357static int 1358arm_typed_reg_parse (char **ccp, enum arm_reg_type type, 1359 enum arm_reg_type *rtype, struct neon_type_el *vectype) 1360{ 1361 struct neon_typed_alias atype; 1362 char *str = *ccp; 1363 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); 1364 1365 if (reg == FAIL) 1366 return FAIL; 1367 1368 /* Do not allow a scalar (reg+index) to parse as a register. */ 1369 if ((atype.defined & NTA_HASINDEX) != 0) 1370 { 1371 first_error (_("register operand expected, but got scalar")); 1372 return FAIL; 1373 } 1374 1375 if (vectype) 1376 *vectype = atype.eltype; 1377 1378 *ccp = str; 1379 1380 return reg; 1381} 1382 1383#define NEON_SCALAR_REG(X) ((X) >> 4) 1384#define NEON_SCALAR_INDEX(X) ((X) & 15) 1385 1386/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't 1387 have enough information to be able to do a good job bounds-checking. So, we 1388 just do easy checks here, and do further checks later. */ 1389 1390static int 1391parse_scalar (char **ccp, int elsize, struct neon_type_el *type) 1392{ 1393 int reg; 1394 char *str = *ccp; 1395 struct neon_typed_alias atype; 1396 1397 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); 1398 1399 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) 1400 return FAIL; 1401 1402 if (atype.index == NEON_ALL_LANES) 1403 { 1404 first_error (_("scalar must have an index")); 1405 return FAIL; 1406 } 1407 else if (atype.index >= 64 / elsize) 1408 { 1409 first_error (_("scalar index out of range")); 1410 return FAIL; 1411 } 1412 1413 if (type) 1414 *type = atype.eltype; 1415 1416 *ccp = str; 1417 1418 return reg * 16 + atype.index; 1419} 1420 1421/* Parse an ARM register list. Returns the bitmask, or FAIL. */ 1422static long 1423parse_reg_list (char ** strp) 1424{ 1425 char * str = * strp; 1426 long range = 0; 1427 int another_range; 1428 1429 /* We come back here if we get ranges concatenated by '+' or '|'. */ 1430 do 1431 { 1432 another_range = 0; 1433 1434 if (*str == '{') 1435 { 1436 int in_range = 0; 1437 int cur_reg = -1; 1438 1439 str++; 1440 do 1441 { 1442 int reg; 1443 1444 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) 1445 { 1446 first_error (_(reg_expected_msgs[REG_TYPE_RN])); 1447 return FAIL; 1448 } 1449 1450 if (in_range) 1451 { 1452 int i; 1453 1454 if (reg <= cur_reg) 1455 { 1456 first_error (_("bad range in register list")); 1457 return FAIL; 1458 } 1459 1460 for (i = cur_reg + 1; i < reg; i++) 1461 { 1462 if (range & (1 << i)) 1463 as_tsktsk 1464 (_("Warning: duplicated register (r%d) in register list"), 1465 i); 1466 else 1467 range |= 1 << i; 1468 } 1469 in_range = 0; 1470 } 1471 1472 if (range & (1 << reg)) 1473 as_tsktsk (_("Warning: duplicated register (r%d) in register list"), 1474 reg); 1475 else if (reg <= cur_reg) 1476 as_tsktsk (_("Warning: register range not in ascending order")); 1477 1478 range |= 1 << reg; 1479 cur_reg = reg; 1480 } 1481 while (skip_past_comma (&str) != FAIL 1482 || (in_range = 1, *str++ == '-')); 1483 str--; 1484 1485 if (*str++ != '}') 1486 { 1487 first_error (_("missing `}'")); 1488 return FAIL; 1489 } 1490 } 1491 else 1492 { 1493 expressionS expr; 1494 1495 if (my_get_expression (&expr, &str, GE_NO_PREFIX)) 1496 return FAIL; 1497 1498 if (expr.X_op == O_constant) 1499 { 1500 if (expr.X_add_number 1501 != (expr.X_add_number & 0x0000ffff)) 1502 { 1503 inst.error = _("invalid register mask"); 1504 return FAIL; 1505 } 1506 1507 if ((range & expr.X_add_number) != 0) 1508 { 1509 int regno = range & expr.X_add_number; 1510 1511 regno &= -regno; 1512 regno = (1 << regno) - 1; 1513 as_tsktsk 1514 (_("Warning: duplicated register (r%d) in register list"), 1515 regno); 1516 } 1517 1518 range |= expr.X_add_number; 1519 } 1520 else 1521 { 1522 if (inst.reloc.type != 0) 1523 { 1524 inst.error = _("expression too complex"); 1525 return FAIL; 1526 } 1527 1528 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS)); 1529 inst.reloc.type = BFD_RELOC_ARM_MULTI; 1530 inst.reloc.pc_rel = 0; 1531 } 1532 } 1533 1534 if (*str == '|' || *str == '+') 1535 { 1536 str++; 1537 another_range = 1; 1538 } 1539 } 1540 while (another_range); 1541 1542 *strp = str; 1543 return range; 1544} 1545 1546/* Types of registers in a list. */ 1547 1548enum reg_list_els 1549{ 1550 REGLIST_VFP_S, 1551 REGLIST_VFP_D, 1552 REGLIST_NEON_D 1553}; 1554 1555/* Parse a VFP register list. If the string is invalid return FAIL. 1556 Otherwise return the number of registers, and set PBASE to the first 1557 register. Parses registers of type ETYPE. 1558 If REGLIST_NEON_D is used, several syntax enhancements are enabled: 1559 - Q registers can be used to specify pairs of D registers 1560 - { } can be omitted from around a singleton register list 1561 FIXME: This is not implemented, as it would require backtracking in 1562 some cases, e.g.: 1563 vtbl.8 d3,d4,d5 1564 This could be done (the meaning isn't really ambiguous), but doesn't 1565 fit in well with the current parsing framework. 1566 - 32 D registers may be used (also true for VFPv3). 1567 FIXME: Types are ignored in these register lists, which is probably a 1568 bug. */ 1569 1570static int 1571parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) 1572{ 1573 char *str = *ccp; 1574 int base_reg; 1575 int new_base; 1576 enum arm_reg_type regtype = 0; 1577 int max_regs = 0; 1578 int count = 0; 1579 int warned = 0; 1580 unsigned long mask = 0; 1581 int i; 1582 1583 if (*str != '{') 1584 { 1585 inst.error = _("expecting {"); 1586 return FAIL; 1587 } 1588 1589 str++; 1590 1591 switch (etype) 1592 { 1593 case REGLIST_VFP_S: 1594 regtype = REG_TYPE_VFS; 1595 max_regs = 32; 1596 break; 1597 1598 case REGLIST_VFP_D: 1599 regtype = REG_TYPE_VFD; 1600 break; 1601 1602 case REGLIST_NEON_D: 1603 regtype = REG_TYPE_NDQ; 1604 break; 1605 } 1606 1607 if (etype != REGLIST_VFP_S) 1608 { 1609 /* VFPv3 allows 32 D registers. */ 1610 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3)) 1611 { 1612 max_regs = 32; 1613 if (thumb_mode) 1614 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 1615 fpu_vfp_ext_v3); 1616 else 1617 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 1618 fpu_vfp_ext_v3); 1619 } 1620 else 1621 max_regs = 16; 1622 } 1623 1624 base_reg = max_regs; 1625 1626 do 1627 { 1628 int setmask = 1, addregs = 1; 1629 1630 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); 1631 1632 if (new_base == FAIL) 1633 { 1634 first_error (_(reg_expected_msgs[regtype])); 1635 return FAIL; 1636 } 1637 1638 if (new_base >= max_regs) 1639 { 1640 first_error (_("register out of range in list")); 1641 return FAIL; 1642 } 1643 1644 /* Note: a value of 2 * n is returned for the register Q<n>. */ 1645 if (regtype == REG_TYPE_NQ) 1646 { 1647 setmask = 3; 1648 addregs = 2; 1649 } 1650 1651 if (new_base < base_reg) 1652 base_reg = new_base; 1653 1654 if (mask & (setmask << new_base)) 1655 { 1656 first_error (_("invalid register list")); 1657 return FAIL; 1658 } 1659 1660 if ((mask >> new_base) != 0 && ! warned) 1661 { 1662 as_tsktsk (_("register list not in ascending order")); 1663 warned = 1; 1664 } 1665 1666 mask |= setmask << new_base; 1667 count += addregs; 1668 1669 if (*str == '-') /* We have the start of a range expression */ 1670 { 1671 int high_range; 1672 1673 str++; 1674 1675 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) 1676 == FAIL) 1677 { 1678 inst.error = gettext (reg_expected_msgs[regtype]); 1679 return FAIL; 1680 } 1681 1682 if (high_range >= max_regs) 1683 { 1684 first_error (_("register out of range in list")); 1685 return FAIL; 1686 } 1687 1688 if (regtype == REG_TYPE_NQ) 1689 high_range = high_range + 1; 1690 1691 if (high_range <= new_base) 1692 { 1693 inst.error = _("register range not in ascending order"); 1694 return FAIL; 1695 } 1696 1697 for (new_base += addregs; new_base <= high_range; new_base += addregs) 1698 { 1699 if (mask & (setmask << new_base)) 1700 { 1701 inst.error = _("invalid register list"); 1702 return FAIL; 1703 } 1704 1705 mask |= setmask << new_base; 1706 count += addregs; 1707 } 1708 } 1709 } 1710 while (skip_past_comma (&str) != FAIL); 1711 1712 str++; 1713 1714 /* Sanity check -- should have raised a parse error above. */ 1715 if (count == 0 || count > max_regs) 1716 abort (); 1717 1718 *pbase = base_reg; 1719 1720 /* Final test -- the registers must be consecutive. */ 1721 mask >>= base_reg; 1722 for (i = 0; i < count; i++) 1723 { 1724 if ((mask & (1u << i)) == 0) 1725 { 1726 inst.error = _("non-contiguous register range"); 1727 return FAIL; 1728 } 1729 } 1730 1731 *ccp = str; 1732 1733 return count; 1734} 1735 1736/* True if two alias types are the same. */ 1737 1738static int 1739neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) 1740{ 1741 if (!a && !b) 1742 return 1; 1743 1744 if (!a || !b) 1745 return 0; 1746 1747 if (a->defined != b->defined) 1748 return 0; 1749 1750 if ((a->defined & NTA_HASTYPE) != 0 1751 && (a->eltype.type != b->eltype.type 1752 || a->eltype.size != b->eltype.size)) 1753 return 0; 1754 1755 if ((a->defined & NTA_HASINDEX) != 0 1756 && (a->index != b->index)) 1757 return 0; 1758 1759 return 1; 1760} 1761 1762/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. 1763 The base register is put in *PBASE. 1764 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of 1765 the return value. 1766 The register stride (minus one) is put in bit 4 of the return value. 1767 Bits [6:5] encode the list length (minus one). 1768 The type of the list elements is put in *ELTYPE, if non-NULL. */ 1769 1770#define NEON_LANE(X) ((X) & 0xf) 1771#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) 1772#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) 1773 1774static int 1775parse_neon_el_struct_list (char **str, unsigned *pbase, 1776 struct neon_type_el *eltype) 1777{ 1778 char *ptr = *str; 1779 int base_reg = -1; 1780 int reg_incr = -1; 1781 int count = 0; 1782 int lane = -1; 1783 int leading_brace = 0; 1784 enum arm_reg_type rtype = REG_TYPE_NDQ; 1785 int addregs = 1; 1786 const char *const incr_error = "register stride must be 1 or 2"; 1787 const char *const type_error = "mismatched element/structure types in list"; 1788 struct neon_typed_alias firsttype; 1789 1790 if (skip_past_char (&ptr, '{') == SUCCESS) 1791 leading_brace = 1; 1792 1793 do 1794 { 1795 struct neon_typed_alias atype; 1796 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); 1797 1798 if (getreg == FAIL) 1799 { 1800 first_error (_(reg_expected_msgs[rtype])); 1801 return FAIL; 1802 } 1803 1804 if (base_reg == -1) 1805 { 1806 base_reg = getreg; 1807 if (rtype == REG_TYPE_NQ) 1808 { 1809 reg_incr = 1; 1810 addregs = 2; 1811 } 1812 firsttype = atype; 1813 } 1814 else if (reg_incr == -1) 1815 { 1816 reg_incr = getreg - base_reg; 1817 if (reg_incr < 1 || reg_incr > 2) 1818 { 1819 first_error (_(incr_error)); 1820 return FAIL; 1821 } 1822 } 1823 else if (getreg != base_reg + reg_incr * count) 1824 { 1825 first_error (_(incr_error)); 1826 return FAIL; 1827 } 1828 1829 if (!neon_alias_types_same (&atype, &firsttype)) 1830 { 1831 first_error (_(type_error)); 1832 return FAIL; 1833 } 1834 1835 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list 1836 modes. */ 1837 if (ptr[0] == '-') 1838 { 1839 struct neon_typed_alias htype; 1840 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; 1841 if (lane == -1) 1842 lane = NEON_INTERLEAVE_LANES; 1843 else if (lane != NEON_INTERLEAVE_LANES) 1844 { 1845 first_error (_(type_error)); 1846 return FAIL; 1847 } 1848 if (reg_incr == -1) 1849 reg_incr = 1; 1850 else if (reg_incr != 1) 1851 { 1852 first_error (_("don't use Rn-Rm syntax with non-unit stride")); 1853 return FAIL; 1854 } 1855 ptr++; 1856 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); 1857 if (hireg == FAIL) 1858 { 1859 first_error (_(reg_expected_msgs[rtype])); 1860 return FAIL; 1861 } 1862 if (!neon_alias_types_same (&htype, &firsttype)) 1863 { 1864 first_error (_(type_error)); 1865 return FAIL; 1866 } 1867 count += hireg + dregs - getreg; 1868 continue; 1869 } 1870 1871 /* If we're using Q registers, we can't use [] or [n] syntax. */ 1872 if (rtype == REG_TYPE_NQ) 1873 { 1874 count += 2; 1875 continue; 1876 } 1877 1878 if ((atype.defined & NTA_HASINDEX) != 0) 1879 { 1880 if (lane == -1) 1881 lane = atype.index; 1882 else if (lane != atype.index) 1883 { 1884 first_error (_(type_error)); 1885 return FAIL; 1886 } 1887 } 1888 else if (lane == -1) 1889 lane = NEON_INTERLEAVE_LANES; 1890 else if (lane != NEON_INTERLEAVE_LANES) 1891 { 1892 first_error (_(type_error)); 1893 return FAIL; 1894 } 1895 count++; 1896 } 1897 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); 1898 1899 /* No lane set by [x]. We must be interleaving structures. */ 1900 if (lane == -1) 1901 lane = NEON_INTERLEAVE_LANES; 1902 1903 /* Sanity check. */ 1904 if (lane == -1 || base_reg == -1 || count < 1 || count > 4 1905 || (count > 1 && reg_incr == -1)) 1906 { 1907 first_error (_("error parsing element/structure list")); 1908 return FAIL; 1909 } 1910 1911 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) 1912 { 1913 first_error (_("expected }")); 1914 return FAIL; 1915 } 1916 1917 if (reg_incr == -1) 1918 reg_incr = 1; 1919 1920 if (eltype) 1921 *eltype = firsttype.eltype; 1922 1923 *pbase = base_reg; 1924 *str = ptr; 1925 1926 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); 1927} 1928 1929/* Parse an explicit relocation suffix on an expression. This is 1930 either nothing, or a word in parentheses. Note that if !OBJ_ELF, 1931 arm_reloc_hsh contains no entries, so this function can only 1932 succeed if there is no () after the word. Returns -1 on error, 1933 BFD_RELOC_UNUSED if there wasn't any suffix. */ 1934static int 1935parse_reloc (char **str) 1936{ 1937 struct reloc_entry *r; 1938 char *p, *q; 1939 1940 if (**str != '(') 1941 return BFD_RELOC_UNUSED; 1942 1943 p = *str + 1; 1944 q = p; 1945 1946 while (*q && *q != ')' && *q != ',') 1947 q++; 1948 if (*q != ')') 1949 return -1; 1950 1951 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) 1952 return -1; 1953 1954 *str = q + 1; 1955 return r->reloc; 1956} 1957 1958/* Directives: register aliases. */ 1959 1960static struct reg_entry * 1961insert_reg_alias (char *str, int number, int type) 1962{ 1963 struct reg_entry *new; 1964 const char *name; 1965 1966 if ((new = hash_find (arm_reg_hsh, str)) != 0) 1967 { 1968 if (new->builtin) 1969 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); 1970 1971 /* Only warn about a redefinition if it's not defined as the 1972 same register. */ 1973 else if (new->number != number || new->type != type) 1974 as_warn (_("ignoring redefinition of register alias '%s'"), str); 1975 1976 return 0; 1977 } 1978 1979 name = xstrdup (str); 1980 new = xmalloc (sizeof (struct reg_entry)); 1981 1982 new->name = name; 1983 new->number = number; 1984 new->type = type; 1985 new->builtin = FALSE; 1986 new->neon = NULL; 1987 1988 if (hash_insert (arm_reg_hsh, name, (PTR) new)) 1989 abort (); 1990 1991 return new; 1992} 1993 1994static void 1995insert_neon_reg_alias (char *str, int number, int type, 1996 struct neon_typed_alias *atype) 1997{ 1998 struct reg_entry *reg = insert_reg_alias (str, number, type); 1999 2000 if (!reg) 2001 { 2002 first_error (_("attempt to redefine typed alias")); 2003 return; 2004 } 2005 2006 if (atype) 2007 { 2008 reg->neon = xmalloc (sizeof (struct neon_typed_alias)); 2009 *reg->neon = *atype; 2010 } 2011} 2012 2013/* Look for the .req directive. This is of the form: 2014 2015 new_register_name .req existing_register_name 2016 2017 If we find one, or if it looks sufficiently like one that we want to 2018 handle any error here, return non-zero. Otherwise return zero. */ 2019 2020static int 2021create_register_alias (char * newname, char *p) 2022{ 2023 struct reg_entry *old; 2024 char *oldname, *nbuf; 2025 size_t nlen; 2026 2027 /* The input scrubber ensures that whitespace after the mnemonic is 2028 collapsed to single spaces. */ 2029 oldname = p; 2030 if (strncmp (oldname, " .req ", 6) != 0) 2031 return 0; 2032 2033 oldname += 6; 2034 if (*oldname == '\0') 2035 return 0; 2036 2037 old = hash_find (arm_reg_hsh, oldname); 2038 if (!old) 2039 { 2040 as_warn (_("unknown register '%s' -- .req ignored"), oldname); 2041 return 1; 2042 } 2043 2044 /* If TC_CASE_SENSITIVE is defined, then newname already points to 2045 the desired alias name, and p points to its end. If not, then 2046 the desired alias name is in the global original_case_string. */ 2047#ifdef TC_CASE_SENSITIVE 2048 nlen = p - newname; 2049#else 2050 newname = original_case_string; 2051 nlen = strlen (newname); 2052#endif 2053 2054 nbuf = alloca (nlen + 1); 2055 memcpy (nbuf, newname, nlen); 2056 nbuf[nlen] = '\0'; 2057 2058 /* Create aliases under the new name as stated; an all-lowercase 2059 version of the new name; and an all-uppercase version of the new 2060 name. */ 2061 insert_reg_alias (nbuf, old->number, old->type); 2062 2063 for (p = nbuf; *p; p++) 2064 *p = TOUPPER (*p); 2065 2066 if (strncmp (nbuf, newname, nlen)) 2067 insert_reg_alias (nbuf, old->number, old->type); 2068 2069 for (p = nbuf; *p; p++) 2070 *p = TOLOWER (*p); 2071 2072 if (strncmp (nbuf, newname, nlen)) 2073 insert_reg_alias (nbuf, old->number, old->type); 2074 2075 return 1; 2076} 2077 2078/* Create a Neon typed/indexed register alias using directives, e.g.: 2079 X .dn d5.s32[1] 2080 Y .qn 6.s16 2081 Z .dn d7 2082 T .dn Z[0] 2083 These typed registers can be used instead of the types specified after the 2084 Neon mnemonic, so long as all operands given have types. Types can also be 2085 specified directly, e.g.: 2086 vadd d0.s32, d1.s32, d2.s32 2087*/ 2088 2089static int 2090create_neon_reg_alias (char *newname, char *p) 2091{ 2092 enum arm_reg_type basetype; 2093 struct reg_entry *basereg; 2094 struct reg_entry mybasereg; 2095 struct neon_type ntype; 2096 struct neon_typed_alias typeinfo; 2097 char *namebuf, *nameend; 2098 int namelen; 2099 2100 typeinfo.defined = 0; 2101 typeinfo.eltype.type = NT_invtype; 2102 typeinfo.eltype.size = -1; 2103 typeinfo.index = -1; 2104 2105 nameend = p; 2106 2107 if (strncmp (p, " .dn ", 5) == 0) 2108 basetype = REG_TYPE_VFD; 2109 else if (strncmp (p, " .qn ", 5) == 0) 2110 basetype = REG_TYPE_NQ; 2111 else 2112 return 0; 2113 2114 p += 5; 2115 2116 if (*p == '\0') 2117 return 0; 2118 2119 basereg = arm_reg_parse_multi (&p); 2120 2121 if (basereg && basereg->type != basetype) 2122 { 2123 as_bad (_("bad type for register")); 2124 return 0; 2125 } 2126 2127 if (basereg == NULL) 2128 { 2129 expressionS exp; 2130 /* Try parsing as an integer. */ 2131 my_get_expression (&exp, &p, GE_NO_PREFIX); 2132 if (exp.X_op != O_constant) 2133 { 2134 as_bad (_("expression must be constant")); 2135 return 0; 2136 } 2137 basereg = &mybasereg; 2138 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 2139 : exp.X_add_number; 2140 basereg->neon = 0; 2141 } 2142 2143 if (basereg->neon) 2144 typeinfo = *basereg->neon; 2145 2146 if (parse_neon_type (&ntype, &p) == SUCCESS) 2147 { 2148 /* We got a type. */ 2149 if (typeinfo.defined & NTA_HASTYPE) 2150 { 2151 as_bad (_("can't redefine the type of a register alias")); 2152 return 0; 2153 } 2154 2155 typeinfo.defined |= NTA_HASTYPE; 2156 if (ntype.elems != 1) 2157 { 2158 as_bad (_("you must specify a single type only")); 2159 return 0; 2160 } 2161 typeinfo.eltype = ntype.el[0]; 2162 } 2163 2164 if (skip_past_char (&p, '[') == SUCCESS) 2165 { 2166 expressionS exp; 2167 /* We got a scalar index. */ 2168 2169 if (typeinfo.defined & NTA_HASINDEX) 2170 { 2171 as_bad (_("can't redefine the index of a scalar alias")); 2172 return 0; 2173 } 2174 2175 my_get_expression (&exp, &p, GE_NO_PREFIX); 2176 2177 if (exp.X_op != O_constant) 2178 { 2179 as_bad (_("scalar index must be constant")); 2180 return 0; 2181 } 2182 2183 typeinfo.defined |= NTA_HASINDEX; 2184 typeinfo.index = exp.X_add_number; 2185 2186 if (skip_past_char (&p, ']') == FAIL) 2187 { 2188 as_bad (_("expecting ]")); 2189 return 0; 2190 } 2191 } 2192 2193 namelen = nameend - newname; 2194 namebuf = alloca (namelen + 1); 2195 strncpy (namebuf, newname, namelen); 2196 namebuf[namelen] = '\0'; 2197 2198 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2199 typeinfo.defined != 0 ? &typeinfo : NULL); 2200 2201 /* Insert name in all uppercase. */ 2202 for (p = namebuf; *p; p++) 2203 *p = TOUPPER (*p); 2204 2205 if (strncmp (namebuf, newname, namelen)) 2206 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2207 typeinfo.defined != 0 ? &typeinfo : NULL); 2208 2209 /* Insert name in all lowercase. */ 2210 for (p = namebuf; *p; p++) 2211 *p = TOLOWER (*p); 2212 2213 if (strncmp (namebuf, newname, namelen)) 2214 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2215 typeinfo.defined != 0 ? &typeinfo : NULL); 2216 2217 return 1; 2218} 2219 2220/* Should never be called, as .req goes between the alias and the 2221 register name, not at the beginning of the line. */ 2222static void 2223s_req (int a ATTRIBUTE_UNUSED) 2224{ 2225 as_bad (_("invalid syntax for .req directive")); 2226} 2227 2228static void 2229s_dn (int a ATTRIBUTE_UNUSED) 2230{ 2231 as_bad (_("invalid syntax for .dn directive")); 2232} 2233 2234static void 2235s_qn (int a ATTRIBUTE_UNUSED) 2236{ 2237 as_bad (_("invalid syntax for .qn directive")); 2238} 2239 2240/* The .unreq directive deletes an alias which was previously defined 2241 by .req. For example: 2242 2243 my_alias .req r11 2244 .unreq my_alias */ 2245 2246static void 2247s_unreq (int a ATTRIBUTE_UNUSED) 2248{ 2249 char * name; 2250 char saved_char; 2251 2252 name = input_line_pointer; 2253 2254 while (*input_line_pointer != 0 2255 && *input_line_pointer != ' ' 2256 && *input_line_pointer != '\n') 2257 ++input_line_pointer; 2258 2259 saved_char = *input_line_pointer; 2260 *input_line_pointer = 0; 2261 2262 if (!*name) 2263 as_bad (_("invalid syntax for .unreq directive")); 2264 else 2265 { 2266 struct reg_entry *reg = hash_find (arm_reg_hsh, name); 2267 2268 if (!reg) 2269 as_bad (_("unknown register alias '%s'"), name); 2270 else if (reg->builtin) 2271 as_warn (_("ignoring attempt to undefine built-in register '%s'"), 2272 name); 2273 else 2274 { 2275 hash_delete (arm_reg_hsh, name); 2276 free ((char *) reg->name); 2277 if (reg->neon) 2278 free (reg->neon); 2279 free (reg); 2280 } 2281 } 2282 2283 *input_line_pointer = saved_char; 2284 demand_empty_rest_of_line (); 2285} 2286 2287/* Directives: Instruction set selection. */ 2288 2289#ifdef OBJ_ELF 2290/* This code is to handle mapping symbols as defined in the ARM ELF spec. 2291 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). 2292 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), 2293 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ 2294 2295static enum mstate mapstate = MAP_UNDEFINED; 2296 2297void 2298mapping_state (enum mstate state) 2299{ 2300 symbolS * symbolP; 2301 const char * symname; 2302 int type; 2303 2304 if (mapstate == state) 2305 /* The mapping symbol has already been emitted. 2306 There is nothing else to do. */ 2307 return; 2308 2309 mapstate = state; 2310 2311 switch (state) 2312 { 2313 case MAP_DATA: 2314 symname = "$d"; 2315 type = BSF_NO_FLAGS; 2316 break; 2317 case MAP_ARM: 2318 symname = "$a"; 2319 type = BSF_NO_FLAGS; 2320 break; 2321 case MAP_THUMB: 2322 symname = "$t"; 2323 type = BSF_NO_FLAGS; 2324 break; 2325 case MAP_UNDEFINED: 2326 return; 2327 default: 2328 abort (); 2329 } 2330 2331 seg_info (now_seg)->tc_segment_info_data.mapstate = state; 2332 2333 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now); 2334 symbol_table_insert (symbolP); 2335 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; 2336 2337 switch (state) 2338 { 2339 case MAP_ARM: 2340 THUMB_SET_FUNC (symbolP, 0); 2341 ARM_SET_THUMB (symbolP, 0); 2342 ARM_SET_INTERWORK (symbolP, support_interwork); 2343 break; 2344 2345 case MAP_THUMB: 2346 THUMB_SET_FUNC (symbolP, 1); 2347 ARM_SET_THUMB (symbolP, 1); 2348 ARM_SET_INTERWORK (symbolP, support_interwork); 2349 break; 2350 2351 case MAP_DATA: 2352 default: 2353 return; 2354 } 2355} 2356#else 2357#define mapping_state(x) /* nothing */ 2358#endif 2359 2360/* Find the real, Thumb encoded start of a Thumb function. */ 2361 2362static symbolS * 2363find_real_start (symbolS * symbolP) 2364{ 2365 char * real_start; 2366 const char * name = S_GET_NAME (symbolP); 2367 symbolS * new_target; 2368 2369 /* This definition must agree with the one in gcc/config/arm/thumb.c. */ 2370#define STUB_NAME ".real_start_of" 2371 2372 if (name == NULL) 2373 abort (); 2374 2375 /* The compiler may generate BL instructions to local labels because 2376 it needs to perform a branch to a far away location. These labels 2377 do not have a corresponding ".real_start_of" label. We check 2378 both for S_IS_LOCAL and for a leading dot, to give a way to bypass 2379 the ".real_start_of" convention for nonlocal branches. */ 2380 if (S_IS_LOCAL (symbolP) || name[0] == '.') 2381 return symbolP; 2382 2383 real_start = ACONCAT ((STUB_NAME, name, NULL)); 2384 new_target = symbol_find (real_start); 2385 2386 if (new_target == NULL) 2387 { 2388 as_warn ("Failed to find real start of function: %s\n", name); 2389 new_target = symbolP; 2390 } 2391 2392 return new_target; 2393} 2394 2395static void 2396opcode_select (int width) 2397{ 2398 switch (width) 2399 { 2400 case 16: 2401 if (! thumb_mode) 2402 { 2403 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 2404 as_bad (_("selected processor does not support THUMB opcodes")); 2405 2406 thumb_mode = 1; 2407 /* No need to force the alignment, since we will have been 2408 coming from ARM mode, which is word-aligned. */ 2409 record_alignment (now_seg, 1); 2410 } 2411 mapping_state (MAP_THUMB); 2412 break; 2413 2414 case 32: 2415 if (thumb_mode) 2416 { 2417 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 2418 as_bad (_("selected processor does not support ARM opcodes")); 2419 2420 thumb_mode = 0; 2421 2422 if (!need_pass_2) 2423 frag_align (2, 0, 0); 2424 2425 record_alignment (now_seg, 1); 2426 } 2427 mapping_state (MAP_ARM); 2428 break; 2429 2430 default: 2431 as_bad (_("invalid instruction size selected (%d)"), width); 2432 } 2433} 2434 2435static void 2436s_arm (int ignore ATTRIBUTE_UNUSED) 2437{ 2438 opcode_select (32); 2439 demand_empty_rest_of_line (); 2440} 2441 2442static void 2443s_thumb (int ignore ATTRIBUTE_UNUSED) 2444{ 2445 opcode_select (16); 2446 demand_empty_rest_of_line (); 2447} 2448 2449static void 2450s_code (int unused ATTRIBUTE_UNUSED) 2451{ 2452 int temp; 2453 2454 temp = get_absolute_expression (); 2455 switch (temp) 2456 { 2457 case 16: 2458 case 32: 2459 opcode_select (temp); 2460 break; 2461 2462 default: 2463 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); 2464 } 2465} 2466 2467static void 2468s_force_thumb (int ignore ATTRIBUTE_UNUSED) 2469{ 2470 /* If we are not already in thumb mode go into it, EVEN if 2471 the target processor does not support thumb instructions. 2472 This is used by gcc/config/arm/lib1funcs.asm for example 2473 to compile interworking support functions even if the 2474 target processor should not support interworking. */ 2475 if (! thumb_mode) 2476 { 2477 thumb_mode = 2; 2478 record_alignment (now_seg, 1); 2479 } 2480 2481 demand_empty_rest_of_line (); 2482} 2483 2484static void 2485s_thumb_func (int ignore ATTRIBUTE_UNUSED) 2486{ 2487 s_thumb (0); 2488 2489 /* The following label is the name/address of the start of a Thumb function. 2490 We need to know this for the interworking support. */ 2491 label_is_thumb_function_name = TRUE; 2492} 2493 2494/* Perform a .set directive, but also mark the alias as 2495 being a thumb function. */ 2496 2497static void 2498s_thumb_set (int equiv) 2499{ 2500 /* XXX the following is a duplicate of the code for s_set() in read.c 2501 We cannot just call that code as we need to get at the symbol that 2502 is created. */ 2503 char * name; 2504 char delim; 2505 char * end_name; 2506 symbolS * symbolP; 2507 2508 /* Especial apologies for the random logic: 2509 This just grew, and could be parsed much more simply! 2510 Dean - in haste. */ 2511 name = input_line_pointer; 2512 delim = get_symbol_end (); 2513 end_name = input_line_pointer; 2514 *end_name = delim; 2515 2516 if (*input_line_pointer != ',') 2517 { 2518 *end_name = 0; 2519 as_bad (_("expected comma after name \"%s\""), name); 2520 *end_name = delim; 2521 ignore_rest_of_line (); 2522 return; 2523 } 2524 2525 input_line_pointer++; 2526 *end_name = 0; 2527 2528 if (name[0] == '.' && name[1] == '\0') 2529 { 2530 /* XXX - this should not happen to .thumb_set. */ 2531 abort (); 2532 } 2533 2534 if ((symbolP = symbol_find (name)) == NULL 2535 && (symbolP = md_undefined_symbol (name)) == NULL) 2536 { 2537#ifndef NO_LISTING 2538 /* When doing symbol listings, play games with dummy fragments living 2539 outside the normal fragment chain to record the file and line info 2540 for this symbol. */ 2541 if (listing & LISTING_SYMBOLS) 2542 { 2543 extern struct list_info_struct * listing_tail; 2544 fragS * dummy_frag = xmalloc (sizeof (fragS)); 2545 2546 memset (dummy_frag, 0, sizeof (fragS)); 2547 dummy_frag->fr_type = rs_fill; 2548 dummy_frag->line = listing_tail; 2549 symbolP = symbol_new (name, undefined_section, 0, dummy_frag); 2550 dummy_frag->fr_symbol = symbolP; 2551 } 2552 else 2553#endif 2554 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); 2555 2556#ifdef OBJ_COFF 2557 /* "set" symbols are local unless otherwise specified. */ 2558 SF_SET_LOCAL (symbolP); 2559#endif /* OBJ_COFF */ 2560 } /* Make a new symbol. */ 2561 2562 symbol_table_insert (symbolP); 2563 2564 * end_name = delim; 2565 2566 if (equiv 2567 && S_IS_DEFINED (symbolP) 2568 && S_GET_SEGMENT (symbolP) != reg_section) 2569 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); 2570 2571 pseudo_set (symbolP); 2572 2573 demand_empty_rest_of_line (); 2574 2575 /* XXX Now we come to the Thumb specific bit of code. */ 2576 2577 THUMB_SET_FUNC (symbolP, 1); 2578 ARM_SET_THUMB (symbolP, 1); 2579#if defined OBJ_ELF || defined OBJ_COFF 2580 ARM_SET_INTERWORK (symbolP, support_interwork); 2581#endif 2582} 2583 2584/* Directives: Mode selection. */ 2585 2586/* .syntax [unified|divided] - choose the new unified syntax 2587 (same for Arm and Thumb encoding, modulo slight differences in what 2588 can be represented) or the old divergent syntax for each mode. */ 2589static void 2590s_syntax (int unused ATTRIBUTE_UNUSED) 2591{ 2592 char *name, delim; 2593 2594 name = input_line_pointer; 2595 delim = get_symbol_end (); 2596 2597 if (!strcasecmp (name, "unified")) 2598 unified_syntax = TRUE; 2599 else if (!strcasecmp (name, "divided")) 2600 unified_syntax = FALSE; 2601 else 2602 { 2603 as_bad (_("unrecognized syntax mode \"%s\""), name); 2604 return; 2605 } 2606 *input_line_pointer = delim; 2607 demand_empty_rest_of_line (); 2608} 2609 2610/* Directives: sectioning and alignment. */ 2611 2612/* Same as s_align_ptwo but align 0 => align 2. */ 2613 2614static void 2615s_align (int unused ATTRIBUTE_UNUSED) 2616{ 2617 int temp; 2618 bfd_boolean fill_p; 2619 long temp_fill; 2620 long max_alignment = 15; 2621 2622 temp = get_absolute_expression (); 2623 if (temp > max_alignment) 2624 as_bad (_("alignment too large: %d assumed"), temp = max_alignment); 2625 else if (temp < 0) 2626 { 2627 as_bad (_("alignment negative. 0 assumed.")); 2628 temp = 0; 2629 } 2630 2631 if (*input_line_pointer == ',') 2632 { 2633 input_line_pointer++; 2634 temp_fill = get_absolute_expression (); 2635 fill_p = TRUE; 2636 } 2637 else 2638 { 2639 fill_p = FALSE; 2640 temp_fill = 0; 2641 } 2642 2643 if (!temp) 2644 temp = 2; 2645 2646 /* Only make a frag if we HAVE to. */ 2647 if (temp && !need_pass_2) 2648 { 2649 if (!fill_p && subseg_text_p (now_seg)) 2650 frag_align_code (temp, 0); 2651 else 2652 frag_align (temp, (int) temp_fill, 0); 2653 } 2654 demand_empty_rest_of_line (); 2655 2656 record_alignment (now_seg, temp); 2657} 2658 2659static void 2660s_bss (int ignore ATTRIBUTE_UNUSED) 2661{ 2662 /* We don't support putting frags in the BSS segment, we fake it by 2663 marking in_bss, then looking at s_skip for clues. */ 2664 subseg_set (bss_section, 0); 2665 demand_empty_rest_of_line (); 2666 mapping_state (MAP_DATA); 2667} 2668 2669static void 2670s_even (int ignore ATTRIBUTE_UNUSED) 2671{ 2672 /* Never make frag if expect extra pass. */ 2673 if (!need_pass_2) 2674 frag_align (1, 0, 0); 2675 2676 record_alignment (now_seg, 1); 2677 2678 demand_empty_rest_of_line (); 2679} 2680 2681/* Directives: Literal pools. */ 2682 2683static literal_pool * 2684find_literal_pool (void) 2685{ 2686 literal_pool * pool; 2687 2688 for (pool = list_of_pools; pool != NULL; pool = pool->next) 2689 { 2690 if (pool->section == now_seg 2691 && pool->sub_section == now_subseg) 2692 break; 2693 } 2694 2695 return pool; 2696} 2697 2698static literal_pool * 2699find_or_make_literal_pool (void) 2700{ 2701 /* Next literal pool ID number. */ 2702 static unsigned int latest_pool_num = 1; 2703 literal_pool * pool; 2704 2705 pool = find_literal_pool (); 2706 2707 if (pool == NULL) 2708 { 2709 /* Create a new pool. */ 2710 pool = xmalloc (sizeof (* pool)); 2711 if (! pool) 2712 return NULL; 2713 2714 pool->next_free_entry = 0; 2715 pool->section = now_seg; 2716 pool->sub_section = now_subseg; 2717 pool->next = list_of_pools; 2718 pool->symbol = NULL; 2719 2720 /* Add it to the list. */ 2721 list_of_pools = pool; 2722 } 2723 2724 /* New pools, and emptied pools, will have a NULL symbol. */ 2725 if (pool->symbol == NULL) 2726 { 2727 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, 2728 (valueT) 0, &zero_address_frag); 2729 pool->id = latest_pool_num ++; 2730 } 2731 2732 /* Done. */ 2733 return pool; 2734} 2735 2736/* Add the literal in the global 'inst' 2737 structure to the relevent literal pool. */ 2738 2739static int 2740add_to_lit_pool (void) 2741{ 2742 literal_pool * pool; 2743 unsigned int entry; 2744 2745 pool = find_or_make_literal_pool (); 2746 2747 /* Check if this literal value is already in the pool. */ 2748 for (entry = 0; entry < pool->next_free_entry; entry ++) 2749 { 2750 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) 2751 && (inst.reloc.exp.X_op == O_constant) 2752 && (pool->literals[entry].X_add_number 2753 == inst.reloc.exp.X_add_number) 2754 && (pool->literals[entry].X_unsigned 2755 == inst.reloc.exp.X_unsigned)) 2756 break; 2757 2758 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) 2759 && (inst.reloc.exp.X_op == O_symbol) 2760 && (pool->literals[entry].X_add_number 2761 == inst.reloc.exp.X_add_number) 2762 && (pool->literals[entry].X_add_symbol 2763 == inst.reloc.exp.X_add_symbol) 2764 && (pool->literals[entry].X_op_symbol 2765 == inst.reloc.exp.X_op_symbol)) 2766 break; 2767 } 2768 2769 /* Do we need to create a new entry? */ 2770 if (entry == pool->next_free_entry) 2771 { 2772 if (entry >= MAX_LITERAL_POOL_SIZE) 2773 { 2774 inst.error = _("literal pool overflow"); 2775 return FAIL; 2776 } 2777 2778 pool->literals[entry] = inst.reloc.exp; 2779 pool->next_free_entry += 1; 2780 } 2781 2782 inst.reloc.exp.X_op = O_symbol; 2783 inst.reloc.exp.X_add_number = ((int) entry) * 4; 2784 inst.reloc.exp.X_add_symbol = pool->symbol; 2785 2786 return SUCCESS; 2787} 2788 2789/* Can't use symbol_new here, so have to create a symbol and then at 2790 a later date assign it a value. Thats what these functions do. */ 2791 2792static void 2793symbol_locate (symbolS * symbolP, 2794 const char * name, /* It is copied, the caller can modify. */ 2795 segT segment, /* Segment identifier (SEG_<something>). */ 2796 valueT valu, /* Symbol value. */ 2797 fragS * frag) /* Associated fragment. */ 2798{ 2799 unsigned int name_length; 2800 char * preserved_copy_of_name; 2801 2802 name_length = strlen (name) + 1; /* +1 for \0. */ 2803 obstack_grow (¬es, name, name_length); 2804 preserved_copy_of_name = obstack_finish (¬es); 2805 2806#ifdef tc_canonicalize_symbol_name 2807 preserved_copy_of_name = 2808 tc_canonicalize_symbol_name (preserved_copy_of_name); 2809#endif 2810 2811 S_SET_NAME (symbolP, preserved_copy_of_name); 2812 2813 S_SET_SEGMENT (symbolP, segment); 2814 S_SET_VALUE (symbolP, valu); 2815 symbol_clear_list_pointers (symbolP); 2816 2817 symbol_set_frag (symbolP, frag); 2818 2819 /* Link to end of symbol chain. */ 2820 { 2821 extern int symbol_table_frozen; 2822 2823 if (symbol_table_frozen) 2824 abort (); 2825 } 2826 2827 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); 2828 2829 obj_symbol_new_hook (symbolP); 2830 2831#ifdef tc_symbol_new_hook 2832 tc_symbol_new_hook (symbolP); 2833#endif 2834 2835#ifdef DEBUG_SYMS 2836 verify_symbol_chain (symbol_rootP, symbol_lastP); 2837#endif /* DEBUG_SYMS */ 2838} 2839 2840 2841static void 2842s_ltorg (int ignored ATTRIBUTE_UNUSED) 2843{ 2844 unsigned int entry; 2845 literal_pool * pool; 2846 char sym_name[20]; 2847 2848 pool = find_literal_pool (); 2849 if (pool == NULL 2850 || pool->symbol == NULL 2851 || pool->next_free_entry == 0) 2852 return; 2853 2854 mapping_state (MAP_DATA); 2855 2856 /* Align pool as you have word accesses. 2857 Only make a frag if we have to. */ 2858 if (!need_pass_2) 2859 frag_align (2, 0, 0); 2860 2861 record_alignment (now_seg, 2); 2862 2863 sprintf (sym_name, "$$lit_\002%x", pool->id); 2864 2865 symbol_locate (pool->symbol, sym_name, now_seg, 2866 (valueT) frag_now_fix (), frag_now); 2867 symbol_table_insert (pool->symbol); 2868 2869 ARM_SET_THUMB (pool->symbol, thumb_mode); 2870 2871#if defined OBJ_COFF || defined OBJ_ELF 2872 ARM_SET_INTERWORK (pool->symbol, support_interwork); 2873#endif 2874 2875 for (entry = 0; entry < pool->next_free_entry; entry ++) 2876 /* First output the expression in the instruction to the pool. */ 2877 emit_expr (&(pool->literals[entry]), 4); /* .word */ 2878 2879 /* Mark the pool as empty. */ 2880 pool->next_free_entry = 0; 2881 pool->symbol = NULL; 2882} 2883 2884#ifdef OBJ_ELF 2885/* Forward declarations for functions below, in the MD interface 2886 section. */ 2887static void fix_new_arm (fragS *, int, short, expressionS *, int, int); 2888static valueT create_unwind_entry (int); 2889static void start_unwind_section (const segT, int); 2890static void add_unwind_opcode (valueT, int); 2891static void flush_pending_unwind (void); 2892 2893/* Directives: Data. */ 2894 2895static void 2896s_arm_elf_cons (int nbytes) 2897{ 2898 expressionS exp; 2899 2900#ifdef md_flush_pending_output 2901 md_flush_pending_output (); 2902#endif 2903 2904 if (is_it_end_of_statement ()) 2905 { 2906 demand_empty_rest_of_line (); 2907 return; 2908 } 2909 2910#ifdef md_cons_align 2911 md_cons_align (nbytes); 2912#endif 2913 2914 mapping_state (MAP_DATA); 2915 do 2916 { 2917 int reloc; 2918 char *base = input_line_pointer; 2919 2920 expression (& exp); 2921 2922 if (exp.X_op != O_symbol) 2923 emit_expr (&exp, (unsigned int) nbytes); 2924 else 2925 { 2926 char *before_reloc = input_line_pointer; 2927 reloc = parse_reloc (&input_line_pointer); 2928 if (reloc == -1) 2929 { 2930 as_bad (_("unrecognized relocation suffix")); 2931 ignore_rest_of_line (); 2932 return; 2933 } 2934 else if (reloc == BFD_RELOC_UNUSED) 2935 emit_expr (&exp, (unsigned int) nbytes); 2936 else 2937 { 2938 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc); 2939 int size = bfd_get_reloc_size (howto); 2940 2941 if (reloc == BFD_RELOC_ARM_PLT32) 2942 { 2943 as_bad (_("(plt) is only valid on branch targets")); 2944 reloc = BFD_RELOC_UNUSED; 2945 size = 0; 2946 } 2947 2948 if (size > nbytes) 2949 as_bad (_("%s relocations do not fit in %d bytes"), 2950 howto->name, nbytes); 2951 else 2952 { 2953 /* We've parsed an expression stopping at O_symbol. 2954 But there may be more expression left now that we 2955 have parsed the relocation marker. Parse it again. 2956 XXX Surely there is a cleaner way to do this. */ 2957 char *p = input_line_pointer; 2958 int offset; 2959 char *save_buf = alloca (input_line_pointer - base); 2960 memcpy (save_buf, base, input_line_pointer - base); 2961 memmove (base + (input_line_pointer - before_reloc), 2962 base, before_reloc - base); 2963 2964 input_line_pointer = base + (input_line_pointer-before_reloc); 2965 expression (&exp); 2966 memcpy (base, save_buf, p - base); 2967 2968 offset = nbytes - size; 2969 p = frag_more ((int) nbytes); 2970 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, 2971 size, &exp, 0, reloc); 2972 } 2973 } 2974 } 2975 } 2976 while (*input_line_pointer++ == ','); 2977 2978 /* Put terminator back into stream. */ 2979 input_line_pointer --; 2980 demand_empty_rest_of_line (); 2981} 2982 2983 2984/* Parse a .rel31 directive. */ 2985 2986static void 2987s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) 2988{ 2989 expressionS exp; 2990 char *p; 2991 valueT highbit; 2992 2993 highbit = 0; 2994 if (*input_line_pointer == '1') 2995 highbit = 0x80000000; 2996 else if (*input_line_pointer != '0') 2997 as_bad (_("expected 0 or 1")); 2998 2999 input_line_pointer++; 3000 if (*input_line_pointer != ',') 3001 as_bad (_("missing comma")); 3002 input_line_pointer++; 3003 3004#ifdef md_flush_pending_output 3005 md_flush_pending_output (); 3006#endif 3007 3008#ifdef md_cons_align 3009 md_cons_align (4); 3010#endif 3011 3012 mapping_state (MAP_DATA); 3013 3014 expression (&exp); 3015 3016 p = frag_more (4); 3017 md_number_to_chars (p, highbit, 4); 3018 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, 3019 BFD_RELOC_ARM_PREL31); 3020 3021 demand_empty_rest_of_line (); 3022} 3023 3024/* Directives: AEABI stack-unwind tables. */ 3025 3026/* Parse an unwind_fnstart directive. Simply records the current location. */ 3027 3028static void 3029s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) 3030{ 3031 demand_empty_rest_of_line (); 3032 /* Mark the start of the function. */ 3033 unwind.proc_start = expr_build_dot (); 3034 3035 /* Reset the rest of the unwind info. */ 3036 unwind.opcode_count = 0; 3037 unwind.table_entry = NULL; 3038 unwind.personality_routine = NULL; 3039 unwind.personality_index = -1; 3040 unwind.frame_size = 0; 3041 unwind.fp_offset = 0; 3042 unwind.fp_reg = 13; 3043 unwind.fp_used = 0; 3044 unwind.sp_restored = 0; 3045} 3046 3047 3048/* Parse a handlerdata directive. Creates the exception handling table entry 3049 for the function. */ 3050 3051static void 3052s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) 3053{ 3054 demand_empty_rest_of_line (); 3055 if (unwind.table_entry) 3056 as_bad (_("dupicate .handlerdata directive")); 3057 3058 create_unwind_entry (1); 3059} 3060 3061/* Parse an unwind_fnend directive. Generates the index table entry. */ 3062 3063static void 3064s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) 3065{ 3066 long where; 3067 char *ptr; 3068 valueT val; 3069 3070 demand_empty_rest_of_line (); 3071 3072 /* Add eh table entry. */ 3073 if (unwind.table_entry == NULL) 3074 val = create_unwind_entry (0); 3075 else 3076 val = 0; 3077 3078 /* Add index table entry. This is two words. */ 3079 start_unwind_section (unwind.saved_seg, 1); 3080 frag_align (2, 0, 0); 3081 record_alignment (now_seg, 2); 3082 3083 ptr = frag_more (8); 3084 memset(ptr, 0, 8); 3085 where = frag_now_fix () - 8; 3086 3087 /* Self relative offset of the function start. */ 3088 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, 3089 BFD_RELOC_ARM_PREL31); 3090 3091 /* Indicate dependency on EHABI-defined personality routines to the 3092 linker, if it hasn't been done already. */ 3093 if (unwind.personality_index >= 0 && unwind.personality_index < 3 3094 && !(marked_pr_dependency & (1 << unwind.personality_index))) 3095 { 3096 static const char *const name[] = { 3097 "__aeabi_unwind_cpp_pr0", 3098 "__aeabi_unwind_cpp_pr1", 3099 "__aeabi_unwind_cpp_pr2" 3100 }; 3101 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); 3102 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); 3103 marked_pr_dependency |= 1 << unwind.personality_index; 3104 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency 3105 = marked_pr_dependency; 3106 } 3107 3108 if (val) 3109 /* Inline exception table entry. */ 3110 md_number_to_chars (ptr + 4, val, 4); 3111 else 3112 /* Self relative offset of the table entry. */ 3113 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, 3114 BFD_RELOC_ARM_PREL31); 3115 3116 /* Restore the original section. */ 3117 subseg_set (unwind.saved_seg, unwind.saved_subseg); 3118} 3119 3120 3121/* Parse an unwind_cantunwind directive. */ 3122 3123static void 3124s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) 3125{ 3126 demand_empty_rest_of_line (); 3127 if (unwind.personality_routine || unwind.personality_index != -1) 3128 as_bad (_("personality routine specified for cantunwind frame")); 3129 3130 unwind.personality_index = -2; 3131} 3132 3133 3134/* Parse a personalityindex directive. */ 3135 3136static void 3137s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) 3138{ 3139 expressionS exp; 3140 3141 if (unwind.personality_routine || unwind.personality_index != -1) 3142 as_bad (_("duplicate .personalityindex directive")); 3143 3144 expression (&exp); 3145 3146 if (exp.X_op != O_constant 3147 || exp.X_add_number < 0 || exp.X_add_number > 15) 3148 { 3149 as_bad (_("bad personality routine number")); 3150 ignore_rest_of_line (); 3151 return; 3152 } 3153 3154 unwind.personality_index = exp.X_add_number; 3155 3156 demand_empty_rest_of_line (); 3157} 3158 3159 3160/* Parse a personality directive. */ 3161 3162static void 3163s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) 3164{ 3165 char *name, *p, c; 3166 3167 if (unwind.personality_routine || unwind.personality_index != -1) 3168 as_bad (_("duplicate .personality directive")); 3169 3170 name = input_line_pointer; 3171 c = get_symbol_end (); 3172 p = input_line_pointer; 3173 unwind.personality_routine = symbol_find_or_make (name); 3174 *p = c; 3175 demand_empty_rest_of_line (); 3176} 3177 3178 3179/* Parse a directive saving core registers. */ 3180 3181static void 3182s_arm_unwind_save_core (void) 3183{ 3184 valueT op; 3185 long range; 3186 int n; 3187 3188 range = parse_reg_list (&input_line_pointer); 3189 if (range == FAIL) 3190 { 3191 as_bad (_("expected register list")); 3192 ignore_rest_of_line (); 3193 return; 3194 } 3195 3196 demand_empty_rest_of_line (); 3197 3198 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} 3199 into .unwind_save {..., sp...}. We aren't bothered about the value of 3200 ip because it is clobbered by calls. */ 3201 if (unwind.sp_restored && unwind.fp_reg == 12 3202 && (range & 0x3000) == 0x1000) 3203 { 3204 unwind.opcode_count--; 3205 unwind.sp_restored = 0; 3206 range = (range | 0x2000) & ~0x1000; 3207 unwind.pending_offset = 0; 3208 } 3209 3210 /* Pop r4-r15. */ 3211 if (range & 0xfff0) 3212 { 3213 /* See if we can use the short opcodes. These pop a block of up to 8 3214 registers starting with r4, plus maybe r14. */ 3215 for (n = 0; n < 8; n++) 3216 { 3217 /* Break at the first non-saved register. */ 3218 if ((range & (1 << (n + 4))) == 0) 3219 break; 3220 } 3221 /* See if there are any other bits set. */ 3222 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) 3223 { 3224 /* Use the long form. */ 3225 op = 0x8000 | ((range >> 4) & 0xfff); 3226 add_unwind_opcode (op, 2); 3227 } 3228 else 3229 { 3230 /* Use the short form. */ 3231 if (range & 0x4000) 3232 op = 0xa8; /* Pop r14. */ 3233 else 3234 op = 0xa0; /* Do not pop r14. */ 3235 op |= (n - 1); 3236 add_unwind_opcode (op, 1); 3237 } 3238 } 3239 3240 /* Pop r0-r3. */ 3241 if (range & 0xf) 3242 { 3243 op = 0xb100 | (range & 0xf); 3244 add_unwind_opcode (op, 2); 3245 } 3246 3247 /* Record the number of bytes pushed. */ 3248 for (n = 0; n < 16; n++) 3249 { 3250 if (range & (1 << n)) 3251 unwind.frame_size += 4; 3252 } 3253} 3254 3255 3256/* Parse a directive saving FPA registers. */ 3257 3258static void 3259s_arm_unwind_save_fpa (int reg) 3260{ 3261 expressionS exp; 3262 int num_regs; 3263 valueT op; 3264 3265 /* Get Number of registers to transfer. */ 3266 if (skip_past_comma (&input_line_pointer) != FAIL) 3267 expression (&exp); 3268 else 3269 exp.X_op = O_illegal; 3270 3271 if (exp.X_op != O_constant) 3272 { 3273 as_bad (_("expected , <constant>")); 3274 ignore_rest_of_line (); 3275 return; 3276 } 3277 3278 num_regs = exp.X_add_number; 3279 3280 if (num_regs < 1 || num_regs > 4) 3281 { 3282 as_bad (_("number of registers must be in the range [1:4]")); 3283 ignore_rest_of_line (); 3284 return; 3285 } 3286 3287 demand_empty_rest_of_line (); 3288 3289 if (reg == 4) 3290 { 3291 /* Short form. */ 3292 op = 0xb4 | (num_regs - 1); 3293 add_unwind_opcode (op, 1); 3294 } 3295 else 3296 { 3297 /* Long form. */ 3298 op = 0xc800 | (reg << 4) | (num_regs - 1); 3299 add_unwind_opcode (op, 2); 3300 } 3301 unwind.frame_size += num_regs * 12; 3302} 3303 3304 3305/* Parse a directive saving VFP registers for ARMv6 and above. */ 3306 3307static void 3308s_arm_unwind_save_vfp_armv6 (void) 3309{ 3310 int count; 3311 unsigned int start; 3312 valueT op; 3313 int num_vfpv3_regs = 0; 3314 int num_regs_below_16; 3315 3316 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); 3317 if (count == FAIL) 3318 { 3319 as_bad (_("expected register list")); 3320 ignore_rest_of_line (); 3321 return; 3322 } 3323 3324 demand_empty_rest_of_line (); 3325 3326 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather 3327 than FSTMX/FLDMX-style ones). */ 3328 3329 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ 3330 if (start >= 16) 3331 num_vfpv3_regs = count; 3332 else if (start + count > 16) 3333 num_vfpv3_regs = start + count - 16; 3334 3335 if (num_vfpv3_regs > 0) 3336 { 3337 int start_offset = start > 16 ? start - 16 : 0; 3338 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); 3339 add_unwind_opcode (op, 2); 3340 } 3341 3342 /* Generate opcode for registers numbered in the range 0 .. 15. */ 3343 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; 3344 assert (num_regs_below_16 + num_vfpv3_regs == count); 3345 if (num_regs_below_16 > 0) 3346 { 3347 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); 3348 add_unwind_opcode (op, 2); 3349 } 3350 3351 unwind.frame_size += count * 8; 3352} 3353 3354 3355/* Parse a directive saving VFP registers for pre-ARMv6. */ 3356 3357static void 3358s_arm_unwind_save_vfp (void) 3359{ 3360 int count; 3361 unsigned int reg; 3362 valueT op; 3363 3364 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); 3365 if (count == FAIL) 3366 { 3367 as_bad (_("expected register list")); 3368 ignore_rest_of_line (); 3369 return; 3370 } 3371 3372 demand_empty_rest_of_line (); 3373 3374 if (reg == 8) 3375 { 3376 /* Short form. */ 3377 op = 0xb8 | (count - 1); 3378 add_unwind_opcode (op, 1); 3379 } 3380 else 3381 { 3382 /* Long form. */ 3383 op = 0xb300 | (reg << 4) | (count - 1); 3384 add_unwind_opcode (op, 2); 3385 } 3386 unwind.frame_size += count * 8 + 4; 3387} 3388 3389 3390/* Parse a directive saving iWMMXt data registers. */ 3391 3392static void 3393s_arm_unwind_save_mmxwr (void) 3394{ 3395 int reg; 3396 int hi_reg; 3397 int i; 3398 unsigned mask = 0; 3399 valueT op; 3400 3401 if (*input_line_pointer == '{') 3402 input_line_pointer++; 3403 3404 do 3405 { 3406 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); 3407 3408 if (reg == FAIL) 3409 { 3410 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); 3411 goto error; 3412 } 3413 3414 if (mask >> reg) 3415 as_tsktsk (_("register list not in ascending order")); 3416 mask |= 1 << reg; 3417 3418 if (*input_line_pointer == '-') 3419 { 3420 input_line_pointer++; 3421 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); 3422 if (hi_reg == FAIL) 3423 { 3424 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); 3425 goto error; 3426 } 3427 else if (reg >= hi_reg) 3428 { 3429 as_bad (_("bad register range")); 3430 goto error; 3431 } 3432 for (; reg < hi_reg; reg++) 3433 mask |= 1 << reg; 3434 } 3435 } 3436 while (skip_past_comma (&input_line_pointer) != FAIL); 3437 3438 if (*input_line_pointer == '}') 3439 input_line_pointer++; 3440 3441 demand_empty_rest_of_line (); 3442 3443 /* Generate any deferred opcodes because we're going to be looking at 3444 the list. */ 3445 flush_pending_unwind (); 3446 3447 for (i = 0; i < 16; i++) 3448 { 3449 if (mask & (1 << i)) 3450 unwind.frame_size += 8; 3451 } 3452 3453 /* Attempt to combine with a previous opcode. We do this because gcc 3454 likes to output separate unwind directives for a single block of 3455 registers. */ 3456 if (unwind.opcode_count > 0) 3457 { 3458 i = unwind.opcodes[unwind.opcode_count - 1]; 3459 if ((i & 0xf8) == 0xc0) 3460 { 3461 i &= 7; 3462 /* Only merge if the blocks are contiguous. */ 3463 if (i < 6) 3464 { 3465 if ((mask & 0xfe00) == (1 << 9)) 3466 { 3467 mask |= ((1 << (i + 11)) - 1) & 0xfc00; 3468 unwind.opcode_count--; 3469 } 3470 } 3471 else if (i == 6 && unwind.opcode_count >= 2) 3472 { 3473 i = unwind.opcodes[unwind.opcode_count - 2]; 3474 reg = i >> 4; 3475 i &= 0xf; 3476 3477 op = 0xffff << (reg - 1); 3478 if (reg > 0 3479 && ((mask & op) == (1u << (reg - 1)))) 3480 { 3481 op = (1 << (reg + i + 1)) - 1; 3482 op &= ~((1 << reg) - 1); 3483 mask |= op; 3484 unwind.opcode_count -= 2; 3485 } 3486 } 3487 } 3488 } 3489 3490 hi_reg = 15; 3491 /* We want to generate opcodes in the order the registers have been 3492 saved, ie. descending order. */ 3493 for (reg = 15; reg >= -1; reg--) 3494 { 3495 /* Save registers in blocks. */ 3496 if (reg < 0 3497 || !(mask & (1 << reg))) 3498 { 3499 /* We found an unsaved reg. Generate opcodes to save the 3500 preceeding block. */ 3501 if (reg != hi_reg) 3502 { 3503 if (reg == 9) 3504 { 3505 /* Short form. */ 3506 op = 0xc0 | (hi_reg - 10); 3507 add_unwind_opcode (op, 1); 3508 } 3509 else 3510 { 3511 /* Long form. */ 3512 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); 3513 add_unwind_opcode (op, 2); 3514 } 3515 } 3516 hi_reg = reg - 1; 3517 } 3518 } 3519 3520 return; 3521error: 3522 ignore_rest_of_line (); 3523} 3524 3525static void 3526s_arm_unwind_save_mmxwcg (void) 3527{ 3528 int reg; 3529 int hi_reg; 3530 unsigned mask = 0; 3531 valueT op; 3532 3533 if (*input_line_pointer == '{') 3534 input_line_pointer++; 3535 3536 do 3537 { 3538 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); 3539 3540 if (reg == FAIL) 3541 { 3542 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); 3543 goto error; 3544 } 3545 3546 reg -= 8; 3547 if (mask >> reg) 3548 as_tsktsk (_("register list not in ascending order")); 3549 mask |= 1 << reg; 3550 3551 if (*input_line_pointer == '-') 3552 { 3553 input_line_pointer++; 3554 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); 3555 if (hi_reg == FAIL) 3556 { 3557 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); 3558 goto error; 3559 } 3560 else if (reg >= hi_reg) 3561 { 3562 as_bad (_("bad register range")); 3563 goto error; 3564 } 3565 for (; reg < hi_reg; reg++) 3566 mask |= 1 << reg; 3567 } 3568 } 3569 while (skip_past_comma (&input_line_pointer) != FAIL); 3570 3571 if (*input_line_pointer == '}') 3572 input_line_pointer++; 3573 3574 demand_empty_rest_of_line (); 3575 3576 /* Generate any deferred opcodes because we're going to be looking at 3577 the list. */ 3578 flush_pending_unwind (); 3579 3580 for (reg = 0; reg < 16; reg++) 3581 { 3582 if (mask & (1 << reg)) 3583 unwind.frame_size += 4; 3584 } 3585 op = 0xc700 | mask; 3586 add_unwind_opcode (op, 2); 3587 return; 3588error: 3589 ignore_rest_of_line (); 3590} 3591 3592 3593/* Parse an unwind_save directive. 3594 If the argument is non-zero, this is a .vsave directive. */ 3595 3596static void 3597s_arm_unwind_save (int arch_v6) 3598{ 3599 char *peek; 3600 struct reg_entry *reg; 3601 bfd_boolean had_brace = FALSE; 3602 3603 /* Figure out what sort of save we have. */ 3604 peek = input_line_pointer; 3605 3606 if (*peek == '{') 3607 { 3608 had_brace = TRUE; 3609 peek++; 3610 } 3611 3612 reg = arm_reg_parse_multi (&peek); 3613 3614 if (!reg) 3615 { 3616 as_bad (_("register expected")); 3617 ignore_rest_of_line (); 3618 return; 3619 } 3620 3621 switch (reg->type) 3622 { 3623 case REG_TYPE_FN: 3624 if (had_brace) 3625 { 3626 as_bad (_("FPA .unwind_save does not take a register list")); 3627 ignore_rest_of_line (); 3628 return; 3629 } 3630 s_arm_unwind_save_fpa (reg->number); 3631 return; 3632 3633 case REG_TYPE_RN: s_arm_unwind_save_core (); return; 3634 case REG_TYPE_VFD: 3635 if (arch_v6) 3636 s_arm_unwind_save_vfp_armv6 (); 3637 else 3638 s_arm_unwind_save_vfp (); 3639 return; 3640 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; 3641 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; 3642 3643 default: 3644 as_bad (_(".unwind_save does not support this kind of register")); 3645 ignore_rest_of_line (); 3646 } 3647} 3648 3649 3650/* Parse an unwind_movsp directive. */ 3651 3652static void 3653s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) 3654{ 3655 int reg; 3656 valueT op; 3657 int offset; 3658 3659 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 3660 if (reg == FAIL) 3661 { 3662 as_bad (_(reg_expected_msgs[REG_TYPE_RN])); 3663 ignore_rest_of_line (); 3664 return; 3665 } 3666 3667 /* Optional constant. */ 3668 if (skip_past_comma (&input_line_pointer) != FAIL) 3669 { 3670 if (immediate_for_directive (&offset) == FAIL) 3671 return; 3672 } 3673 else 3674 offset = 0; 3675 3676 demand_empty_rest_of_line (); 3677 3678 if (reg == REG_SP || reg == REG_PC) 3679 { 3680 as_bad (_("SP and PC not permitted in .unwind_movsp directive")); 3681 return; 3682 } 3683 3684 if (unwind.fp_reg != REG_SP) 3685 as_bad (_("unexpected .unwind_movsp directive")); 3686 3687 /* Generate opcode to restore the value. */ 3688 op = 0x90 | reg; 3689 add_unwind_opcode (op, 1); 3690 3691 /* Record the information for later. */ 3692 unwind.fp_reg = reg; 3693 unwind.fp_offset = unwind.frame_size - offset; 3694 unwind.sp_restored = 1; 3695} 3696 3697/* Parse an unwind_pad directive. */ 3698 3699static void 3700s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) 3701{ 3702 int offset; 3703 3704 if (immediate_for_directive (&offset) == FAIL) 3705 return; 3706 3707 if (offset & 3) 3708 { 3709 as_bad (_("stack increment must be multiple of 4")); 3710 ignore_rest_of_line (); 3711 return; 3712 } 3713 3714 /* Don't generate any opcodes, just record the details for later. */ 3715 unwind.frame_size += offset; 3716 unwind.pending_offset += offset; 3717 3718 demand_empty_rest_of_line (); 3719} 3720 3721/* Parse an unwind_setfp directive. */ 3722 3723static void 3724s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) 3725{ 3726 int sp_reg; 3727 int fp_reg; 3728 int offset; 3729 3730 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 3731 if (skip_past_comma (&input_line_pointer) == FAIL) 3732 sp_reg = FAIL; 3733 else 3734 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 3735 3736 if (fp_reg == FAIL || sp_reg == FAIL) 3737 { 3738 as_bad (_("expected <reg>, <reg>")); 3739 ignore_rest_of_line (); 3740 return; 3741 } 3742 3743 /* Optional constant. */ 3744 if (skip_past_comma (&input_line_pointer) != FAIL) 3745 { 3746 if (immediate_for_directive (&offset) == FAIL) 3747 return; 3748 } 3749 else 3750 offset = 0; 3751 3752 demand_empty_rest_of_line (); 3753 3754 if (sp_reg != 13 && sp_reg != unwind.fp_reg) 3755 { 3756 as_bad (_("register must be either sp or set by a previous" 3757 "unwind_movsp directive")); 3758 return; 3759 } 3760 3761 /* Don't generate any opcodes, just record the information for later. */ 3762 unwind.fp_reg = fp_reg; 3763 unwind.fp_used = 1; 3764 if (sp_reg == 13) 3765 unwind.fp_offset = unwind.frame_size - offset; 3766 else 3767 unwind.fp_offset -= offset; 3768} 3769 3770/* Parse an unwind_raw directive. */ 3771 3772static void 3773s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) 3774{ 3775 expressionS exp; 3776 /* This is an arbitrary limit. */ 3777 unsigned char op[16]; 3778 int count; 3779 3780 expression (&exp); 3781 if (exp.X_op == O_constant 3782 && skip_past_comma (&input_line_pointer) != FAIL) 3783 { 3784 unwind.frame_size += exp.X_add_number; 3785 expression (&exp); 3786 } 3787 else 3788 exp.X_op = O_illegal; 3789 3790 if (exp.X_op != O_constant) 3791 { 3792 as_bad (_("expected <offset>, <opcode>")); 3793 ignore_rest_of_line (); 3794 return; 3795 } 3796 3797 count = 0; 3798 3799 /* Parse the opcode. */ 3800 for (;;) 3801 { 3802 if (count >= 16) 3803 { 3804 as_bad (_("unwind opcode too long")); 3805 ignore_rest_of_line (); 3806 } 3807 if (exp.X_op != O_constant || exp.X_add_number & ~0xff) 3808 { 3809 as_bad (_("invalid unwind opcode")); 3810 ignore_rest_of_line (); 3811 return; 3812 } 3813 op[count++] = exp.X_add_number; 3814 3815 /* Parse the next byte. */ 3816 if (skip_past_comma (&input_line_pointer) == FAIL) 3817 break; 3818 3819 expression (&exp); 3820 } 3821 3822 /* Add the opcode bytes in reverse order. */ 3823 while (count--) 3824 add_unwind_opcode (op[count], 1); 3825 3826 demand_empty_rest_of_line (); 3827} 3828 3829 3830/* Parse a .eabi_attribute directive. */ 3831 3832static void 3833s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) 3834{ 3835 s_vendor_attribute (OBJ_ATTR_PROC); 3836} 3837#endif /* OBJ_ELF */ 3838 3839static void s_arm_arch (int); 3840static void s_arm_object_arch (int); 3841static void s_arm_cpu (int); 3842static void s_arm_fpu (int); 3843static void s_arm_arch_extension (int); 3844 3845#ifdef TE_PE 3846 3847static void 3848pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) 3849{ 3850 expressionS exp; 3851 3852 do 3853 { 3854 expression (&exp); 3855 if (exp.X_op == O_symbol) 3856 exp.X_op = O_secrel; 3857 3858 emit_expr (&exp, 4); 3859 } 3860 while (*input_line_pointer++ == ','); 3861 3862 input_line_pointer--; 3863 demand_empty_rest_of_line (); 3864} 3865#endif /* TE_PE */ 3866 3867/* This table describes all the machine specific pseudo-ops the assembler 3868 has to support. The fields are: 3869 pseudo-op name without dot 3870 function to call to execute this pseudo-op 3871 Integer arg to pass to the function. */ 3872 3873const pseudo_typeS md_pseudo_table[] = 3874{ 3875 /* Never called because '.req' does not start a line. */ 3876 { "req", s_req, 0 }, 3877 /* Following two are likewise never called. */ 3878 { "dn", s_dn, 0 }, 3879 { "qn", s_qn, 0 }, 3880 { "unreq", s_unreq, 0 }, 3881 { "bss", s_bss, 0 }, 3882 { "align", s_align, 0 }, 3883 { "arm", s_arm, 0 }, 3884 { "thumb", s_thumb, 0 }, 3885 { "code", s_code, 0 }, 3886 { "force_thumb", s_force_thumb, 0 }, 3887 { "thumb_func", s_thumb_func, 0 }, 3888 { "thumb_set", s_thumb_set, 0 }, 3889 { "even", s_even, 0 }, 3890 { "ltorg", s_ltorg, 0 }, 3891 { "pool", s_ltorg, 0 }, 3892 { "syntax", s_syntax, 0 }, 3893 { "cpu", s_arm_cpu, 0 }, 3894 { "arch", s_arm_arch, 0 }, 3895 { "object_arch", s_arm_object_arch, 0 }, 3896 { "fpu", s_arm_fpu, 0 }, 3897 { "arch_extension", s_arm_arch_extension, 0 }, 3898#ifdef OBJ_ELF 3899 { "word", s_arm_elf_cons, 4 }, 3900 { "long", s_arm_elf_cons, 4 }, 3901 { "rel31", s_arm_rel31, 0 }, 3902 { "fnstart", s_arm_unwind_fnstart, 0 }, 3903 { "fnend", s_arm_unwind_fnend, 0 }, 3904 { "cantunwind", s_arm_unwind_cantunwind, 0 }, 3905 { "personality", s_arm_unwind_personality, 0 }, 3906 { "personalityindex", s_arm_unwind_personalityindex, 0 }, 3907 { "handlerdata", s_arm_unwind_handlerdata, 0 }, 3908 { "save", s_arm_unwind_save, 0 }, 3909 { "vsave", s_arm_unwind_save, 1 }, 3910 { "movsp", s_arm_unwind_movsp, 0 }, 3911 { "pad", s_arm_unwind_pad, 0 }, 3912 { "setfp", s_arm_unwind_setfp, 0 }, 3913 { "unwind_raw", s_arm_unwind_raw, 0 }, 3914 { "eabi_attribute", s_arm_eabi_attribute, 0 }, 3915#else 3916 { "word", cons, 4}, 3917 3918 /* These are used for dwarf. */ 3919 {"2byte", cons, 2}, 3920 {"4byte", cons, 4}, 3921 {"8byte", cons, 8}, 3922 /* These are used for dwarf2. */ 3923 { "file", (void (*) (int)) dwarf2_directive_file, 0 }, 3924 { "loc", dwarf2_directive_loc, 0 }, 3925 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, 3926#endif 3927 { "extend", float_cons, 'x' }, 3928 { "ldouble", float_cons, 'x' }, 3929 { "packed", float_cons, 'p' }, 3930#ifdef TE_PE 3931 {"secrel32", pe_directive_secrel, 0}, 3932#endif 3933 { 0, 0, 0 } 3934}; 3935 3936/* Parser functions used exclusively in instruction operands. */ 3937 3938/* Generic immediate-value read function for use in insn parsing. 3939 STR points to the beginning of the immediate (the leading #); 3940 VAL receives the value; if the value is outside [MIN, MAX] 3941 issue an error. PREFIX_OPT is true if the immediate prefix is 3942 optional. */ 3943 3944static int 3945parse_immediate (char **str, int *val, int min, int max, 3946 bfd_boolean prefix_opt) 3947{ 3948 expressionS exp; 3949 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); 3950 if (exp.X_op != O_constant) 3951 { 3952 inst.error = _("constant expression required"); 3953 return FAIL; 3954 } 3955 3956 if (exp.X_add_number < min || exp.X_add_number > max) 3957 { 3958 inst.error = _("immediate value out of range"); 3959 return FAIL; 3960 } 3961 3962 *val = exp.X_add_number; 3963 return SUCCESS; 3964} 3965 3966/* Less-generic immediate-value read function with the possibility of loading a 3967 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate 3968 instructions. Puts the result directly in inst.operands[i]. */ 3969 3970static int 3971parse_big_immediate (char **str, int i) 3972{ 3973 expressionS exp; 3974 char *ptr = *str; 3975 3976 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG); 3977 3978 if (exp.X_op == O_constant) 3979 { 3980 inst.operands[i].imm = exp.X_add_number & 0xffffffff; 3981 /* If we're on a 64-bit host, then a 64-bit number can be returned using 3982 O_constant. We have to be careful not to break compilation for 3983 32-bit X_add_number, though. */ 3984 if ((exp.X_add_number & ~0xffffffffl) != 0) 3985 { 3986 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */ 3987 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff; 3988 inst.operands[i].regisimm = 1; 3989 } 3990 } 3991 else if (exp.X_op == O_big 3992 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32 3993 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64) 3994 { 3995 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; 3996 /* Bignums have their least significant bits in 3997 generic_bignum[0]. Make sure we put 32 bits in imm and 3998 32 bits in reg, in a (hopefully) portable way. */ 3999 assert (parts != 0); 4000 inst.operands[i].imm = 0; 4001 for (j = 0; j < parts; j++, idx++) 4002 inst.operands[i].imm |= generic_bignum[idx] 4003 << (LITTLENUM_NUMBER_OF_BITS * j); 4004 inst.operands[i].reg = 0; 4005 for (j = 0; j < parts; j++, idx++) 4006 inst.operands[i].reg |= generic_bignum[idx] 4007 << (LITTLENUM_NUMBER_OF_BITS * j); 4008 inst.operands[i].regisimm = 1; 4009 } 4010 else 4011 return FAIL; 4012 4013 *str = ptr; 4014 4015 return SUCCESS; 4016} 4017 4018/* Returns the pseudo-register number of an FPA immediate constant, 4019 or FAIL if there isn't a valid constant here. */ 4020 4021static int 4022parse_fpa_immediate (char ** str) 4023{ 4024 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 4025 char * save_in; 4026 expressionS exp; 4027 int i; 4028 int j; 4029 4030 /* First try and match exact strings, this is to guarantee 4031 that some formats will work even for cross assembly. */ 4032 4033 for (i = 0; fp_const[i]; i++) 4034 { 4035 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) 4036 { 4037 char *start = *str; 4038 4039 *str += strlen (fp_const[i]); 4040 if (is_end_of_line[(unsigned char) **str]) 4041 return i + 8; 4042 *str = start; 4043 } 4044 } 4045 4046 /* Just because we didn't get a match doesn't mean that the constant 4047 isn't valid, just that it is in a format that we don't 4048 automatically recognize. Try parsing it with the standard 4049 expression routines. */ 4050 4051 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); 4052 4053 /* Look for a raw floating point number. */ 4054 if ((save_in = atof_ieee (*str, 'x', words)) != NULL 4055 && is_end_of_line[(unsigned char) *save_in]) 4056 { 4057 for (i = 0; i < NUM_FLOAT_VALS; i++) 4058 { 4059 for (j = 0; j < MAX_LITTLENUMS; j++) 4060 { 4061 if (words[j] != fp_values[i][j]) 4062 break; 4063 } 4064 4065 if (j == MAX_LITTLENUMS) 4066 { 4067 *str = save_in; 4068 return i + 8; 4069 } 4070 } 4071 } 4072 4073 /* Try and parse a more complex expression, this will probably fail 4074 unless the code uses a floating point prefix (eg "0f"). */ 4075 save_in = input_line_pointer; 4076 input_line_pointer = *str; 4077 if (expression (&exp) == absolute_section 4078 && exp.X_op == O_big 4079 && exp.X_add_number < 0) 4080 { 4081 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. 4082 Ditto for 15. */ 4083 if (gen_to_words (words, 5, (long) 15) == 0) 4084 { 4085 for (i = 0; i < NUM_FLOAT_VALS; i++) 4086 { 4087 for (j = 0; j < MAX_LITTLENUMS; j++) 4088 { 4089 if (words[j] != fp_values[i][j]) 4090 break; 4091 } 4092 4093 if (j == MAX_LITTLENUMS) 4094 { 4095 *str = input_line_pointer; 4096 input_line_pointer = save_in; 4097 return i + 8; 4098 } 4099 } 4100 } 4101 } 4102 4103 *str = input_line_pointer; 4104 input_line_pointer = save_in; 4105 inst.error = _("invalid FPA immediate expression"); 4106 return FAIL; 4107} 4108 4109/* Returns 1 if a number has "quarter-precision" float format 4110 0baBbbbbbc defgh000 00000000 00000000. */ 4111 4112static int 4113is_quarter_float (unsigned imm) 4114{ 4115 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; 4116 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; 4117} 4118 4119/* Parse an 8-bit "quarter-precision" floating point number of the form: 4120 0baBbbbbbc defgh000 00000000 00000000. 4121 The zero and minus-zero cases need special handling, since they can't be 4122 encoded in the "quarter-precision" float format, but can nonetheless be 4123 loaded as integer constants. */ 4124 4125static unsigned 4126parse_qfloat_immediate (char **ccp, int *immed) 4127{ 4128 char *str = *ccp; 4129 char *fpnum; 4130 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 4131 int found_fpchar = 0; 4132 4133 skip_past_char (&str, '#'); 4134 4135 /* We must not accidentally parse an integer as a floating-point number. Make 4136 sure that the value we parse is not an integer by checking for special 4137 characters '.' or 'e'. 4138 FIXME: This is a horrible hack, but doing better is tricky because type 4139 information isn't in a very usable state at parse time. */ 4140 fpnum = str; 4141 skip_whitespace (fpnum); 4142 4143 if (strncmp (fpnum, "0x", 2) == 0) 4144 return FAIL; 4145 else 4146 { 4147 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) 4148 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') 4149 { 4150 found_fpchar = 1; 4151 break; 4152 } 4153 4154 if (!found_fpchar) 4155 return FAIL; 4156 } 4157 4158 if ((str = atof_ieee (str, 's', words)) != NULL) 4159 { 4160 unsigned fpword = 0; 4161 int i; 4162 4163 /* Our FP word must be 32 bits (single-precision FP). */ 4164 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) 4165 { 4166 fpword <<= LITTLENUM_NUMBER_OF_BITS; 4167 fpword |= words[i]; 4168 } 4169 4170 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) 4171 *immed = fpword; 4172 else 4173 return FAIL; 4174 4175 *ccp = str; 4176 4177 return SUCCESS; 4178 } 4179 4180 return FAIL; 4181} 4182 4183/* Shift operands. */ 4184enum shift_kind 4185{ 4186 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX 4187}; 4188 4189struct asm_shift_name 4190{ 4191 const char *name; 4192 enum shift_kind kind; 4193}; 4194 4195/* Third argument to parse_shift. */ 4196enum parse_shift_mode 4197{ 4198 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ 4199 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ 4200 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ 4201 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ 4202 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ 4203}; 4204 4205/* Parse a <shift> specifier on an ARM data processing instruction. 4206 This has three forms: 4207 4208 (LSL|LSR|ASL|ASR|ROR) Rs 4209 (LSL|LSR|ASL|ASR|ROR) #imm 4210 RRX 4211 4212 Note that ASL is assimilated to LSL in the instruction encoding, and 4213 RRX to ROR #0 (which cannot be written as such). */ 4214 4215static int 4216parse_shift (char **str, int i, enum parse_shift_mode mode) 4217{ 4218 const struct asm_shift_name *shift_name; 4219 enum shift_kind shift; 4220 char *s = *str; 4221 char *p = s; 4222 int reg; 4223 4224 for (p = *str; ISALPHA (*p); p++) 4225 ; 4226 4227 if (p == *str) 4228 { 4229 inst.error = _("shift expression expected"); 4230 return FAIL; 4231 } 4232 4233 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str); 4234 4235 if (shift_name == NULL) 4236 { 4237 inst.error = _("shift expression expected"); 4238 return FAIL; 4239 } 4240 4241 shift = shift_name->kind; 4242 4243 switch (mode) 4244 { 4245 case NO_SHIFT_RESTRICT: 4246 case SHIFT_IMMEDIATE: break; 4247 4248 case SHIFT_LSL_OR_ASR_IMMEDIATE: 4249 if (shift != SHIFT_LSL && shift != SHIFT_ASR) 4250 { 4251 inst.error = _("'LSL' or 'ASR' required"); 4252 return FAIL; 4253 } 4254 break; 4255 4256 case SHIFT_LSL_IMMEDIATE: 4257 if (shift != SHIFT_LSL) 4258 { 4259 inst.error = _("'LSL' required"); 4260 return FAIL; 4261 } 4262 break; 4263 4264 case SHIFT_ASR_IMMEDIATE: 4265 if (shift != SHIFT_ASR) 4266 { 4267 inst.error = _("'ASR' required"); 4268 return FAIL; 4269 } 4270 break; 4271 4272 default: abort (); 4273 } 4274 4275 if (shift != SHIFT_RRX) 4276 { 4277 /* Whitespace can appear here if the next thing is a bare digit. */ 4278 skip_whitespace (p); 4279 4280 if (mode == NO_SHIFT_RESTRICT 4281 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 4282 { 4283 inst.operands[i].imm = reg; 4284 inst.operands[i].immisreg = 1; 4285 } 4286 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 4287 return FAIL; 4288 } 4289 inst.operands[i].shift_kind = shift; 4290 inst.operands[i].shifted = 1; 4291 *str = p; 4292 return SUCCESS; 4293} 4294 4295/* Parse a <shifter_operand> for an ARM data processing instruction: 4296 4297 #<immediate> 4298 #<immediate>, <rotate> 4299 <Rm> 4300 <Rm>, <shift> 4301 4302 where <shift> is defined by parse_shift above, and <rotate> is a 4303 multiple of 2 between 0 and 30. Validation of immediate operands 4304 is deferred to md_apply_fix. */ 4305 4306static int 4307parse_shifter_operand (char **str, int i) 4308{ 4309 int value; 4310 expressionS expr; 4311 4312 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) 4313 { 4314 inst.operands[i].reg = value; 4315 inst.operands[i].isreg = 1; 4316 4317 /* parse_shift will override this if appropriate */ 4318 inst.reloc.exp.X_op = O_constant; 4319 inst.reloc.exp.X_add_number = 0; 4320 4321 if (skip_past_comma (str) == FAIL) 4322 return SUCCESS; 4323 4324 /* Shift operation on register. */ 4325 return parse_shift (str, i, NO_SHIFT_RESTRICT); 4326 } 4327 4328 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) 4329 return FAIL; 4330 4331 if (skip_past_comma (str) == SUCCESS) 4332 { 4333 /* #x, y -- ie explicit rotation by Y. */ 4334 if (my_get_expression (&expr, str, GE_NO_PREFIX)) 4335 return FAIL; 4336 4337 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant) 4338 { 4339 inst.error = _("constant expression expected"); 4340 return FAIL; 4341 } 4342 4343 value = expr.X_add_number; 4344 if (value < 0 || value > 30 || value % 2 != 0) 4345 { 4346 inst.error = _("invalid rotation"); 4347 return FAIL; 4348 } 4349 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) 4350 { 4351 inst.error = _("invalid constant"); 4352 return FAIL; 4353 } 4354 4355 /* Convert to decoded value. md_apply_fix will put it back. */ 4356 inst.reloc.exp.X_add_number 4357 = (((inst.reloc.exp.X_add_number << (32 - value)) 4358 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff); 4359 } 4360 4361 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 4362 inst.reloc.pc_rel = 0; 4363 return SUCCESS; 4364} 4365 4366/* Group relocation information. Each entry in the table contains the 4367 textual name of the relocation as may appear in assembler source 4368 and must end with a colon. 4369 Along with this textual name are the relocation codes to be used if 4370 the corresponding instruction is an ALU instruction (ADD or SUB only), 4371 an LDR, an LDRS, or an LDC. */ 4372 4373struct group_reloc_table_entry 4374{ 4375 const char *name; 4376 int alu_code; 4377 int ldr_code; 4378 int ldrs_code; 4379 int ldc_code; 4380}; 4381 4382typedef enum 4383{ 4384 /* Varieties of non-ALU group relocation. */ 4385 4386 GROUP_LDR, 4387 GROUP_LDRS, 4388 GROUP_LDC 4389} group_reloc_type; 4390 4391static struct group_reloc_table_entry group_reloc_table[] = 4392 { /* Program counter relative: */ 4393 { "pc_g0_nc", 4394 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ 4395 0, /* LDR */ 4396 0, /* LDRS */ 4397 0 }, /* LDC */ 4398 { "pc_g0", 4399 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ 4400 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ 4401 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ 4402 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ 4403 { "pc_g1_nc", 4404 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ 4405 0, /* LDR */ 4406 0, /* LDRS */ 4407 0 }, /* LDC */ 4408 { "pc_g1", 4409 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ 4410 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ 4411 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ 4412 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ 4413 { "pc_g2", 4414 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ 4415 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ 4416 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ 4417 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ 4418 /* Section base relative */ 4419 { "sb_g0_nc", 4420 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ 4421 0, /* LDR */ 4422 0, /* LDRS */ 4423 0 }, /* LDC */ 4424 { "sb_g0", 4425 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ 4426 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ 4427 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ 4428 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ 4429 { "sb_g1_nc", 4430 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ 4431 0, /* LDR */ 4432 0, /* LDRS */ 4433 0 }, /* LDC */ 4434 { "sb_g1", 4435 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ 4436 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ 4437 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ 4438 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ 4439 { "sb_g2", 4440 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ 4441 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ 4442 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ 4443 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ 4444 4445/* Given the address of a pointer pointing to the textual name of a group 4446 relocation as may appear in assembler source, attempt to find its details 4447 in group_reloc_table. The pointer will be updated to the character after 4448 the trailing colon. On failure, FAIL will be returned; SUCCESS 4449 otherwise. On success, *entry will be updated to point at the relevant 4450 group_reloc_table entry. */ 4451 4452static int 4453find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) 4454{ 4455 unsigned int i; 4456 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) 4457 { 4458 int length = strlen (group_reloc_table[i].name); 4459 4460 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 && 4461 (*str)[length] == ':') 4462 { 4463 *out = &group_reloc_table[i]; 4464 *str += (length + 1); 4465 return SUCCESS; 4466 } 4467 } 4468 4469 return FAIL; 4470} 4471 4472/* Parse a <shifter_operand> for an ARM data processing instruction 4473 (as for parse_shifter_operand) where group relocations are allowed: 4474 4475 #<immediate> 4476 #<immediate>, <rotate> 4477 #:<group_reloc>:<expression> 4478 <Rm> 4479 <Rm>, <shift> 4480 4481 where <group_reloc> is one of the strings defined in group_reloc_table. 4482 The hashes are optional. 4483 4484 Everything else is as for parse_shifter_operand. */ 4485 4486static parse_operand_result 4487parse_shifter_operand_group_reloc (char **str, int i) 4488{ 4489 /* Determine if we have the sequence of characters #: or just : 4490 coming next. If we do, then we check for a group relocation. 4491 If we don't, punt the whole lot to parse_shifter_operand. */ 4492 4493 if (((*str)[0] == '#' && (*str)[1] == ':') 4494 || (*str)[0] == ':') 4495 { 4496 struct group_reloc_table_entry *entry; 4497 4498 if ((*str)[0] == '#') 4499 (*str) += 2; 4500 else 4501 (*str)++; 4502 4503 /* Try to parse a group relocation. Anything else is an error. */ 4504 if (find_group_reloc_table_entry (str, &entry) == FAIL) 4505 { 4506 inst.error = _("unknown group relocation"); 4507 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4508 } 4509 4510 /* We now have the group relocation table entry corresponding to 4511 the name in the assembler source. Next, we parse the expression. */ 4512 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) 4513 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4514 4515 /* Record the relocation type (always the ALU variant here). */ 4516 inst.reloc.type = entry->alu_code; 4517 assert (inst.reloc.type != 0); 4518 4519 return PARSE_OPERAND_SUCCESS; 4520 } 4521 else 4522 return parse_shifter_operand (str, i) == SUCCESS 4523 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; 4524 4525 /* Never reached. */ 4526} 4527 4528/* Parse all forms of an ARM address expression. Information is written 4529 to inst.operands[i] and/or inst.reloc. 4530 4531 Preindexed addressing (.preind=1): 4532 4533 [Rn, #offset] .reg=Rn .reloc.exp=offset 4534 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4535 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4536 .shift_kind=shift .reloc.exp=shift_imm 4537 4538 These three may have a trailing ! which causes .writeback to be set also. 4539 4540 Postindexed addressing (.postind=1, .writeback=1): 4541 4542 [Rn], #offset .reg=Rn .reloc.exp=offset 4543 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4544 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4545 .shift_kind=shift .reloc.exp=shift_imm 4546 4547 Unindexed addressing (.preind=0, .postind=0): 4548 4549 [Rn], {option} .reg=Rn .imm=option .immisreg=0 4550 4551 Other: 4552 4553 [Rn]{!} shorthand for [Rn,#0]{!} 4554 =immediate .isreg=0 .reloc.exp=immediate 4555 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label 4556 4557 It is the caller's responsibility to check for addressing modes not 4558 supported by the instruction, and to set inst.reloc.type. */ 4559 4560static parse_operand_result 4561parse_address_main (char **str, int i, int group_relocations, 4562 group_reloc_type group_type) 4563{ 4564 char *p = *str; 4565 int reg; 4566 4567 if (skip_past_char (&p, '[') == FAIL) 4568 { 4569 if (skip_past_char (&p, '=') == FAIL) 4570 { 4571 /* bare address - translate to PC-relative offset */ 4572 inst.reloc.pc_rel = 1; 4573 inst.operands[i].reg = REG_PC; 4574 inst.operands[i].isreg = 1; 4575 inst.operands[i].preind = 1; 4576 } 4577 /* else a load-constant pseudo op, no special treatment needed here */ 4578 4579 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 4580 return PARSE_OPERAND_FAIL; 4581 4582 *str = p; 4583 return PARSE_OPERAND_SUCCESS; 4584 } 4585 4586 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 4587 { 4588 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 4589 return PARSE_OPERAND_FAIL; 4590 } 4591 inst.operands[i].reg = reg; 4592 inst.operands[i].isreg = 1; 4593 4594 if (skip_past_comma (&p) == SUCCESS) 4595 { 4596 inst.operands[i].preind = 1; 4597 4598 if (*p == '+') p++; 4599 else if (*p == '-') p++, inst.operands[i].negative = 1; 4600 4601 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 4602 { 4603 inst.operands[i].imm = reg; 4604 inst.operands[i].immisreg = 1; 4605 4606 if (skip_past_comma (&p) == SUCCESS) 4607 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) 4608 return PARSE_OPERAND_FAIL; 4609 } 4610 else if (skip_past_char (&p, ':') == SUCCESS) 4611 { 4612 /* FIXME: '@' should be used here, but it's filtered out by generic 4613 code before we get to see it here. This may be subject to 4614 change. */ 4615 expressionS exp; 4616 my_get_expression (&exp, &p, GE_NO_PREFIX); 4617 if (exp.X_op != O_constant) 4618 { 4619 inst.error = _("alignment must be constant"); 4620 return PARSE_OPERAND_FAIL; 4621 } 4622 inst.operands[i].imm = exp.X_add_number << 8; 4623 inst.operands[i].immisalign = 1; 4624 /* Alignments are not pre-indexes. */ 4625 inst.operands[i].preind = 0; 4626 } 4627 else 4628 { 4629 if (inst.operands[i].negative) 4630 { 4631 inst.operands[i].negative = 0; 4632 p--; 4633 } 4634 4635 if (group_relocations && 4636 ((*p == '#' && *(p + 1) == ':') || *p == ':')) 4637 4638 { 4639 struct group_reloc_table_entry *entry; 4640 4641 /* Skip over the #: or : sequence. */ 4642 if (*p == '#') 4643 p += 2; 4644 else 4645 p++; 4646 4647 /* Try to parse a group relocation. Anything else is an 4648 error. */ 4649 if (find_group_reloc_table_entry (&p, &entry) == FAIL) 4650 { 4651 inst.error = _("unknown group relocation"); 4652 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4653 } 4654 4655 /* We now have the group relocation table entry corresponding to 4656 the name in the assembler source. Next, we parse the 4657 expression. */ 4658 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 4659 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4660 4661 /* Record the relocation type. */ 4662 switch (group_type) 4663 { 4664 case GROUP_LDR: 4665 inst.reloc.type = entry->ldr_code; 4666 break; 4667 4668 case GROUP_LDRS: 4669 inst.reloc.type = entry->ldrs_code; 4670 break; 4671 4672 case GROUP_LDC: 4673 inst.reloc.type = entry->ldc_code; 4674 break; 4675 4676 default: 4677 assert (0); 4678 } 4679 4680 if (inst.reloc.type == 0) 4681 { 4682 inst.error = _("this group relocation is not allowed on this instruction"); 4683 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4684 } 4685 } 4686 else 4687 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 4688 return PARSE_OPERAND_FAIL; 4689 } 4690 } 4691 4692 if (skip_past_char (&p, ']') == FAIL) 4693 { 4694 inst.error = _("']' expected"); 4695 return PARSE_OPERAND_FAIL; 4696 } 4697 4698 if (skip_past_char (&p, '!') == SUCCESS) 4699 inst.operands[i].writeback = 1; 4700 4701 else if (skip_past_comma (&p) == SUCCESS) 4702 { 4703 if (skip_past_char (&p, '{') == SUCCESS) 4704 { 4705 /* [Rn], {expr} - unindexed, with option */ 4706 if (parse_immediate (&p, &inst.operands[i].imm, 4707 0, 255, TRUE) == FAIL) 4708 return PARSE_OPERAND_FAIL; 4709 4710 if (skip_past_char (&p, '}') == FAIL) 4711 { 4712 inst.error = _("'}' expected at end of 'option' field"); 4713 return PARSE_OPERAND_FAIL; 4714 } 4715 if (inst.operands[i].preind) 4716 { 4717 inst.error = _("cannot combine index with option"); 4718 return PARSE_OPERAND_FAIL; 4719 } 4720 *str = p; 4721 return PARSE_OPERAND_SUCCESS; 4722 } 4723 else 4724 { 4725 inst.operands[i].postind = 1; 4726 inst.operands[i].writeback = 1; 4727 4728 if (inst.operands[i].preind) 4729 { 4730 inst.error = _("cannot combine pre- and post-indexing"); 4731 return PARSE_OPERAND_FAIL; 4732 } 4733 4734 if (*p == '+') p++; 4735 else if (*p == '-') p++, inst.operands[i].negative = 1; 4736 4737 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 4738 { 4739 /* We might be using the immediate for alignment already. If we 4740 are, OR the register number into the low-order bits. */ 4741 if (inst.operands[i].immisalign) 4742 inst.operands[i].imm |= reg; 4743 else 4744 inst.operands[i].imm = reg; 4745 inst.operands[i].immisreg = 1; 4746 4747 if (skip_past_comma (&p) == SUCCESS) 4748 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) 4749 return PARSE_OPERAND_FAIL; 4750 } 4751 else 4752 { 4753 if (inst.operands[i].negative) 4754 { 4755 inst.operands[i].negative = 0; 4756 p--; 4757 } 4758 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 4759 return PARSE_OPERAND_FAIL; 4760 } 4761 } 4762 } 4763 4764 /* If at this point neither .preind nor .postind is set, we have a 4765 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ 4766 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) 4767 { 4768 inst.operands[i].preind = 1; 4769 inst.reloc.exp.X_op = O_constant; 4770 inst.reloc.exp.X_add_number = 0; 4771 } 4772 *str = p; 4773 return PARSE_OPERAND_SUCCESS; 4774} 4775 4776static int 4777parse_address (char **str, int i) 4778{ 4779 return parse_address_main (str, i, 0, 0) == PARSE_OPERAND_SUCCESS 4780 ? SUCCESS : FAIL; 4781} 4782 4783static parse_operand_result 4784parse_address_group_reloc (char **str, int i, group_reloc_type type) 4785{ 4786 return parse_address_main (str, i, 1, type); 4787} 4788 4789/* Parse an operand for a MOVW or MOVT instruction. */ 4790static int 4791parse_half (char **str) 4792{ 4793 char * p; 4794 4795 p = *str; 4796 skip_past_char (&p, '#'); 4797 if (strncasecmp (p, ":lower16:", 9) == 0) 4798 inst.reloc.type = BFD_RELOC_ARM_MOVW; 4799 else if (strncasecmp (p, ":upper16:", 9) == 0) 4800 inst.reloc.type = BFD_RELOC_ARM_MOVT; 4801 4802 if (inst.reloc.type != BFD_RELOC_UNUSED) 4803 { 4804 p += 9; 4805 skip_whitespace(p); 4806 } 4807 4808 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 4809 return FAIL; 4810 4811 if (inst.reloc.type == BFD_RELOC_UNUSED) 4812 { 4813 if (inst.reloc.exp.X_op != O_constant) 4814 { 4815 inst.error = _("constant expression expected"); 4816 return FAIL; 4817 } 4818 if (inst.reloc.exp.X_add_number < 0 4819 || inst.reloc.exp.X_add_number > 0xffff) 4820 { 4821 inst.error = _("immediate value out of range"); 4822 return FAIL; 4823 } 4824 } 4825 *str = p; 4826 return SUCCESS; 4827} 4828 4829/* Miscellaneous. */ 4830 4831/* Parse a PSR flag operand. The value returned is FAIL on syntax error, 4832 or a bitmask suitable to be or-ed into the ARM msr instruction. */ 4833static int 4834parse_psr (char **str) 4835{ 4836 char *p; 4837 unsigned long psr_field; 4838 const struct asm_psr *psr; 4839 char *start; 4840 4841 /* CPSR's and SPSR's can now be lowercase. This is just a convenience 4842 feature for ease of use and backwards compatibility. */ 4843 p = *str; 4844 if (strncasecmp (p, "SPSR", 4) == 0) 4845 psr_field = SPSR_BIT; 4846 else if (strncasecmp (p, "CPSR", 4) == 0) 4847 psr_field = 0; 4848 else 4849 { 4850 start = p; 4851 do 4852 p++; 4853 while (ISALNUM (*p) || *p == '_'); 4854 4855 psr = hash_find_n (arm_v7m_psr_hsh, start, p - start); 4856 if (!psr) 4857 return FAIL; 4858 4859 *str = p; 4860 return psr->field; 4861 } 4862 4863 p += 4; 4864 if (*p == '_') 4865 { 4866 /* A suffix follows. */ 4867 p++; 4868 start = p; 4869 4870 do 4871 p++; 4872 while (ISALNUM (*p) || *p == '_'); 4873 4874 psr = hash_find_n (arm_psr_hsh, start, p - start); 4875 if (!psr) 4876 goto error; 4877 4878 psr_field |= psr->field; 4879 } 4880 else 4881 { 4882 if (ISALNUM (*p)) 4883 goto error; /* Garbage after "[CS]PSR". */ 4884 4885 psr_field |= (PSR_c | PSR_f); 4886 } 4887 *str = p; 4888 return psr_field; 4889 4890 error: 4891 inst.error = _("flag for {c}psr instruction expected"); 4892 return FAIL; 4893} 4894 4895/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a 4896 value suitable for splatting into the AIF field of the instruction. */ 4897 4898static int 4899parse_cps_flags (char **str) 4900{ 4901 int val = 0; 4902 int saw_a_flag = 0; 4903 char *s = *str; 4904 4905 for (;;) 4906 switch (*s++) 4907 { 4908 case '\0': case ',': 4909 goto done; 4910 4911 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; 4912 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; 4913 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; 4914 4915 default: 4916 inst.error = _("unrecognized CPS flag"); 4917 return FAIL; 4918 } 4919 4920 done: 4921 if (saw_a_flag == 0) 4922 { 4923 inst.error = _("missing CPS flags"); 4924 return FAIL; 4925 } 4926 4927 *str = s - 1; 4928 return val; 4929} 4930 4931/* Parse an endian specifier ("BE" or "LE", case insensitive); 4932 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ 4933 4934static int 4935parse_endian_specifier (char **str) 4936{ 4937 int little_endian; 4938 char *s = *str; 4939 4940 if (strncasecmp (s, "BE", 2)) 4941 little_endian = 0; 4942 else if (strncasecmp (s, "LE", 2)) 4943 little_endian = 1; 4944 else 4945 { 4946 inst.error = _("valid endian specifiers are be or le"); 4947 return FAIL; 4948 } 4949 4950 if (ISALNUM (s[2]) || s[2] == '_') 4951 { 4952 inst.error = _("valid endian specifiers are be or le"); 4953 return FAIL; 4954 } 4955 4956 *str = s + 2; 4957 return little_endian; 4958} 4959 4960/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a 4961 value suitable for poking into the rotate field of an sxt or sxta 4962 instruction, or FAIL on error. */ 4963 4964static int 4965parse_ror (char **str) 4966{ 4967 int rot; 4968 char *s = *str; 4969 4970 if (strncasecmp (s, "ROR", 3) == 0) 4971 s += 3; 4972 else 4973 { 4974 inst.error = _("missing rotation field after comma"); 4975 return FAIL; 4976 } 4977 4978 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) 4979 return FAIL; 4980 4981 switch (rot) 4982 { 4983 case 0: *str = s; return 0x0; 4984 case 8: *str = s; return 0x1; 4985 case 16: *str = s; return 0x2; 4986 case 24: *str = s; return 0x3; 4987 4988 default: 4989 inst.error = _("rotation can only be 0, 8, 16, or 24"); 4990 return FAIL; 4991 } 4992} 4993 4994/* Parse a conditional code (from conds[] below). The value returned is in the 4995 range 0 .. 14, or FAIL. */ 4996static int 4997parse_cond (char **str) 4998{ 4999 char *p, *q; 5000 const struct asm_cond *c; 5001 5002 p = q = *str; 5003 while (ISALPHA (*q)) 5004 q++; 5005 5006 c = hash_find_n (arm_cond_hsh, p, q - p); 5007 if (!c) 5008 { 5009 inst.error = _("condition required"); 5010 return FAIL; 5011 } 5012 5013 *str = q; 5014 return c->value; 5015} 5016 5017/* Parse an option for a barrier instruction. Returns the encoding for the 5018 option, or FAIL. */ 5019static int 5020parse_barrier (char **str) 5021{ 5022 char *p, *q; 5023 const struct asm_barrier_opt *o; 5024 5025 p = q = *str; 5026 while (ISALPHA (*q)) 5027 q++; 5028 5029 o = hash_find_n (arm_barrier_opt_hsh, p, q - p); 5030 if (!o) 5031 return FAIL; 5032 5033 *str = q; 5034 return o->value; 5035} 5036 5037/* Parse the operands of a table branch instruction. Similar to a memory 5038 operand. */ 5039static int 5040parse_tb (char **str) 5041{ 5042 char * p = *str; 5043 int reg; 5044 5045 if (skip_past_char (&p, '[') == FAIL) 5046 { 5047 inst.error = _("'[' expected"); 5048 return FAIL; 5049 } 5050 5051 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 5052 { 5053 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 5054 return FAIL; 5055 } 5056 inst.operands[0].reg = reg; 5057 5058 if (skip_past_comma (&p) == FAIL) 5059 { 5060 inst.error = _("',' expected"); 5061 return FAIL; 5062 } 5063 5064 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 5065 { 5066 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 5067 return FAIL; 5068 } 5069 inst.operands[0].imm = reg; 5070 5071 if (skip_past_comma (&p) == SUCCESS) 5072 { 5073 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) 5074 return FAIL; 5075 if (inst.reloc.exp.X_add_number != 1) 5076 { 5077 inst.error = _("invalid shift"); 5078 return FAIL; 5079 } 5080 inst.operands[0].shifted = 1; 5081 } 5082 5083 if (skip_past_char (&p, ']') == FAIL) 5084 { 5085 inst.error = _("']' expected"); 5086 return FAIL; 5087 } 5088 *str = p; 5089 return SUCCESS; 5090} 5091 5092/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more 5093 information on the types the operands can take and how they are encoded. 5094 Up to four operands may be read; this function handles setting the 5095 ".present" field for each read operand itself. 5096 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, 5097 else returns FAIL. */ 5098 5099static int 5100parse_neon_mov (char **str, int *which_operand) 5101{ 5102 int i = *which_operand, val; 5103 enum arm_reg_type rtype; 5104 char *ptr = *str; 5105 struct neon_type_el optype; 5106 5107 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) 5108 { 5109 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ 5110 inst.operands[i].reg = val; 5111 inst.operands[i].isscalar = 1; 5112 inst.operands[i].vectype = optype; 5113 inst.operands[i++].present = 1; 5114 5115 if (skip_past_comma (&ptr) == FAIL) 5116 goto wanted_comma; 5117 5118 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5119 goto wanted_arm; 5120 5121 inst.operands[i].reg = val; 5122 inst.operands[i].isreg = 1; 5123 inst.operands[i].present = 1; 5124 } 5125 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) 5126 != FAIL) 5127 { 5128 /* Cases 0, 1, 2, 3, 5 (D only). */ 5129 if (skip_past_comma (&ptr) == FAIL) 5130 goto wanted_comma; 5131 5132 inst.operands[i].reg = val; 5133 inst.operands[i].isreg = 1; 5134 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); 5135 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5136 inst.operands[i].isvec = 1; 5137 inst.operands[i].vectype = optype; 5138 inst.operands[i++].present = 1; 5139 5140 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5141 { 5142 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. 5143 Case 13: VMOV <Sd>, <Rm> */ 5144 inst.operands[i].reg = val; 5145 inst.operands[i].isreg = 1; 5146 inst.operands[i].present = 1; 5147 5148 if (rtype == REG_TYPE_NQ) 5149 { 5150 first_error (_("can't use Neon quad register here")); 5151 return FAIL; 5152 } 5153 else if (rtype != REG_TYPE_VFS) 5154 { 5155 i++; 5156 if (skip_past_comma (&ptr) == FAIL) 5157 goto wanted_comma; 5158 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5159 goto wanted_arm; 5160 inst.operands[i].reg = val; 5161 inst.operands[i].isreg = 1; 5162 inst.operands[i].present = 1; 5163 } 5164 } 5165 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) 5166 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> 5167 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> 5168 Case 10: VMOV.F32 <Sd>, #<imm> 5169 Case 11: VMOV.F64 <Dd>, #<imm> */ 5170 inst.operands[i].immisfloat = 1; 5171 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, 5172 &optype)) != FAIL) 5173 { 5174 /* Case 0: VMOV<c><q> <Qd>, <Qm> 5175 Case 1: VMOV<c><q> <Dd>, <Dm> 5176 Case 8: VMOV.F32 <Sd>, <Sm> 5177 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ 5178 5179 inst.operands[i].reg = val; 5180 inst.operands[i].isreg = 1; 5181 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); 5182 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5183 inst.operands[i].isvec = 1; 5184 inst.operands[i].vectype = optype; 5185 inst.operands[i].present = 1; 5186 5187 if (skip_past_comma (&ptr) == SUCCESS) 5188 { 5189 /* Case 15. */ 5190 i++; 5191 5192 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5193 goto wanted_arm; 5194 5195 inst.operands[i].reg = val; 5196 inst.operands[i].isreg = 1; 5197 inst.operands[i++].present = 1; 5198 5199 if (skip_past_comma (&ptr) == FAIL) 5200 goto wanted_comma; 5201 5202 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5203 goto wanted_arm; 5204 5205 inst.operands[i].reg = val; 5206 inst.operands[i].isreg = 1; 5207 inst.operands[i++].present = 1; 5208 } 5209 } 5210 else if (parse_big_immediate (&ptr, i) == SUCCESS) 5211 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> 5212 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ 5213 ; 5214 else 5215 { 5216 first_error (_("expected <Rm> or <Dm> or <Qm> operand")); 5217 return FAIL; 5218 } 5219 } 5220 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5221 { 5222 /* Cases 6, 7. */ 5223 inst.operands[i].reg = val; 5224 inst.operands[i].isreg = 1; 5225 inst.operands[i++].present = 1; 5226 5227 if (skip_past_comma (&ptr) == FAIL) 5228 goto wanted_comma; 5229 5230 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) 5231 { 5232 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ 5233 inst.operands[i].reg = val; 5234 inst.operands[i].isscalar = 1; 5235 inst.operands[i].present = 1; 5236 inst.operands[i].vectype = optype; 5237 } 5238 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5239 { 5240 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ 5241 inst.operands[i].reg = val; 5242 inst.operands[i].isreg = 1; 5243 inst.operands[i++].present = 1; 5244 5245 if (skip_past_comma (&ptr) == FAIL) 5246 goto wanted_comma; 5247 5248 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) 5249 == FAIL) 5250 { 5251 first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); 5252 return FAIL; 5253 } 5254 5255 inst.operands[i].reg = val; 5256 inst.operands[i].isreg = 1; 5257 inst.operands[i].isvec = 1; 5258 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5259 inst.operands[i].vectype = optype; 5260 inst.operands[i].present = 1; 5261 5262 if (rtype == REG_TYPE_VFS) 5263 { 5264 /* Case 14. */ 5265 i++; 5266 if (skip_past_comma (&ptr) == FAIL) 5267 goto wanted_comma; 5268 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, 5269 &optype)) == FAIL) 5270 { 5271 first_error (_(reg_expected_msgs[REG_TYPE_VFS])); 5272 return FAIL; 5273 } 5274 inst.operands[i].reg = val; 5275 inst.operands[i].isreg = 1; 5276 inst.operands[i].isvec = 1; 5277 inst.operands[i].issingle = 1; 5278 inst.operands[i].vectype = optype; 5279 inst.operands[i].present = 1; 5280 } 5281 } 5282 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) 5283 != FAIL) 5284 { 5285 /* Case 13. */ 5286 inst.operands[i].reg = val; 5287 inst.operands[i].isreg = 1; 5288 inst.operands[i].isvec = 1; 5289 inst.operands[i].issingle = 1; 5290 inst.operands[i].vectype = optype; 5291 inst.operands[i++].present = 1; 5292 } 5293 } 5294 else 5295 { 5296 first_error (_("parse error")); 5297 return FAIL; 5298 } 5299 5300 /* Successfully parsed the operands. Update args. */ 5301 *which_operand = i; 5302 *str = ptr; 5303 return SUCCESS; 5304 5305 wanted_comma: 5306 first_error (_("expected comma")); 5307 return FAIL; 5308 5309 wanted_arm: 5310 first_error (_(reg_expected_msgs[REG_TYPE_RN])); 5311 return FAIL; 5312} 5313 5314/* Matcher codes for parse_operands. */ 5315enum operand_parse_code 5316{ 5317 OP_stop, /* end of line */ 5318 5319 OP_RR, /* ARM register */ 5320 OP_RRnpc, /* ARM register, not r15 */ 5321 OP_RRnpcb, /* ARM register, not r15, in square brackets */ 5322 OP_RRw, /* ARM register, not r15, optional trailing ! */ 5323 OP_RCP, /* Coprocessor number */ 5324 OP_RCN, /* Coprocessor register */ 5325 OP_RF, /* FPA register */ 5326 OP_RVS, /* VFP single precision register */ 5327 OP_RVD, /* VFP double precision register (0..15) */ 5328 OP_RND, /* Neon double precision register (0..31) */ 5329 OP_RNQ, /* Neon quad precision register */ 5330 OP_RVSD, /* VFP single or double precision register */ 5331 OP_RNDQ, /* Neon double or quad precision register */ 5332 OP_RNSDQ, /* Neon single, double or quad precision register */ 5333 OP_RNSC, /* Neon scalar D[X] */ 5334 OP_RVC, /* VFP control register */ 5335 OP_RMF, /* Maverick F register */ 5336 OP_RMD, /* Maverick D register */ 5337 OP_RMFX, /* Maverick FX register */ 5338 OP_RMDX, /* Maverick DX register */ 5339 OP_RMAX, /* Maverick AX register */ 5340 OP_RMDS, /* Maverick DSPSC register */ 5341 OP_RIWR, /* iWMMXt wR register */ 5342 OP_RIWC, /* iWMMXt wC register */ 5343 OP_RIWG, /* iWMMXt wCG register */ 5344 OP_RXA, /* XScale accumulator register */ 5345 5346 OP_REGLST, /* ARM register list */ 5347 OP_VRSLST, /* VFP single-precision register list */ 5348 OP_VRDLST, /* VFP double-precision register list */ 5349 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ 5350 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ 5351 OP_NSTRLST, /* Neon element/structure list */ 5352 5353 OP_NILO, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */ 5354 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ 5355 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ 5356 OP_RR_RNSC, /* ARM reg or Neon scalar. */ 5357 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ 5358 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ 5359 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ 5360 OP_VMOV, /* Neon VMOV operands. */ 5361 OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN. */ 5362 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ 5363 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ 5364 5365 OP_I0, /* immediate zero */ 5366 OP_I7, /* immediate value 0 .. 7 */ 5367 OP_I15, /* 0 .. 15 */ 5368 OP_I16, /* 1 .. 16 */ 5369 OP_I16z, /* 0 .. 16 */ 5370 OP_I31, /* 0 .. 31 */ 5371 OP_I31w, /* 0 .. 31, optional trailing ! */ 5372 OP_I32, /* 1 .. 32 */ 5373 OP_I32z, /* 0 .. 32 */ 5374 OP_I63, /* 0 .. 63 */ 5375 OP_I63s, /* -64 .. 63 */ 5376 OP_I64, /* 1 .. 64 */ 5377 OP_I64z, /* 0 .. 64 */ 5378 OP_I255, /* 0 .. 255 */ 5379 5380 OP_I4b, /* immediate, prefix optional, 1 .. 4 */ 5381 OP_I7b, /* 0 .. 7 */ 5382 OP_I15b, /* 0 .. 15 */ 5383 OP_I31b, /* 0 .. 31 */ 5384 5385 OP_SH, /* shifter operand */ 5386 OP_SHG, /* shifter operand with possible group relocation */ 5387 OP_ADDR, /* Memory address expression (any mode) */ 5388 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ 5389 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ 5390 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ 5391 OP_EXP, /* arbitrary expression */ 5392 OP_EXPi, /* same, with optional immediate prefix */ 5393 OP_EXPr, /* same, with optional relocation suffix */ 5394 OP_HALF, /* 0 .. 65535 or low/high reloc. */ 5395 5396 OP_CPSF, /* CPS flags */ 5397 OP_ENDI, /* Endianness specifier */ 5398 OP_PSR, /* CPSR/SPSR mask for msr */ 5399 OP_COND, /* conditional code */ 5400 OP_TB, /* Table branch. */ 5401 5402 OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */ 5403 OP_APSR_RR, /* ARM register or "APSR_nzcv". */ 5404 5405 OP_RRnpc_I0, /* ARM register or literal 0 */ 5406 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ 5407 OP_RR_EXi, /* ARM register or expression with imm prefix */ 5408 OP_RF_IF, /* FPA register or immediate */ 5409 OP_RIWR_RIWC, /* iWMMXt R or C reg */ 5410 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ 5411 5412 /* Optional operands. */ 5413 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ 5414 OP_oI31b, /* 0 .. 31 */ 5415 OP_oI32b, /* 1 .. 32 */ 5416 OP_oIffffb, /* 0 .. 65535 */ 5417 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ 5418 5419 OP_oRR, /* ARM register */ 5420 OP_oRRnpc, /* ARM register, not the PC */ 5421 OP_oRRw, /* ARM register, not r15, optional trailing ! */ 5422 OP_oRND, /* Optional Neon double precision register */ 5423 OP_oRNQ, /* Optional Neon quad precision register */ 5424 OP_oRNDQ, /* Optional Neon double or quad precision register */ 5425 OP_oRNSDQ, /* Optional single, double or quad precision vector register */ 5426 OP_oSHll, /* LSL immediate */ 5427 OP_oSHar, /* ASR immediate */ 5428 OP_oSHllar, /* LSL or ASR immediate */ 5429 OP_oROR, /* ROR 0/8/16/24 */ 5430 OP_oBARRIER, /* Option argument for a barrier instruction. */ 5431 5432 OP_FIRST_OPTIONAL = OP_oI7b 5433}; 5434 5435/* Generic instruction operand parser. This does no encoding and no 5436 semantic validation; it merely squirrels values away in the inst 5437 structure. Returns SUCCESS or FAIL depending on whether the 5438 specified grammar matched. */ 5439static int 5440parse_operands (char *str, const unsigned char *pattern) 5441{ 5442 unsigned const char *upat = pattern; 5443 char *backtrack_pos = 0; 5444 const char *backtrack_error = 0; 5445 int i, val, backtrack_index = 0; 5446 enum arm_reg_type rtype; 5447 parse_operand_result result; 5448 5449#define po_char_or_fail(chr) do { \ 5450 if (skip_past_char (&str, chr) == FAIL) \ 5451 goto bad_args; \ 5452} while (0) 5453 5454#define po_reg_or_fail(regtype) do { \ 5455 val = arm_typed_reg_parse (&str, regtype, &rtype, \ 5456 &inst.operands[i].vectype); \ 5457 if (val == FAIL) \ 5458 { \ 5459 first_error (_(reg_expected_msgs[regtype])); \ 5460 goto failure; \ 5461 } \ 5462 inst.operands[i].reg = val; \ 5463 inst.operands[i].isreg = 1; \ 5464 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ 5465 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ 5466 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ 5467 || rtype == REG_TYPE_VFD \ 5468 || rtype == REG_TYPE_NQ); \ 5469} while (0) 5470 5471#define po_reg_or_goto(regtype, label) do { \ 5472 val = arm_typed_reg_parse (&str, regtype, &rtype, \ 5473 &inst.operands[i].vectype); \ 5474 if (val == FAIL) \ 5475 goto label; \ 5476 \ 5477 inst.operands[i].reg = val; \ 5478 inst.operands[i].isreg = 1; \ 5479 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ 5480 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ 5481 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ 5482 || rtype == REG_TYPE_VFD \ 5483 || rtype == REG_TYPE_NQ); \ 5484} while (0) 5485 5486#define po_imm_or_fail(min, max, popt) do { \ 5487 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ 5488 goto failure; \ 5489 inst.operands[i].imm = val; \ 5490} while (0) 5491 5492#define po_scalar_or_goto(elsz, label) do { \ 5493 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \ 5494 if (val == FAIL) \ 5495 goto label; \ 5496 inst.operands[i].reg = val; \ 5497 inst.operands[i].isscalar = 1; \ 5498} while (0) 5499 5500#define po_misc_or_fail(expr) do { \ 5501 if (expr) \ 5502 goto failure; \ 5503} while (0) 5504 5505#define po_misc_or_fail_no_backtrack(expr) do { \ 5506 result = expr; \ 5507 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\ 5508 backtrack_pos = 0; \ 5509 if (result != PARSE_OPERAND_SUCCESS) \ 5510 goto failure; \ 5511} while (0) 5512 5513 skip_whitespace (str); 5514 5515 for (i = 0; upat[i] != OP_stop; i++) 5516 { 5517 if (upat[i] >= OP_FIRST_OPTIONAL) 5518 { 5519 /* Remember where we are in case we need to backtrack. */ 5520 assert (!backtrack_pos); 5521 backtrack_pos = str; 5522 backtrack_error = inst.error; 5523 backtrack_index = i; 5524 } 5525 5526 if (i > 0 && (i > 1 || inst.operands[0].present)) 5527 po_char_or_fail (','); 5528 5529 switch (upat[i]) 5530 { 5531 /* Registers */ 5532 case OP_oRRnpc: 5533 case OP_RRnpc: 5534 case OP_oRR: 5535 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; 5536 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; 5537 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; 5538 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; 5539 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; 5540 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; 5541 case OP_oRND: 5542 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; 5543 case OP_RVC: 5544 po_reg_or_goto (REG_TYPE_VFC, coproc_reg); 5545 break; 5546 /* Also accept generic coprocessor regs for unknown registers. */ 5547 coproc_reg: 5548 po_reg_or_fail (REG_TYPE_CN); 5549 break; 5550 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; 5551 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; 5552 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; 5553 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; 5554 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; 5555 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; 5556 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; 5557 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; 5558 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; 5559 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; 5560 case OP_oRNQ: 5561 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; 5562 case OP_oRNDQ: 5563 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; 5564 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; 5565 case OP_oRNSDQ: 5566 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; 5567 5568 /* Neon scalar. Using an element size of 8 means that some invalid 5569 scalars are accepted here, so deal with those in later code. */ 5570 case OP_RNSC: po_scalar_or_goto (8, failure); break; 5571 5572 /* WARNING: We can expand to two operands here. This has the potential 5573 to totally confuse the backtracking mechanism! It will be OK at 5574 least as long as we don't try to use optional args as well, 5575 though. */ 5576 case OP_NILO: 5577 { 5578 po_reg_or_goto (REG_TYPE_NDQ, try_imm); 5579 inst.operands[i].present = 1; 5580 i++; 5581 skip_past_comma (&str); 5582 po_reg_or_goto (REG_TYPE_NDQ, one_reg_only); 5583 break; 5584 one_reg_only: 5585 /* Optional register operand was omitted. Unfortunately, it's in 5586 operands[i-1] and we need it to be in inst.operands[i]. Fix that 5587 here (this is a bit grotty). */ 5588 inst.operands[i] = inst.operands[i-1]; 5589 inst.operands[i-1].present = 0; 5590 break; 5591 try_imm: 5592 /* There's a possibility of getting a 64-bit immediate here, so 5593 we need special handling. */ 5594 if (parse_big_immediate (&str, i) == FAIL) 5595 { 5596 inst.error = _("immediate value is out of range"); 5597 goto failure; 5598 } 5599 } 5600 break; 5601 5602 case OP_RNDQ_I0: 5603 { 5604 po_reg_or_goto (REG_TYPE_NDQ, try_imm0); 5605 break; 5606 try_imm0: 5607 po_imm_or_fail (0, 0, TRUE); 5608 } 5609 break; 5610 5611 case OP_RVSD_I0: 5612 po_reg_or_goto (REG_TYPE_VFSD, try_imm0); 5613 break; 5614 5615 case OP_RR_RNSC: 5616 { 5617 po_scalar_or_goto (8, try_rr); 5618 break; 5619 try_rr: 5620 po_reg_or_fail (REG_TYPE_RN); 5621 } 5622 break; 5623 5624 case OP_RNSDQ_RNSC: 5625 { 5626 po_scalar_or_goto (8, try_nsdq); 5627 break; 5628 try_nsdq: 5629 po_reg_or_fail (REG_TYPE_NSDQ); 5630 } 5631 break; 5632 5633 case OP_RNDQ_RNSC: 5634 { 5635 po_scalar_or_goto (8, try_ndq); 5636 break; 5637 try_ndq: 5638 po_reg_or_fail (REG_TYPE_NDQ); 5639 } 5640 break; 5641 5642 case OP_RND_RNSC: 5643 { 5644 po_scalar_or_goto (8, try_vfd); 5645 break; 5646 try_vfd: 5647 po_reg_or_fail (REG_TYPE_VFD); 5648 } 5649 break; 5650 5651 case OP_VMOV: 5652 /* WARNING: parse_neon_mov can move the operand counter, i. If we're 5653 not careful then bad things might happen. */ 5654 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); 5655 break; 5656 5657 case OP_RNDQ_IMVNb: 5658 { 5659 po_reg_or_goto (REG_TYPE_NDQ, try_mvnimm); 5660 break; 5661 try_mvnimm: 5662 /* There's a possibility of getting a 64-bit immediate here, so 5663 we need special handling. */ 5664 if (parse_big_immediate (&str, i) == FAIL) 5665 { 5666 inst.error = _("immediate value is out of range"); 5667 goto failure; 5668 } 5669 } 5670 break; 5671 5672 case OP_RNDQ_I63b: 5673 { 5674 po_reg_or_goto (REG_TYPE_NDQ, try_shimm); 5675 break; 5676 try_shimm: 5677 po_imm_or_fail (0, 63, TRUE); 5678 } 5679 break; 5680 5681 case OP_RRnpcb: 5682 po_char_or_fail ('['); 5683 po_reg_or_fail (REG_TYPE_RN); 5684 po_char_or_fail (']'); 5685 break; 5686 5687 case OP_RRw: 5688 case OP_oRRw: 5689 po_reg_or_fail (REG_TYPE_RN); 5690 if (skip_past_char (&str, '!') == SUCCESS) 5691 inst.operands[i].writeback = 1; 5692 break; 5693 5694 /* Immediates */ 5695 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; 5696 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; 5697 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; 5698 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; 5699 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; 5700 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; 5701 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; 5702 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; 5703 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; 5704 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; 5705 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; 5706 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; 5707 5708 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; 5709 case OP_oI7b: 5710 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; 5711 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; 5712 case OP_oI31b: 5713 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; 5714 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; 5715 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; 5716 5717 /* Immediate variants */ 5718 case OP_oI255c: 5719 po_char_or_fail ('{'); 5720 po_imm_or_fail (0, 255, TRUE); 5721 po_char_or_fail ('}'); 5722 break; 5723 5724 case OP_I31w: 5725 /* The expression parser chokes on a trailing !, so we have 5726 to find it first and zap it. */ 5727 { 5728 char *s = str; 5729 while (*s && *s != ',') 5730 s++; 5731 if (s[-1] == '!') 5732 { 5733 s[-1] = '\0'; 5734 inst.operands[i].writeback = 1; 5735 } 5736 po_imm_or_fail (0, 31, TRUE); 5737 if (str == s - 1) 5738 str = s; 5739 } 5740 break; 5741 5742 /* Expressions */ 5743 case OP_EXPi: EXPi: 5744 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 5745 GE_OPT_PREFIX)); 5746 break; 5747 5748 case OP_EXP: 5749 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 5750 GE_NO_PREFIX)); 5751 break; 5752 5753 case OP_EXPr: EXPr: 5754 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 5755 GE_NO_PREFIX)); 5756 if (inst.reloc.exp.X_op == O_symbol) 5757 { 5758 val = parse_reloc (&str); 5759 if (val == -1) 5760 { 5761 inst.error = _("unrecognized relocation suffix"); 5762 goto failure; 5763 } 5764 else if (val != BFD_RELOC_UNUSED) 5765 { 5766 inst.operands[i].imm = val; 5767 inst.operands[i].hasreloc = 1; 5768 } 5769 } 5770 break; 5771 5772 /* Operand for MOVW or MOVT. */ 5773 case OP_HALF: 5774 po_misc_or_fail (parse_half (&str)); 5775 break; 5776 5777 /* Register or expression */ 5778 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; 5779 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; 5780 5781 /* Register or immediate */ 5782 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; 5783 I0: po_imm_or_fail (0, 0, FALSE); break; 5784 5785 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; 5786 IF: 5787 if (!is_immediate_prefix (*str)) 5788 goto bad_args; 5789 str++; 5790 val = parse_fpa_immediate (&str); 5791 if (val == FAIL) 5792 goto failure; 5793 /* FPA immediates are encoded as registers 8-15. 5794 parse_fpa_immediate has already applied the offset. */ 5795 inst.operands[i].reg = val; 5796 inst.operands[i].isreg = 1; 5797 break; 5798 5799 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; 5800 I32z: po_imm_or_fail (0, 32, FALSE); break; 5801 5802 /* Two kinds of register */ 5803 case OP_RIWR_RIWC: 5804 { 5805 struct reg_entry *rege = arm_reg_parse_multi (&str); 5806 if (!rege 5807 || (rege->type != REG_TYPE_MMXWR 5808 && rege->type != REG_TYPE_MMXWC 5809 && rege->type != REG_TYPE_MMXWCG)) 5810 { 5811 inst.error = _("iWMMXt data or control register expected"); 5812 goto failure; 5813 } 5814 inst.operands[i].reg = rege->number; 5815 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); 5816 } 5817 break; 5818 5819 case OP_RIWC_RIWG: 5820 { 5821 struct reg_entry *rege = arm_reg_parse_multi (&str); 5822 if (!rege 5823 || (rege->type != REG_TYPE_MMXWC 5824 && rege->type != REG_TYPE_MMXWCG)) 5825 { 5826 inst.error = _("iWMMXt control register expected"); 5827 goto failure; 5828 } 5829 inst.operands[i].reg = rege->number; 5830 inst.operands[i].isreg = 1; 5831 } 5832 break; 5833 5834 /* Misc */ 5835 case OP_CPSF: val = parse_cps_flags (&str); break; 5836 case OP_ENDI: val = parse_endian_specifier (&str); break; 5837 case OP_oROR: val = parse_ror (&str); break; 5838 case OP_PSR: val = parse_psr (&str); break; 5839 case OP_COND: val = parse_cond (&str); break; 5840 case OP_oBARRIER:val = parse_barrier (&str); break; 5841 5842 case OP_RVC_PSR: 5843 po_reg_or_goto (REG_TYPE_VFC, try_psr); 5844 inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */ 5845 break; 5846 try_psr: 5847 val = parse_psr (&str); 5848 break; 5849 5850 case OP_APSR_RR: 5851 po_reg_or_goto (REG_TYPE_RN, try_apsr); 5852 break; 5853 try_apsr: 5854 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS 5855 instruction). */ 5856 if (strncasecmp (str, "APSR_", 5) == 0) 5857 { 5858 unsigned found = 0; 5859 str += 5; 5860 while (found < 15) 5861 switch (*str++) 5862 { 5863 case 'c': found = (found & 1) ? 16 : found | 1; break; 5864 case 'n': found = (found & 2) ? 16 : found | 2; break; 5865 case 'z': found = (found & 4) ? 16 : found | 4; break; 5866 case 'v': found = (found & 8) ? 16 : found | 8; break; 5867 default: found = 16; 5868 } 5869 if (found != 15) 5870 goto failure; 5871 inst.operands[i].isvec = 1; 5872 } 5873 else 5874 goto failure; 5875 break; 5876 5877 case OP_TB: 5878 po_misc_or_fail (parse_tb (&str)); 5879 break; 5880 5881 /* Register lists */ 5882 case OP_REGLST: 5883 val = parse_reg_list (&str); 5884 if (*str == '^') 5885 { 5886 inst.operands[1].writeback = 1; 5887 str++; 5888 } 5889 break; 5890 5891 case OP_VRSLST: 5892 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); 5893 break; 5894 5895 case OP_VRDLST: 5896 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); 5897 break; 5898 5899 case OP_VRSDLST: 5900 /* Allow Q registers too. */ 5901 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 5902 REGLIST_NEON_D); 5903 if (val == FAIL) 5904 { 5905 inst.error = NULL; 5906 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 5907 REGLIST_VFP_S); 5908 inst.operands[i].issingle = 1; 5909 } 5910 break; 5911 5912 case OP_NRDLST: 5913 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 5914 REGLIST_NEON_D); 5915 break; 5916 5917 case OP_NSTRLST: 5918 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, 5919 &inst.operands[i].vectype); 5920 break; 5921 5922 /* Addressing modes */ 5923 case OP_ADDR: 5924 po_misc_or_fail (parse_address (&str, i)); 5925 break; 5926 5927 case OP_ADDRGLDR: 5928 po_misc_or_fail_no_backtrack ( 5929 parse_address_group_reloc (&str, i, GROUP_LDR)); 5930 break; 5931 5932 case OP_ADDRGLDRS: 5933 po_misc_or_fail_no_backtrack ( 5934 parse_address_group_reloc (&str, i, GROUP_LDRS)); 5935 break; 5936 5937 case OP_ADDRGLDC: 5938 po_misc_or_fail_no_backtrack ( 5939 parse_address_group_reloc (&str, i, GROUP_LDC)); 5940 break; 5941 5942 case OP_SH: 5943 po_misc_or_fail (parse_shifter_operand (&str, i)); 5944 break; 5945 5946 case OP_SHG: 5947 po_misc_or_fail_no_backtrack ( 5948 parse_shifter_operand_group_reloc (&str, i)); 5949 break; 5950 5951 case OP_oSHll: 5952 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); 5953 break; 5954 5955 case OP_oSHar: 5956 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); 5957 break; 5958 5959 case OP_oSHllar: 5960 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); 5961 break; 5962 5963 default: 5964 as_fatal ("unhandled operand code %d", upat[i]); 5965 } 5966 5967 /* Various value-based sanity checks and shared operations. We 5968 do not signal immediate failures for the register constraints; 5969 this allows a syntax error to take precedence. */ 5970 switch (upat[i]) 5971 { 5972 case OP_oRRnpc: 5973 case OP_RRnpc: 5974 case OP_RRnpcb: 5975 case OP_RRw: 5976 case OP_oRRw: 5977 case OP_RRnpc_I0: 5978 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) 5979 inst.error = BAD_PC; 5980 break; 5981 5982 case OP_CPSF: 5983 case OP_ENDI: 5984 case OP_oROR: 5985 case OP_PSR: 5986 case OP_RVC_PSR: 5987 case OP_COND: 5988 case OP_oBARRIER: 5989 case OP_REGLST: 5990 case OP_VRSLST: 5991 case OP_VRDLST: 5992 case OP_VRSDLST: 5993 case OP_NRDLST: 5994 case OP_NSTRLST: 5995 if (val == FAIL) 5996 goto failure; 5997 inst.operands[i].imm = val; 5998 break; 5999 6000 default: 6001 break; 6002 } 6003 6004 /* If we get here, this operand was successfully parsed. */ 6005 inst.operands[i].present = 1; 6006 continue; 6007 6008 bad_args: 6009 inst.error = BAD_ARGS; 6010 6011 failure: 6012 if (!backtrack_pos) 6013 { 6014 /* The parse routine should already have set inst.error, but set a 6015 defaut here just in case. */ 6016 if (!inst.error) 6017 inst.error = _("syntax error"); 6018 return FAIL; 6019 } 6020 6021 /* Do not backtrack over a trailing optional argument that 6022 absorbed some text. We will only fail again, with the 6023 'garbage following instruction' error message, which is 6024 probably less helpful than the current one. */ 6025 if (backtrack_index == i && backtrack_pos != str 6026 && upat[i+1] == OP_stop) 6027 { 6028 if (!inst.error) 6029 inst.error = _("syntax error"); 6030 return FAIL; 6031 } 6032 6033 /* Try again, skipping the optional argument at backtrack_pos. */ 6034 str = backtrack_pos; 6035 inst.error = backtrack_error; 6036 inst.operands[backtrack_index].present = 0; 6037 i = backtrack_index; 6038 backtrack_pos = 0; 6039 } 6040 6041 /* Check that we have parsed all the arguments. */ 6042 if (*str != '\0' && !inst.error) 6043 inst.error = _("garbage following instruction"); 6044 6045 return inst.error ? FAIL : SUCCESS; 6046} 6047 6048#undef po_char_or_fail 6049#undef po_reg_or_fail 6050#undef po_reg_or_goto 6051#undef po_imm_or_fail 6052#undef po_scalar_or_fail 6053 6054/* Shorthand macro for instruction encoding functions issuing errors. */ 6055#define constraint(expr, err) do { \ 6056 if (expr) \ 6057 { \ 6058 inst.error = err; \ 6059 return; \ 6060 } \ 6061} while (0) 6062 6063/* Functions for operand encoding. ARM, then Thumb. */ 6064 6065#define rotate_left(v, n) (v << (n % 32) | v >> ((32 - n) % 32)) 6066 6067/* If VAL can be encoded in the immediate field of an ARM instruction, 6068 return the encoded form. Otherwise, return FAIL. */ 6069 6070static unsigned int 6071encode_arm_immediate (unsigned int val) 6072{ 6073 unsigned int a, i; 6074 6075 for (i = 0; i < 32; i += 2) 6076 if ((a = rotate_left (val, i)) <= 0xff) 6077 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ 6078 6079 return FAIL; 6080} 6081 6082/* If VAL can be encoded in the immediate field of a Thumb32 instruction, 6083 return the encoded form. Otherwise, return FAIL. */ 6084static unsigned int 6085encode_thumb32_immediate (unsigned int val) 6086{ 6087 unsigned int a, i; 6088 6089 if (val <= 0xff) 6090 return val; 6091 6092 for (i = 1; i <= 24; i++) 6093 { 6094 a = val >> i; 6095 if ((val & ~(0xff << i)) == 0) 6096 return ((val >> i) & 0x7f) | ((32 - i) << 7); 6097 } 6098 6099 a = val & 0xff; 6100 if (val == ((a << 16) | a)) 6101 return 0x100 | a; 6102 if (val == ((a << 24) | (a << 16) | (a << 8) | a)) 6103 return 0x300 | a; 6104 6105 a = val & 0xff00; 6106 if (val == ((a << 16) | a)) 6107 return 0x200 | (a >> 8); 6108 6109 return FAIL; 6110} 6111/* Encode a VFP SP or DP register number into inst.instruction. */ 6112 6113static void 6114encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) 6115{ 6116 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) 6117 && reg > 15) 6118 { 6119 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3)) 6120 { 6121 if (thumb_mode) 6122 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 6123 fpu_vfp_ext_v3); 6124 else 6125 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 6126 fpu_vfp_ext_v3); 6127 } 6128 else 6129 { 6130 first_error (_("D register out of range for selected VFP version")); 6131 return; 6132 } 6133 } 6134 6135 switch (pos) 6136 { 6137 case VFP_REG_Sd: 6138 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); 6139 break; 6140 6141 case VFP_REG_Sn: 6142 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); 6143 break; 6144 6145 case VFP_REG_Sm: 6146 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); 6147 break; 6148 6149 case VFP_REG_Dd: 6150 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); 6151 break; 6152 6153 case VFP_REG_Dn: 6154 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); 6155 break; 6156 6157 case VFP_REG_Dm: 6158 inst.instruction |= (reg & 15) | ((reg >> 4) << 5); 6159 break; 6160 6161 default: 6162 abort (); 6163 } 6164} 6165 6166/* Encode a <shift> in an ARM-format instruction. The immediate, 6167 if any, is handled by md_apply_fix. */ 6168static void 6169encode_arm_shift (int i) 6170{ 6171 if (inst.operands[i].shift_kind == SHIFT_RRX) 6172 inst.instruction |= SHIFT_ROR << 5; 6173 else 6174 { 6175 inst.instruction |= inst.operands[i].shift_kind << 5; 6176 if (inst.operands[i].immisreg) 6177 { 6178 inst.instruction |= SHIFT_BY_REG; 6179 inst.instruction |= inst.operands[i].imm << 8; 6180 } 6181 else 6182 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 6183 } 6184} 6185 6186static void 6187encode_arm_shifter_operand (int i) 6188{ 6189 if (inst.operands[i].isreg) 6190 { 6191 inst.instruction |= inst.operands[i].reg; 6192 encode_arm_shift (i); 6193 } 6194 else 6195 inst.instruction |= INST_IMMEDIATE; 6196} 6197 6198/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ 6199static void 6200encode_arm_addr_mode_common (int i, bfd_boolean is_t) 6201{ 6202 assert (inst.operands[i].isreg); 6203 inst.instruction |= inst.operands[i].reg << 16; 6204 6205 if (inst.operands[i].preind) 6206 { 6207 if (is_t) 6208 { 6209 inst.error = _("instruction does not accept preindexed addressing"); 6210 return; 6211 } 6212 inst.instruction |= PRE_INDEX; 6213 if (inst.operands[i].writeback) 6214 inst.instruction |= WRITE_BACK; 6215 6216 } 6217 else if (inst.operands[i].postind) 6218 { 6219 assert (inst.operands[i].writeback); 6220 if (is_t) 6221 inst.instruction |= WRITE_BACK; 6222 } 6223 else /* unindexed - only for coprocessor */ 6224 { 6225 inst.error = _("instruction does not accept unindexed addressing"); 6226 return; 6227 } 6228 6229 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) 6230 && (((inst.instruction & 0x000f0000) >> 16) 6231 == ((inst.instruction & 0x0000f000) >> 12))) 6232 as_warn ((inst.instruction & LOAD_BIT) 6233 ? _("destination register same as write-back base") 6234 : _("source register same as write-back base")); 6235} 6236 6237/* inst.operands[i] was set up by parse_address. Encode it into an 6238 ARM-format mode 2 load or store instruction. If is_t is true, 6239 reject forms that cannot be used with a T instruction (i.e. not 6240 post-indexed). */ 6241static void 6242encode_arm_addr_mode_2 (int i, bfd_boolean is_t) 6243{ 6244 encode_arm_addr_mode_common (i, is_t); 6245 6246 if (inst.operands[i].immisreg) 6247 { 6248 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ 6249 inst.instruction |= inst.operands[i].imm; 6250 if (!inst.operands[i].negative) 6251 inst.instruction |= INDEX_UP; 6252 if (inst.operands[i].shifted) 6253 { 6254 if (inst.operands[i].shift_kind == SHIFT_RRX) 6255 inst.instruction |= SHIFT_ROR << 5; 6256 else 6257 { 6258 inst.instruction |= inst.operands[i].shift_kind << 5; 6259 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 6260 } 6261 } 6262 } 6263 else /* immediate offset in inst.reloc */ 6264 { 6265 if (inst.reloc.type == BFD_RELOC_UNUSED) 6266 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; 6267 } 6268} 6269 6270/* inst.operands[i] was set up by parse_address. Encode it into an 6271 ARM-format mode 3 load or store instruction. Reject forms that 6272 cannot be used with such instructions. If is_t is true, reject 6273 forms that cannot be used with a T instruction (i.e. not 6274 post-indexed). */ 6275static void 6276encode_arm_addr_mode_3 (int i, bfd_boolean is_t) 6277{ 6278 if (inst.operands[i].immisreg && inst.operands[i].shifted) 6279 { 6280 inst.error = _("instruction does not accept scaled register index"); 6281 return; 6282 } 6283 6284 encode_arm_addr_mode_common (i, is_t); 6285 6286 if (inst.operands[i].immisreg) 6287 { 6288 inst.instruction |= inst.operands[i].imm; 6289 if (!inst.operands[i].negative) 6290 inst.instruction |= INDEX_UP; 6291 } 6292 else /* immediate offset in inst.reloc */ 6293 { 6294 inst.instruction |= HWOFFSET_IMM; 6295 if (inst.reloc.type == BFD_RELOC_UNUSED) 6296 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; 6297 } 6298} 6299 6300/* inst.operands[i] was set up by parse_address. Encode it into an 6301 ARM-format instruction. Reject all forms which cannot be encoded 6302 into a coprocessor load/store instruction. If wb_ok is false, 6303 reject use of writeback; if unind_ok is false, reject use of 6304 unindexed addressing. If reloc_override is not 0, use it instead 6305 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one 6306 (in which case it is preserved). */ 6307 6308static int 6309encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) 6310{ 6311 inst.instruction |= inst.operands[i].reg << 16; 6312 6313 assert (!(inst.operands[i].preind && inst.operands[i].postind)); 6314 6315 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ 6316 { 6317 assert (!inst.operands[i].writeback); 6318 if (!unind_ok) 6319 { 6320 inst.error = _("instruction does not support unindexed addressing"); 6321 return FAIL; 6322 } 6323 inst.instruction |= inst.operands[i].imm; 6324 inst.instruction |= INDEX_UP; 6325 return SUCCESS; 6326 } 6327 6328 if (inst.operands[i].preind) 6329 inst.instruction |= PRE_INDEX; 6330 6331 if (inst.operands[i].writeback) 6332 { 6333 if (inst.operands[i].reg == REG_PC) 6334 { 6335 inst.error = _("pc may not be used with write-back"); 6336 return FAIL; 6337 } 6338 if (!wb_ok) 6339 { 6340 inst.error = _("instruction does not support writeback"); 6341 return FAIL; 6342 } 6343 inst.instruction |= WRITE_BACK; 6344 } 6345 6346 if (reloc_override) 6347 inst.reloc.type = reloc_override; 6348 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC 6349 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) 6350 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) 6351 { 6352 if (thumb_mode) 6353 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; 6354 else 6355 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; 6356 } 6357 6358 return SUCCESS; 6359} 6360 6361/* inst.reloc.exp describes an "=expr" load pseudo-operation. 6362 Determine whether it can be performed with a move instruction; if 6363 it can, convert inst.instruction to that move instruction and 6364 return 1; if it can't, convert inst.instruction to a literal-pool 6365 load and return 0. If this is not a valid thing to do in the 6366 current context, set inst.error and return 1. 6367 6368 inst.operands[i] describes the destination register. */ 6369 6370static int 6371move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) 6372{ 6373 unsigned long tbit; 6374 6375 if (thumb_p) 6376 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; 6377 else 6378 tbit = LOAD_BIT; 6379 6380 if ((inst.instruction & tbit) == 0) 6381 { 6382 inst.error = _("invalid pseudo operation"); 6383 return 1; 6384 } 6385 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) 6386 { 6387 inst.error = _("constant expression expected"); 6388 return 1; 6389 } 6390 if (inst.reloc.exp.X_op == O_constant) 6391 { 6392 if (thumb_p) 6393 { 6394 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) 6395 { 6396 /* This can be done with a mov(1) instruction. */ 6397 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); 6398 inst.instruction |= inst.reloc.exp.X_add_number; 6399 return 1; 6400 } 6401 } 6402 else 6403 { 6404 int value = encode_arm_immediate (inst.reloc.exp.X_add_number); 6405 if (value != FAIL) 6406 { 6407 /* This can be done with a mov instruction. */ 6408 inst.instruction &= LITERAL_MASK; 6409 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); 6410 inst.instruction |= value & 0xfff; 6411 return 1; 6412 } 6413 6414 value = encode_arm_immediate (~inst.reloc.exp.X_add_number); 6415 if (value != FAIL) 6416 { 6417 /* This can be done with a mvn instruction. */ 6418 inst.instruction &= LITERAL_MASK; 6419 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); 6420 inst.instruction |= value & 0xfff; 6421 return 1; 6422 } 6423 } 6424 } 6425 6426 if (add_to_lit_pool () == FAIL) 6427 { 6428 inst.error = _("literal pool insertion failed"); 6429 return 1; 6430 } 6431 inst.operands[1].reg = REG_PC; 6432 inst.operands[1].isreg = 1; 6433 inst.operands[1].preind = 1; 6434 inst.reloc.pc_rel = 1; 6435 inst.reloc.type = (thumb_p 6436 ? BFD_RELOC_ARM_THUMB_OFFSET 6437 : (mode_3 6438 ? BFD_RELOC_ARM_HWLITERAL 6439 : BFD_RELOC_ARM_LITERAL)); 6440 return 0; 6441} 6442 6443/* Functions for instruction encoding, sorted by subarchitecture. 6444 First some generics; their names are taken from the conventional 6445 bit positions for register arguments in ARM format instructions. */ 6446 6447static void 6448do_noargs (void) 6449{ 6450} 6451 6452static void 6453do_rd (void) 6454{ 6455 inst.instruction |= inst.operands[0].reg << 12; 6456} 6457 6458static void 6459do_rd_rm (void) 6460{ 6461 inst.instruction |= inst.operands[0].reg << 12; 6462 inst.instruction |= inst.operands[1].reg; 6463} 6464 6465static void 6466do_rd_rn (void) 6467{ 6468 inst.instruction |= inst.operands[0].reg << 12; 6469 inst.instruction |= inst.operands[1].reg << 16; 6470} 6471 6472static void 6473do_rn_rd (void) 6474{ 6475 inst.instruction |= inst.operands[0].reg << 16; 6476 inst.instruction |= inst.operands[1].reg << 12; 6477} 6478 6479static void 6480do_rd_rm_rn (void) 6481{ 6482 unsigned Rn = inst.operands[2].reg; 6483 /* Enforce restrictions on SWP instruction. */ 6484 if ((inst.instruction & 0x0fbfffff) == 0x01000090) 6485 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, 6486 _("Rn must not overlap other operands")); 6487 inst.instruction |= inst.operands[0].reg << 12; 6488 inst.instruction |= inst.operands[1].reg; 6489 inst.instruction |= Rn << 16; 6490} 6491 6492static void 6493do_rd_rn_rm (void) 6494{ 6495 inst.instruction |= inst.operands[0].reg << 12; 6496 inst.instruction |= inst.operands[1].reg << 16; 6497 inst.instruction |= inst.operands[2].reg; 6498} 6499 6500static void 6501do_rm_rd_rn (void) 6502{ 6503 inst.instruction |= inst.operands[0].reg; 6504 inst.instruction |= inst.operands[1].reg << 12; 6505 inst.instruction |= inst.operands[2].reg << 16; 6506} 6507 6508static void 6509do_imm0 (void) 6510{ 6511 inst.instruction |= inst.operands[0].imm; 6512} 6513 6514static void 6515do_rd_cpaddr (void) 6516{ 6517 inst.instruction |= inst.operands[0].reg << 12; 6518 encode_arm_cp_address (1, TRUE, TRUE, 0); 6519} 6520 6521/* ARM instructions, in alphabetical order by function name (except 6522 that wrapper functions appear immediately after the function they 6523 wrap). */ 6524 6525/* This is a pseudo-op of the form "adr rd, label" to be converted 6526 into a relative address of the form "add rd, pc, #label-.-8". */ 6527 6528static void 6529do_adr (void) 6530{ 6531 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ 6532 6533 /* Frag hacking will turn this into a sub instruction if the offset turns 6534 out to be negative. */ 6535 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 6536 inst.reloc.pc_rel = 1; 6537 inst.reloc.exp.X_add_number -= 8; 6538} 6539 6540/* This is a pseudo-op of the form "adrl rd, label" to be converted 6541 into a relative address of the form: 6542 add rd, pc, #low(label-.-8)" 6543 add rd, rd, #high(label-.-8)" */ 6544 6545static void 6546do_adrl (void) 6547{ 6548 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ 6549 6550 /* Frag hacking will turn this into a sub instruction if the offset turns 6551 out to be negative. */ 6552 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; 6553 inst.reloc.pc_rel = 1; 6554 inst.size = INSN_SIZE * 2; 6555 inst.reloc.exp.X_add_number -= 8; 6556} 6557 6558static void 6559do_arit (void) 6560{ 6561 if (!inst.operands[1].present) 6562 inst.operands[1].reg = inst.operands[0].reg; 6563 inst.instruction |= inst.operands[0].reg << 12; 6564 inst.instruction |= inst.operands[1].reg << 16; 6565 encode_arm_shifter_operand (2); 6566} 6567 6568static void 6569do_barrier (void) 6570{ 6571 if (inst.operands[0].present) 6572 { 6573 constraint ((inst.instruction & 0xf0) != 0x40 6574 && inst.operands[0].imm != 0xf, 6575 "bad barrier type"); 6576 inst.instruction |= inst.operands[0].imm; 6577 } 6578 else 6579 inst.instruction |= 0xf; 6580} 6581 6582static void 6583do_bfc (void) 6584{ 6585 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; 6586 constraint (msb > 32, _("bit-field extends past end of register")); 6587 /* The instruction encoding stores the LSB and MSB, 6588 not the LSB and width. */ 6589 inst.instruction |= inst.operands[0].reg << 12; 6590 inst.instruction |= inst.operands[1].imm << 7; 6591 inst.instruction |= (msb - 1) << 16; 6592} 6593 6594static void 6595do_bfi (void) 6596{ 6597 unsigned int msb; 6598 6599 /* #0 in second position is alternative syntax for bfc, which is 6600 the same instruction but with REG_PC in the Rm field. */ 6601 if (!inst.operands[1].isreg) 6602 inst.operands[1].reg = REG_PC; 6603 6604 msb = inst.operands[2].imm + inst.operands[3].imm; 6605 constraint (msb > 32, _("bit-field extends past end of register")); 6606 /* The instruction encoding stores the LSB and MSB, 6607 not the LSB and width. */ 6608 inst.instruction |= inst.operands[0].reg << 12; 6609 inst.instruction |= inst.operands[1].reg; 6610 inst.instruction |= inst.operands[2].imm << 7; 6611 inst.instruction |= (msb - 1) << 16; 6612} 6613 6614static void 6615do_bfx (void) 6616{ 6617 constraint (inst.operands[2].imm + inst.operands[3].imm > 32, 6618 _("bit-field extends past end of register")); 6619 inst.instruction |= inst.operands[0].reg << 12; 6620 inst.instruction |= inst.operands[1].reg; 6621 inst.instruction |= inst.operands[2].imm << 7; 6622 inst.instruction |= (inst.operands[3].imm - 1) << 16; 6623} 6624 6625/* ARM V5 breakpoint instruction (argument parse) 6626 BKPT <16 bit unsigned immediate> 6627 Instruction is not conditional. 6628 The bit pattern given in insns[] has the COND_ALWAYS condition, 6629 and it is an error if the caller tried to override that. */ 6630 6631static void 6632do_bkpt (void) 6633{ 6634 /* Top 12 of 16 bits to bits 19:8. */ 6635 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; 6636 6637 /* Bottom 4 of 16 bits to bits 3:0. */ 6638 inst.instruction |= inst.operands[0].imm & 0xf; 6639} 6640 6641static void 6642encode_branch (int default_reloc) 6643{ 6644 if (inst.operands[0].hasreloc) 6645 { 6646 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32, 6647 _("the only suffix valid here is '(plt)'")); 6648 inst.reloc.type = BFD_RELOC_ARM_PLT32; 6649 } 6650 else 6651 { 6652 inst.reloc.type = default_reloc; 6653 } 6654 inst.reloc.pc_rel = 1; 6655} 6656 6657static void 6658do_branch (void) 6659{ 6660#ifdef OBJ_ELF 6661 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 6662 encode_branch (BFD_RELOC_ARM_PCREL_JUMP); 6663 else 6664#endif 6665 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); 6666} 6667 6668static void 6669do_bl (void) 6670{ 6671#ifdef OBJ_ELF 6672 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 6673 { 6674 if (inst.cond == COND_ALWAYS) 6675 encode_branch (BFD_RELOC_ARM_PCREL_CALL); 6676 else 6677 encode_branch (BFD_RELOC_ARM_PCREL_JUMP); 6678 } 6679 else 6680#endif 6681 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); 6682} 6683 6684/* ARM V5 branch-link-exchange instruction (argument parse) 6685 BLX <target_addr> ie BLX(1) 6686 BLX{<condition>} <Rm> ie BLX(2) 6687 Unfortunately, there are two different opcodes for this mnemonic. 6688 So, the insns[].value is not used, and the code here zaps values 6689 into inst.instruction. 6690 Also, the <target_addr> can be 25 bits, hence has its own reloc. */ 6691 6692static void 6693do_blx (void) 6694{ 6695 if (inst.operands[0].isreg) 6696 { 6697 /* Arg is a register; the opcode provided by insns[] is correct. 6698 It is not illegal to do "blx pc", just useless. */ 6699 if (inst.operands[0].reg == REG_PC) 6700 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); 6701 6702 inst.instruction |= inst.operands[0].reg; 6703 } 6704 else 6705 { 6706 /* Arg is an address; this instruction cannot be executed 6707 conditionally, and the opcode must be adjusted. */ 6708 constraint (inst.cond != COND_ALWAYS, BAD_COND); 6709 inst.instruction = 0xfa000000; 6710#ifdef OBJ_ELF 6711 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 6712 encode_branch (BFD_RELOC_ARM_PCREL_CALL); 6713 else 6714#endif 6715 encode_branch (BFD_RELOC_ARM_PCREL_BLX); 6716 } 6717} 6718 6719static void 6720do_bx (void) 6721{ 6722 if (inst.operands[0].reg == REG_PC) 6723 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); 6724 6725 inst.instruction |= inst.operands[0].reg; 6726} 6727 6728 6729/* ARM v5TEJ. Jump to Jazelle code. */ 6730 6731static void 6732do_bxj (void) 6733{ 6734 if (inst.operands[0].reg == REG_PC) 6735 as_tsktsk (_("use of r15 in bxj is not really useful")); 6736 6737 inst.instruction |= inst.operands[0].reg; 6738} 6739 6740/* Co-processor data operation: 6741 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} 6742 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ 6743static void 6744do_cdp (void) 6745{ 6746 inst.instruction |= inst.operands[0].reg << 8; 6747 inst.instruction |= inst.operands[1].imm << 20; 6748 inst.instruction |= inst.operands[2].reg << 12; 6749 inst.instruction |= inst.operands[3].reg << 16; 6750 inst.instruction |= inst.operands[4].reg; 6751 inst.instruction |= inst.operands[5].imm << 5; 6752} 6753 6754static void 6755do_cmp (void) 6756{ 6757 inst.instruction |= inst.operands[0].reg << 16; 6758 encode_arm_shifter_operand (1); 6759} 6760 6761/* Transfer between coprocessor and ARM registers. 6762 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} 6763 MRC2 6764 MCR{cond} 6765 MCR2 6766 6767 No special properties. */ 6768 6769static void 6770do_co_reg (void) 6771{ 6772 inst.instruction |= inst.operands[0].reg << 8; 6773 inst.instruction |= inst.operands[1].imm << 21; 6774 /* If this is a vector we are using the APSR_nzcv syntax, encode as r15 */ 6775 if (inst.operands[2].isvec != 0) 6776 inst.instruction |= 15 << 12; 6777 else 6778 inst.instruction |= inst.operands[2].reg << 12; 6779 inst.instruction |= inst.operands[3].reg << 16; 6780 inst.instruction |= inst.operands[4].reg; 6781 inst.instruction |= inst.operands[5].imm << 5; 6782} 6783 6784/* Transfer between coprocessor register and pair of ARM registers. 6785 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. 6786 MCRR2 6787 MRRC{cond} 6788 MRRC2 6789 6790 Two XScale instructions are special cases of these: 6791 6792 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 6793 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 6794 6795 Result unpredicatable if Rd or Rn is R15. */ 6796 6797static void 6798do_co_reg2c (void) 6799{ 6800 inst.instruction |= inst.operands[0].reg << 8; 6801 inst.instruction |= inst.operands[1].imm << 4; 6802 inst.instruction |= inst.operands[2].reg << 12; 6803 inst.instruction |= inst.operands[3].reg << 16; 6804 inst.instruction |= inst.operands[4].reg; 6805} 6806 6807static void 6808do_cpsi (void) 6809{ 6810 inst.instruction |= inst.operands[0].imm << 6; 6811 if (inst.operands[1].present) 6812 { 6813 inst.instruction |= CPSI_MMOD; 6814 inst.instruction |= inst.operands[1].imm; 6815 } 6816} 6817 6818static void 6819do_dbg (void) 6820{ 6821 inst.instruction |= inst.operands[0].imm; 6822} 6823 6824static void 6825do_it (void) 6826{ 6827 /* There is no IT instruction in ARM mode. We 6828 process it but do not generate code for it. */ 6829 inst.size = 0; 6830} 6831 6832static void 6833do_ldmstm (void) 6834{ 6835 int base_reg = inst.operands[0].reg; 6836 int range = inst.operands[1].imm; 6837 6838 inst.instruction |= base_reg << 16; 6839 inst.instruction |= range; 6840 6841 if (inst.operands[1].writeback) 6842 inst.instruction |= LDM_TYPE_2_OR_3; 6843 6844 if (inst.operands[0].writeback) 6845 { 6846 inst.instruction |= WRITE_BACK; 6847 /* Check for unpredictable uses of writeback. */ 6848 if (inst.instruction & LOAD_BIT) 6849 { 6850 /* Not allowed in LDM type 2. */ 6851 if ((inst.instruction & LDM_TYPE_2_OR_3) 6852 && ((range & (1 << REG_PC)) == 0)) 6853 as_warn (_("writeback of base register is UNPREDICTABLE")); 6854 /* Only allowed if base reg not in list for other types. */ 6855 else if (range & (1 << base_reg)) 6856 as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); 6857 } 6858 else /* STM. */ 6859 { 6860 /* Not allowed for type 2. */ 6861 if (inst.instruction & LDM_TYPE_2_OR_3) 6862 as_warn (_("writeback of base register is UNPREDICTABLE")); 6863 /* Only allowed if base reg not in list, or first in list. */ 6864 else if ((range & (1 << base_reg)) 6865 && (range & ((1 << base_reg) - 1))) 6866 as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); 6867 } 6868 } 6869} 6870 6871/* ARMv5TE load-consecutive (argument parse) 6872 Mode is like LDRH. 6873 6874 LDRccD R, mode 6875 STRccD R, mode. */ 6876 6877static void 6878do_ldrd (void) 6879{ 6880 constraint (inst.operands[0].reg % 2 != 0, 6881 _("first destination register must be even")); 6882 constraint (inst.operands[1].present 6883 && inst.operands[1].reg != inst.operands[0].reg + 1, 6884 _("can only load two consecutive registers")); 6885 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); 6886 constraint (!inst.operands[2].isreg, _("'[' expected")); 6887 6888 if (!inst.operands[1].present) 6889 inst.operands[1].reg = inst.operands[0].reg + 1; 6890 6891 if (inst.instruction & LOAD_BIT) 6892 { 6893 /* encode_arm_addr_mode_3 will diagnose overlap between the base 6894 register and the first register written; we have to diagnose 6895 overlap between the base and the second register written here. */ 6896 6897 if (inst.operands[2].reg == inst.operands[1].reg 6898 && (inst.operands[2].writeback || inst.operands[2].postind)) 6899 as_warn (_("base register written back, and overlaps " 6900 "second destination register")); 6901 6902 /* For an index-register load, the index register must not overlap the 6903 destination (even if not write-back). */ 6904 else if (inst.operands[2].immisreg 6905 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg 6906 || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) 6907 as_warn (_("index register overlaps destination register")); 6908 } 6909 6910 inst.instruction |= inst.operands[0].reg << 12; 6911 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); 6912} 6913 6914static void 6915do_ldrex (void) 6916{ 6917 constraint (!inst.operands[1].isreg || !inst.operands[1].preind 6918 || inst.operands[1].postind || inst.operands[1].writeback 6919 || inst.operands[1].immisreg || inst.operands[1].shifted 6920 || inst.operands[1].negative 6921 /* This can arise if the programmer has written 6922 strex rN, rM, foo 6923 or if they have mistakenly used a register name as the last 6924 operand, eg: 6925 strex rN, rM, rX 6926 It is very difficult to distinguish between these two cases 6927 because "rX" might actually be a label. ie the register 6928 name has been occluded by a symbol of the same name. So we 6929 just generate a general 'bad addressing mode' type error 6930 message and leave it up to the programmer to discover the 6931 true cause and fix their mistake. */ 6932 || (inst.operands[1].reg == REG_PC), 6933 BAD_ADDR_MODE); 6934 6935 constraint (inst.reloc.exp.X_op != O_constant 6936 || inst.reloc.exp.X_add_number != 0, 6937 _("offset must be zero in ARM encoding")); 6938 6939 inst.instruction |= inst.operands[0].reg << 12; 6940 inst.instruction |= inst.operands[1].reg << 16; 6941 inst.reloc.type = BFD_RELOC_UNUSED; 6942} 6943 6944static void 6945do_ldrexd (void) 6946{ 6947 constraint (inst.operands[0].reg % 2 != 0, 6948 _("even register required")); 6949 constraint (inst.operands[1].present 6950 && inst.operands[1].reg != inst.operands[0].reg + 1, 6951 _("can only load two consecutive registers")); 6952 /* If op 1 were present and equal to PC, this function wouldn't 6953 have been called in the first place. */ 6954 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); 6955 6956 inst.instruction |= inst.operands[0].reg << 12; 6957 inst.instruction |= inst.operands[2].reg << 16; 6958} 6959 6960static void 6961do_ldst (void) 6962{ 6963 inst.instruction |= inst.operands[0].reg << 12; 6964 if (!inst.operands[1].isreg) 6965 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) 6966 return; 6967 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); 6968} 6969 6970static void 6971do_ldstt (void) 6972{ 6973 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and 6974 reject [Rn,...]. */ 6975 if (inst.operands[1].preind) 6976 { 6977 constraint (inst.reloc.exp.X_op != O_constant || 6978 inst.reloc.exp.X_add_number != 0, 6979 _("this instruction requires a post-indexed address")); 6980 6981 inst.operands[1].preind = 0; 6982 inst.operands[1].postind = 1; 6983 inst.operands[1].writeback = 1; 6984 } 6985 inst.instruction |= inst.operands[0].reg << 12; 6986 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); 6987} 6988 6989/* Halfword and signed-byte load/store operations. */ 6990 6991static void 6992do_ldstv4 (void) 6993{ 6994 inst.instruction |= inst.operands[0].reg << 12; 6995 if (!inst.operands[1].isreg) 6996 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) 6997 return; 6998 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); 6999} 7000 7001static void 7002do_ldsttv4 (void) 7003{ 7004 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and 7005 reject [Rn,...]. */ 7006 if (inst.operands[1].preind) 7007 { 7008 constraint (inst.reloc.exp.X_op != O_constant || 7009 inst.reloc.exp.X_add_number != 0, 7010 _("this instruction requires a post-indexed address")); 7011 7012 inst.operands[1].preind = 0; 7013 inst.operands[1].postind = 1; 7014 inst.operands[1].writeback = 1; 7015 } 7016 inst.instruction |= inst.operands[0].reg << 12; 7017 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); 7018} 7019 7020/* Co-processor register load/store. 7021 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ 7022static void 7023do_lstc (void) 7024{ 7025 inst.instruction |= inst.operands[0].reg << 8; 7026 inst.instruction |= inst.operands[1].reg << 12; 7027 encode_arm_cp_address (2, TRUE, TRUE, 0); 7028} 7029 7030static void 7031do_mlas (void) 7032{ 7033 /* This restriction does not apply to mls (nor to mla in v6 or later). */ 7034 if (inst.operands[0].reg == inst.operands[1].reg 7035 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) 7036 && !(inst.instruction & 0x00400000)) 7037 as_tsktsk (_("Rd and Rm should be different in mla")); 7038 7039 inst.instruction |= inst.operands[0].reg << 16; 7040 inst.instruction |= inst.operands[1].reg; 7041 inst.instruction |= inst.operands[2].reg << 8; 7042 inst.instruction |= inst.operands[3].reg << 12; 7043} 7044 7045static void 7046do_mov (void) 7047{ 7048 inst.instruction |= inst.operands[0].reg << 12; 7049 encode_arm_shifter_operand (1); 7050} 7051 7052/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ 7053static void 7054do_mov16 (void) 7055{ 7056 bfd_vma imm; 7057 bfd_boolean top; 7058 7059 top = (inst.instruction & 0x00400000) != 0; 7060 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, 7061 _(":lower16: not allowed this instruction")); 7062 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, 7063 _(":upper16: not allowed instruction")); 7064 inst.instruction |= inst.operands[0].reg << 12; 7065 if (inst.reloc.type == BFD_RELOC_UNUSED) 7066 { 7067 imm = inst.reloc.exp.X_add_number; 7068 /* The value is in two pieces: 0:11, 16:19. */ 7069 inst.instruction |= (imm & 0x00000fff); 7070 inst.instruction |= (imm & 0x0000f000) << 4; 7071 } 7072} 7073 7074static void do_vfp_nsyn_opcode (const char *); 7075 7076static int 7077do_vfp_nsyn_mrs (void) 7078{ 7079 if (inst.operands[0].isvec) 7080 { 7081 if (inst.operands[1].reg != 1) 7082 first_error (_("operand 1 must be FPSCR")); 7083 memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); 7084 memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); 7085 do_vfp_nsyn_opcode ("fmstat"); 7086 } 7087 else if (inst.operands[1].isvec) 7088 do_vfp_nsyn_opcode ("fmrx"); 7089 else 7090 return FAIL; 7091 7092 return SUCCESS; 7093} 7094 7095static int 7096do_vfp_nsyn_msr (void) 7097{ 7098 if (inst.operands[0].isvec) 7099 do_vfp_nsyn_opcode ("fmxr"); 7100 else 7101 return FAIL; 7102 7103 return SUCCESS; 7104} 7105 7106static void 7107do_vfp_vmrs (void) 7108{ 7109 int rt; 7110 7111 /* The destination register can be r0-r14 or APSR_nzcv */ 7112 if (inst.operands[0].reg > 14) 7113 { 7114 inst.error = BAD_PC; 7115 return; 7116 } 7117 7118 /* If the destination is r13 and not in ARM mode then unprefictable */ 7119 if (thumb_mode && inst.operands[0].reg == REG_SP) 7120 { 7121 inst.error = BAD_SP; 7122 return; 7123 } 7124 7125 /* If the destination is APSR_nzcv */ 7126 if (inst.operands[0].isvec && inst.operands[1].reg != 1) 7127 { 7128 inst.error = BAD_VMRS; 7129 return; 7130 } 7131 7132 if (inst.operands[0].isvec) 7133 rt = 15; 7134 else 7135 rt = inst.operands[0].reg; 7136 7137 /* Or in the registers to use */ 7138 inst.instruction |= rt << 12; 7139 inst.instruction |= inst.operands[1].reg << 16; 7140} 7141 7142static void 7143do_vfp_vmsr (void) 7144{ 7145 /* The destination register can be r0-r14 or APSR_nzcv */ 7146 if (inst.operands[1].reg > 14) 7147 { 7148 inst.error = BAD_PC; 7149 return; 7150 } 7151 7152 /* If the destination is r13 and not in ARM mode then unprefictable */ 7153 if (thumb_mode && inst.operands[0].reg == REG_SP) 7154 { 7155 inst.error = BAD_SP; 7156 return; 7157 } 7158 7159 /* Or in the registers to use */ 7160 inst.instruction |= inst.operands[1].reg << 12; 7161 inst.instruction |= inst.operands[0].reg << 16; 7162} 7163 7164static void 7165do_mrs (void) 7166{ 7167 if (do_vfp_nsyn_mrs () == SUCCESS) 7168 return; 7169 7170 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ 7171 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) 7172 != (PSR_c|PSR_f), 7173 _("'CPSR' or 'SPSR' expected")); 7174 inst.instruction |= inst.operands[0].reg << 12; 7175 inst.instruction |= (inst.operands[1].imm & SPSR_BIT); 7176} 7177 7178/* Two possible forms: 7179 "{C|S}PSR_<field>, Rm", 7180 "{C|S}PSR_f, #expression". */ 7181 7182static void 7183do_msr (void) 7184{ 7185 if (do_vfp_nsyn_msr () == SUCCESS) 7186 return; 7187 7188 inst.instruction |= inst.operands[0].imm; 7189 if (inst.operands[1].isreg) 7190 inst.instruction |= inst.operands[1].reg; 7191 else 7192 { 7193 inst.instruction |= INST_IMMEDIATE; 7194 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 7195 inst.reloc.pc_rel = 0; 7196 } 7197} 7198 7199static void 7200do_mul (void) 7201{ 7202 if (!inst.operands[2].present) 7203 inst.operands[2].reg = inst.operands[0].reg; 7204 inst.instruction |= inst.operands[0].reg << 16; 7205 inst.instruction |= inst.operands[1].reg; 7206 inst.instruction |= inst.operands[2].reg << 8; 7207 7208 if (inst.operands[0].reg == inst.operands[1].reg 7209 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) 7210 as_tsktsk (_("Rd and Rm should be different in mul")); 7211} 7212 7213/* Long Multiply Parser 7214 UMULL RdLo, RdHi, Rm, Rs 7215 SMULL RdLo, RdHi, Rm, Rs 7216 UMLAL RdLo, RdHi, Rm, Rs 7217 SMLAL RdLo, RdHi, Rm, Rs. */ 7218 7219static void 7220do_mull (void) 7221{ 7222 inst.instruction |= inst.operands[0].reg << 12; 7223 inst.instruction |= inst.operands[1].reg << 16; 7224 inst.instruction |= inst.operands[2].reg; 7225 inst.instruction |= inst.operands[3].reg << 8; 7226 7227 /* rdhi, rdlo and rm must all be different prior to ARMv6. */ 7228 if (inst.operands[0].reg == inst.operands[1].reg 7229 || ((inst.operands[0].reg == inst.operands[2].reg 7230 || inst.operands[1].reg == inst.operands[2].reg) 7231 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))) 7232 as_tsktsk (_("rdhi, rdlo and rm must all be different")); 7233} 7234 7235static void 7236do_nop (void) 7237{ 7238 if (inst.operands[0].present) 7239 { 7240 /* Architectural NOP hints are CPSR sets with no bits selected. */ 7241 inst.instruction &= 0xf0000000; 7242 inst.instruction |= 0x0320f000 + inst.operands[0].imm; 7243 } 7244} 7245 7246/* ARM V6 Pack Halfword Bottom Top instruction (argument parse). 7247 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} 7248 Condition defaults to COND_ALWAYS. 7249 Error if Rd, Rn or Rm are R15. */ 7250 7251static void 7252do_pkhbt (void) 7253{ 7254 inst.instruction |= inst.operands[0].reg << 12; 7255 inst.instruction |= inst.operands[1].reg << 16; 7256 inst.instruction |= inst.operands[2].reg; 7257 if (inst.operands[3].present) 7258 encode_arm_shift (3); 7259} 7260 7261/* ARM V6 PKHTB (Argument Parse). */ 7262 7263static void 7264do_pkhtb (void) 7265{ 7266 if (!inst.operands[3].present) 7267 { 7268 /* If the shift specifier is omitted, turn the instruction 7269 into pkhbt rd, rm, rn. */ 7270 inst.instruction &= 0xfff00010; 7271 inst.instruction |= inst.operands[0].reg << 12; 7272 inst.instruction |= inst.operands[1].reg; 7273 inst.instruction |= inst.operands[2].reg << 16; 7274 } 7275 else 7276 { 7277 inst.instruction |= inst.operands[0].reg << 12; 7278 inst.instruction |= inst.operands[1].reg << 16; 7279 inst.instruction |= inst.operands[2].reg; 7280 encode_arm_shift (3); 7281 } 7282} 7283 7284/* ARMv5TE: Preload-Cache 7285 7286 PLD <addr_mode> 7287 7288 Syntactically, like LDR with B=1, W=0, L=1. */ 7289 7290static void 7291do_pld (void) 7292{ 7293 constraint (!inst.operands[0].isreg, 7294 _("'[' expected after PLD mnemonic")); 7295 constraint (inst.operands[0].postind, 7296 _("post-indexed expression used in preload instruction")); 7297 constraint (inst.operands[0].writeback, 7298 _("writeback used in preload instruction")); 7299 constraint (!inst.operands[0].preind, 7300 _("unindexed addressing used in preload instruction")); 7301 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); 7302} 7303 7304/* ARMv7: PLI <addr_mode> */ 7305static void 7306do_pli (void) 7307{ 7308 constraint (!inst.operands[0].isreg, 7309 _("'[' expected after PLI mnemonic")); 7310 constraint (inst.operands[0].postind, 7311 _("post-indexed expression used in preload instruction")); 7312 constraint (inst.operands[0].writeback, 7313 _("writeback used in preload instruction")); 7314 constraint (!inst.operands[0].preind, 7315 _("unindexed addressing used in preload instruction")); 7316 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); 7317 inst.instruction &= ~PRE_INDEX; 7318} 7319 7320static void 7321do_push_pop (void) 7322{ 7323 inst.operands[1] = inst.operands[0]; 7324 memset (&inst.operands[0], 0, sizeof inst.operands[0]); 7325 inst.operands[0].isreg = 1; 7326 inst.operands[0].writeback = 1; 7327 inst.operands[0].reg = REG_SP; 7328 do_ldmstm (); 7329} 7330 7331/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the 7332 word at the specified address and the following word 7333 respectively. 7334 Unconditionally executed. 7335 Error if Rn is R15. */ 7336 7337static void 7338do_rfe (void) 7339{ 7340 inst.instruction |= inst.operands[0].reg << 16; 7341 if (inst.operands[0].writeback) 7342 inst.instruction |= WRITE_BACK; 7343} 7344 7345/* ARM V6 ssat (argument parse). */ 7346 7347static void 7348do_ssat (void) 7349{ 7350 inst.instruction |= inst.operands[0].reg << 12; 7351 inst.instruction |= (inst.operands[1].imm - 1) << 16; 7352 inst.instruction |= inst.operands[2].reg; 7353 7354 if (inst.operands[3].present) 7355 encode_arm_shift (3); 7356} 7357 7358/* ARM V6 usat (argument parse). */ 7359 7360static void 7361do_usat (void) 7362{ 7363 inst.instruction |= inst.operands[0].reg << 12; 7364 inst.instruction |= inst.operands[1].imm << 16; 7365 inst.instruction |= inst.operands[2].reg; 7366 7367 if (inst.operands[3].present) 7368 encode_arm_shift (3); 7369} 7370 7371/* ARM V6 ssat16 (argument parse). */ 7372 7373static void 7374do_ssat16 (void) 7375{ 7376 inst.instruction |= inst.operands[0].reg << 12; 7377 inst.instruction |= ((inst.operands[1].imm - 1) << 16); 7378 inst.instruction |= inst.operands[2].reg; 7379} 7380 7381static void 7382do_usat16 (void) 7383{ 7384 inst.instruction |= inst.operands[0].reg << 12; 7385 inst.instruction |= inst.operands[1].imm << 16; 7386 inst.instruction |= inst.operands[2].reg; 7387} 7388 7389/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while 7390 preserving the other bits. 7391 7392 setend <endian_specifier>, where <endian_specifier> is either 7393 BE or LE. */ 7394 7395static void 7396do_setend (void) 7397{ 7398 if (inst.operands[0].imm) 7399 inst.instruction |= 0x200; 7400} 7401 7402static void 7403do_shift (void) 7404{ 7405 unsigned int Rm = (inst.operands[1].present 7406 ? inst.operands[1].reg 7407 : inst.operands[0].reg); 7408 7409 inst.instruction |= inst.operands[0].reg << 12; 7410 inst.instruction |= Rm; 7411 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ 7412 { 7413 inst.instruction |= inst.operands[2].reg << 8; 7414 inst.instruction |= SHIFT_BY_REG; 7415 } 7416 else 7417 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 7418} 7419 7420static void 7421do_smc (void) 7422{ 7423 inst.reloc.type = BFD_RELOC_ARM_SMC; 7424 inst.reloc.pc_rel = 0; 7425} 7426 7427static void 7428do_swi (void) 7429{ 7430 inst.reloc.type = BFD_RELOC_ARM_SWI; 7431 inst.reloc.pc_rel = 0; 7432} 7433 7434/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) 7435 SMLAxy{cond} Rd,Rm,Rs,Rn 7436 SMLAWy{cond} Rd,Rm,Rs,Rn 7437 Error if any register is R15. */ 7438 7439static void 7440do_smla (void) 7441{ 7442 inst.instruction |= inst.operands[0].reg << 16; 7443 inst.instruction |= inst.operands[1].reg; 7444 inst.instruction |= inst.operands[2].reg << 8; 7445 inst.instruction |= inst.operands[3].reg << 12; 7446} 7447 7448/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) 7449 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs 7450 Error if any register is R15. 7451 Warning if Rdlo == Rdhi. */ 7452 7453static void 7454do_smlal (void) 7455{ 7456 inst.instruction |= inst.operands[0].reg << 12; 7457 inst.instruction |= inst.operands[1].reg << 16; 7458 inst.instruction |= inst.operands[2].reg; 7459 inst.instruction |= inst.operands[3].reg << 8; 7460 7461 if (inst.operands[0].reg == inst.operands[1].reg) 7462 as_tsktsk (_("rdhi and rdlo must be different")); 7463} 7464 7465/* ARM V5E (El Segundo) signed-multiply (argument parse) 7466 SMULxy{cond} Rd,Rm,Rs 7467 Error if any register is R15. */ 7468 7469static void 7470do_smul (void) 7471{ 7472 inst.instruction |= inst.operands[0].reg << 16; 7473 inst.instruction |= inst.operands[1].reg; 7474 inst.instruction |= inst.operands[2].reg << 8; 7475} 7476 7477/* ARM V6 srs (argument parse). The variable fields in the encoding are 7478 the same for both ARM and Thumb-2. */ 7479 7480static void 7481do_srs (void) 7482{ 7483 int reg; 7484 7485 if (inst.operands[0].present) 7486 { 7487 reg = inst.operands[0].reg; 7488 constraint (reg != 13, _("SRS base register must be r13")); 7489 } 7490 else 7491 reg = 13; 7492 7493 inst.instruction |= reg << 16; 7494 inst.instruction |= inst.operands[1].imm; 7495 if (inst.operands[0].writeback || inst.operands[1].writeback) 7496 inst.instruction |= WRITE_BACK; 7497} 7498 7499/* ARM V6 strex (argument parse). */ 7500 7501static void 7502do_strex (void) 7503{ 7504 constraint (!inst.operands[2].isreg || !inst.operands[2].preind 7505 || inst.operands[2].postind || inst.operands[2].writeback 7506 || inst.operands[2].immisreg || inst.operands[2].shifted 7507 || inst.operands[2].negative 7508 /* See comment in do_ldrex(). */ 7509 || (inst.operands[2].reg == REG_PC), 7510 BAD_ADDR_MODE); 7511 7512 constraint (inst.operands[0].reg == inst.operands[1].reg 7513 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); 7514 7515 constraint (inst.reloc.exp.X_op != O_constant 7516 || inst.reloc.exp.X_add_number != 0, 7517 _("offset must be zero in ARM encoding")); 7518 7519 inst.instruction |= inst.operands[0].reg << 12; 7520 inst.instruction |= inst.operands[1].reg; 7521 inst.instruction |= inst.operands[2].reg << 16; 7522 inst.reloc.type = BFD_RELOC_UNUSED; 7523} 7524 7525static void 7526do_strexd (void) 7527{ 7528 constraint (inst.operands[1].reg % 2 != 0, 7529 _("even register required")); 7530 constraint (inst.operands[2].present 7531 && inst.operands[2].reg != inst.operands[1].reg + 1, 7532 _("can only store two consecutive registers")); 7533 /* If op 2 were present and equal to PC, this function wouldn't 7534 have been called in the first place. */ 7535 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); 7536 7537 constraint (inst.operands[0].reg == inst.operands[1].reg 7538 || inst.operands[0].reg == inst.operands[1].reg + 1 7539 || inst.operands[0].reg == inst.operands[3].reg, 7540 BAD_OVERLAP); 7541 7542 inst.instruction |= inst.operands[0].reg << 12; 7543 inst.instruction |= inst.operands[1].reg; 7544 inst.instruction |= inst.operands[3].reg << 16; 7545} 7546 7547/* ARM V6 SXTAH extracts a 16-bit value from a register, sign 7548 extends it to 32-bits, and adds the result to a value in another 7549 register. You can specify a rotation by 0, 8, 16, or 24 bits 7550 before extracting the 16-bit value. 7551 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} 7552 Condition defaults to COND_ALWAYS. 7553 Error if any register uses R15. */ 7554 7555static void 7556do_sxtah (void) 7557{ 7558 inst.instruction |= inst.operands[0].reg << 12; 7559 inst.instruction |= inst.operands[1].reg << 16; 7560 inst.instruction |= inst.operands[2].reg; 7561 inst.instruction |= inst.operands[3].imm << 10; 7562} 7563 7564/* ARM V6 SXTH. 7565 7566 SXTH {<cond>} <Rd>, <Rm>{, <rotation>} 7567 Condition defaults to COND_ALWAYS. 7568 Error if any register uses R15. */ 7569 7570static void 7571do_sxth (void) 7572{ 7573 inst.instruction |= inst.operands[0].reg << 12; 7574 inst.instruction |= inst.operands[1].reg; 7575 inst.instruction |= inst.operands[2].imm << 10; 7576} 7577 7578/* VFP instructions. In a logical order: SP variant first, monad 7579 before dyad, arithmetic then move then load/store. */ 7580 7581static void 7582do_vfp_sp_monadic (void) 7583{ 7584 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7585 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); 7586} 7587 7588static void 7589do_vfp_sp_dyadic (void) 7590{ 7591 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7592 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); 7593 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); 7594} 7595 7596static void 7597do_vfp_sp_compare_z (void) 7598{ 7599 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7600} 7601 7602static void 7603do_vfp_dp_sp_cvt (void) 7604{ 7605 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7606 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); 7607} 7608 7609static void 7610do_vfp_sp_dp_cvt (void) 7611{ 7612 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7613 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); 7614} 7615 7616static void 7617do_vfp_reg_from_sp (void) 7618{ 7619 inst.instruction |= inst.operands[0].reg << 12; 7620 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); 7621} 7622 7623static void 7624do_vfp_reg2_from_sp2 (void) 7625{ 7626 constraint (inst.operands[2].imm != 2, 7627 _("only two consecutive VFP SP registers allowed here")); 7628 inst.instruction |= inst.operands[0].reg << 12; 7629 inst.instruction |= inst.operands[1].reg << 16; 7630 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); 7631} 7632 7633static void 7634do_vfp_sp_from_reg (void) 7635{ 7636 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); 7637 inst.instruction |= inst.operands[1].reg << 12; 7638} 7639 7640static void 7641do_vfp_sp2_from_reg2 (void) 7642{ 7643 constraint (inst.operands[0].imm != 2, 7644 _("only two consecutive VFP SP registers allowed here")); 7645 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); 7646 inst.instruction |= inst.operands[1].reg << 12; 7647 inst.instruction |= inst.operands[2].reg << 16; 7648} 7649 7650static void 7651do_vfp_sp_ldst (void) 7652{ 7653 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7654 encode_arm_cp_address (1, FALSE, TRUE, 0); 7655} 7656 7657static void 7658do_vfp_dp_ldst (void) 7659{ 7660 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7661 encode_arm_cp_address (1, FALSE, TRUE, 0); 7662} 7663 7664 7665static void 7666vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) 7667{ 7668 if (inst.operands[0].writeback) 7669 inst.instruction |= WRITE_BACK; 7670 else 7671 constraint (ldstm_type != VFP_LDSTMIA, 7672 _("this addressing mode requires base-register writeback")); 7673 inst.instruction |= inst.operands[0].reg << 16; 7674 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); 7675 inst.instruction |= inst.operands[1].imm; 7676} 7677 7678static void 7679vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) 7680{ 7681 int count; 7682 7683 if (inst.operands[0].writeback) 7684 inst.instruction |= WRITE_BACK; 7685 else 7686 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, 7687 _("this addressing mode requires base-register writeback")); 7688 7689 inst.instruction |= inst.operands[0].reg << 16; 7690 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 7691 7692 count = inst.operands[1].imm << 1; 7693 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) 7694 count += 1; 7695 7696 inst.instruction |= count; 7697} 7698 7699static void 7700do_vfp_sp_ldstmia (void) 7701{ 7702 vfp_sp_ldstm (VFP_LDSTMIA); 7703} 7704 7705static void 7706do_vfp_sp_ldstmdb (void) 7707{ 7708 vfp_sp_ldstm (VFP_LDSTMDB); 7709} 7710 7711static void 7712do_vfp_dp_ldstmia (void) 7713{ 7714 vfp_dp_ldstm (VFP_LDSTMIA); 7715} 7716 7717static void 7718do_vfp_dp_ldstmdb (void) 7719{ 7720 vfp_dp_ldstm (VFP_LDSTMDB); 7721} 7722 7723static void 7724do_vfp_xp_ldstmia (void) 7725{ 7726 vfp_dp_ldstm (VFP_LDSTMIAX); 7727} 7728 7729static void 7730do_vfp_xp_ldstmdb (void) 7731{ 7732 vfp_dp_ldstm (VFP_LDSTMDBX); 7733} 7734 7735static void 7736do_vfp_dp_rd_rm (void) 7737{ 7738 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7739 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); 7740} 7741 7742static void 7743do_vfp_dp_rn_rd (void) 7744{ 7745 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); 7746 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 7747} 7748 7749static void 7750do_vfp_dp_rd_rn (void) 7751{ 7752 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7753 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); 7754} 7755 7756static void 7757do_vfp_dp_rd_rn_rm (void) 7758{ 7759 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7760 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); 7761 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); 7762} 7763 7764static void 7765do_vfp_dp_rd (void) 7766{ 7767 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7768} 7769 7770static void 7771do_vfp_dp_rm_rd_rn (void) 7772{ 7773 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); 7774 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 7775 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); 7776} 7777 7778/* VFPv3 instructions. */ 7779static void 7780do_vfp_sp_const (void) 7781{ 7782 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7783 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; 7784 inst.instruction |= (inst.operands[1].imm & 0x0f); 7785} 7786 7787static void 7788do_vfp_dp_const (void) 7789{ 7790 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7791 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; 7792 inst.instruction |= (inst.operands[1].imm & 0x0f); 7793} 7794 7795static void 7796vfp_conv (int srcsize) 7797{ 7798 unsigned immbits = srcsize - inst.operands[1].imm; 7799 inst.instruction |= (immbits & 1) << 5; 7800 inst.instruction |= (immbits >> 1); 7801} 7802 7803static void 7804do_vfp_sp_conv_16 (void) 7805{ 7806 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7807 vfp_conv (16); 7808} 7809 7810static void 7811do_vfp_dp_conv_16 (void) 7812{ 7813 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7814 vfp_conv (16); 7815} 7816 7817static void 7818do_vfp_sp_conv_32 (void) 7819{ 7820 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7821 vfp_conv (32); 7822} 7823 7824static void 7825do_vfp_dp_conv_32 (void) 7826{ 7827 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7828 vfp_conv (32); 7829} 7830 7831 7832/* FPA instructions. Also in a logical order. */ 7833 7834static void 7835do_fpa_cmp (void) 7836{ 7837 inst.instruction |= inst.operands[0].reg << 16; 7838 inst.instruction |= inst.operands[1].reg; 7839} 7840 7841static void 7842do_fpa_ldmstm (void) 7843{ 7844 inst.instruction |= inst.operands[0].reg << 12; 7845 switch (inst.operands[1].imm) 7846 { 7847 case 1: inst.instruction |= CP_T_X; break; 7848 case 2: inst.instruction |= CP_T_Y; break; 7849 case 3: inst.instruction |= CP_T_Y | CP_T_X; break; 7850 case 4: break; 7851 default: abort (); 7852 } 7853 7854 if (inst.instruction & (PRE_INDEX | INDEX_UP)) 7855 { 7856 /* The instruction specified "ea" or "fd", so we can only accept 7857 [Rn]{!}. The instruction does not really support stacking or 7858 unstacking, so we have to emulate these by setting appropriate 7859 bits and offsets. */ 7860 constraint (inst.reloc.exp.X_op != O_constant 7861 || inst.reloc.exp.X_add_number != 0, 7862 _("this instruction does not support indexing")); 7863 7864 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) 7865 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; 7866 7867 if (!(inst.instruction & INDEX_UP)) 7868 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; 7869 7870 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) 7871 { 7872 inst.operands[2].preind = 0; 7873 inst.operands[2].postind = 1; 7874 } 7875 } 7876 7877 encode_arm_cp_address (2, TRUE, TRUE, 0); 7878} 7879 7880 7881/* iWMMXt instructions: strictly in alphabetical order. */ 7882 7883static void 7884do_iwmmxt_tandorc (void) 7885{ 7886 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); 7887} 7888 7889static void 7890do_iwmmxt_textrc (void) 7891{ 7892 inst.instruction |= inst.operands[0].reg << 12; 7893 inst.instruction |= inst.operands[1].imm; 7894} 7895 7896static void 7897do_iwmmxt_textrm (void) 7898{ 7899 inst.instruction |= inst.operands[0].reg << 12; 7900 inst.instruction |= inst.operands[1].reg << 16; 7901 inst.instruction |= inst.operands[2].imm; 7902} 7903 7904static void 7905do_iwmmxt_tinsr (void) 7906{ 7907 inst.instruction |= inst.operands[0].reg << 16; 7908 inst.instruction |= inst.operands[1].reg << 12; 7909 inst.instruction |= inst.operands[2].imm; 7910} 7911 7912static void 7913do_iwmmxt_tmia (void) 7914{ 7915 inst.instruction |= inst.operands[0].reg << 5; 7916 inst.instruction |= inst.operands[1].reg; 7917 inst.instruction |= inst.operands[2].reg << 12; 7918} 7919 7920static void 7921do_iwmmxt_waligni (void) 7922{ 7923 inst.instruction |= inst.operands[0].reg << 12; 7924 inst.instruction |= inst.operands[1].reg << 16; 7925 inst.instruction |= inst.operands[2].reg; 7926 inst.instruction |= inst.operands[3].imm << 20; 7927} 7928 7929static void 7930do_iwmmxt_wmerge (void) 7931{ 7932 inst.instruction |= inst.operands[0].reg << 12; 7933 inst.instruction |= inst.operands[1].reg << 16; 7934 inst.instruction |= inst.operands[2].reg; 7935 inst.instruction |= inst.operands[3].imm << 21; 7936} 7937 7938static void 7939do_iwmmxt_wmov (void) 7940{ 7941 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ 7942 inst.instruction |= inst.operands[0].reg << 12; 7943 inst.instruction |= inst.operands[1].reg << 16; 7944 inst.instruction |= inst.operands[1].reg; 7945} 7946 7947static void 7948do_iwmmxt_wldstbh (void) 7949{ 7950 int reloc; 7951 inst.instruction |= inst.operands[0].reg << 12; 7952 if (thumb_mode) 7953 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; 7954 else 7955 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; 7956 encode_arm_cp_address (1, TRUE, FALSE, reloc); 7957} 7958 7959static void 7960do_iwmmxt_wldstw (void) 7961{ 7962 /* RIWR_RIWC clears .isreg for a control register. */ 7963 if (!inst.operands[0].isreg) 7964 { 7965 constraint (inst.cond != COND_ALWAYS, BAD_COND); 7966 inst.instruction |= 0xf0000000; 7967 } 7968 7969 inst.instruction |= inst.operands[0].reg << 12; 7970 encode_arm_cp_address (1, TRUE, TRUE, 0); 7971} 7972 7973static void 7974do_iwmmxt_wldstd (void) 7975{ 7976 inst.instruction |= inst.operands[0].reg << 12; 7977 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) 7978 && inst.operands[1].immisreg) 7979 { 7980 inst.instruction &= ~0x1a000ff; 7981 inst.instruction |= (0xf << 28); 7982 if (inst.operands[1].preind) 7983 inst.instruction |= PRE_INDEX; 7984 if (!inst.operands[1].negative) 7985 inst.instruction |= INDEX_UP; 7986 if (inst.operands[1].writeback) 7987 inst.instruction |= WRITE_BACK; 7988 inst.instruction |= inst.operands[1].reg << 16; 7989 inst.instruction |= inst.reloc.exp.X_add_number << 4; 7990 inst.instruction |= inst.operands[1].imm; 7991 } 7992 else 7993 encode_arm_cp_address (1, TRUE, FALSE, 0); 7994} 7995 7996static void 7997do_iwmmxt_wshufh (void) 7998{ 7999 inst.instruction |= inst.operands[0].reg << 12; 8000 inst.instruction |= inst.operands[1].reg << 16; 8001 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); 8002 inst.instruction |= (inst.operands[2].imm & 0x0f); 8003} 8004 8005static void 8006do_iwmmxt_wzero (void) 8007{ 8008 /* WZERO reg is an alias for WANDN reg, reg, reg. */ 8009 inst.instruction |= inst.operands[0].reg; 8010 inst.instruction |= inst.operands[0].reg << 12; 8011 inst.instruction |= inst.operands[0].reg << 16; 8012} 8013 8014static void 8015do_iwmmxt_wrwrwr_or_imm5 (void) 8016{ 8017 if (inst.operands[2].isreg) 8018 do_rd_rn_rm (); 8019 else { 8020 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), 8021 _("immediate operand requires iWMMXt2")); 8022 do_rd_rn (); 8023 if (inst.operands[2].imm == 0) 8024 { 8025 switch ((inst.instruction >> 20) & 0xf) 8026 { 8027 case 4: 8028 case 5: 8029 case 6: 8030 case 7: 8031 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ 8032 inst.operands[2].imm = 16; 8033 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); 8034 break; 8035 case 8: 8036 case 9: 8037 case 10: 8038 case 11: 8039 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ 8040 inst.operands[2].imm = 32; 8041 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); 8042 break; 8043 case 12: 8044 case 13: 8045 case 14: 8046 case 15: 8047 { 8048 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ 8049 unsigned long wrn; 8050 wrn = (inst.instruction >> 16) & 0xf; 8051 inst.instruction &= 0xff0fff0f; 8052 inst.instruction |= wrn; 8053 /* Bail out here; the instruction is now assembled. */ 8054 return; 8055 } 8056 } 8057 } 8058 /* Map 32 -> 0, etc. */ 8059 inst.operands[2].imm &= 0x1f; 8060 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); 8061 } 8062} 8063 8064/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register 8065 operations first, then control, shift, and load/store. */ 8066 8067/* Insns like "foo X,Y,Z". */ 8068 8069static void 8070do_mav_triple (void) 8071{ 8072 inst.instruction |= inst.operands[0].reg << 16; 8073 inst.instruction |= inst.operands[1].reg; 8074 inst.instruction |= inst.operands[2].reg << 12; 8075} 8076 8077/* Insns like "foo W,X,Y,Z". 8078 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ 8079 8080static void 8081do_mav_quad (void) 8082{ 8083 inst.instruction |= inst.operands[0].reg << 5; 8084 inst.instruction |= inst.operands[1].reg << 12; 8085 inst.instruction |= inst.operands[2].reg << 16; 8086 inst.instruction |= inst.operands[3].reg; 8087} 8088 8089/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ 8090static void 8091do_mav_dspsc (void) 8092{ 8093 inst.instruction |= inst.operands[1].reg << 12; 8094} 8095 8096/* Maverick shift immediate instructions. 8097 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. 8098 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ 8099 8100static void 8101do_mav_shift (void) 8102{ 8103 int imm = inst.operands[2].imm; 8104 8105 inst.instruction |= inst.operands[0].reg << 12; 8106 inst.instruction |= inst.operands[1].reg << 16; 8107 8108 /* Bits 0-3 of the insn should have bits 0-3 of the immediate. 8109 Bits 5-7 of the insn should have bits 4-6 of the immediate. 8110 Bit 4 should be 0. */ 8111 imm = (imm & 0xf) | ((imm & 0x70) << 1); 8112 8113 inst.instruction |= imm; 8114} 8115 8116/* XScale instructions. Also sorted arithmetic before move. */ 8117 8118/* Xscale multiply-accumulate (argument parse) 8119 MIAcc acc0,Rm,Rs 8120 MIAPHcc acc0,Rm,Rs 8121 MIAxycc acc0,Rm,Rs. */ 8122 8123static void 8124do_xsc_mia (void) 8125{ 8126 inst.instruction |= inst.operands[1].reg; 8127 inst.instruction |= inst.operands[2].reg << 12; 8128} 8129 8130/* Xscale move-accumulator-register (argument parse) 8131 8132 MARcc acc0,RdLo,RdHi. */ 8133 8134static void 8135do_xsc_mar (void) 8136{ 8137 inst.instruction |= inst.operands[1].reg << 12; 8138 inst.instruction |= inst.operands[2].reg << 16; 8139} 8140 8141/* Xscale move-register-accumulator (argument parse) 8142 8143 MRAcc RdLo,RdHi,acc0. */ 8144 8145static void 8146do_xsc_mra (void) 8147{ 8148 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); 8149 inst.instruction |= inst.operands[0].reg << 12; 8150 inst.instruction |= inst.operands[1].reg << 16; 8151} 8152 8153/* Encoding functions relevant only to Thumb. */ 8154 8155/* inst.operands[i] is a shifted-register operand; encode 8156 it into inst.instruction in the format used by Thumb32. */ 8157 8158static void 8159encode_thumb32_shifted_operand (int i) 8160{ 8161 unsigned int value = inst.reloc.exp.X_add_number; 8162 unsigned int shift = inst.operands[i].shift_kind; 8163 8164 constraint (inst.operands[i].immisreg, 8165 _("shift by register not allowed in thumb mode")); 8166 inst.instruction |= inst.operands[i].reg; 8167 if (shift == SHIFT_RRX) 8168 inst.instruction |= SHIFT_ROR << 4; 8169 else 8170 { 8171 constraint (inst.reloc.exp.X_op != O_constant, 8172 _("expression too complex")); 8173 8174 constraint (value > 32 8175 || (value == 32 && (shift == SHIFT_LSL 8176 || shift == SHIFT_ROR)), 8177 _("shift expression is too large")); 8178 8179 if (value == 0) 8180 shift = SHIFT_LSL; 8181 else if (value == 32) 8182 value = 0; 8183 8184 inst.instruction |= shift << 4; 8185 inst.instruction |= (value & 0x1c) << 10; 8186 inst.instruction |= (value & 0x03) << 6; 8187 } 8188} 8189 8190 8191/* inst.operands[i] was set up by parse_address. Encode it into a 8192 Thumb32 format load or store instruction. Reject forms that cannot 8193 be used with such instructions. If is_t is true, reject forms that 8194 cannot be used with a T instruction; if is_d is true, reject forms 8195 that cannot be used with a D instruction. */ 8196 8197static void 8198encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) 8199{ 8200 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); 8201 8202 constraint (!inst.operands[i].isreg, 8203 _("Instruction does not support =N addresses")); 8204 8205 inst.instruction |= inst.operands[i].reg << 16; 8206 if (inst.operands[i].immisreg) 8207 { 8208 constraint (is_pc, _("cannot use register index with PC-relative addressing")); 8209 constraint (is_t || is_d, _("cannot use register index with this instruction")); 8210 constraint (inst.operands[i].negative, 8211 _("Thumb does not support negative register indexing")); 8212 constraint (inst.operands[i].postind, 8213 _("Thumb does not support register post-indexing")); 8214 constraint (inst.operands[i].writeback, 8215 _("Thumb does not support register indexing with writeback")); 8216 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, 8217 _("Thumb supports only LSL in shifted register indexing")); 8218 8219 inst.instruction |= inst.operands[i].imm; 8220 if (inst.operands[i].shifted) 8221 { 8222 constraint (inst.reloc.exp.X_op != O_constant, 8223 _("expression too complex")); 8224 constraint (inst.reloc.exp.X_add_number < 0 8225 || inst.reloc.exp.X_add_number > 3, 8226 _("shift out of range")); 8227 inst.instruction |= inst.reloc.exp.X_add_number << 4; 8228 } 8229 inst.reloc.type = BFD_RELOC_UNUSED; 8230 } 8231 else if (inst.operands[i].preind) 8232 { 8233 constraint (is_pc && inst.operands[i].writeback, 8234 _("cannot use writeback with PC-relative addressing")); 8235 constraint (is_t && inst.operands[i].writeback, 8236 _("cannot use writeback with this instruction")); 8237 8238 if (is_d) 8239 { 8240 inst.instruction |= 0x01000000; 8241 if (inst.operands[i].writeback) 8242 inst.instruction |= 0x00200000; 8243 } 8244 else 8245 { 8246 inst.instruction |= 0x00000c00; 8247 if (inst.operands[i].writeback) 8248 inst.instruction |= 0x00000100; 8249 } 8250 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; 8251 } 8252 else if (inst.operands[i].postind) 8253 { 8254 assert (inst.operands[i].writeback); 8255 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); 8256 constraint (is_t, _("cannot use post-indexing with this instruction")); 8257 8258 if (is_d) 8259 inst.instruction |= 0x00200000; 8260 else 8261 inst.instruction |= 0x00000900; 8262 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; 8263 } 8264 else /* unindexed - only for coprocessor */ 8265 inst.error = _("instruction does not accept unindexed addressing"); 8266} 8267 8268/* Table of Thumb instructions which exist in both 16- and 32-bit 8269 encodings (the latter only in post-V6T2 cores). The index is the 8270 value used in the insns table below. When there is more than one 8271 possible 16-bit encoding for the instruction, this table always 8272 holds variant (1). 8273 Also contains several pseudo-instructions used during relaxation. */ 8274#define T16_32_TAB \ 8275 X(adc, 4140, eb400000), \ 8276 X(adcs, 4140, eb500000), \ 8277 X(add, 1c00, eb000000), \ 8278 X(adds, 1c00, eb100000), \ 8279 X(addi, 0000, f1000000), \ 8280 X(addis, 0000, f1100000), \ 8281 X(add_pc,000f, f20f0000), \ 8282 X(add_sp,000d, f10d0000), \ 8283 X(adr, 000f, f20f0000), \ 8284 X(and, 4000, ea000000), \ 8285 X(ands, 4000, ea100000), \ 8286 X(asr, 1000, fa40f000), \ 8287 X(asrs, 1000, fa50f000), \ 8288 X(b, e000, f000b000), \ 8289 X(bcond, d000, f0008000), \ 8290 X(bic, 4380, ea200000), \ 8291 X(bics, 4380, ea300000), \ 8292 X(cmn, 42c0, eb100f00), \ 8293 X(cmp, 2800, ebb00f00), \ 8294 X(cpsie, b660, f3af8400), \ 8295 X(cpsid, b670, f3af8600), \ 8296 X(cpy, 4600, ea4f0000), \ 8297 X(dec_sp,80dd, f1ad0d00), \ 8298 X(eor, 4040, ea800000), \ 8299 X(eors, 4040, ea900000), \ 8300 X(inc_sp,00dd, f10d0d00), \ 8301 X(ldmia, c800, e8900000), \ 8302 X(ldr, 6800, f8500000), \ 8303 X(ldrb, 7800, f8100000), \ 8304 X(ldrh, 8800, f8300000), \ 8305 X(ldrsb, 5600, f9100000), \ 8306 X(ldrsh, 5e00, f9300000), \ 8307 X(ldr_pc,4800, f85f0000), \ 8308 X(ldr_pc2,4800, f85f0000), \ 8309 X(ldr_sp,9800, f85d0000), \ 8310 X(lsl, 0000, fa00f000), \ 8311 X(lsls, 0000, fa10f000), \ 8312 X(lsr, 0800, fa20f000), \ 8313 X(lsrs, 0800, fa30f000), \ 8314 X(mov, 2000, ea4f0000), \ 8315 X(movs, 2000, ea5f0000), \ 8316 X(mul, 4340, fb00f000), \ 8317 X(muls, 4340, ffffffff), /* no 32b muls */ \ 8318 X(mvn, 43c0, ea6f0000), \ 8319 X(mvns, 43c0, ea7f0000), \ 8320 X(neg, 4240, f1c00000), /* rsb #0 */ \ 8321 X(negs, 4240, f1d00000), /* rsbs #0 */ \ 8322 X(orr, 4300, ea400000), \ 8323 X(orrs, 4300, ea500000), \ 8324 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \ 8325 X(push, b400, e92d0000), /* stmdb sp!,... */ \ 8326 X(rev, ba00, fa90f080), \ 8327 X(rev16, ba40, fa90f090), \ 8328 X(revsh, bac0, fa90f0b0), \ 8329 X(ror, 41c0, fa60f000), \ 8330 X(rors, 41c0, fa70f000), \ 8331 X(sbc, 4180, eb600000), \ 8332 X(sbcs, 4180, eb700000), \ 8333 X(stmia, c000, e8800000), \ 8334 X(str, 6000, f8400000), \ 8335 X(strb, 7000, f8000000), \ 8336 X(strh, 8000, f8200000), \ 8337 X(str_sp,9000, f84d0000), \ 8338 X(sub, 1e00, eba00000), \ 8339 X(subs, 1e00, ebb00000), \ 8340 X(subi, 8000, f1a00000), \ 8341 X(subis, 8000, f1b00000), \ 8342 X(sxtb, b240, fa4ff080), \ 8343 X(sxth, b200, fa0ff080), \ 8344 X(tst, 4200, ea100f00), \ 8345 X(uxtb, b2c0, fa5ff080), \ 8346 X(uxth, b280, fa1ff080), \ 8347 X(nop, bf00, f3af8000), \ 8348 X(yield, bf10, f3af8001), \ 8349 X(wfe, bf20, f3af8002), \ 8350 X(wfi, bf30, f3af8003), \ 8351 X(sev, bf40, f3af9004), /* typo, 8004? */ 8352 8353/* To catch errors in encoding functions, the codes are all offset by 8354 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined 8355 as 16-bit instructions. */ 8356#define X(a,b,c) T_MNEM_##a 8357enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; 8358#undef X 8359 8360#define X(a,b,c) 0x##b 8361static const unsigned short thumb_op16[] = { T16_32_TAB }; 8362#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) 8363#undef X 8364 8365#define X(a,b,c) 0x##c 8366static const unsigned int thumb_op32[] = { T16_32_TAB }; 8367#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) 8368#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) 8369#undef X 8370#undef T16_32_TAB 8371 8372/* Thumb instruction encoders, in alphabetical order. */ 8373 8374/* ADDW or SUBW. */ 8375static void 8376do_t_add_sub_w (void) 8377{ 8378 int Rd, Rn; 8379 8380 Rd = inst.operands[0].reg; 8381 Rn = inst.operands[1].reg; 8382 8383 constraint (Rd == 15, _("PC not allowed as destination")); 8384 inst.instruction |= (Rn << 16) | (Rd << 8); 8385 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; 8386} 8387 8388/* Parse an add or subtract instruction. We get here with inst.instruction 8389 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ 8390 8391static void 8392do_t_add_sub (void) 8393{ 8394 int Rd, Rs, Rn; 8395 8396 Rd = inst.operands[0].reg; 8397 Rs = (inst.operands[1].present 8398 ? inst.operands[1].reg /* Rd, Rs, foo */ 8399 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 8400 8401 if (unified_syntax) 8402 { 8403 bfd_boolean flags; 8404 bfd_boolean narrow; 8405 int opcode; 8406 8407 flags = (inst.instruction == T_MNEM_adds 8408 || inst.instruction == T_MNEM_subs); 8409 if (flags) 8410 narrow = (current_it_mask == 0); 8411 else 8412 narrow = (current_it_mask != 0); 8413 if (!inst.operands[2].isreg) 8414 { 8415 int add; 8416 8417 add = (inst.instruction == T_MNEM_add 8418 || inst.instruction == T_MNEM_adds); 8419 opcode = 0; 8420 if (inst.size_req != 4) 8421 { 8422 /* Attempt to use a narrow opcode, with relaxation if 8423 appropriate. */ 8424 if (Rd == REG_SP && Rs == REG_SP && !flags) 8425 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; 8426 else if (Rd <= 7 && Rs == REG_SP && add && !flags) 8427 opcode = T_MNEM_add_sp; 8428 else if (Rd <= 7 && Rs == REG_PC && add && !flags) 8429 opcode = T_MNEM_add_pc; 8430 else if (Rd <= 7 && Rs <= 7 && narrow) 8431 { 8432 if (flags) 8433 opcode = add ? T_MNEM_addis : T_MNEM_subis; 8434 else 8435 opcode = add ? T_MNEM_addi : T_MNEM_subi; 8436 } 8437 if (opcode) 8438 { 8439 inst.instruction = THUMB_OP16(opcode); 8440 inst.instruction |= (Rd << 4) | Rs; 8441 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 8442 if (inst.size_req != 2) 8443 inst.relax = opcode; 8444 } 8445 else 8446 constraint (inst.size_req == 2, BAD_HIREG); 8447 } 8448 if (inst.size_req == 4 8449 || (inst.size_req != 2 && !opcode)) 8450 { 8451 if (Rd == REG_PC) 8452 { 8453 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, 8454 _("only SUBS PC, LR, #const allowed")); 8455 constraint (inst.reloc.exp.X_op != O_constant, 8456 _("expression too complex")); 8457 constraint (inst.reloc.exp.X_add_number < 0 8458 || inst.reloc.exp.X_add_number > 0xff, 8459 _("immediate value out of range")); 8460 inst.instruction = T2_SUBS_PC_LR 8461 | inst.reloc.exp.X_add_number; 8462 inst.reloc.type = BFD_RELOC_UNUSED; 8463 return; 8464 } 8465 else if (Rs == REG_PC) 8466 { 8467 /* Always use addw/subw. */ 8468 inst.instruction = add ? 0xf20f0000 : 0xf2af0000; 8469 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; 8470 } 8471 else 8472 { 8473 inst.instruction = THUMB_OP32 (inst.instruction); 8474 inst.instruction = (inst.instruction & 0xe1ffffff) 8475 | 0x10000000; 8476 if (flags) 8477 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 8478 else 8479 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; 8480 } 8481 inst.instruction |= Rd << 8; 8482 inst.instruction |= Rs << 16; 8483 } 8484 } 8485 else 8486 { 8487 Rn = inst.operands[2].reg; 8488 /* See if we can do this with a 16-bit instruction. */ 8489 if (!inst.operands[2].shifted && inst.size_req != 4) 8490 { 8491 if (Rd > 7 || Rs > 7 || Rn > 7) 8492 narrow = FALSE; 8493 8494 if (narrow) 8495 { 8496 inst.instruction = ((inst.instruction == T_MNEM_adds 8497 || inst.instruction == T_MNEM_add) 8498 ? T_OPCODE_ADD_R3 8499 : T_OPCODE_SUB_R3); 8500 inst.instruction |= Rd | (Rs << 3) | (Rn << 6); 8501 return; 8502 } 8503 8504 if (inst.instruction == T_MNEM_add) 8505 { 8506 if (Rd == Rs) 8507 { 8508 inst.instruction = T_OPCODE_ADD_HI; 8509 inst.instruction |= (Rd & 8) << 4; 8510 inst.instruction |= (Rd & 7); 8511 inst.instruction |= Rn << 3; 8512 return; 8513 } 8514 /* ... because addition is commutative! */ 8515 else if (Rd == Rn) 8516 { 8517 inst.instruction = T_OPCODE_ADD_HI; 8518 inst.instruction |= (Rd & 8) << 4; 8519 inst.instruction |= (Rd & 7); 8520 inst.instruction |= Rs << 3; 8521 return; 8522 } 8523 } 8524 } 8525 /* If we get here, it can't be done in 16 bits. */ 8526 constraint (inst.operands[2].shifted && inst.operands[2].immisreg, 8527 _("shift must be constant")); 8528 inst.instruction = THUMB_OP32 (inst.instruction); 8529 inst.instruction |= Rd << 8; 8530 inst.instruction |= Rs << 16; 8531 encode_thumb32_shifted_operand (2); 8532 } 8533 } 8534 else 8535 { 8536 constraint (inst.instruction == T_MNEM_adds 8537 || inst.instruction == T_MNEM_subs, 8538 BAD_THUMB32); 8539 8540 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ 8541 { 8542 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) 8543 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), 8544 BAD_HIREG); 8545 8546 inst.instruction = (inst.instruction == T_MNEM_add 8547 ? 0x0000 : 0x8000); 8548 inst.instruction |= (Rd << 4) | Rs; 8549 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 8550 return; 8551 } 8552 8553 Rn = inst.operands[2].reg; 8554 constraint (inst.operands[2].shifted, _("unshifted register required")); 8555 8556 /* We now have Rd, Rs, and Rn set to registers. */ 8557 if (Rd > 7 || Rs > 7 || Rn > 7) 8558 { 8559 /* Can't do this for SUB. */ 8560 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); 8561 inst.instruction = T_OPCODE_ADD_HI; 8562 inst.instruction |= (Rd & 8) << 4; 8563 inst.instruction |= (Rd & 7); 8564 if (Rs == Rd) 8565 inst.instruction |= Rn << 3; 8566 else if (Rn == Rd) 8567 inst.instruction |= Rs << 3; 8568 else 8569 constraint (1, _("dest must overlap one source register")); 8570 } 8571 else 8572 { 8573 inst.instruction = (inst.instruction == T_MNEM_add 8574 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); 8575 inst.instruction |= Rd | (Rs << 3) | (Rn << 6); 8576 } 8577 } 8578} 8579 8580static void 8581do_t_adr (void) 8582{ 8583 if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7) 8584 { 8585 /* Defer to section relaxation. */ 8586 inst.relax = inst.instruction; 8587 inst.instruction = THUMB_OP16 (inst.instruction); 8588 inst.instruction |= inst.operands[0].reg << 4; 8589 } 8590 else if (unified_syntax && inst.size_req != 2) 8591 { 8592 /* Generate a 32-bit opcode. */ 8593 inst.instruction = THUMB_OP32 (inst.instruction); 8594 inst.instruction |= inst.operands[0].reg << 8; 8595 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; 8596 inst.reloc.pc_rel = 1; 8597 } 8598 else 8599 { 8600 /* Generate a 16-bit opcode. */ 8601 inst.instruction = THUMB_OP16 (inst.instruction); 8602 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 8603 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ 8604 inst.reloc.pc_rel = 1; 8605 8606 inst.instruction |= inst.operands[0].reg << 4; 8607 } 8608} 8609 8610/* Arithmetic instructions for which there is just one 16-bit 8611 instruction encoding, and it allows only two low registers. 8612 For maximal compatibility with ARM syntax, we allow three register 8613 operands even when Thumb-32 instructions are not available, as long 8614 as the first two are identical. For instance, both "sbc r0,r1" and 8615 "sbc r0,r0,r1" are allowed. */ 8616static void 8617do_t_arit3 (void) 8618{ 8619 int Rd, Rs, Rn; 8620 8621 Rd = inst.operands[0].reg; 8622 Rs = (inst.operands[1].present 8623 ? inst.operands[1].reg /* Rd, Rs, foo */ 8624 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 8625 Rn = inst.operands[2].reg; 8626 8627 if (unified_syntax) 8628 { 8629 if (!inst.operands[2].isreg) 8630 { 8631 /* For an immediate, we always generate a 32-bit opcode; 8632 section relaxation will shrink it later if possible. */ 8633 inst.instruction = THUMB_OP32 (inst.instruction); 8634 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 8635 inst.instruction |= Rd << 8; 8636 inst.instruction |= Rs << 16; 8637 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 8638 } 8639 else 8640 { 8641 bfd_boolean narrow; 8642 8643 /* See if we can do this with a 16-bit instruction. */ 8644 if (THUMB_SETS_FLAGS (inst.instruction)) 8645 narrow = current_it_mask == 0; 8646 else 8647 narrow = current_it_mask != 0; 8648 8649 if (Rd > 7 || Rn > 7 || Rs > 7) 8650 narrow = FALSE; 8651 if (inst.operands[2].shifted) 8652 narrow = FALSE; 8653 if (inst.size_req == 4) 8654 narrow = FALSE; 8655 8656 if (narrow 8657 && Rd == Rs) 8658 { 8659 inst.instruction = THUMB_OP16 (inst.instruction); 8660 inst.instruction |= Rd; 8661 inst.instruction |= Rn << 3; 8662 return; 8663 } 8664 8665 /* If we get here, it can't be done in 16 bits. */ 8666 constraint (inst.operands[2].shifted 8667 && inst.operands[2].immisreg, 8668 _("shift must be constant")); 8669 inst.instruction = THUMB_OP32 (inst.instruction); 8670 inst.instruction |= Rd << 8; 8671 inst.instruction |= Rs << 16; 8672 encode_thumb32_shifted_operand (2); 8673 } 8674 } 8675 else 8676 { 8677 /* On its face this is a lie - the instruction does set the 8678 flags. However, the only supported mnemonic in this mode 8679 says it doesn't. */ 8680 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 8681 8682 constraint (!inst.operands[2].isreg || inst.operands[2].shifted, 8683 _("unshifted register required")); 8684 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); 8685 constraint (Rd != Rs, 8686 _("dest and source1 must be the same register")); 8687 8688 inst.instruction = THUMB_OP16 (inst.instruction); 8689 inst.instruction |= Rd; 8690 inst.instruction |= Rn << 3; 8691 } 8692} 8693 8694/* Similarly, but for instructions where the arithmetic operation is 8695 commutative, so we can allow either of them to be different from 8696 the destination operand in a 16-bit instruction. For instance, all 8697 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are 8698 accepted. */ 8699static void 8700do_t_arit3c (void) 8701{ 8702 int Rd, Rs, Rn; 8703 8704 Rd = inst.operands[0].reg; 8705 Rs = (inst.operands[1].present 8706 ? inst.operands[1].reg /* Rd, Rs, foo */ 8707 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 8708 Rn = inst.operands[2].reg; 8709 8710 if (unified_syntax) 8711 { 8712 if (!inst.operands[2].isreg) 8713 { 8714 /* For an immediate, we always generate a 32-bit opcode; 8715 section relaxation will shrink it later if possible. */ 8716 inst.instruction = THUMB_OP32 (inst.instruction); 8717 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 8718 inst.instruction |= Rd << 8; 8719 inst.instruction |= Rs << 16; 8720 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 8721 } 8722 else 8723 { 8724 bfd_boolean narrow; 8725 8726 /* See if we can do this with a 16-bit instruction. */ 8727 if (THUMB_SETS_FLAGS (inst.instruction)) 8728 narrow = current_it_mask == 0; 8729 else 8730 narrow = current_it_mask != 0; 8731 8732 if (Rd > 7 || Rn > 7 || Rs > 7) 8733 narrow = FALSE; 8734 if (inst.operands[2].shifted) 8735 narrow = FALSE; 8736 if (inst.size_req == 4) 8737 narrow = FALSE; 8738 8739 if (narrow) 8740 { 8741 if (Rd == Rs) 8742 { 8743 inst.instruction = THUMB_OP16 (inst.instruction); 8744 inst.instruction |= Rd; 8745 inst.instruction |= Rn << 3; 8746 return; 8747 } 8748 if (Rd == Rn) 8749 { 8750 inst.instruction = THUMB_OP16 (inst.instruction); 8751 inst.instruction |= Rd; 8752 inst.instruction |= Rs << 3; 8753 return; 8754 } 8755 } 8756 8757 /* If we get here, it can't be done in 16 bits. */ 8758 constraint (inst.operands[2].shifted 8759 && inst.operands[2].immisreg, 8760 _("shift must be constant")); 8761 inst.instruction = THUMB_OP32 (inst.instruction); 8762 inst.instruction |= Rd << 8; 8763 inst.instruction |= Rs << 16; 8764 encode_thumb32_shifted_operand (2); 8765 } 8766 } 8767 else 8768 { 8769 /* On its face this is a lie - the instruction does set the 8770 flags. However, the only supported mnemonic in this mode 8771 says it doesn't. */ 8772 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 8773 8774 constraint (!inst.operands[2].isreg || inst.operands[2].shifted, 8775 _("unshifted register required")); 8776 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); 8777 8778 inst.instruction = THUMB_OP16 (inst.instruction); 8779 inst.instruction |= Rd; 8780 8781 if (Rd == Rs) 8782 inst.instruction |= Rn << 3; 8783 else if (Rd == Rn) 8784 inst.instruction |= Rs << 3; 8785 else 8786 constraint (1, _("dest must overlap one source register")); 8787 } 8788} 8789 8790static void 8791do_t_barrier (void) 8792{ 8793 if (inst.operands[0].present) 8794 { 8795 constraint ((inst.instruction & 0xf0) != 0x40 8796 && inst.operands[0].imm != 0xf, 8797 "bad barrier type"); 8798 inst.instruction |= inst.operands[0].imm; 8799 } 8800 else 8801 inst.instruction |= 0xf; 8802} 8803 8804static void 8805do_t_bfc (void) 8806{ 8807 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; 8808 constraint (msb > 32, _("bit-field extends past end of register")); 8809 /* The instruction encoding stores the LSB and MSB, 8810 not the LSB and width. */ 8811 inst.instruction |= inst.operands[0].reg << 8; 8812 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; 8813 inst.instruction |= (inst.operands[1].imm & 0x03) << 6; 8814 inst.instruction |= msb - 1; 8815} 8816 8817static void 8818do_t_bfi (void) 8819{ 8820 unsigned int msb; 8821 8822 /* #0 in second position is alternative syntax for bfc, which is 8823 the same instruction but with REG_PC in the Rm field. */ 8824 if (!inst.operands[1].isreg) 8825 inst.operands[1].reg = REG_PC; 8826 8827 msb = inst.operands[2].imm + inst.operands[3].imm; 8828 constraint (msb > 32, _("bit-field extends past end of register")); 8829 /* The instruction encoding stores the LSB and MSB, 8830 not the LSB and width. */ 8831 inst.instruction |= inst.operands[0].reg << 8; 8832 inst.instruction |= inst.operands[1].reg << 16; 8833 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; 8834 inst.instruction |= (inst.operands[2].imm & 0x03) << 6; 8835 inst.instruction |= msb - 1; 8836} 8837 8838static void 8839do_t_bfx (void) 8840{ 8841 constraint (inst.operands[2].imm + inst.operands[3].imm > 32, 8842 _("bit-field extends past end of register")); 8843 inst.instruction |= inst.operands[0].reg << 8; 8844 inst.instruction |= inst.operands[1].reg << 16; 8845 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; 8846 inst.instruction |= (inst.operands[2].imm & 0x03) << 6; 8847 inst.instruction |= inst.operands[3].imm - 1; 8848} 8849 8850/* ARM V5 Thumb BLX (argument parse) 8851 BLX <target_addr> which is BLX(1) 8852 BLX <Rm> which is BLX(2) 8853 Unfortunately, there are two different opcodes for this mnemonic. 8854 So, the insns[].value is not used, and the code here zaps values 8855 into inst.instruction. 8856 8857 ??? How to take advantage of the additional two bits of displacement 8858 available in Thumb32 mode? Need new relocation? */ 8859 8860static void 8861do_t_blx (void) 8862{ 8863 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 8864 if (inst.operands[0].isreg) 8865 /* We have a register, so this is BLX(2). */ 8866 inst.instruction |= inst.operands[0].reg << 3; 8867 else 8868 { 8869 /* No register. This must be BLX(1). */ 8870 inst.instruction = 0xf000e800; 8871#ifdef OBJ_ELF 8872 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 8873 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; 8874 else 8875#endif 8876 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX; 8877 inst.reloc.pc_rel = 1; 8878 } 8879} 8880 8881static void 8882do_t_branch (void) 8883{ 8884 int opcode; 8885 int cond; 8886 8887 if (current_it_mask) 8888 { 8889 /* Conditional branches inside IT blocks are encoded as unconditional 8890 branches. */ 8891 cond = COND_ALWAYS; 8892 /* A branch must be the last instruction in an IT block. */ 8893 constraint (current_it_mask != 0x10, BAD_BRANCH); 8894 } 8895 else 8896 cond = inst.cond; 8897 8898 if (cond != COND_ALWAYS) 8899 opcode = T_MNEM_bcond; 8900 else 8901 opcode = inst.instruction; 8902 8903 if (unified_syntax && inst.size_req == 4) 8904 { 8905 inst.instruction = THUMB_OP32(opcode); 8906 if (cond == COND_ALWAYS) 8907 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25; 8908 else 8909 { 8910 assert (cond != 0xF); 8911 inst.instruction |= cond << 22; 8912 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20; 8913 } 8914 } 8915 else 8916 { 8917 inst.instruction = THUMB_OP16(opcode); 8918 if (cond == COND_ALWAYS) 8919 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12; 8920 else 8921 { 8922 inst.instruction |= cond << 8; 8923 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9; 8924 } 8925 /* Allow section relaxation. */ 8926 if (unified_syntax && inst.size_req != 2) 8927 inst.relax = opcode; 8928 } 8929 8930 inst.reloc.pc_rel = 1; 8931} 8932 8933static void 8934do_t_bkpt (void) 8935{ 8936 constraint (inst.cond != COND_ALWAYS, 8937 _("instruction is always unconditional")); 8938 if (inst.operands[0].present) 8939 { 8940 constraint (inst.operands[0].imm > 255, 8941 _("immediate value out of range")); 8942 inst.instruction |= inst.operands[0].imm; 8943 } 8944} 8945 8946static void 8947do_t_branch23 (void) 8948{ 8949 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 8950 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; 8951 inst.reloc.pc_rel = 1; 8952 8953 /* If the destination of the branch is a defined symbol which does not have 8954 the THUMB_FUNC attribute, then we must be calling a function which has 8955 the (interfacearm) attribute. We look for the Thumb entry point to that 8956 function and change the branch to refer to that function instead. */ 8957 if ( inst.reloc.exp.X_op == O_symbol 8958 && inst.reloc.exp.X_add_symbol != NULL 8959 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) 8960 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) 8961 inst.reloc.exp.X_add_symbol = 8962 find_real_start (inst.reloc.exp.X_add_symbol); 8963} 8964 8965static void 8966do_t_bx (void) 8967{ 8968 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 8969 inst.instruction |= inst.operands[0].reg << 3; 8970 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc 8971 should cause the alignment to be checked once it is known. This is 8972 because BX PC only works if the instruction is word aligned. */ 8973} 8974 8975static void 8976do_t_bxj (void) 8977{ 8978 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 8979 if (inst.operands[0].reg == REG_PC) 8980 as_tsktsk (_("use of r15 in bxj is not really useful")); 8981 8982 inst.instruction |= inst.operands[0].reg << 16; 8983} 8984 8985static void 8986do_t_clz (void) 8987{ 8988 inst.instruction |= inst.operands[0].reg << 8; 8989 inst.instruction |= inst.operands[1].reg << 16; 8990 inst.instruction |= inst.operands[1].reg; 8991} 8992 8993static void 8994do_t_cps (void) 8995{ 8996 constraint (current_it_mask, BAD_NOT_IT); 8997 inst.instruction |= inst.operands[0].imm; 8998} 8999 9000static void 9001do_t_cpsi (void) 9002{ 9003 constraint (current_it_mask, BAD_NOT_IT); 9004 if (unified_syntax 9005 && (inst.operands[1].present || inst.size_req == 4) 9006 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) 9007 { 9008 unsigned int imod = (inst.instruction & 0x0030) >> 4; 9009 inst.instruction = 0xf3af8000; 9010 inst.instruction |= imod << 9; 9011 inst.instruction |= inst.operands[0].imm << 5; 9012 if (inst.operands[1].present) 9013 inst.instruction |= 0x100 | inst.operands[1].imm; 9014 } 9015 else 9016 { 9017 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) 9018 && (inst.operands[0].imm & 4), 9019 _("selected processor does not support 'A' form " 9020 "of this instruction")); 9021 constraint (inst.operands[1].present || inst.size_req == 4, 9022 _("Thumb does not support the 2-argument " 9023 "form of this instruction")); 9024 inst.instruction |= inst.operands[0].imm; 9025 } 9026} 9027 9028/* THUMB CPY instruction (argument parse). */ 9029 9030static void 9031do_t_cpy (void) 9032{ 9033 if (inst.size_req == 4) 9034 { 9035 inst.instruction = THUMB_OP32 (T_MNEM_mov); 9036 inst.instruction |= inst.operands[0].reg << 8; 9037 inst.instruction |= inst.operands[1].reg; 9038 } 9039 else 9040 { 9041 inst.instruction |= (inst.operands[0].reg & 0x8) << 4; 9042 inst.instruction |= (inst.operands[0].reg & 0x7); 9043 inst.instruction |= inst.operands[1].reg << 3; 9044 } 9045} 9046 9047static void 9048do_t_cbz (void) 9049{ 9050 constraint (current_it_mask, BAD_NOT_IT); 9051 constraint (inst.operands[0].reg > 7, BAD_HIREG); 9052 inst.instruction |= inst.operands[0].reg; 9053 inst.reloc.pc_rel = 1; 9054 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; 9055} 9056 9057static void 9058do_t_dbg (void) 9059{ 9060 inst.instruction |= inst.operands[0].imm; 9061} 9062 9063static void 9064do_t_div (void) 9065{ 9066 if (!inst.operands[1].present) 9067 inst.operands[1].reg = inst.operands[0].reg; 9068 inst.instruction |= inst.operands[0].reg << 8; 9069 inst.instruction |= inst.operands[1].reg << 16; 9070 inst.instruction |= inst.operands[2].reg; 9071} 9072 9073static void 9074do_t_hint (void) 9075{ 9076 if (unified_syntax && inst.size_req == 4) 9077 inst.instruction = THUMB_OP32 (inst.instruction); 9078 else 9079 inst.instruction = THUMB_OP16 (inst.instruction); 9080} 9081 9082static void 9083do_t_it (void) 9084{ 9085 unsigned int cond = inst.operands[0].imm; 9086 9087 constraint (current_it_mask, BAD_NOT_IT); 9088 current_it_mask = (inst.instruction & 0xf) | 0x10; 9089 current_cc = cond; 9090 9091 /* If the condition is a negative condition, invert the mask. */ 9092 if ((cond & 0x1) == 0x0) 9093 { 9094 unsigned int mask = inst.instruction & 0x000f; 9095 9096 if ((mask & 0x7) == 0) 9097 /* no conversion needed */; 9098 else if ((mask & 0x3) == 0) 9099 mask ^= 0x8; 9100 else if ((mask & 0x1) == 0) 9101 mask ^= 0xC; 9102 else 9103 mask ^= 0xE; 9104 9105 inst.instruction &= 0xfff0; 9106 inst.instruction |= mask; 9107 } 9108 9109 inst.instruction |= cond << 4; 9110} 9111 9112/* Helper function used for both push/pop and ldm/stm. */ 9113static void 9114encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) 9115{ 9116 bfd_boolean load; 9117 9118 load = (inst.instruction & (1 << 20)) != 0; 9119 9120 if (mask & (1 << 13)) 9121 inst.error = _("SP not allowed in register list"); 9122 if (load) 9123 { 9124 if (mask & (1 << 14) 9125 && mask & (1 << 15)) 9126 inst.error = _("LR and PC should not both be in register list"); 9127 9128 if ((mask & (1 << base)) != 0 9129 && writeback) 9130 as_warn (_("base register should not be in register list " 9131 "when written back")); 9132 } 9133 else 9134 { 9135 if (mask & (1 << 15)) 9136 inst.error = _("PC not allowed in register list"); 9137 9138 if (mask & (1 << base)) 9139 as_warn (_("value stored for r%d is UNPREDICTABLE"), base); 9140 } 9141 9142 if ((mask & (mask - 1)) == 0) 9143 { 9144 /* Single register transfers implemented as str/ldr. */ 9145 if (writeback) 9146 { 9147 if (inst.instruction & (1 << 23)) 9148 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ 9149 else 9150 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ 9151 } 9152 else 9153 { 9154 if (inst.instruction & (1 << 23)) 9155 inst.instruction = 0x00800000; /* ia -> [base] */ 9156 else 9157 inst.instruction = 0x00000c04; /* db -> [base, #-4] */ 9158 } 9159 9160 inst.instruction |= 0xf8400000; 9161 if (load) 9162 inst.instruction |= 0x00100000; 9163 9164 mask = ffs(mask) - 1; 9165 mask <<= 12; 9166 } 9167 else if (writeback) 9168 inst.instruction |= WRITE_BACK; 9169 9170 inst.instruction |= mask; 9171 inst.instruction |= base << 16; 9172} 9173 9174static void 9175do_t_ldmstm (void) 9176{ 9177 /* This really doesn't seem worth it. */ 9178 constraint (inst.reloc.type != BFD_RELOC_UNUSED, 9179 _("expression too complex")); 9180 constraint (inst.operands[1].writeback, 9181 _("Thumb load/store multiple does not support {reglist}^")); 9182 9183 if (unified_syntax) 9184 { 9185 bfd_boolean narrow; 9186 unsigned mask; 9187 9188 narrow = FALSE; 9189 /* See if we can use a 16-bit instruction. */ 9190 if (inst.instruction < 0xffff /* not ldmdb/stmdb */ 9191 && inst.size_req != 4 9192 && !(inst.operands[1].imm & ~0xff)) 9193 { 9194 mask = 1 << inst.operands[0].reg; 9195 9196 if (inst.operands[0].reg <= 7 9197 && (inst.instruction == T_MNEM_stmia 9198 ? inst.operands[0].writeback 9199 : (inst.operands[0].writeback 9200 == !(inst.operands[1].imm & mask)))) 9201 { 9202 if (inst.instruction == T_MNEM_stmia 9203 && (inst.operands[1].imm & mask) 9204 && (inst.operands[1].imm & (mask - 1))) 9205 as_warn (_("value stored for r%d is UNPREDICTABLE"), 9206 inst.operands[0].reg); 9207 9208 inst.instruction = THUMB_OP16 (inst.instruction); 9209 inst.instruction |= inst.operands[0].reg << 8; 9210 inst.instruction |= inst.operands[1].imm; 9211 narrow = TRUE; 9212 } 9213 else if (inst.operands[0] .reg == REG_SP 9214 && inst.operands[0].writeback) 9215 { 9216 inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia 9217 ? T_MNEM_push : T_MNEM_pop); 9218 inst.instruction |= inst.operands[1].imm; 9219 narrow = TRUE; 9220 } 9221 } 9222 9223 if (!narrow) 9224 { 9225 if (inst.instruction < 0xffff) 9226 inst.instruction = THUMB_OP32 (inst.instruction); 9227 9228 encode_thumb2_ldmstm(inst.operands[0].reg, inst.operands[1].imm, 9229 inst.operands[0].writeback); 9230 } 9231 } 9232 else 9233 { 9234 constraint (inst.operands[0].reg > 7 9235 || (inst.operands[1].imm & ~0xff), BAD_HIREG); 9236 constraint (inst.instruction != T_MNEM_ldmia 9237 && inst.instruction != T_MNEM_stmia, 9238 _("Thumb-2 instruction only valid in unified syntax")); 9239 if (inst.instruction == T_MNEM_stmia) 9240 { 9241 if (!inst.operands[0].writeback) 9242 as_warn (_("this instruction will write back the base register")); 9243 if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) 9244 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) 9245 as_warn (_("value stored for r%d is UNPREDICTABLE"), 9246 inst.operands[0].reg); 9247 } 9248 else 9249 { 9250 if (!inst.operands[0].writeback 9251 && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) 9252 as_warn (_("this instruction will write back the base register")); 9253 else if (inst.operands[0].writeback 9254 && (inst.operands[1].imm & (1 << inst.operands[0].reg))) 9255 as_warn (_("this instruction will not write back the base register")); 9256 } 9257 9258 inst.instruction = THUMB_OP16 (inst.instruction); 9259 inst.instruction |= inst.operands[0].reg << 8; 9260 inst.instruction |= inst.operands[1].imm; 9261 } 9262} 9263 9264static void 9265do_t_ldrex (void) 9266{ 9267 constraint (!inst.operands[1].isreg || !inst.operands[1].preind 9268 || inst.operands[1].postind || inst.operands[1].writeback 9269 || inst.operands[1].immisreg || inst.operands[1].shifted 9270 || inst.operands[1].negative, 9271 BAD_ADDR_MODE); 9272 9273 inst.instruction |= inst.operands[0].reg << 12; 9274 inst.instruction |= inst.operands[1].reg << 16; 9275 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; 9276} 9277 9278static void 9279do_t_ldrexd (void) 9280{ 9281 if (!inst.operands[1].present) 9282 { 9283 constraint (inst.operands[0].reg == REG_LR, 9284 _("r14 not allowed as first register " 9285 "when second register is omitted")); 9286 inst.operands[1].reg = inst.operands[0].reg + 1; 9287 } 9288 constraint (inst.operands[0].reg == inst.operands[1].reg, 9289 BAD_OVERLAP); 9290 9291 inst.instruction |= inst.operands[0].reg << 12; 9292 inst.instruction |= inst.operands[1].reg << 8; 9293 inst.instruction |= inst.operands[2].reg << 16; 9294} 9295 9296static void 9297do_t_ldst (void) 9298{ 9299 unsigned long opcode; 9300 int Rn; 9301 9302 opcode = inst.instruction; 9303 if (unified_syntax) 9304 { 9305 if (!inst.operands[1].isreg) 9306 { 9307 if (opcode <= 0xffff) 9308 inst.instruction = THUMB_OP32 (opcode); 9309 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) 9310 return; 9311 } 9312 if (inst.operands[1].isreg 9313 && !inst.operands[1].writeback 9314 && !inst.operands[1].shifted && !inst.operands[1].postind 9315 && !inst.operands[1].negative && inst.operands[0].reg <= 7 9316 && opcode <= 0xffff 9317 && inst.size_req != 4) 9318 { 9319 /* Insn may have a 16-bit form. */ 9320 Rn = inst.operands[1].reg; 9321 if (inst.operands[1].immisreg) 9322 { 9323 inst.instruction = THUMB_OP16 (opcode); 9324 /* [Rn, Ri] */ 9325 if (Rn <= 7 && inst.operands[1].imm <= 7) 9326 goto op16; 9327 } 9328 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh 9329 && opcode != T_MNEM_ldrsb) 9330 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) 9331 || (Rn == REG_SP && opcode == T_MNEM_str)) 9332 { 9333 /* [Rn, #const] */ 9334 if (Rn > 7) 9335 { 9336 if (Rn == REG_PC) 9337 { 9338 if (inst.reloc.pc_rel) 9339 opcode = T_MNEM_ldr_pc2; 9340 else 9341 opcode = T_MNEM_ldr_pc; 9342 } 9343 else 9344 { 9345 if (opcode == T_MNEM_ldr) 9346 opcode = T_MNEM_ldr_sp; 9347 else 9348 opcode = T_MNEM_str_sp; 9349 } 9350 inst.instruction = inst.operands[0].reg << 8; 9351 } 9352 else 9353 { 9354 inst.instruction = inst.operands[0].reg; 9355 inst.instruction |= inst.operands[1].reg << 3; 9356 } 9357 inst.instruction |= THUMB_OP16 (opcode); 9358 if (inst.size_req == 2) 9359 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 9360 else 9361 inst.relax = opcode; 9362 return; 9363 } 9364 } 9365 /* Definitely a 32-bit variant. */ 9366 inst.instruction = THUMB_OP32 (opcode); 9367 inst.instruction |= inst.operands[0].reg << 12; 9368 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); 9369 return; 9370 } 9371 9372 constraint (inst.operands[0].reg > 7, BAD_HIREG); 9373 9374 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) 9375 { 9376 /* Only [Rn,Rm] is acceptable. */ 9377 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); 9378 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg 9379 || inst.operands[1].postind || inst.operands[1].shifted 9380 || inst.operands[1].negative, 9381 _("Thumb does not support this addressing mode")); 9382 inst.instruction = THUMB_OP16 (inst.instruction); 9383 goto op16; 9384 } 9385 9386 inst.instruction = THUMB_OP16 (inst.instruction); 9387 if (!inst.operands[1].isreg) 9388 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) 9389 return; 9390 9391 constraint (!inst.operands[1].preind 9392 || inst.operands[1].shifted 9393 || inst.operands[1].writeback, 9394 _("Thumb does not support this addressing mode")); 9395 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) 9396 { 9397 constraint (inst.instruction & 0x0600, 9398 _("byte or halfword not valid for base register")); 9399 constraint (inst.operands[1].reg == REG_PC 9400 && !(inst.instruction & THUMB_LOAD_BIT), 9401 _("r15 based store not allowed")); 9402 constraint (inst.operands[1].immisreg, 9403 _("invalid base register for register offset")); 9404 9405 if (inst.operands[1].reg == REG_PC) 9406 inst.instruction = T_OPCODE_LDR_PC; 9407 else if (inst.instruction & THUMB_LOAD_BIT) 9408 inst.instruction = T_OPCODE_LDR_SP; 9409 else 9410 inst.instruction = T_OPCODE_STR_SP; 9411 9412 inst.instruction |= inst.operands[0].reg << 8; 9413 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 9414 return; 9415 } 9416 9417 constraint (inst.operands[1].reg > 7, BAD_HIREG); 9418 if (!inst.operands[1].immisreg) 9419 { 9420 /* Immediate offset. */ 9421 inst.instruction |= inst.operands[0].reg; 9422 inst.instruction |= inst.operands[1].reg << 3; 9423 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 9424 return; 9425 } 9426 9427 /* Register offset. */ 9428 constraint (inst.operands[1].imm > 7, BAD_HIREG); 9429 constraint (inst.operands[1].negative, 9430 _("Thumb does not support this addressing mode")); 9431 9432 op16: 9433 switch (inst.instruction) 9434 { 9435 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; 9436 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; 9437 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; 9438 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; 9439 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; 9440 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; 9441 case 0x5600 /* ldrsb */: 9442 case 0x5e00 /* ldrsh */: break; 9443 default: abort (); 9444 } 9445 9446 inst.instruction |= inst.operands[0].reg; 9447 inst.instruction |= inst.operands[1].reg << 3; 9448 inst.instruction |= inst.operands[1].imm << 6; 9449} 9450 9451static void 9452do_t_ldstd (void) 9453{ 9454 if (!inst.operands[1].present) 9455 { 9456 inst.operands[1].reg = inst.operands[0].reg + 1; 9457 constraint (inst.operands[0].reg == REG_LR, 9458 _("r14 not allowed here")); 9459 } 9460 inst.instruction |= inst.operands[0].reg << 12; 9461 inst.instruction |= inst.operands[1].reg << 8; 9462 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); 9463 9464} 9465 9466static void 9467do_t_ldstt (void) 9468{ 9469 inst.instruction |= inst.operands[0].reg << 12; 9470 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); 9471} 9472 9473static void 9474do_t_mla (void) 9475{ 9476 inst.instruction |= inst.operands[0].reg << 8; 9477 inst.instruction |= inst.operands[1].reg << 16; 9478 inst.instruction |= inst.operands[2].reg; 9479 inst.instruction |= inst.operands[3].reg << 12; 9480} 9481 9482static void 9483do_t_mlal (void) 9484{ 9485 inst.instruction |= inst.operands[0].reg << 12; 9486 inst.instruction |= inst.operands[1].reg << 8; 9487 inst.instruction |= inst.operands[2].reg << 16; 9488 inst.instruction |= inst.operands[3].reg; 9489} 9490 9491static void 9492do_t_mov_cmp (void) 9493{ 9494 if (unified_syntax) 9495 { 9496 int r0off = (inst.instruction == T_MNEM_mov 9497 || inst.instruction == T_MNEM_movs) ? 8 : 16; 9498 unsigned long opcode; 9499 bfd_boolean narrow; 9500 bfd_boolean low_regs; 9501 9502 low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7); 9503 opcode = inst.instruction; 9504 if (current_it_mask) 9505 narrow = opcode != T_MNEM_movs; 9506 else 9507 narrow = opcode != T_MNEM_movs || low_regs; 9508 if (inst.size_req == 4 9509 || inst.operands[1].shifted) 9510 narrow = FALSE; 9511 9512 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ 9513 if (opcode == T_MNEM_movs && inst.operands[1].isreg 9514 && !inst.operands[1].shifted 9515 && inst.operands[0].reg == REG_PC 9516 && inst.operands[1].reg == REG_LR) 9517 { 9518 inst.instruction = T2_SUBS_PC_LR; 9519 return; 9520 } 9521 9522 if (!inst.operands[1].isreg) 9523 { 9524 /* Immediate operand. */ 9525 if (current_it_mask == 0 && opcode == T_MNEM_mov) 9526 narrow = 0; 9527 if (low_regs && narrow) 9528 { 9529 inst.instruction = THUMB_OP16 (opcode); 9530 inst.instruction |= inst.operands[0].reg << 8; 9531 if (inst.size_req == 2) 9532 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; 9533 else 9534 inst.relax = opcode; 9535 } 9536 else 9537 { 9538 inst.instruction = THUMB_OP32 (inst.instruction); 9539 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 9540 inst.instruction |= inst.operands[0].reg << r0off; 9541 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 9542 } 9543 } 9544 else if (inst.operands[1].shifted && inst.operands[1].immisreg 9545 && (inst.instruction == T_MNEM_mov 9546 || inst.instruction == T_MNEM_movs)) 9547 { 9548 /* Register shifts are encoded as separate shift instructions. */ 9549 bfd_boolean flags = (inst.instruction == T_MNEM_movs); 9550 9551 if (current_it_mask) 9552 narrow = !flags; 9553 else 9554 narrow = flags; 9555 9556 if (inst.size_req == 4) 9557 narrow = FALSE; 9558 9559 if (!low_regs || inst.operands[1].imm > 7) 9560 narrow = FALSE; 9561 9562 if (inst.operands[0].reg != inst.operands[1].reg) 9563 narrow = FALSE; 9564 9565 switch (inst.operands[1].shift_kind) 9566 { 9567 case SHIFT_LSL: 9568 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); 9569 break; 9570 case SHIFT_ASR: 9571 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); 9572 break; 9573 case SHIFT_LSR: 9574 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); 9575 break; 9576 case SHIFT_ROR: 9577 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); 9578 break; 9579 default: 9580 abort(); 9581 } 9582 9583 inst.instruction = opcode; 9584 if (narrow) 9585 { 9586 inst.instruction |= inst.operands[0].reg; 9587 inst.instruction |= inst.operands[1].imm << 3; 9588 } 9589 else 9590 { 9591 if (flags) 9592 inst.instruction |= CONDS_BIT; 9593 9594 inst.instruction |= inst.operands[0].reg << 8; 9595 inst.instruction |= inst.operands[1].reg << 16; 9596 inst.instruction |= inst.operands[1].imm; 9597 } 9598 } 9599 else if (!narrow) 9600 { 9601 /* Some mov with immediate shift have narrow variants. 9602 Register shifts are handled above. */ 9603 if (low_regs && inst.operands[1].shifted 9604 && (inst.instruction == T_MNEM_mov 9605 || inst.instruction == T_MNEM_movs)) 9606 { 9607 if (current_it_mask) 9608 narrow = (inst.instruction == T_MNEM_mov); 9609 else 9610 narrow = (inst.instruction == T_MNEM_movs); 9611 } 9612 9613 if (narrow) 9614 { 9615 switch (inst.operands[1].shift_kind) 9616 { 9617 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; 9618 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; 9619 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; 9620 default: narrow = FALSE; break; 9621 } 9622 } 9623 9624 if (narrow) 9625 { 9626 inst.instruction |= inst.operands[0].reg; 9627 inst.instruction |= inst.operands[1].reg << 3; 9628 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 9629 } 9630 else 9631 { 9632 inst.instruction = THUMB_OP32 (inst.instruction); 9633 inst.instruction |= inst.operands[0].reg << r0off; 9634 encode_thumb32_shifted_operand (1); 9635 } 9636 } 9637 else 9638 switch (inst.instruction) 9639 { 9640 case T_MNEM_mov: 9641 inst.instruction = T_OPCODE_MOV_HR; 9642 inst.instruction |= (inst.operands[0].reg & 0x8) << 4; 9643 inst.instruction |= (inst.operands[0].reg & 0x7); 9644 inst.instruction |= inst.operands[1].reg << 3; 9645 break; 9646 9647 case T_MNEM_movs: 9648 /* We know we have low registers at this point. 9649 Generate ADD Rd, Rs, #0. */ 9650 inst.instruction = T_OPCODE_ADD_I3; 9651 inst.instruction |= inst.operands[0].reg; 9652 inst.instruction |= inst.operands[1].reg << 3; 9653 break; 9654 9655 case T_MNEM_cmp: 9656 if (low_regs) 9657 { 9658 inst.instruction = T_OPCODE_CMP_LR; 9659 inst.instruction |= inst.operands[0].reg; 9660 inst.instruction |= inst.operands[1].reg << 3; 9661 } 9662 else 9663 { 9664 inst.instruction = T_OPCODE_CMP_HR; 9665 inst.instruction |= (inst.operands[0].reg & 0x8) << 4; 9666 inst.instruction |= (inst.operands[0].reg & 0x7); 9667 inst.instruction |= inst.operands[1].reg << 3; 9668 } 9669 break; 9670 } 9671 return; 9672 } 9673 9674 inst.instruction = THUMB_OP16 (inst.instruction); 9675 if (inst.operands[1].isreg) 9676 { 9677 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8) 9678 { 9679 /* A move of two lowregs is encoded as ADD Rd, Rs, #0 9680 since a MOV instruction produces unpredictable results. */ 9681 if (inst.instruction == T_OPCODE_MOV_I8) 9682 inst.instruction = T_OPCODE_ADD_I3; 9683 else 9684 inst.instruction = T_OPCODE_CMP_LR; 9685 9686 inst.instruction |= inst.operands[0].reg; 9687 inst.instruction |= inst.operands[1].reg << 3; 9688 } 9689 else 9690 { 9691 if (inst.instruction == T_OPCODE_MOV_I8) 9692 inst.instruction = T_OPCODE_MOV_HR; 9693 else 9694 inst.instruction = T_OPCODE_CMP_HR; 9695 do_t_cpy (); 9696 } 9697 } 9698 else 9699 { 9700 constraint (inst.operands[0].reg > 7, 9701 _("only lo regs allowed with immediate")); 9702 inst.instruction |= inst.operands[0].reg << 8; 9703 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; 9704 } 9705} 9706 9707static void 9708do_t_mov16 (void) 9709{ 9710 bfd_vma imm; 9711 bfd_boolean top; 9712 9713 top = (inst.instruction & 0x00800000) != 0; 9714 if (inst.reloc.type == BFD_RELOC_ARM_MOVW) 9715 { 9716 constraint (top, _(":lower16: not allowed this instruction")); 9717 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; 9718 } 9719 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) 9720 { 9721 constraint (!top, _(":upper16: not allowed this instruction")); 9722 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; 9723 } 9724 9725 inst.instruction |= inst.operands[0].reg << 8; 9726 if (inst.reloc.type == BFD_RELOC_UNUSED) 9727 { 9728 imm = inst.reloc.exp.X_add_number; 9729 inst.instruction |= (imm & 0xf000) << 4; 9730 inst.instruction |= (imm & 0x0800) << 15; 9731 inst.instruction |= (imm & 0x0700) << 4; 9732 inst.instruction |= (imm & 0x00ff); 9733 } 9734} 9735 9736static void 9737do_t_mvn_tst (void) 9738{ 9739 if (unified_syntax) 9740 { 9741 int r0off = (inst.instruction == T_MNEM_mvn 9742 || inst.instruction == T_MNEM_mvns) ? 8 : 16; 9743 bfd_boolean narrow; 9744 9745 if (inst.size_req == 4 9746 || inst.instruction > 0xffff 9747 || inst.operands[1].shifted 9748 || inst.operands[0].reg > 7 || inst.operands[1].reg > 7) 9749 narrow = FALSE; 9750 else if (inst.instruction == T_MNEM_cmn) 9751 narrow = TRUE; 9752 else if (THUMB_SETS_FLAGS (inst.instruction)) 9753 narrow = (current_it_mask == 0); 9754 else 9755 narrow = (current_it_mask != 0); 9756 9757 if (!inst.operands[1].isreg) 9758 { 9759 /* For an immediate, we always generate a 32-bit opcode; 9760 section relaxation will shrink it later if possible. */ 9761 if (inst.instruction < 0xffff) 9762 inst.instruction = THUMB_OP32 (inst.instruction); 9763 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 9764 inst.instruction |= inst.operands[0].reg << r0off; 9765 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 9766 } 9767 else 9768 { 9769 /* See if we can do this with a 16-bit instruction. */ 9770 if (narrow) 9771 { 9772 inst.instruction = THUMB_OP16 (inst.instruction); 9773 inst.instruction |= inst.operands[0].reg; 9774 inst.instruction |= inst.operands[1].reg << 3; 9775 } 9776 else 9777 { 9778 constraint (inst.operands[1].shifted 9779 && inst.operands[1].immisreg, 9780 _("shift must be constant")); 9781 if (inst.instruction < 0xffff) 9782 inst.instruction = THUMB_OP32 (inst.instruction); 9783 inst.instruction |= inst.operands[0].reg << r0off; 9784 encode_thumb32_shifted_operand (1); 9785 } 9786 } 9787 } 9788 else 9789 { 9790 constraint (inst.instruction > 0xffff 9791 || inst.instruction == T_MNEM_mvns, BAD_THUMB32); 9792 constraint (!inst.operands[1].isreg || inst.operands[1].shifted, 9793 _("unshifted register required")); 9794 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, 9795 BAD_HIREG); 9796 9797 inst.instruction = THUMB_OP16 (inst.instruction); 9798 inst.instruction |= inst.operands[0].reg; 9799 inst.instruction |= inst.operands[1].reg << 3; 9800 } 9801} 9802 9803static void 9804do_t_mrs (void) 9805{ 9806 int flags; 9807 9808 if (do_vfp_nsyn_mrs () == SUCCESS) 9809 return; 9810 9811 flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); 9812 if (flags == 0) 9813 { 9814 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m), 9815 _("selected processor does not support " 9816 "requested special purpose register")); 9817 } 9818 else 9819 { 9820 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), 9821 _("selected processor does not support " 9822 "requested special purpose register %x")); 9823 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ 9824 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), 9825 _("'CPSR' or 'SPSR' expected")); 9826 } 9827 9828 inst.instruction |= inst.operands[0].reg << 8; 9829 inst.instruction |= (flags & SPSR_BIT) >> 2; 9830 inst.instruction |= inst.operands[1].imm & 0xff; 9831} 9832 9833static void 9834do_t_msr (void) 9835{ 9836 int flags; 9837 9838 if (do_vfp_nsyn_msr () == SUCCESS) 9839 return; 9840 9841 constraint (!inst.operands[1].isreg, 9842 _("Thumb encoding does not support an immediate here")); 9843 flags = inst.operands[0].imm; 9844 if (flags & ~0xff) 9845 { 9846 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), 9847 _("selected processor does not support " 9848 "requested special purpose register")); 9849 } 9850 else 9851 { 9852 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m), 9853 _("selected processor does not support " 9854 "requested special purpose register")); 9855 flags |= PSR_f; 9856 } 9857 inst.instruction |= (flags & SPSR_BIT) >> 2; 9858 inst.instruction |= (flags & ~SPSR_BIT) >> 8; 9859 inst.instruction |= (flags & 0xff); 9860 inst.instruction |= inst.operands[1].reg << 16; 9861} 9862 9863static void 9864do_t_mul (void) 9865{ 9866 if (!inst.operands[2].present) 9867 inst.operands[2].reg = inst.operands[0].reg; 9868 9869 /* There is no 32-bit MULS and no 16-bit MUL. */ 9870 if (unified_syntax && inst.instruction == T_MNEM_mul) 9871 { 9872 inst.instruction = THUMB_OP32 (inst.instruction); 9873 inst.instruction |= inst.operands[0].reg << 8; 9874 inst.instruction |= inst.operands[1].reg << 16; 9875 inst.instruction |= inst.operands[2].reg << 0; 9876 } 9877 else 9878 { 9879 constraint (!unified_syntax 9880 && inst.instruction == T_MNEM_muls, BAD_THUMB32); 9881 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, 9882 BAD_HIREG); 9883 9884 inst.instruction = THUMB_OP16 (inst.instruction); 9885 inst.instruction |= inst.operands[0].reg; 9886 9887 if (inst.operands[0].reg == inst.operands[1].reg) 9888 inst.instruction |= inst.operands[2].reg << 3; 9889 else if (inst.operands[0].reg == inst.operands[2].reg) 9890 inst.instruction |= inst.operands[1].reg << 3; 9891 else 9892 constraint (1, _("dest must overlap one source register")); 9893 } 9894} 9895 9896static void 9897do_t_mull (void) 9898{ 9899 inst.instruction |= inst.operands[0].reg << 12; 9900 inst.instruction |= inst.operands[1].reg << 8; 9901 inst.instruction |= inst.operands[2].reg << 16; 9902 inst.instruction |= inst.operands[3].reg; 9903 9904 if (inst.operands[0].reg == inst.operands[1].reg) 9905 as_tsktsk (_("rdhi and rdlo must be different")); 9906} 9907 9908static void 9909do_t_nop (void) 9910{ 9911 if (unified_syntax) 9912 { 9913 if (inst.size_req == 4 || inst.operands[0].imm > 15) 9914 { 9915 inst.instruction = THUMB_OP32 (inst.instruction); 9916 inst.instruction |= inst.operands[0].imm; 9917 } 9918 else 9919 { 9920 inst.instruction = THUMB_OP16 (inst.instruction); 9921 inst.instruction |= inst.operands[0].imm << 4; 9922 } 9923 } 9924 else 9925 { 9926 constraint (inst.operands[0].present, 9927 _("Thumb does not support NOP with hints")); 9928 inst.instruction = 0x46c0; 9929 } 9930} 9931 9932static void 9933do_t_neg (void) 9934{ 9935 if (unified_syntax) 9936 { 9937 bfd_boolean narrow; 9938 9939 if (THUMB_SETS_FLAGS (inst.instruction)) 9940 narrow = (current_it_mask == 0); 9941 else 9942 narrow = (current_it_mask != 0); 9943 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) 9944 narrow = FALSE; 9945 if (inst.size_req == 4) 9946 narrow = FALSE; 9947 9948 if (!narrow) 9949 { 9950 inst.instruction = THUMB_OP32 (inst.instruction); 9951 inst.instruction |= inst.operands[0].reg << 8; 9952 inst.instruction |= inst.operands[1].reg << 16; 9953 } 9954 else 9955 { 9956 inst.instruction = THUMB_OP16 (inst.instruction); 9957 inst.instruction |= inst.operands[0].reg; 9958 inst.instruction |= inst.operands[1].reg << 3; 9959 } 9960 } 9961 else 9962 { 9963 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, 9964 BAD_HIREG); 9965 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 9966 9967 inst.instruction = THUMB_OP16 (inst.instruction); 9968 inst.instruction |= inst.operands[0].reg; 9969 inst.instruction |= inst.operands[1].reg << 3; 9970 } 9971} 9972 9973static void 9974do_t_pkhbt (void) 9975{ 9976 inst.instruction |= inst.operands[0].reg << 8; 9977 inst.instruction |= inst.operands[1].reg << 16; 9978 inst.instruction |= inst.operands[2].reg; 9979 if (inst.operands[3].present) 9980 { 9981 unsigned int val = inst.reloc.exp.X_add_number; 9982 constraint (inst.reloc.exp.X_op != O_constant, 9983 _("expression too complex")); 9984 inst.instruction |= (val & 0x1c) << 10; 9985 inst.instruction |= (val & 0x03) << 6; 9986 } 9987} 9988 9989static void 9990do_t_pkhtb (void) 9991{ 9992 if (!inst.operands[3].present) 9993 inst.instruction &= ~0x00000020; 9994 do_t_pkhbt (); 9995} 9996 9997static void 9998do_t_pld (void) 9999{ 10000 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); 10001} 10002 10003static void 10004do_t_push_pop (void) 10005{ 10006 unsigned mask; 10007 10008 constraint (inst.operands[0].writeback, 10009 _("push/pop do not support {reglist}^")); 10010 constraint (inst.reloc.type != BFD_RELOC_UNUSED, 10011 _("expression too complex")); 10012 10013 mask = inst.operands[0].imm; 10014 if ((mask & ~0xff) == 0) 10015 inst.instruction = THUMB_OP16 (inst.instruction) | mask; 10016 else if ((inst.instruction == T_MNEM_push 10017 && (mask & ~0xff) == 1 << REG_LR) 10018 || (inst.instruction == T_MNEM_pop 10019 && (mask & ~0xff) == 1 << REG_PC)) 10020 { 10021 inst.instruction = THUMB_OP16 (inst.instruction); 10022 inst.instruction |= THUMB_PP_PC_LR; 10023 inst.instruction |= mask & 0xff; 10024 } 10025 else if (unified_syntax) 10026 { 10027 inst.instruction = THUMB_OP32 (inst.instruction); 10028 encode_thumb2_ldmstm(13, mask, TRUE); 10029 } 10030 else 10031 { 10032 inst.error = _("invalid register list to push/pop instruction"); 10033 return; 10034 } 10035} 10036 10037static void 10038do_t_rbit (void) 10039{ 10040 inst.instruction |= inst.operands[0].reg << 8; 10041 inst.instruction |= inst.operands[1].reg << 16; 10042} 10043 10044static void 10045do_t_rd_rm (void) 10046{ 10047 inst.instruction |= inst.operands[0].reg << 8; 10048 inst.instruction |= inst.operands[1].reg; 10049} 10050 10051static void 10052do_t_rev (void) 10053{ 10054 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 10055 && inst.size_req != 4) 10056 { 10057 inst.instruction = THUMB_OP16 (inst.instruction); 10058 inst.instruction |= inst.operands[0].reg; 10059 inst.instruction |= inst.operands[1].reg << 3; 10060 } 10061 else if (unified_syntax) 10062 { 10063 inst.instruction = THUMB_OP32 (inst.instruction); 10064 inst.instruction |= inst.operands[0].reg << 8; 10065 inst.instruction |= inst.operands[1].reg << 16; 10066 inst.instruction |= inst.operands[1].reg; 10067 } 10068 else 10069 inst.error = BAD_HIREG; 10070} 10071 10072static void 10073do_t_rsb (void) 10074{ 10075 int Rd, Rs; 10076 10077 Rd = inst.operands[0].reg; 10078 Rs = (inst.operands[1].present 10079 ? inst.operands[1].reg /* Rd, Rs, foo */ 10080 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 10081 10082 inst.instruction |= Rd << 8; 10083 inst.instruction |= Rs << 16; 10084 if (!inst.operands[2].isreg) 10085 { 10086 bfd_boolean narrow; 10087 10088 if ((inst.instruction & 0x00100000) != 0) 10089 narrow = (current_it_mask == 0); 10090 else 10091 narrow = (current_it_mask != 0); 10092 10093 if (Rd > 7 || Rs > 7) 10094 narrow = FALSE; 10095 10096 if (inst.size_req == 4 || !unified_syntax) 10097 narrow = FALSE; 10098 10099 if (inst.reloc.exp.X_op != O_constant 10100 || inst.reloc.exp.X_add_number != 0) 10101 narrow = FALSE; 10102 10103 /* Turn rsb #0 into 16-bit neg. We should probably do this via 10104 relaxation, but it doesn't seem worth the hassle. */ 10105 if (narrow) 10106 { 10107 inst.reloc.type = BFD_RELOC_UNUSED; 10108 inst.instruction = THUMB_OP16 (T_MNEM_negs); 10109 inst.instruction |= Rs << 3; 10110 inst.instruction |= Rd; 10111 } 10112 else 10113 { 10114 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 10115 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 10116 } 10117 } 10118 else 10119 encode_thumb32_shifted_operand (2); 10120} 10121 10122static void 10123do_t_setend (void) 10124{ 10125 constraint (current_it_mask, BAD_NOT_IT); 10126 if (inst.operands[0].imm) 10127 inst.instruction |= 0x8; 10128} 10129 10130static void 10131do_t_shift (void) 10132{ 10133 if (!inst.operands[1].present) 10134 inst.operands[1].reg = inst.operands[0].reg; 10135 10136 if (unified_syntax) 10137 { 10138 bfd_boolean narrow; 10139 int shift_kind; 10140 10141 switch (inst.instruction) 10142 { 10143 case T_MNEM_asr: 10144 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; 10145 case T_MNEM_lsl: 10146 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; 10147 case T_MNEM_lsr: 10148 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; 10149 case T_MNEM_ror: 10150 case T_MNEM_rors: shift_kind = SHIFT_ROR; break; 10151 default: abort (); 10152 } 10153 10154 if (THUMB_SETS_FLAGS (inst.instruction)) 10155 narrow = (current_it_mask == 0); 10156 else 10157 narrow = (current_it_mask != 0); 10158 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) 10159 narrow = FALSE; 10160 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) 10161 narrow = FALSE; 10162 if (inst.operands[2].isreg 10163 && (inst.operands[1].reg != inst.operands[0].reg 10164 || inst.operands[2].reg > 7)) 10165 narrow = FALSE; 10166 if (inst.size_req == 4) 10167 narrow = FALSE; 10168 10169 if (!narrow) 10170 { 10171 if (inst.operands[2].isreg) 10172 { 10173 inst.instruction = THUMB_OP32 (inst.instruction); 10174 inst.instruction |= inst.operands[0].reg << 8; 10175 inst.instruction |= inst.operands[1].reg << 16; 10176 inst.instruction |= inst.operands[2].reg; 10177 } 10178 else 10179 { 10180 inst.operands[1].shifted = 1; 10181 inst.operands[1].shift_kind = shift_kind; 10182 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) 10183 ? T_MNEM_movs : T_MNEM_mov); 10184 inst.instruction |= inst.operands[0].reg << 8; 10185 encode_thumb32_shifted_operand (1); 10186 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ 10187 inst.reloc.type = BFD_RELOC_UNUSED; 10188 } 10189 } 10190 else 10191 { 10192 if (inst.operands[2].isreg) 10193 { 10194 switch (shift_kind) 10195 { 10196 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; 10197 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; 10198 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; 10199 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; 10200 default: abort (); 10201 } 10202 10203 inst.instruction |= inst.operands[0].reg; 10204 inst.instruction |= inst.operands[2].reg << 3; 10205 } 10206 else 10207 { 10208 switch (shift_kind) 10209 { 10210 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; 10211 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; 10212 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; 10213 default: abort (); 10214 } 10215 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 10216 inst.instruction |= inst.operands[0].reg; 10217 inst.instruction |= inst.operands[1].reg << 3; 10218 } 10219 } 10220 } 10221 else 10222 { 10223 constraint (inst.operands[0].reg > 7 10224 || inst.operands[1].reg > 7, BAD_HIREG); 10225 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 10226 10227 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ 10228 { 10229 constraint (inst.operands[2].reg > 7, BAD_HIREG); 10230 constraint (inst.operands[0].reg != inst.operands[1].reg, 10231 _("source1 and dest must be same register")); 10232 10233 switch (inst.instruction) 10234 { 10235 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; 10236 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; 10237 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; 10238 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; 10239 default: abort (); 10240 } 10241 10242 inst.instruction |= inst.operands[0].reg; 10243 inst.instruction |= inst.operands[2].reg << 3; 10244 } 10245 else 10246 { 10247 switch (inst.instruction) 10248 { 10249 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; 10250 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; 10251 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; 10252 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; 10253 default: abort (); 10254 } 10255 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 10256 inst.instruction |= inst.operands[0].reg; 10257 inst.instruction |= inst.operands[1].reg << 3; 10258 } 10259 } 10260} 10261 10262static void 10263do_t_simd (void) 10264{ 10265 inst.instruction |= inst.operands[0].reg << 8; 10266 inst.instruction |= inst.operands[1].reg << 16; 10267 inst.instruction |= inst.operands[2].reg; 10268} 10269 10270static void 10271do_t_smc (void) 10272{ 10273 unsigned int value = inst.reloc.exp.X_add_number; 10274 constraint (inst.reloc.exp.X_op != O_constant, 10275 _("expression too complex")); 10276 inst.reloc.type = BFD_RELOC_UNUSED; 10277 inst.instruction |= (value & 0xf000) >> 12; 10278 inst.instruction |= (value & 0x0ff0); 10279 inst.instruction |= (value & 0x000f) << 16; 10280} 10281 10282static void 10283do_t_ssat (void) 10284{ 10285 inst.instruction |= inst.operands[0].reg << 8; 10286 inst.instruction |= inst.operands[1].imm - 1; 10287 inst.instruction |= inst.operands[2].reg << 16; 10288 10289 if (inst.operands[3].present) 10290 { 10291 constraint (inst.reloc.exp.X_op != O_constant, 10292 _("expression too complex")); 10293 10294 if (inst.reloc.exp.X_add_number != 0) 10295 { 10296 if (inst.operands[3].shift_kind == SHIFT_ASR) 10297 inst.instruction |= 0x00200000; /* sh bit */ 10298 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; 10299 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; 10300 } 10301 inst.reloc.type = BFD_RELOC_UNUSED; 10302 } 10303} 10304 10305static void 10306do_t_ssat16 (void) 10307{ 10308 inst.instruction |= inst.operands[0].reg << 8; 10309 inst.instruction |= inst.operands[1].imm - 1; 10310 inst.instruction |= inst.operands[2].reg << 16; 10311} 10312 10313static void 10314do_t_strex (void) 10315{ 10316 constraint (!inst.operands[2].isreg || !inst.operands[2].preind 10317 || inst.operands[2].postind || inst.operands[2].writeback 10318 || inst.operands[2].immisreg || inst.operands[2].shifted 10319 || inst.operands[2].negative, 10320 BAD_ADDR_MODE); 10321 10322 inst.instruction |= inst.operands[0].reg << 8; 10323 inst.instruction |= inst.operands[1].reg << 12; 10324 inst.instruction |= inst.operands[2].reg << 16; 10325 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; 10326} 10327 10328static void 10329do_t_strexd (void) 10330{ 10331 if (!inst.operands[2].present) 10332 inst.operands[2].reg = inst.operands[1].reg + 1; 10333 10334 constraint (inst.operands[0].reg == inst.operands[1].reg 10335 || inst.operands[0].reg == inst.operands[2].reg 10336 || inst.operands[0].reg == inst.operands[3].reg 10337 || inst.operands[1].reg == inst.operands[2].reg, 10338 BAD_OVERLAP); 10339 10340 inst.instruction |= inst.operands[0].reg; 10341 inst.instruction |= inst.operands[1].reg << 12; 10342 inst.instruction |= inst.operands[2].reg << 8; 10343 inst.instruction |= inst.operands[3].reg << 16; 10344} 10345 10346static void 10347do_t_sxtah (void) 10348{ 10349 inst.instruction |= inst.operands[0].reg << 8; 10350 inst.instruction |= inst.operands[1].reg << 16; 10351 inst.instruction |= inst.operands[2].reg; 10352 inst.instruction |= inst.operands[3].imm << 4; 10353} 10354 10355static void 10356do_t_sxth (void) 10357{ 10358 if (inst.instruction <= 0xffff && inst.size_req != 4 10359 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 10360 && (!inst.operands[2].present || inst.operands[2].imm == 0)) 10361 { 10362 inst.instruction = THUMB_OP16 (inst.instruction); 10363 inst.instruction |= inst.operands[0].reg; 10364 inst.instruction |= inst.operands[1].reg << 3; 10365 } 10366 else if (unified_syntax) 10367 { 10368 if (inst.instruction <= 0xffff) 10369 inst.instruction = THUMB_OP32 (inst.instruction); 10370 inst.instruction |= inst.operands[0].reg << 8; 10371 inst.instruction |= inst.operands[1].reg; 10372 inst.instruction |= inst.operands[2].imm << 4; 10373 } 10374 else 10375 { 10376 constraint (inst.operands[2].present && inst.operands[2].imm != 0, 10377 _("Thumb encoding does not support rotation")); 10378 constraint (1, BAD_HIREG); 10379 } 10380} 10381 10382static void 10383do_t_swi (void) 10384{ 10385 inst.reloc.type = BFD_RELOC_ARM_SWI; 10386} 10387 10388static void 10389do_t_tb (void) 10390{ 10391 int half; 10392 10393 half = (inst.instruction & 0x10) != 0; 10394 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 10395 constraint (inst.operands[0].immisreg, 10396 _("instruction requires register index")); 10397 constraint (inst.operands[0].imm == 15, 10398 _("PC is not a valid index register")); 10399 constraint (!half && inst.operands[0].shifted, 10400 _("instruction does not allow shifted index")); 10401 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm; 10402} 10403 10404static void 10405do_t_usat (void) 10406{ 10407 inst.instruction |= inst.operands[0].reg << 8; 10408 inst.instruction |= inst.operands[1].imm; 10409 inst.instruction |= inst.operands[2].reg << 16; 10410 10411 if (inst.operands[3].present) 10412 { 10413 constraint (inst.reloc.exp.X_op != O_constant, 10414 _("expression too complex")); 10415 if (inst.reloc.exp.X_add_number != 0) 10416 { 10417 if (inst.operands[3].shift_kind == SHIFT_ASR) 10418 inst.instruction |= 0x00200000; /* sh bit */ 10419 10420 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; 10421 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; 10422 } 10423 inst.reloc.type = BFD_RELOC_UNUSED; 10424 } 10425} 10426 10427static void 10428do_t_usat16 (void) 10429{ 10430 inst.instruction |= inst.operands[0].reg << 8; 10431 inst.instruction |= inst.operands[1].imm; 10432 inst.instruction |= inst.operands[2].reg << 16; 10433} 10434 10435/* Neon instruction encoder helpers. */ 10436 10437/* Encodings for the different types for various Neon opcodes. */ 10438 10439/* An "invalid" code for the following tables. */ 10440#define N_INV -1u 10441 10442struct neon_tab_entry 10443{ 10444 unsigned integer; 10445 unsigned float_or_poly; 10446 unsigned scalar_or_imm; 10447}; 10448 10449/* Map overloaded Neon opcodes to their respective encodings. */ 10450#define NEON_ENC_TAB \ 10451 X(vabd, 0x0000700, 0x1200d00, N_INV), \ 10452 X(vmax, 0x0000600, 0x0000f00, N_INV), \ 10453 X(vmin, 0x0000610, 0x0200f00, N_INV), \ 10454 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ 10455 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ 10456 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ 10457 X(vadd, 0x0000800, 0x0000d00, N_INV), \ 10458 X(vsub, 0x1000800, 0x0200d00, N_INV), \ 10459 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ 10460 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ 10461 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ 10462 /* Register variants of the following two instructions are encoded as 10463 vcge / vcgt with the operands reversed. */ \ 10464 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ 10465 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ 10466 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ 10467 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ 10468 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ 10469 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ 10470 X(vmlal, 0x0800800, N_INV, 0x0800240), \ 10471 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ 10472 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ 10473 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ 10474 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ 10475 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ 10476 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ 10477 X(vshl, 0x0000400, N_INV, 0x0800510), \ 10478 X(vqshl, 0x0000410, N_INV, 0x0800710), \ 10479 X(vand, 0x0000110, N_INV, 0x0800030), \ 10480 X(vbic, 0x0100110, N_INV, 0x0800030), \ 10481 X(veor, 0x1000110, N_INV, N_INV), \ 10482 X(vorn, 0x0300110, N_INV, 0x0800010), \ 10483 X(vorr, 0x0200110, N_INV, 0x0800010), \ 10484 X(vmvn, 0x1b00580, N_INV, 0x0800030), \ 10485 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ 10486 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ 10487 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ 10488 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ 10489 X(vst1, 0x0000000, 0x0800000, N_INV), \ 10490 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ 10491 X(vst2, 0x0000100, 0x0800100, N_INV), \ 10492 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ 10493 X(vst3, 0x0000200, 0x0800200, N_INV), \ 10494 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ 10495 X(vst4, 0x0000300, 0x0800300, N_INV), \ 10496 X(vmovn, 0x1b20200, N_INV, N_INV), \ 10497 X(vtrn, 0x1b20080, N_INV, N_INV), \ 10498 X(vqmovn, 0x1b20200, N_INV, N_INV), \ 10499 X(vqmovun, 0x1b20240, N_INV, N_INV), \ 10500 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ 10501 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \ 10502 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \ 10503 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ 10504 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ 10505 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ 10506 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV) 10507 10508enum neon_opc 10509{ 10510#define X(OPC,I,F,S) N_MNEM_##OPC 10511NEON_ENC_TAB 10512#undef X 10513}; 10514 10515static const struct neon_tab_entry neon_enc_tab[] = 10516{ 10517#define X(OPC,I,F,S) { (I), (F), (S) } 10518NEON_ENC_TAB 10519#undef X 10520}; 10521 10522#define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 10523#define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 10524#define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 10525#define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 10526#define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 10527#define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 10528#define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 10529#define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 10530#define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 10531#define NEON_ENC_SINGLE(X) \ 10532 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) 10533#define NEON_ENC_DOUBLE(X) \ 10534 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) 10535 10536/* Define shapes for instruction operands. The following mnemonic characters 10537 are used in this table: 10538 10539 F - VFP S<n> register 10540 D - Neon D<n> register 10541 Q - Neon Q<n> register 10542 I - Immediate 10543 S - Scalar 10544 R - ARM register 10545 L - D<n> register list 10546 10547 This table is used to generate various data: 10548 - enumerations of the form NS_DDR to be used as arguments to 10549 neon_select_shape. 10550 - a table classifying shapes into single, double, quad, mixed. 10551 - a table used to drive neon_select_shape. 10552*/ 10553 10554#define NEON_SHAPE_DEF \ 10555 X(3, (D, D, D), DOUBLE), \ 10556 X(3, (Q, Q, Q), QUAD), \ 10557 X(3, (D, D, I), DOUBLE), \ 10558 X(3, (Q, Q, I), QUAD), \ 10559 X(3, (D, D, S), DOUBLE), \ 10560 X(3, (Q, Q, S), QUAD), \ 10561 X(2, (D, D), DOUBLE), \ 10562 X(2, (Q, Q), QUAD), \ 10563 X(2, (D, S), DOUBLE), \ 10564 X(2, (Q, S), QUAD), \ 10565 X(2, (D, R), DOUBLE), \ 10566 X(2, (Q, R), QUAD), \ 10567 X(2, (D, I), DOUBLE), \ 10568 X(2, (Q, I), QUAD), \ 10569 X(3, (D, L, D), DOUBLE), \ 10570 X(2, (D, Q), MIXED), \ 10571 X(2, (Q, D), MIXED), \ 10572 X(3, (D, Q, I), MIXED), \ 10573 X(3, (Q, D, I), MIXED), \ 10574 X(3, (Q, D, D), MIXED), \ 10575 X(3, (D, Q, Q), MIXED), \ 10576 X(3, (Q, Q, D), MIXED), \ 10577 X(3, (Q, D, S), MIXED), \ 10578 X(3, (D, Q, S), MIXED), \ 10579 X(4, (D, D, D, I), DOUBLE), \ 10580 X(4, (Q, Q, Q, I), QUAD), \ 10581 X(2, (F, F), SINGLE), \ 10582 X(3, (F, F, F), SINGLE), \ 10583 X(2, (F, I), SINGLE), \ 10584 X(2, (F, D), MIXED), \ 10585 X(2, (D, F), MIXED), \ 10586 X(3, (F, F, I), MIXED), \ 10587 X(4, (R, R, F, F), SINGLE), \ 10588 X(4, (F, F, R, R), SINGLE), \ 10589 X(3, (D, R, R), DOUBLE), \ 10590 X(3, (R, R, D), DOUBLE), \ 10591 X(2, (S, R), SINGLE), \ 10592 X(2, (R, S), SINGLE), \ 10593 X(2, (F, R), SINGLE), \ 10594 X(2, (R, F), SINGLE) 10595 10596#define S2(A,B) NS_##A##B 10597#define S3(A,B,C) NS_##A##B##C 10598#define S4(A,B,C,D) NS_##A##B##C##D 10599 10600#define X(N, L, C) S##N L 10601 10602enum neon_shape 10603{ 10604 NEON_SHAPE_DEF, 10605 NS_NULL 10606}; 10607 10608#undef X 10609#undef S2 10610#undef S3 10611#undef S4 10612 10613enum neon_shape_class 10614{ 10615 SC_SINGLE, 10616 SC_DOUBLE, 10617 SC_QUAD, 10618 SC_MIXED 10619}; 10620 10621#define X(N, L, C) SC_##C 10622 10623static enum neon_shape_class neon_shape_class[] = 10624{ 10625 NEON_SHAPE_DEF 10626}; 10627 10628#undef X 10629 10630enum neon_shape_el 10631{ 10632 SE_F, 10633 SE_D, 10634 SE_Q, 10635 SE_I, 10636 SE_S, 10637 SE_R, 10638 SE_L 10639}; 10640 10641/* Register widths of above. */ 10642static unsigned neon_shape_el_size[] = 10643{ 10644 32, 10645 64, 10646 128, 10647 0, 10648 32, 10649 32, 10650 0 10651}; 10652 10653struct neon_shape_info 10654{ 10655 unsigned els; 10656 enum neon_shape_el el[NEON_MAX_TYPE_ELS]; 10657}; 10658 10659#define S2(A,B) { SE_##A, SE_##B } 10660#define S3(A,B,C) { SE_##A, SE_##B, SE_##C } 10661#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } 10662 10663#define X(N, L, C) { N, S##N L } 10664 10665static struct neon_shape_info neon_shape_tab[] = 10666{ 10667 NEON_SHAPE_DEF 10668}; 10669 10670#undef X 10671#undef S2 10672#undef S3 10673#undef S4 10674 10675/* Bit masks used in type checking given instructions. 10676 'N_EQK' means the type must be the same as (or based on in some way) the key 10677 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is 10678 set, various other bits can be set as well in order to modify the meaning of 10679 the type constraint. */ 10680 10681enum neon_type_mask 10682{ 10683 N_S8 = 0x000001, 10684 N_S16 = 0x000002, 10685 N_S32 = 0x000004, 10686 N_S64 = 0x000008, 10687 N_U8 = 0x000010, 10688 N_U16 = 0x000020, 10689 N_U32 = 0x000040, 10690 N_U64 = 0x000080, 10691 N_I8 = 0x000100, 10692 N_I16 = 0x000200, 10693 N_I32 = 0x000400, 10694 N_I64 = 0x000800, 10695 N_8 = 0x001000, 10696 N_16 = 0x002000, 10697 N_32 = 0x004000, 10698 N_64 = 0x008000, 10699 N_P8 = 0x010000, 10700 N_P16 = 0x020000, 10701 N_F32 = 0x040000, 10702 N_F64 = 0x080000, 10703 N_KEY = 0x100000, /* key element (main type specifier). */ 10704 N_EQK = 0x200000, /* given operand has the same type & size as the key. */ 10705 N_VFP = 0x400000, /* VFP mode: operand size must match register width. */ 10706 N_DBL = 0x000001, /* if N_EQK, this operand is twice the size. */ 10707 N_HLF = 0x000002, /* if N_EQK, this operand is half the size. */ 10708 N_SGN = 0x000004, /* if N_EQK, this operand is forced to be signed. */ 10709 N_UNS = 0x000008, /* if N_EQK, this operand is forced to be unsigned. */ 10710 N_INT = 0x000010, /* if N_EQK, this operand is forced to be integer. */ 10711 N_FLT = 0x000020, /* if N_EQK, this operand is forced to be float. */ 10712 N_SIZ = 0x000040, /* if N_EQK, this operand is forced to be size-only. */ 10713 N_UTYP = 0, 10714 N_MAX_NONSPECIAL = N_F64 10715}; 10716 10717#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) 10718 10719#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) 10720#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) 10721#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) 10722#define N_SUF_32 (N_SU_32 | N_F32) 10723#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) 10724#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) 10725 10726/* Pass this as the first type argument to neon_check_type to ignore types 10727 altogether. */ 10728#define N_IGNORE_TYPE (N_KEY | N_EQK) 10729 10730/* Select a "shape" for the current instruction (describing register types or 10731 sizes) from a list of alternatives. Return NS_NULL if the current instruction 10732 doesn't fit. For non-polymorphic shapes, checking is usually done as a 10733 function of operand parsing, so this function doesn't need to be called. 10734 Shapes should be listed in order of decreasing length. */ 10735 10736static enum neon_shape 10737neon_select_shape (enum neon_shape shape, ...) 10738{ 10739 va_list ap; 10740 enum neon_shape first_shape = shape; 10741 10742 /* Fix missing optional operands. FIXME: we don't know at this point how 10743 many arguments we should have, so this makes the assumption that we have 10744 > 1. This is true of all current Neon opcodes, I think, but may not be 10745 true in the future. */ 10746 if (!inst.operands[1].present) 10747 inst.operands[1] = inst.operands[0]; 10748 10749 va_start (ap, shape); 10750 10751 for (; shape != NS_NULL; shape = va_arg (ap, int)) 10752 { 10753 unsigned j; 10754 int matches = 1; 10755 10756 for (j = 0; j < neon_shape_tab[shape].els; j++) 10757 { 10758 if (!inst.operands[j].present) 10759 { 10760 matches = 0; 10761 break; 10762 } 10763 10764 switch (neon_shape_tab[shape].el[j]) 10765 { 10766 case SE_F: 10767 if (!(inst.operands[j].isreg 10768 && inst.operands[j].isvec 10769 && inst.operands[j].issingle 10770 && !inst.operands[j].isquad)) 10771 matches = 0; 10772 break; 10773 10774 case SE_D: 10775 if (!(inst.operands[j].isreg 10776 && inst.operands[j].isvec 10777 && !inst.operands[j].isquad 10778 && !inst.operands[j].issingle)) 10779 matches = 0; 10780 break; 10781 10782 case SE_R: 10783 if (!(inst.operands[j].isreg 10784 && !inst.operands[j].isvec)) 10785 matches = 0; 10786 break; 10787 10788 case SE_Q: 10789 if (!(inst.operands[j].isreg 10790 && inst.operands[j].isvec 10791 && inst.operands[j].isquad 10792 && !inst.operands[j].issingle)) 10793 matches = 0; 10794 break; 10795 10796 case SE_I: 10797 if (!(!inst.operands[j].isreg 10798 && !inst.operands[j].isscalar)) 10799 matches = 0; 10800 break; 10801 10802 case SE_S: 10803 if (!(!inst.operands[j].isreg 10804 && inst.operands[j].isscalar)) 10805 matches = 0; 10806 break; 10807 10808 case SE_L: 10809 break; 10810 } 10811 } 10812 if (matches) 10813 break; 10814 } 10815 10816 va_end (ap); 10817 10818 if (shape == NS_NULL && first_shape != NS_NULL) 10819 first_error (_("invalid instruction shape")); 10820 10821 return shape; 10822} 10823 10824/* True if SHAPE is predominantly a quadword operation (most of the time, this 10825 means the Q bit should be set). */ 10826 10827static int 10828neon_quad (enum neon_shape shape) 10829{ 10830 return neon_shape_class[shape] == SC_QUAD; 10831} 10832 10833static void 10834neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, 10835 unsigned *g_size) 10836{ 10837 /* Allow modification to be made to types which are constrained to be 10838 based on the key element, based on bits set alongside N_EQK. */ 10839 if ((typebits & N_EQK) != 0) 10840 { 10841 if ((typebits & N_HLF) != 0) 10842 *g_size /= 2; 10843 else if ((typebits & N_DBL) != 0) 10844 *g_size *= 2; 10845 if ((typebits & N_SGN) != 0) 10846 *g_type = NT_signed; 10847 else if ((typebits & N_UNS) != 0) 10848 *g_type = NT_unsigned; 10849 else if ((typebits & N_INT) != 0) 10850 *g_type = NT_integer; 10851 else if ((typebits & N_FLT) != 0) 10852 *g_type = NT_float; 10853 else if ((typebits & N_SIZ) != 0) 10854 *g_type = NT_untyped; 10855 } 10856} 10857 10858/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" 10859 operand type, i.e. the single type specified in a Neon instruction when it 10860 is the only one given. */ 10861 10862static struct neon_type_el 10863neon_type_promote (struct neon_type_el *key, unsigned thisarg) 10864{ 10865 struct neon_type_el dest = *key; 10866 10867 assert ((thisarg & N_EQK) != 0); 10868 10869 neon_modify_type_size (thisarg, &dest.type, &dest.size); 10870 10871 return dest; 10872} 10873 10874/* Convert Neon type and size into compact bitmask representation. */ 10875 10876static enum neon_type_mask 10877type_chk_of_el_type (enum neon_el_type type, unsigned size) 10878{ 10879 switch (type) 10880 { 10881 case NT_untyped: 10882 switch (size) 10883 { 10884 case 8: return N_8; 10885 case 16: return N_16; 10886 case 32: return N_32; 10887 case 64: return N_64; 10888 default: ; 10889 } 10890 break; 10891 10892 case NT_integer: 10893 switch (size) 10894 { 10895 case 8: return N_I8; 10896 case 16: return N_I16; 10897 case 32: return N_I32; 10898 case 64: return N_I64; 10899 default: ; 10900 } 10901 break; 10902 10903 case NT_float: 10904 switch (size) 10905 { 10906 case 32: return N_F32; 10907 case 64: return N_F64; 10908 default: ; 10909 } 10910 break; 10911 10912 case NT_poly: 10913 switch (size) 10914 { 10915 case 8: return N_P8; 10916 case 16: return N_P16; 10917 default: ; 10918 } 10919 break; 10920 10921 case NT_signed: 10922 switch (size) 10923 { 10924 case 8: return N_S8; 10925 case 16: return N_S16; 10926 case 32: return N_S32; 10927 case 64: return N_S64; 10928 default: ; 10929 } 10930 break; 10931 10932 case NT_unsigned: 10933 switch (size) 10934 { 10935 case 8: return N_U8; 10936 case 16: return N_U16; 10937 case 32: return N_U32; 10938 case 64: return N_U64; 10939 default: ; 10940 } 10941 break; 10942 10943 default: ; 10944 } 10945 10946 return N_UTYP; 10947} 10948 10949/* Convert compact Neon bitmask type representation to a type and size. Only 10950 handles the case where a single bit is set in the mask. */ 10951 10952static int 10953el_type_of_type_chk (enum neon_el_type *type, unsigned *size, 10954 enum neon_type_mask mask) 10955{ 10956 if ((mask & N_EQK) != 0) 10957 return FAIL; 10958 10959 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) 10960 *size = 8; 10961 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0) 10962 *size = 16; 10963 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) 10964 *size = 32; 10965 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0) 10966 *size = 64; 10967 else 10968 return FAIL; 10969 10970 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) 10971 *type = NT_signed; 10972 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) 10973 *type = NT_unsigned; 10974 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) 10975 *type = NT_integer; 10976 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) 10977 *type = NT_untyped; 10978 else if ((mask & (N_P8 | N_P16)) != 0) 10979 *type = NT_poly; 10980 else if ((mask & (N_F32 | N_F64)) != 0) 10981 *type = NT_float; 10982 else 10983 return FAIL; 10984 10985 return SUCCESS; 10986} 10987 10988/* Modify a bitmask of allowed types. This is only needed for type 10989 relaxation. */ 10990 10991static unsigned 10992modify_types_allowed (unsigned allowed, unsigned mods) 10993{ 10994 unsigned size; 10995 enum neon_el_type type; 10996 unsigned destmask; 10997 int i; 10998 10999 destmask = 0; 11000 11001 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) 11002 { 11003 if (el_type_of_type_chk (&type, &size, allowed & i) == SUCCESS) 11004 { 11005 neon_modify_type_size (mods, &type, &size); 11006 destmask |= type_chk_of_el_type (type, size); 11007 } 11008 } 11009 11010 return destmask; 11011} 11012 11013/* Check type and return type classification. 11014 The manual states (paraphrase): If one datatype is given, it indicates the 11015 type given in: 11016 - the second operand, if there is one 11017 - the operand, if there is no second operand 11018 - the result, if there are no operands. 11019 This isn't quite good enough though, so we use a concept of a "key" datatype 11020 which is set on a per-instruction basis, which is the one which matters when 11021 only one data type is written. 11022 Note: this function has side-effects (e.g. filling in missing operands). All 11023 Neon instructions should call it before performing bit encoding. */ 11024 11025static struct neon_type_el 11026neon_check_type (unsigned els, enum neon_shape ns, ...) 11027{ 11028 va_list ap; 11029 unsigned i, pass, key_el = 0; 11030 unsigned types[NEON_MAX_TYPE_ELS]; 11031 enum neon_el_type k_type = NT_invtype; 11032 unsigned k_size = -1u; 11033 struct neon_type_el badtype = {NT_invtype, -1}; 11034 unsigned key_allowed = 0; 11035 11036 /* Optional registers in Neon instructions are always (not) in operand 1. 11037 Fill in the missing operand here, if it was omitted. */ 11038 if (els > 1 && !inst.operands[1].present) 11039 inst.operands[1] = inst.operands[0]; 11040 11041 /* Suck up all the varargs. */ 11042 va_start (ap, ns); 11043 for (i = 0; i < els; i++) 11044 { 11045 unsigned thisarg = va_arg (ap, unsigned); 11046 if (thisarg == N_IGNORE_TYPE) 11047 { 11048 va_end (ap); 11049 return badtype; 11050 } 11051 types[i] = thisarg; 11052 if ((thisarg & N_KEY) != 0) 11053 key_el = i; 11054 } 11055 va_end (ap); 11056 11057 if (inst.vectype.elems > 0) 11058 for (i = 0; i < els; i++) 11059 if (inst.operands[i].vectype.type != NT_invtype) 11060 { 11061 first_error (_("types specified in both the mnemonic and operands")); 11062 return badtype; 11063 } 11064 11065 /* Duplicate inst.vectype elements here as necessary. 11066 FIXME: No idea if this is exactly the same as the ARM assembler, 11067 particularly when an insn takes one register and one non-register 11068 operand. */ 11069 if (inst.vectype.elems == 1 && els > 1) 11070 { 11071 unsigned j; 11072 inst.vectype.elems = els; 11073 inst.vectype.el[key_el] = inst.vectype.el[0]; 11074 for (j = 0; j < els; j++) 11075 if (j != key_el) 11076 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], 11077 types[j]); 11078 } 11079 else if (inst.vectype.elems == 0 && els > 0) 11080 { 11081 unsigned j; 11082 /* No types were given after the mnemonic, so look for types specified 11083 after each operand. We allow some flexibility here; as long as the 11084 "key" operand has a type, we can infer the others. */ 11085 for (j = 0; j < els; j++) 11086 if (inst.operands[j].vectype.type != NT_invtype) 11087 inst.vectype.el[j] = inst.operands[j].vectype; 11088 11089 if (inst.operands[key_el].vectype.type != NT_invtype) 11090 { 11091 for (j = 0; j < els; j++) 11092 if (inst.operands[j].vectype.type == NT_invtype) 11093 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], 11094 types[j]); 11095 } 11096 else 11097 { 11098 first_error (_("operand types can't be inferred")); 11099 return badtype; 11100 } 11101 } 11102 else if (inst.vectype.elems != els) 11103 { 11104 first_error (_("type specifier has the wrong number of parts")); 11105 return badtype; 11106 } 11107 11108 for (pass = 0; pass < 2; pass++) 11109 { 11110 for (i = 0; i < els; i++) 11111 { 11112 unsigned thisarg = types[i]; 11113 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) 11114 ? modify_types_allowed (key_allowed, thisarg) : thisarg; 11115 enum neon_el_type g_type = inst.vectype.el[i].type; 11116 unsigned g_size = inst.vectype.el[i].size; 11117 11118 /* Decay more-specific signed & unsigned types to sign-insensitive 11119 integer types if sign-specific variants are unavailable. */ 11120 if ((g_type == NT_signed || g_type == NT_unsigned) 11121 && (types_allowed & N_SU_ALL) == 0) 11122 g_type = NT_integer; 11123 11124 /* If only untyped args are allowed, decay any more specific types to 11125 them. Some instructions only care about signs for some element 11126 sizes, so handle that properly. */ 11127 if ((g_size == 8 && (types_allowed & N_8) != 0) 11128 || (g_size == 16 && (types_allowed & N_16) != 0) 11129 || (g_size == 32 && (types_allowed & N_32) != 0) 11130 || (g_size == 64 && (types_allowed & N_64) != 0)) 11131 g_type = NT_untyped; 11132 11133 if (pass == 0) 11134 { 11135 if ((thisarg & N_KEY) != 0) 11136 { 11137 k_type = g_type; 11138 k_size = g_size; 11139 key_allowed = thisarg & ~N_KEY; 11140 } 11141 } 11142 else 11143 { 11144 if ((thisarg & N_VFP) != 0) 11145 { 11146 enum neon_shape_el regshape = neon_shape_tab[ns].el[i]; 11147 unsigned regwidth = neon_shape_el_size[regshape], match; 11148 11149 /* In VFP mode, operands must match register widths. If we 11150 have a key operand, use its width, else use the width of 11151 the current operand. */ 11152 if (k_size != -1u) 11153 match = k_size; 11154 else 11155 match = g_size; 11156 11157 if (regwidth != match) 11158 { 11159 first_error (_("operand size must match register width")); 11160 return badtype; 11161 } 11162 } 11163 11164 if ((thisarg & N_EQK) == 0) 11165 { 11166 unsigned given_type = type_chk_of_el_type (g_type, g_size); 11167 11168 if ((given_type & types_allowed) == 0) 11169 { 11170 first_error (_("bad type in Neon instruction")); 11171 return badtype; 11172 } 11173 } 11174 else 11175 { 11176 enum neon_el_type mod_k_type = k_type; 11177 unsigned mod_k_size = k_size; 11178 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); 11179 if (g_type != mod_k_type || g_size != mod_k_size) 11180 { 11181 first_error (_("inconsistent types in Neon instruction")); 11182 return badtype; 11183 } 11184 } 11185 } 11186 } 11187 } 11188 11189 return inst.vectype.el[key_el]; 11190} 11191 11192/* Neon-style VFP instruction forwarding. */ 11193 11194/* Thumb VFP instructions have 0xE in the condition field. */ 11195 11196static void 11197do_vfp_cond_or_thumb (void) 11198{ 11199 if (thumb_mode) 11200 inst.instruction |= 0xe0000000; 11201 else 11202 inst.instruction |= inst.cond << 28; 11203} 11204 11205/* Look up and encode a simple mnemonic, for use as a helper function for the 11206 Neon-style VFP syntax. This avoids duplication of bits of the insns table, 11207 etc. It is assumed that operand parsing has already been done, and that the 11208 operands are in the form expected by the given opcode (this isn't necessarily 11209 the same as the form in which they were parsed, hence some massaging must 11210 take place before this function is called). 11211 Checks current arch version against that in the looked-up opcode. */ 11212 11213static void 11214do_vfp_nsyn_opcode (const char *opname) 11215{ 11216 const struct asm_opcode *opcode; 11217 11218 opcode = hash_find (arm_ops_hsh, opname); 11219 11220 if (!opcode) 11221 abort (); 11222 11223 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, 11224 thumb_mode ? *opcode->tvariant : *opcode->avariant), 11225 _(BAD_FPU)); 11226 11227 if (thumb_mode) 11228 { 11229 inst.instruction = opcode->tvalue; 11230 opcode->tencode (); 11231 } 11232 else 11233 { 11234 inst.instruction = (inst.cond << 28) | opcode->avalue; 11235 opcode->aencode (); 11236 } 11237} 11238 11239static void 11240do_vfp_nsyn_add_sub (enum neon_shape rs) 11241{ 11242 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; 11243 11244 if (rs == NS_FFF) 11245 { 11246 if (is_add) 11247 do_vfp_nsyn_opcode ("fadds"); 11248 else 11249 do_vfp_nsyn_opcode ("fsubs"); 11250 } 11251 else 11252 { 11253 if (is_add) 11254 do_vfp_nsyn_opcode ("faddd"); 11255 else 11256 do_vfp_nsyn_opcode ("fsubd"); 11257 } 11258} 11259 11260/* Check operand types to see if this is a VFP instruction, and if so call 11261 PFN (). */ 11262 11263static int 11264try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) 11265{ 11266 enum neon_shape rs; 11267 struct neon_type_el et; 11268 11269 switch (args) 11270 { 11271 case 2: 11272 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 11273 et = neon_check_type (2, rs, 11274 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11275 break; 11276 11277 case 3: 11278 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 11279 et = neon_check_type (3, rs, 11280 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11281 break; 11282 11283 default: 11284 abort (); 11285 } 11286 11287 if (et.type != NT_invtype) 11288 { 11289 pfn (rs); 11290 return SUCCESS; 11291 } 11292 else 11293 inst.error = NULL; 11294 11295 return FAIL; 11296} 11297 11298static void 11299do_vfp_nsyn_mla_mls (enum neon_shape rs) 11300{ 11301 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; 11302 11303 if (rs == NS_FFF) 11304 { 11305 if (is_mla) 11306 do_vfp_nsyn_opcode ("fmacs"); 11307 else 11308 do_vfp_nsyn_opcode ("fmscs"); 11309 } 11310 else 11311 { 11312 if (is_mla) 11313 do_vfp_nsyn_opcode ("fmacd"); 11314 else 11315 do_vfp_nsyn_opcode ("fmscd"); 11316 } 11317} 11318 11319static void 11320do_vfp_nsyn_mul (enum neon_shape rs) 11321{ 11322 if (rs == NS_FFF) 11323 do_vfp_nsyn_opcode ("fmuls"); 11324 else 11325 do_vfp_nsyn_opcode ("fmuld"); 11326} 11327 11328static void 11329do_vfp_nsyn_abs_neg (enum neon_shape rs) 11330{ 11331 int is_neg = (inst.instruction & 0x80) != 0; 11332 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); 11333 11334 if (rs == NS_FF) 11335 { 11336 if (is_neg) 11337 do_vfp_nsyn_opcode ("fnegs"); 11338 else 11339 do_vfp_nsyn_opcode ("fabss"); 11340 } 11341 else 11342 { 11343 if (is_neg) 11344 do_vfp_nsyn_opcode ("fnegd"); 11345 else 11346 do_vfp_nsyn_opcode ("fabsd"); 11347 } 11348} 11349 11350/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision 11351 insns belong to Neon, and are handled elsewhere. */ 11352 11353static void 11354do_vfp_nsyn_ldm_stm (int is_dbmode) 11355{ 11356 int is_ldm = (inst.instruction & (1 << 20)) != 0; 11357 if (is_ldm) 11358 { 11359 if (is_dbmode) 11360 do_vfp_nsyn_opcode ("fldmdbs"); 11361 else 11362 do_vfp_nsyn_opcode ("fldmias"); 11363 } 11364 else 11365 { 11366 if (is_dbmode) 11367 do_vfp_nsyn_opcode ("fstmdbs"); 11368 else 11369 do_vfp_nsyn_opcode ("fstmias"); 11370 } 11371} 11372 11373static void 11374do_vfp_nsyn_sqrt (void) 11375{ 11376 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 11377 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11378 11379 if (rs == NS_FF) 11380 do_vfp_nsyn_opcode ("fsqrts"); 11381 else 11382 do_vfp_nsyn_opcode ("fsqrtd"); 11383} 11384 11385static void 11386do_vfp_nsyn_div (void) 11387{ 11388 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 11389 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, 11390 N_F32 | N_F64 | N_KEY | N_VFP); 11391 11392 if (rs == NS_FFF) 11393 do_vfp_nsyn_opcode ("fdivs"); 11394 else 11395 do_vfp_nsyn_opcode ("fdivd"); 11396} 11397 11398static void 11399do_vfp_nsyn_nmul (void) 11400{ 11401 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 11402 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, 11403 N_F32 | N_F64 | N_KEY | N_VFP); 11404 11405 if (rs == NS_FFF) 11406 { 11407 inst.instruction = NEON_ENC_SINGLE (inst.instruction); 11408 do_vfp_sp_dyadic (); 11409 } 11410 else 11411 { 11412 inst.instruction = NEON_ENC_DOUBLE (inst.instruction); 11413 do_vfp_dp_rd_rn_rm (); 11414 } 11415 do_vfp_cond_or_thumb (); 11416} 11417 11418static void 11419do_vfp_nsyn_cmp (void) 11420{ 11421 if (inst.operands[1].isreg) 11422 { 11423 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 11424 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11425 11426 if (rs == NS_FF) 11427 { 11428 inst.instruction = NEON_ENC_SINGLE (inst.instruction); 11429 do_vfp_sp_monadic (); 11430 } 11431 else 11432 { 11433 inst.instruction = NEON_ENC_DOUBLE (inst.instruction); 11434 do_vfp_dp_rd_rm (); 11435 } 11436 } 11437 else 11438 { 11439 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); 11440 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); 11441 11442 switch (inst.instruction & 0x0fffffff) 11443 { 11444 case N_MNEM_vcmp: 11445 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; 11446 break; 11447 case N_MNEM_vcmpe: 11448 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; 11449 break; 11450 default: 11451 abort (); 11452 } 11453 11454 if (rs == NS_FI) 11455 { 11456 inst.instruction = NEON_ENC_SINGLE (inst.instruction); 11457 do_vfp_sp_compare_z (); 11458 } 11459 else 11460 { 11461 inst.instruction = NEON_ENC_DOUBLE (inst.instruction); 11462 do_vfp_dp_rd (); 11463 } 11464 } 11465 do_vfp_cond_or_thumb (); 11466} 11467 11468static void 11469nsyn_insert_sp (void) 11470{ 11471 inst.operands[1] = inst.operands[0]; 11472 memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); 11473 inst.operands[0].reg = 13; 11474 inst.operands[0].isreg = 1; 11475 inst.operands[0].writeback = 1; 11476 inst.operands[0].present = 1; 11477} 11478 11479static void 11480do_vfp_nsyn_push (void) 11481{ 11482 nsyn_insert_sp (); 11483 if (inst.operands[1].issingle) 11484 do_vfp_nsyn_opcode ("fstmdbs"); 11485 else 11486 do_vfp_nsyn_opcode ("fstmdbd"); 11487} 11488 11489static void 11490do_vfp_nsyn_pop (void) 11491{ 11492 nsyn_insert_sp (); 11493 if (inst.operands[1].issingle) 11494 do_vfp_nsyn_opcode ("fldmias"); 11495 else 11496 do_vfp_nsyn_opcode ("fldmiad"); 11497} 11498 11499/* Fix up Neon data-processing instructions, ORing in the correct bits for 11500 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ 11501 11502static unsigned 11503neon_dp_fixup (unsigned i) 11504{ 11505 if (thumb_mode) 11506 { 11507 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ 11508 if (i & (1 << 24)) 11509 i |= 1 << 28; 11510 11511 i &= ~(1 << 24); 11512 11513 i |= 0xef000000; 11514 } 11515 else 11516 i |= 0xf2000000; 11517 11518 return i; 11519} 11520 11521/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 11522 (0, 1, 2, 3). */ 11523 11524static unsigned 11525neon_logbits (unsigned x) 11526{ 11527 return ffs (x) - 4; 11528} 11529 11530#define LOW4(R) ((R) & 0xf) 11531#define HI1(R) (((R) >> 4) & 1) 11532 11533/* Encode insns with bit pattern: 11534 11535 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| 11536 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | 11537 11538 SIZE is passed in bits. -1 means size field isn't changed, in case it has a 11539 different meaning for some instruction. */ 11540 11541static void 11542neon_three_same (int isquad, int ubit, int size) 11543{ 11544 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 11545 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 11546 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 11547 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 11548 inst.instruction |= LOW4 (inst.operands[2].reg); 11549 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 11550 inst.instruction |= (isquad != 0) << 6; 11551 inst.instruction |= (ubit != 0) << 24; 11552 if (size != -1) 11553 inst.instruction |= neon_logbits (size) << 20; 11554 11555 inst.instruction = neon_dp_fixup (inst.instruction); 11556} 11557 11558/* Encode instructions of the form: 11559 11560 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| 11561 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | 11562 11563 Don't write size if SIZE == -1. */ 11564 11565static void 11566neon_two_same (int qbit, int ubit, int size) 11567{ 11568 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 11569 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 11570 inst.instruction |= LOW4 (inst.operands[1].reg); 11571 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 11572 inst.instruction |= (qbit != 0) << 6; 11573 inst.instruction |= (ubit != 0) << 24; 11574 11575 if (size != -1) 11576 inst.instruction |= neon_logbits (size) << 18; 11577 11578 inst.instruction = neon_dp_fixup (inst.instruction); 11579} 11580 11581/* Neon instruction encoders, in approximate order of appearance. */ 11582 11583static void 11584do_neon_dyadic_i_su (void) 11585{ 11586 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11587 struct neon_type_el et = neon_check_type (3, rs, 11588 N_EQK, N_EQK, N_SU_32 | N_KEY); 11589 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11590} 11591 11592static void 11593do_neon_dyadic_i64_su (void) 11594{ 11595 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11596 struct neon_type_el et = neon_check_type (3, rs, 11597 N_EQK, N_EQK, N_SU_ALL | N_KEY); 11598 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11599} 11600 11601static void 11602neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, 11603 unsigned immbits) 11604{ 11605 unsigned size = et.size >> 3; 11606 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 11607 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 11608 inst.instruction |= LOW4 (inst.operands[1].reg); 11609 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 11610 inst.instruction |= (isquad != 0) << 6; 11611 inst.instruction |= immbits << 16; 11612 inst.instruction |= (size >> 3) << 7; 11613 inst.instruction |= (size & 0x7) << 19; 11614 if (write_ubit) 11615 inst.instruction |= (uval != 0) << 24; 11616 11617 inst.instruction = neon_dp_fixup (inst.instruction); 11618} 11619 11620static void 11621do_neon_shl_imm (void) 11622{ 11623 if (!inst.operands[2].isreg) 11624 { 11625 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 11626 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); 11627 inst.instruction = NEON_ENC_IMMED (inst.instruction); 11628 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm); 11629 } 11630 else 11631 { 11632 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11633 struct neon_type_el et = neon_check_type (3, rs, 11634 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); 11635 unsigned int tmp; 11636 11637 /* VSHL/VQSHL 3-register variants have syntax such as: 11638 vshl.xx Dd, Dm, Dn 11639 whereas other 3-register operations encoded by neon_three_same have 11640 syntax like: 11641 vadd.xx Dd, Dn, Dm 11642 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg 11643 here. */ 11644 tmp = inst.operands[2].reg; 11645 inst.operands[2].reg = inst.operands[1].reg; 11646 inst.operands[1].reg = tmp; 11647 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 11648 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11649 } 11650} 11651 11652static void 11653do_neon_qshl_imm (void) 11654{ 11655 if (!inst.operands[2].isreg) 11656 { 11657 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 11658 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); 11659 11660 inst.instruction = NEON_ENC_IMMED (inst.instruction); 11661 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, 11662 inst.operands[2].imm); 11663 } 11664 else 11665 { 11666 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11667 struct neon_type_el et = neon_check_type (3, rs, 11668 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); 11669 unsigned int tmp; 11670 11671 /* See note in do_neon_shl_imm. */ 11672 tmp = inst.operands[2].reg; 11673 inst.operands[2].reg = inst.operands[1].reg; 11674 inst.operands[1].reg = tmp; 11675 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 11676 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11677 } 11678} 11679 11680static void 11681do_neon_rshl (void) 11682{ 11683 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11684 struct neon_type_el et = neon_check_type (3, rs, 11685 N_EQK, N_EQK, N_SU_ALL | N_KEY); 11686 unsigned int tmp; 11687 11688 tmp = inst.operands[2].reg; 11689 inst.operands[2].reg = inst.operands[1].reg; 11690 inst.operands[1].reg = tmp; 11691 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11692} 11693 11694static int 11695neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) 11696{ 11697 /* Handle .I8 pseudo-instructions. */ 11698 if (size == 8) 11699 { 11700 /* Unfortunately, this will make everything apart from zero out-of-range. 11701 FIXME is this the intended semantics? There doesn't seem much point in 11702 accepting .I8 if so. */ 11703 immediate |= immediate << 8; 11704 size = 16; 11705 } 11706 11707 if (size >= 32) 11708 { 11709 if (immediate == (immediate & 0x000000ff)) 11710 { 11711 *immbits = immediate; 11712 return 0x1; 11713 } 11714 else if (immediate == (immediate & 0x0000ff00)) 11715 { 11716 *immbits = immediate >> 8; 11717 return 0x3; 11718 } 11719 else if (immediate == (immediate & 0x00ff0000)) 11720 { 11721 *immbits = immediate >> 16; 11722 return 0x5; 11723 } 11724 else if (immediate == (immediate & 0xff000000)) 11725 { 11726 *immbits = immediate >> 24; 11727 return 0x7; 11728 } 11729 if ((immediate & 0xffff) != (immediate >> 16)) 11730 goto bad_immediate; 11731 immediate &= 0xffff; 11732 } 11733 11734 if (immediate == (immediate & 0x000000ff)) 11735 { 11736 *immbits = immediate; 11737 return 0x9; 11738 } 11739 else if (immediate == (immediate & 0x0000ff00)) 11740 { 11741 *immbits = immediate >> 8; 11742 return 0xb; 11743 } 11744 11745 bad_immediate: 11746 first_error (_("immediate value out of range")); 11747 return FAIL; 11748} 11749 11750/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits 11751 A, B, C, D. */ 11752 11753static int 11754neon_bits_same_in_bytes (unsigned imm) 11755{ 11756 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) 11757 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) 11758 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) 11759 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); 11760} 11761 11762/* For immediate of above form, return 0bABCD. */ 11763 11764static unsigned 11765neon_squash_bits (unsigned imm) 11766{ 11767 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) 11768 | ((imm & 0x01000000) >> 21); 11769} 11770 11771/* Compress quarter-float representation to 0b...000 abcdefgh. */ 11772 11773static unsigned 11774neon_qfloat_bits (unsigned imm) 11775{ 11776 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); 11777} 11778 11779/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into 11780 the instruction. *OP is passed as the initial value of the op field, and 11781 may be set to a different value depending on the constant (i.e. 11782 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not 11783 MVN). If the immediate looks like a repeated parttern then also 11784 try smaller element sizes. */ 11785 11786static int 11787neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, 11788 unsigned *immbits, int *op, int size, 11789 enum neon_el_type type) 11790{ 11791 /* Only permit float immediates (including 0.0/-0.0) if the operand type is 11792 float. */ 11793 if (type == NT_float && !float_p) 11794 return FAIL; 11795 11796 if (type == NT_float && is_quarter_float (immlo) && immhi == 0) 11797 { 11798 if (size != 32 || *op == 1) 11799 return FAIL; 11800 *immbits = neon_qfloat_bits (immlo); 11801 return 0xf; 11802 } 11803 11804 if (size == 64) 11805 { 11806 if (neon_bits_same_in_bytes (immhi) 11807 && neon_bits_same_in_bytes (immlo)) 11808 { 11809 if (*op == 1) 11810 return FAIL; 11811 *immbits = (neon_squash_bits (immhi) << 4) 11812 | neon_squash_bits (immlo); 11813 *op = 1; 11814 return 0xe; 11815 } 11816 11817 if (immhi != immlo) 11818 return FAIL; 11819 } 11820 11821 if (size >= 32) 11822 { 11823 if (immlo == (immlo & 0x000000ff)) 11824 { 11825 *immbits = immlo; 11826 return 0x0; 11827 } 11828 else if (immlo == (immlo & 0x0000ff00)) 11829 { 11830 *immbits = immlo >> 8; 11831 return 0x2; 11832 } 11833 else if (immlo == (immlo & 0x00ff0000)) 11834 { 11835 *immbits = immlo >> 16; 11836 return 0x4; 11837 } 11838 else if (immlo == (immlo & 0xff000000)) 11839 { 11840 *immbits = immlo >> 24; 11841 return 0x6; 11842 } 11843 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) 11844 { 11845 *immbits = (immlo >> 8) & 0xff; 11846 return 0xc; 11847 } 11848 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) 11849 { 11850 *immbits = (immlo >> 16) & 0xff; 11851 return 0xd; 11852 } 11853 11854 if ((immlo & 0xffff) != (immlo >> 16)) 11855 return FAIL; 11856 immlo &= 0xffff; 11857 } 11858 11859 if (size >= 16) 11860 { 11861 if (immlo == (immlo & 0x000000ff)) 11862 { 11863 *immbits = immlo; 11864 return 0x8; 11865 } 11866 else if (immlo == (immlo & 0x0000ff00)) 11867 { 11868 *immbits = immlo >> 8; 11869 return 0xa; 11870 } 11871 11872 if ((immlo & 0xff) != (immlo >> 8)) 11873 return FAIL; 11874 immlo &= 0xff; 11875 } 11876 11877 if (immlo == (immlo & 0x000000ff)) 11878 { 11879 /* Don't allow MVN with 8-bit immediate. */ 11880 if (*op == 1) 11881 return FAIL; 11882 *immbits = immlo; 11883 return 0xe; 11884 } 11885 11886 return FAIL; 11887} 11888 11889/* Write immediate bits [7:0] to the following locations: 11890 11891 |28/24|23 19|18 16|15 4|3 0| 11892 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| 11893 11894 This function is used by VMOV/VMVN/VORR/VBIC. */ 11895 11896static void 11897neon_write_immbits (unsigned immbits) 11898{ 11899 inst.instruction |= immbits & 0xf; 11900 inst.instruction |= ((immbits >> 4) & 0x7) << 16; 11901 inst.instruction |= ((immbits >> 7) & 0x1) << 24; 11902} 11903 11904/* Invert low-order SIZE bits of XHI:XLO. */ 11905 11906static void 11907neon_invert_size (unsigned *xlo, unsigned *xhi, int size) 11908{ 11909 unsigned immlo = xlo ? *xlo : 0; 11910 unsigned immhi = xhi ? *xhi : 0; 11911 11912 switch (size) 11913 { 11914 case 8: 11915 immlo = (~immlo) & 0xff; 11916 break; 11917 11918 case 16: 11919 immlo = (~immlo) & 0xffff; 11920 break; 11921 11922 case 64: 11923 immhi = (~immhi) & 0xffffffff; 11924 /* fall through. */ 11925 11926 case 32: 11927 immlo = (~immlo) & 0xffffffff; 11928 break; 11929 11930 default: 11931 abort (); 11932 } 11933 11934 if (xlo) 11935 *xlo = immlo; 11936 11937 if (xhi) 11938 *xhi = immhi; 11939} 11940 11941static void 11942do_neon_logic (void) 11943{ 11944 if (inst.operands[2].present && inst.operands[2].isreg) 11945 { 11946 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11947 neon_check_type (3, rs, N_IGNORE_TYPE); 11948 /* U bit and size field were set as part of the bitmask. */ 11949 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 11950 neon_three_same (neon_quad (rs), 0, -1); 11951 } 11952 else 11953 { 11954 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); 11955 struct neon_type_el et = neon_check_type (2, rs, 11956 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); 11957 enum neon_opc opcode = inst.instruction & 0x0fffffff; 11958 unsigned immbits; 11959 int cmode; 11960 11961 if (et.type == NT_invtype) 11962 return; 11963 11964 inst.instruction = NEON_ENC_IMMED (inst.instruction); 11965 11966 immbits = inst.operands[1].imm; 11967 if (et.size == 64) 11968 { 11969 /* .i64 is a pseudo-op, so the immediate must be a repeating 11970 pattern. */ 11971 if (immbits != (inst.operands[1].regisimm ? 11972 inst.operands[1].reg : 0)) 11973 { 11974 /* Set immbits to an invalid constant. */ 11975 immbits = 0xdeadbeef; 11976 } 11977 } 11978 11979 switch (opcode) 11980 { 11981 case N_MNEM_vbic: 11982 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 11983 break; 11984 11985 case N_MNEM_vorr: 11986 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 11987 break; 11988 11989 case N_MNEM_vand: 11990 /* Pseudo-instruction for VBIC. */ 11991 neon_invert_size (&immbits, 0, et.size); 11992 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 11993 break; 11994 11995 case N_MNEM_vorn: 11996 /* Pseudo-instruction for VORR. */ 11997 neon_invert_size (&immbits, 0, et.size); 11998 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 11999 break; 12000 12001 default: 12002 abort (); 12003 } 12004 12005 if (cmode == FAIL) 12006 return; 12007 12008 inst.instruction |= neon_quad (rs) << 6; 12009 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12010 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12011 inst.instruction |= cmode << 8; 12012 neon_write_immbits (immbits); 12013 12014 inst.instruction = neon_dp_fixup (inst.instruction); 12015 } 12016} 12017 12018static void 12019do_neon_bitfield (void) 12020{ 12021 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12022 neon_check_type (3, rs, N_IGNORE_TYPE); 12023 neon_three_same (neon_quad (rs), 0, -1); 12024} 12025 12026static void 12027neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, 12028 unsigned destbits) 12029{ 12030 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12031 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, 12032 types | N_KEY); 12033 if (et.type == NT_float) 12034 { 12035 inst.instruction = NEON_ENC_FLOAT (inst.instruction); 12036 neon_three_same (neon_quad (rs), 0, -1); 12037 } 12038 else 12039 { 12040 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12041 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); 12042 } 12043} 12044 12045static void 12046do_neon_dyadic_if_su (void) 12047{ 12048 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); 12049} 12050 12051static void 12052do_neon_dyadic_if_su_d (void) 12053{ 12054 /* This version only allow D registers, but that constraint is enforced during 12055 operand parsing so we don't need to do anything extra here. */ 12056 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); 12057} 12058 12059static void 12060do_neon_dyadic_if_i_d (void) 12061{ 12062 /* The "untyped" case can't happen. Do this to stop the "U" bit being 12063 affected if we specify unsigned args. */ 12064 neon_dyadic_misc (NT_untyped, N_IF_32, 0); 12065} 12066 12067enum vfp_or_neon_is_neon_bits 12068{ 12069 NEON_CHECK_CC = 1, 12070 NEON_CHECK_ARCH = 2 12071}; 12072 12073/* Call this function if an instruction which may have belonged to the VFP or 12074 Neon instruction sets, but turned out to be a Neon instruction (due to the 12075 operand types involved, etc.). We have to check and/or fix-up a couple of 12076 things: 12077 12078 - Make sure the user hasn't attempted to make a Neon instruction 12079 conditional. 12080 - Alter the value in the condition code field if necessary. 12081 - Make sure that the arch supports Neon instructions. 12082 12083 Which of these operations take place depends on bits from enum 12084 vfp_or_neon_is_neon_bits. 12085 12086 WARNING: This function has side effects! If NEON_CHECK_CC is used and the 12087 current instruction's condition is COND_ALWAYS, the condition field is 12088 changed to inst.uncond_value. This is necessary because instructions shared 12089 between VFP and Neon may be conditional for the VFP variants only, and the 12090 unconditional Neon version must have, e.g., 0xF in the condition field. */ 12091 12092static int 12093vfp_or_neon_is_neon (unsigned check) 12094{ 12095 /* Conditions are always legal in Thumb mode (IT blocks). */ 12096 if (!thumb_mode && (check & NEON_CHECK_CC)) 12097 { 12098 if (inst.cond != COND_ALWAYS) 12099 { 12100 first_error (_(BAD_COND)); 12101 return FAIL; 12102 } 12103 if (inst.uncond_value != -1) 12104 inst.instruction |= inst.uncond_value << 28; 12105 } 12106 12107 if ((check & NEON_CHECK_ARCH) 12108 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) 12109 { 12110 first_error (_(BAD_FPU)); 12111 return FAIL; 12112 } 12113 12114 return SUCCESS; 12115} 12116 12117static void 12118do_neon_addsub_if_i (void) 12119{ 12120 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) 12121 return; 12122 12123 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12124 return; 12125 12126 /* The "untyped" case can't happen. Do this to stop the "U" bit being 12127 affected if we specify unsigned args. */ 12128 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); 12129} 12130 12131/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the 12132 result to be: 12133 V<op> A,B (A is operand 0, B is operand 2) 12134 to mean: 12135 V<op> A,B,A 12136 not: 12137 V<op> A,B,B 12138 so handle that case specially. */ 12139 12140static void 12141neon_exchange_operands (void) 12142{ 12143 void *scratch = alloca (sizeof (inst.operands[0])); 12144 if (inst.operands[1].present) 12145 { 12146 /* Swap operands[1] and operands[2]. */ 12147 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); 12148 inst.operands[1] = inst.operands[2]; 12149 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); 12150 } 12151 else 12152 { 12153 inst.operands[1] = inst.operands[2]; 12154 inst.operands[2] = inst.operands[0]; 12155 } 12156} 12157 12158static void 12159neon_compare (unsigned regtypes, unsigned immtypes, int invert) 12160{ 12161 if (inst.operands[2].isreg) 12162 { 12163 if (invert) 12164 neon_exchange_operands (); 12165 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); 12166 } 12167 else 12168 { 12169 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12170 struct neon_type_el et = neon_check_type (2, rs, 12171 N_EQK | N_SIZ, immtypes | N_KEY); 12172 12173 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12174 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12175 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12176 inst.instruction |= LOW4 (inst.operands[1].reg); 12177 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12178 inst.instruction |= neon_quad (rs) << 6; 12179 inst.instruction |= (et.type == NT_float) << 10; 12180 inst.instruction |= neon_logbits (et.size) << 18; 12181 12182 inst.instruction = neon_dp_fixup (inst.instruction); 12183 } 12184} 12185 12186static void 12187do_neon_cmp (void) 12188{ 12189 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); 12190} 12191 12192static void 12193do_neon_cmp_inv (void) 12194{ 12195 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); 12196} 12197 12198static void 12199do_neon_ceq (void) 12200{ 12201 neon_compare (N_IF_32, N_IF_32, FALSE); 12202} 12203 12204/* For multiply instructions, we have the possibility of 16-bit or 32-bit 12205 scalars, which are encoded in 5 bits, M : Rm. 12206 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in 12207 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the 12208 index in M. */ 12209 12210static unsigned 12211neon_scalar_for_mul (unsigned scalar, unsigned elsize) 12212{ 12213 unsigned regno = NEON_SCALAR_REG (scalar); 12214 unsigned elno = NEON_SCALAR_INDEX (scalar); 12215 12216 switch (elsize) 12217 { 12218 case 16: 12219 if (regno > 7 || elno > 3) 12220 goto bad_scalar; 12221 return regno | (elno << 3); 12222 12223 case 32: 12224 if (regno > 15 || elno > 1) 12225 goto bad_scalar; 12226 return regno | (elno << 4); 12227 12228 default: 12229 bad_scalar: 12230 first_error (_("scalar out of range for multiply instruction")); 12231 } 12232 12233 return 0; 12234} 12235 12236/* Encode multiply / multiply-accumulate scalar instructions. */ 12237 12238static void 12239neon_mul_mac (struct neon_type_el et, int ubit) 12240{ 12241 unsigned scalar; 12242 12243 /* Give a more helpful error message if we have an invalid type. */ 12244 if (et.type == NT_invtype) 12245 return; 12246 12247 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); 12248 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12249 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12250 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 12251 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 12252 inst.instruction |= LOW4 (scalar); 12253 inst.instruction |= HI1 (scalar) << 5; 12254 inst.instruction |= (et.type == NT_float) << 8; 12255 inst.instruction |= neon_logbits (et.size) << 20; 12256 inst.instruction |= (ubit != 0) << 24; 12257 12258 inst.instruction = neon_dp_fixup (inst.instruction); 12259} 12260 12261static void 12262do_neon_mac_maybe_scalar (void) 12263{ 12264 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) 12265 return; 12266 12267 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12268 return; 12269 12270 if (inst.operands[2].isscalar) 12271 { 12272 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); 12273 struct neon_type_el et = neon_check_type (3, rs, 12274 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); 12275 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 12276 neon_mul_mac (et, neon_quad (rs)); 12277 } 12278 else 12279 { 12280 /* The "untyped" case can't happen. Do this to stop the "U" bit being 12281 affected if we specify unsigned args. */ 12282 neon_dyadic_misc (NT_untyped, N_IF_32, 0); 12283 } 12284} 12285 12286static void 12287do_neon_tst (void) 12288{ 12289 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12290 struct neon_type_el et = neon_check_type (3, rs, 12291 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); 12292 neon_three_same (neon_quad (rs), 0, et.size); 12293} 12294 12295/* VMUL with 3 registers allows the P8 type. The scalar version supports the 12296 same types as the MAC equivalents. The polynomial type for this instruction 12297 is encoded the same as the integer type. */ 12298 12299static void 12300do_neon_mul (void) 12301{ 12302 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) 12303 return; 12304 12305 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12306 return; 12307 12308 if (inst.operands[2].isscalar) 12309 do_neon_mac_maybe_scalar (); 12310 else 12311 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); 12312} 12313 12314static void 12315do_neon_qdmulh (void) 12316{ 12317 if (inst.operands[2].isscalar) 12318 { 12319 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); 12320 struct neon_type_el et = neon_check_type (3, rs, 12321 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); 12322 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 12323 neon_mul_mac (et, neon_quad (rs)); 12324 } 12325 else 12326 { 12327 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12328 struct neon_type_el et = neon_check_type (3, rs, 12329 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); 12330 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12331 /* The U bit (rounding) comes from bit mask. */ 12332 neon_three_same (neon_quad (rs), 0, et.size); 12333 } 12334} 12335 12336static void 12337do_neon_fcmp_absolute (void) 12338{ 12339 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12340 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); 12341 /* Size field comes from bit mask. */ 12342 neon_three_same (neon_quad (rs), 1, -1); 12343} 12344 12345static void 12346do_neon_fcmp_absolute_inv (void) 12347{ 12348 neon_exchange_operands (); 12349 do_neon_fcmp_absolute (); 12350} 12351 12352static void 12353do_neon_step (void) 12354{ 12355 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12356 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); 12357 neon_three_same (neon_quad (rs), 0, -1); 12358} 12359 12360static void 12361do_neon_abs_neg (void) 12362{ 12363 enum neon_shape rs; 12364 struct neon_type_el et; 12365 12366 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) 12367 return; 12368 12369 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12370 return; 12371 12372 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 12373 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); 12374 12375 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12376 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12377 inst.instruction |= LOW4 (inst.operands[1].reg); 12378 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12379 inst.instruction |= neon_quad (rs) << 6; 12380 inst.instruction |= (et.type == NT_float) << 10; 12381 inst.instruction |= neon_logbits (et.size) << 18; 12382 12383 inst.instruction = neon_dp_fixup (inst.instruction); 12384} 12385 12386static void 12387do_neon_sli (void) 12388{ 12389 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12390 struct neon_type_el et = neon_check_type (2, rs, 12391 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 12392 int imm = inst.operands[2].imm; 12393 constraint (imm < 0 || (unsigned)imm >= et.size, 12394 _("immediate out of range for insert")); 12395 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); 12396} 12397 12398static void 12399do_neon_sri (void) 12400{ 12401 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12402 struct neon_type_el et = neon_check_type (2, rs, 12403 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 12404 int imm = inst.operands[2].imm; 12405 constraint (imm < 1 || (unsigned)imm > et.size, 12406 _("immediate out of range for insert")); 12407 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); 12408} 12409 12410static void 12411do_neon_qshlu_imm (void) 12412{ 12413 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12414 struct neon_type_el et = neon_check_type (2, rs, 12415 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); 12416 int imm = inst.operands[2].imm; 12417 constraint (imm < 0 || (unsigned)imm >= et.size, 12418 _("immediate out of range for shift")); 12419 /* Only encodes the 'U present' variant of the instruction. 12420 In this case, signed types have OP (bit 8) set to 0. 12421 Unsigned types have OP set to 1. */ 12422 inst.instruction |= (et.type == NT_unsigned) << 8; 12423 /* The rest of the bits are the same as other immediate shifts. */ 12424 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); 12425} 12426 12427static void 12428do_neon_qmovn (void) 12429{ 12430 struct neon_type_el et = neon_check_type (2, NS_DQ, 12431 N_EQK | N_HLF, N_SU_16_64 | N_KEY); 12432 /* Saturating move where operands can be signed or unsigned, and the 12433 destination has the same signedness. */ 12434 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12435 if (et.type == NT_unsigned) 12436 inst.instruction |= 0xc0; 12437 else 12438 inst.instruction |= 0x80; 12439 neon_two_same (0, 1, et.size / 2); 12440} 12441 12442static void 12443do_neon_qmovun (void) 12444{ 12445 struct neon_type_el et = neon_check_type (2, NS_DQ, 12446 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); 12447 /* Saturating move with unsigned results. Operands must be signed. */ 12448 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12449 neon_two_same (0, 1, et.size / 2); 12450} 12451 12452static void 12453do_neon_rshift_sat_narrow (void) 12454{ 12455 /* FIXME: Types for narrowing. If operands are signed, results can be signed 12456 or unsigned. If operands are unsigned, results must also be unsigned. */ 12457 struct neon_type_el et = neon_check_type (2, NS_DQI, 12458 N_EQK | N_HLF, N_SU_16_64 | N_KEY); 12459 int imm = inst.operands[2].imm; 12460 /* This gets the bounds check, size encoding and immediate bits calculation 12461 right. */ 12462 et.size /= 2; 12463 12464 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for 12465 VQMOVN.I<size> <Dd>, <Qm>. */ 12466 if (imm == 0) 12467 { 12468 inst.operands[2].present = 0; 12469 inst.instruction = N_MNEM_vqmovn; 12470 do_neon_qmovn (); 12471 return; 12472 } 12473 12474 constraint (imm < 1 || (unsigned)imm > et.size, 12475 _("immediate out of range")); 12476 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); 12477} 12478 12479static void 12480do_neon_rshift_sat_narrow_u (void) 12481{ 12482 /* FIXME: Types for narrowing. If operands are signed, results can be signed 12483 or unsigned. If operands are unsigned, results must also be unsigned. */ 12484 struct neon_type_el et = neon_check_type (2, NS_DQI, 12485 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); 12486 int imm = inst.operands[2].imm; 12487 /* This gets the bounds check, size encoding and immediate bits calculation 12488 right. */ 12489 et.size /= 2; 12490 12491 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for 12492 VQMOVUN.I<size> <Dd>, <Qm>. */ 12493 if (imm == 0) 12494 { 12495 inst.operands[2].present = 0; 12496 inst.instruction = N_MNEM_vqmovun; 12497 do_neon_qmovun (); 12498 return; 12499 } 12500 12501 constraint (imm < 1 || (unsigned)imm > et.size, 12502 _("immediate out of range")); 12503 /* FIXME: The manual is kind of unclear about what value U should have in 12504 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it 12505 must be 1. */ 12506 neon_imm_shift (TRUE, 1, 0, et, et.size - imm); 12507} 12508 12509static void 12510do_neon_movn (void) 12511{ 12512 struct neon_type_el et = neon_check_type (2, NS_DQ, 12513 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); 12514 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12515 neon_two_same (0, 1, et.size / 2); 12516} 12517 12518static void 12519do_neon_rshift_narrow (void) 12520{ 12521 struct neon_type_el et = neon_check_type (2, NS_DQI, 12522 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); 12523 int imm = inst.operands[2].imm; 12524 /* This gets the bounds check, size encoding and immediate bits calculation 12525 right. */ 12526 et.size /= 2; 12527 12528 /* If immediate is zero then we are a pseudo-instruction for 12529 VMOVN.I<size> <Dd>, <Qm> */ 12530 if (imm == 0) 12531 { 12532 inst.operands[2].present = 0; 12533 inst.instruction = N_MNEM_vmovn; 12534 do_neon_movn (); 12535 return; 12536 } 12537 12538 constraint (imm < 1 || (unsigned)imm > et.size, 12539 _("immediate out of range for narrowing operation")); 12540 neon_imm_shift (FALSE, 0, 0, et, et.size - imm); 12541} 12542 12543static void 12544do_neon_shll (void) 12545{ 12546 /* FIXME: Type checking when lengthening. */ 12547 struct neon_type_el et = neon_check_type (2, NS_QDI, 12548 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); 12549 unsigned imm = inst.operands[2].imm; 12550 12551 if (imm == et.size) 12552 { 12553 /* Maximum shift variant. */ 12554 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12555 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12556 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12557 inst.instruction |= LOW4 (inst.operands[1].reg); 12558 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12559 inst.instruction |= neon_logbits (et.size) << 18; 12560 12561 inst.instruction = neon_dp_fixup (inst.instruction); 12562 } 12563 else 12564 { 12565 /* A more-specific type check for non-max versions. */ 12566 et = neon_check_type (2, NS_QDI, 12567 N_EQK | N_DBL, N_SU_32 | N_KEY); 12568 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12569 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); 12570 } 12571} 12572 12573/* Check the various types for the VCVT instruction, and return which version 12574 the current instruction is. */ 12575 12576static int 12577neon_cvt_flavour (enum neon_shape rs) 12578{ 12579#define CVT_VAR(C,X,Y) \ 12580 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \ 12581 if (et.type != NT_invtype) \ 12582 { \ 12583 inst.error = NULL; \ 12584 return (C); \ 12585 } 12586 struct neon_type_el et; 12587 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF 12588 || rs == NS_FF) ? N_VFP : 0; 12589 /* The instruction versions which take an immediate take one register 12590 argument, which is extended to the width of the full register. Thus the 12591 "source" and "destination" registers must have the same width. Hack that 12592 here by making the size equal to the key (wider, in this case) operand. */ 12593 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; 12594 12595 CVT_VAR (0, N_S32, N_F32); 12596 CVT_VAR (1, N_U32, N_F32); 12597 CVT_VAR (2, N_F32, N_S32); 12598 CVT_VAR (3, N_F32, N_U32); 12599 12600 whole_reg = N_VFP; 12601 12602 /* VFP instructions. */ 12603 CVT_VAR (4, N_F32, N_F64); 12604 CVT_VAR (5, N_F64, N_F32); 12605 CVT_VAR (6, N_S32, N_F64 | key); 12606 CVT_VAR (7, N_U32, N_F64 | key); 12607 CVT_VAR (8, N_F64 | key, N_S32); 12608 CVT_VAR (9, N_F64 | key, N_U32); 12609 /* VFP instructions with bitshift. */ 12610 CVT_VAR (10, N_F32 | key, N_S16); 12611 CVT_VAR (11, N_F32 | key, N_U16); 12612 CVT_VAR (12, N_F64 | key, N_S16); 12613 CVT_VAR (13, N_F64 | key, N_U16); 12614 CVT_VAR (14, N_S16, N_F32 | key); 12615 CVT_VAR (15, N_U16, N_F32 | key); 12616 CVT_VAR (16, N_S16, N_F64 | key); 12617 CVT_VAR (17, N_U16, N_F64 | key); 12618 12619 return -1; 12620#undef CVT_VAR 12621} 12622 12623/* Neon-syntax VFP conversions. */ 12624 12625static void 12626do_vfp_nsyn_cvt (enum neon_shape rs, int flavour) 12627{ 12628 const char *opname = 0; 12629 12630 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) 12631 { 12632 /* Conversions with immediate bitshift. */ 12633 const char *enc[] = 12634 { 12635 "ftosls", 12636 "ftouls", 12637 "fsltos", 12638 "fultos", 12639 NULL, 12640 NULL, 12641 "ftosld", 12642 "ftould", 12643 "fsltod", 12644 "fultod", 12645 "fshtos", 12646 "fuhtos", 12647 "fshtod", 12648 "fuhtod", 12649 "ftoshs", 12650 "ftouhs", 12651 "ftoshd", 12652 "ftouhd" 12653 }; 12654 12655 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) 12656 { 12657 opname = enc[flavour]; 12658 constraint (inst.operands[0].reg != inst.operands[1].reg, 12659 _("operands 0 and 1 must be the same register")); 12660 inst.operands[1] = inst.operands[2]; 12661 memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); 12662 } 12663 } 12664 else 12665 { 12666 /* Conversions without bitshift. */ 12667 const char *enc[] = 12668 { 12669 "ftosizs", 12670 "ftouizs", 12671 "fsitos", 12672 "fuitos", 12673 "fcvtsd", 12674 "fcvtds", 12675 "ftosizd", 12676 "ftouizd", 12677 "fsitod", 12678 "fuitod" 12679 }; 12680 12681 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) 12682 opname = enc[flavour]; 12683 } 12684 12685 if (opname) 12686 do_vfp_nsyn_opcode (opname); 12687} 12688 12689static void 12690do_vfp_nsyn_cvtz (void) 12691{ 12692 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); 12693 int flavour = neon_cvt_flavour (rs); 12694 const char *enc[] = 12695 { 12696 "ftosizs", 12697 "ftouizs", 12698 NULL, 12699 NULL, 12700 NULL, 12701 NULL, 12702 "ftosizd", 12703 "ftouizd" 12704 }; 12705 12706 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) 12707 do_vfp_nsyn_opcode (enc[flavour]); 12708} 12709 12710static void 12711do_neon_cvt (void) 12712{ 12713 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, 12714 NS_FD, NS_DF, NS_FF, NS_NULL); 12715 int flavour = neon_cvt_flavour (rs); 12716 12717 /* VFP rather than Neon conversions. */ 12718 if (flavour >= 4) 12719 { 12720 do_vfp_nsyn_cvt (rs, flavour); 12721 return; 12722 } 12723 12724 switch (rs) 12725 { 12726 case NS_DDI: 12727 case NS_QQI: 12728 { 12729 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12730 return; 12731 12732 /* Fixed-point conversion with #0 immediate is encoded as an 12733 integer conversion. */ 12734 if (inst.operands[2].present && inst.operands[2].imm == 0) 12735 goto int_encode; 12736 unsigned immbits = 32 - inst.operands[2].imm; 12737 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; 12738 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12739 if (flavour != -1) 12740 inst.instruction |= enctab[flavour]; 12741 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12742 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12743 inst.instruction |= LOW4 (inst.operands[1].reg); 12744 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12745 inst.instruction |= neon_quad (rs) << 6; 12746 inst.instruction |= 1 << 21; 12747 inst.instruction |= immbits << 16; 12748 12749 inst.instruction = neon_dp_fixup (inst.instruction); 12750 } 12751 break; 12752 12753 case NS_DD: 12754 case NS_QQ: 12755 int_encode: 12756 { 12757 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; 12758 12759 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12760 12761 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12762 return; 12763 12764 if (flavour != -1) 12765 inst.instruction |= enctab[flavour]; 12766 12767 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12768 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12769 inst.instruction |= LOW4 (inst.operands[1].reg); 12770 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12771 inst.instruction |= neon_quad (rs) << 6; 12772 inst.instruction |= 2 << 18; 12773 12774 inst.instruction = neon_dp_fixup (inst.instruction); 12775 } 12776 break; 12777 12778 default: 12779 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ 12780 do_vfp_nsyn_cvt (rs, flavour); 12781 } 12782} 12783 12784static void 12785neon_move_immediate (void) 12786{ 12787 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); 12788 struct neon_type_el et = neon_check_type (2, rs, 12789 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); 12790 unsigned immlo, immhi = 0, immbits; 12791 int op, cmode, float_p; 12792 12793 constraint (et.type == NT_invtype, 12794 _("operand size must be specified for immediate VMOV")); 12795 12796 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ 12797 op = (inst.instruction & (1 << 5)) != 0; 12798 12799 immlo = inst.operands[1].imm; 12800 if (inst.operands[1].regisimm) 12801 immhi = inst.operands[1].reg; 12802 12803 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, 12804 _("immediate has bits set outside the operand size")); 12805 12806 float_p = inst.operands[1].immisfloat; 12807 12808 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, 12809 et.size, et.type)) == FAIL) 12810 { 12811 /* Invert relevant bits only. */ 12812 neon_invert_size (&immlo, &immhi, et.size); 12813 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable 12814 with one or the other; those cases are caught by 12815 neon_cmode_for_move_imm. */ 12816 op = !op; 12817 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, 12818 &op, et.size, et.type)) == FAIL) 12819 { 12820 first_error (_("immediate out of range")); 12821 return; 12822 } 12823 } 12824 12825 inst.instruction &= ~(1 << 5); 12826 inst.instruction |= op << 5; 12827 12828 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12829 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12830 inst.instruction |= neon_quad (rs) << 6; 12831 inst.instruction |= cmode << 8; 12832 12833 neon_write_immbits (immbits); 12834} 12835 12836static void 12837do_neon_mvn (void) 12838{ 12839 if (inst.operands[1].isreg) 12840 { 12841 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 12842 12843 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12844 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12845 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12846 inst.instruction |= LOW4 (inst.operands[1].reg); 12847 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12848 inst.instruction |= neon_quad (rs) << 6; 12849 } 12850 else 12851 { 12852 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12853 neon_move_immediate (); 12854 } 12855 12856 inst.instruction = neon_dp_fixup (inst.instruction); 12857} 12858 12859/* Encode instructions of form: 12860 12861 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| 12862 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | 12863 12864*/ 12865 12866static void 12867neon_mixed_length (struct neon_type_el et, unsigned size) 12868{ 12869 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12870 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12871 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 12872 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 12873 inst.instruction |= LOW4 (inst.operands[2].reg); 12874 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 12875 inst.instruction |= (et.type == NT_unsigned) << 24; 12876 inst.instruction |= neon_logbits (size) << 20; 12877 12878 inst.instruction = neon_dp_fixup (inst.instruction); 12879} 12880 12881static void 12882do_neon_dyadic_long (void) 12883{ 12884 /* FIXME: Type checking for lengthening op. */ 12885 struct neon_type_el et = neon_check_type (3, NS_QDD, 12886 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); 12887 neon_mixed_length (et, et.size); 12888} 12889 12890static void 12891do_neon_abal (void) 12892{ 12893 struct neon_type_el et = neon_check_type (3, NS_QDD, 12894 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); 12895 neon_mixed_length (et, et.size); 12896} 12897 12898static void 12899neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) 12900{ 12901 if (inst.operands[2].isscalar) 12902 { 12903 struct neon_type_el et = neon_check_type (3, NS_QDS, 12904 N_EQK | N_DBL, N_EQK, regtypes | N_KEY); 12905 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 12906 neon_mul_mac (et, et.type == NT_unsigned); 12907 } 12908 else 12909 { 12910 struct neon_type_el et = neon_check_type (3, NS_QDD, 12911 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); 12912 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12913 neon_mixed_length (et, et.size); 12914 } 12915} 12916 12917static void 12918do_neon_mac_maybe_scalar_long (void) 12919{ 12920 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); 12921} 12922 12923static void 12924do_neon_dyadic_wide (void) 12925{ 12926 struct neon_type_el et = neon_check_type (3, NS_QQD, 12927 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); 12928 neon_mixed_length (et, et.size); 12929} 12930 12931static void 12932do_neon_dyadic_narrow (void) 12933{ 12934 struct neon_type_el et = neon_check_type (3, NS_QDD, 12935 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); 12936 /* Operand sign is unimportant, and the U bit is part of the opcode, 12937 so force the operand type to integer. */ 12938 et.type = NT_integer; 12939 neon_mixed_length (et, et.size / 2); 12940} 12941 12942static void 12943do_neon_mul_sat_scalar_long (void) 12944{ 12945 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); 12946} 12947 12948static void 12949do_neon_vmull (void) 12950{ 12951 if (inst.operands[2].isscalar) 12952 do_neon_mac_maybe_scalar_long (); 12953 else 12954 { 12955 struct neon_type_el et = neon_check_type (3, NS_QDD, 12956 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY); 12957 if (et.type == NT_poly) 12958 inst.instruction = NEON_ENC_POLY (inst.instruction); 12959 else 12960 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12961 /* For polynomial encoding, size field must be 0b00 and the U bit must be 12962 zero. Should be OK as-is. */ 12963 neon_mixed_length (et, et.size); 12964 } 12965} 12966 12967static void 12968do_neon_ext (void) 12969{ 12970 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); 12971 struct neon_type_el et = neon_check_type (3, rs, 12972 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 12973 unsigned imm = (inst.operands[3].imm * et.size) / 8; 12974 constraint (imm >= (neon_quad (rs) ? 16 : 8), _("shift out of range")); 12975 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12976 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12977 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 12978 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 12979 inst.instruction |= LOW4 (inst.operands[2].reg); 12980 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 12981 inst.instruction |= neon_quad (rs) << 6; 12982 inst.instruction |= imm << 8; 12983 12984 inst.instruction = neon_dp_fixup (inst.instruction); 12985} 12986 12987static void 12988do_neon_rev (void) 12989{ 12990 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 12991 struct neon_type_el et = neon_check_type (2, rs, 12992 N_EQK, N_8 | N_16 | N_32 | N_KEY); 12993 unsigned op = (inst.instruction >> 7) & 3; 12994 /* N (width of reversed regions) is encoded as part of the bitmask. We 12995 extract it here to check the elements to be reversed are smaller. 12996 Otherwise we'd get a reserved instruction. */ 12997 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; 12998 assert (elsize != 0); 12999 constraint (et.size >= elsize, 13000 _("elements must be smaller than reversal region")); 13001 neon_two_same (neon_quad (rs), 1, et.size); 13002} 13003 13004static void 13005do_neon_dup (void) 13006{ 13007 if (inst.operands[1].isscalar) 13008 { 13009 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); 13010 struct neon_type_el et = neon_check_type (2, rs, 13011 N_EQK, N_8 | N_16 | N_32 | N_KEY); 13012 unsigned sizebits = et.size >> 3; 13013 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); 13014 int logsize = neon_logbits (et.size); 13015 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; 13016 13017 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) 13018 return; 13019 13020 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 13021 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13022 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13023 inst.instruction |= LOW4 (dm); 13024 inst.instruction |= HI1 (dm) << 5; 13025 inst.instruction |= neon_quad (rs) << 6; 13026 inst.instruction |= x << 17; 13027 inst.instruction |= sizebits << 16; 13028 13029 inst.instruction = neon_dp_fixup (inst.instruction); 13030 } 13031 else 13032 { 13033 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); 13034 struct neon_type_el et = neon_check_type (2, rs, 13035 N_8 | N_16 | N_32 | N_KEY, N_EQK); 13036 /* Duplicate ARM register to lanes of vector. */ 13037 inst.instruction = NEON_ENC_ARMREG (inst.instruction); 13038 switch (et.size) 13039 { 13040 case 8: inst.instruction |= 0x400000; break; 13041 case 16: inst.instruction |= 0x000020; break; 13042 case 32: inst.instruction |= 0x000000; break; 13043 default: break; 13044 } 13045 inst.instruction |= LOW4 (inst.operands[1].reg) << 12; 13046 inst.instruction |= LOW4 (inst.operands[0].reg) << 16; 13047 inst.instruction |= HI1 (inst.operands[0].reg) << 7; 13048 inst.instruction |= neon_quad (rs) << 21; 13049 /* The encoding for this instruction is identical for the ARM and Thumb 13050 variants, except for the condition field. */ 13051 do_vfp_cond_or_thumb (); 13052 } 13053} 13054 13055/* VMOV has particularly many variations. It can be one of: 13056 0. VMOV<c><q> <Qd>, <Qm> 13057 1. VMOV<c><q> <Dd>, <Dm> 13058 (Register operations, which are VORR with Rm = Rn.) 13059 2. VMOV<c><q>.<dt> <Qd>, #<imm> 13060 3. VMOV<c><q>.<dt> <Dd>, #<imm> 13061 (Immediate loads.) 13062 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> 13063 (ARM register to scalar.) 13064 5. VMOV<c><q> <Dm>, <Rd>, <Rn> 13065 (Two ARM registers to vector.) 13066 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> 13067 (Scalar to ARM register.) 13068 7. VMOV<c><q> <Rd>, <Rn>, <Dm> 13069 (Vector to two ARM registers.) 13070 8. VMOV.F32 <Sd>, <Sm> 13071 9. VMOV.F64 <Dd>, <Dm> 13072 (VFP register moves.) 13073 10. VMOV.F32 <Sd>, #imm 13074 11. VMOV.F64 <Dd>, #imm 13075 (VFP float immediate load.) 13076 12. VMOV <Rd>, <Sm> 13077 (VFP single to ARM reg.) 13078 13. VMOV <Sd>, <Rm> 13079 (ARM reg to VFP single.) 13080 14. VMOV <Rd>, <Re>, <Sn>, <Sm> 13081 (Two ARM regs to two VFP singles.) 13082 15. VMOV <Sd>, <Se>, <Rn>, <Rm> 13083 (Two VFP singles to two ARM regs.) 13084 13085 These cases can be disambiguated using neon_select_shape, except cases 1/9 13086 and 3/11 which depend on the operand type too. 13087 13088 All the encoded bits are hardcoded by this function. 13089 13090 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). 13091 Cases 5, 7 may be used with VFPv2 and above. 13092 13093 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you 13094 can specify a type where it doesn't make sense to, and is ignored). 13095*/ 13096 13097static void 13098do_neon_mov (void) 13099{ 13100 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, 13101 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, 13102 NS_NULL); 13103 struct neon_type_el et; 13104 const char *ldconst = 0; 13105 13106 switch (rs) 13107 { 13108 case NS_DD: /* case 1/9. */ 13109 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); 13110 /* It is not an error here if no type is given. */ 13111 inst.error = NULL; 13112 if (et.type == NT_float && et.size == 64) 13113 { 13114 do_vfp_nsyn_opcode ("fcpyd"); 13115 break; 13116 } 13117 /* fall through. */ 13118 13119 case NS_QQ: /* case 0/1. */ 13120 { 13121 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 13122 return; 13123 /* The architecture manual I have doesn't explicitly state which 13124 value the U bit should have for register->register moves, but 13125 the equivalent VORR instruction has U = 0, so do that. */ 13126 inst.instruction = 0x0200110; 13127 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13128 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13129 inst.instruction |= LOW4 (inst.operands[1].reg); 13130 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 13131 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 13132 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 13133 inst.instruction |= neon_quad (rs) << 6; 13134 13135 inst.instruction = neon_dp_fixup (inst.instruction); 13136 } 13137 break; 13138 13139 case NS_DI: /* case 3/11. */ 13140 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); 13141 inst.error = NULL; 13142 if (et.type == NT_float && et.size == 64) 13143 { 13144 /* case 11 (fconstd). */ 13145 ldconst = "fconstd"; 13146 goto encode_fconstd; 13147 } 13148 /* fall through. */ 13149 13150 case NS_QI: /* case 2/3. */ 13151 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 13152 return; 13153 inst.instruction = 0x0800010; 13154 neon_move_immediate (); 13155 inst.instruction = neon_dp_fixup (inst.instruction); 13156 break; 13157 13158 case NS_SR: /* case 4. */ 13159 { 13160 unsigned bcdebits = 0; 13161 struct neon_type_el et = neon_check_type (2, NS_NULL, 13162 N_8 | N_16 | N_32 | N_KEY, N_EQK); 13163 int logsize = neon_logbits (et.size); 13164 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); 13165 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); 13166 13167 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), 13168 _(BAD_FPU)); 13169 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) 13170 && et.size != 32, _(BAD_FPU)); 13171 constraint (et.type == NT_invtype, _("bad type for scalar")); 13172 constraint (x >= 64 / et.size, _("scalar index out of range")); 13173 13174 switch (et.size) 13175 { 13176 case 8: bcdebits = 0x8; break; 13177 case 16: bcdebits = 0x1; break; 13178 case 32: bcdebits = 0x0; break; 13179 default: ; 13180 } 13181 13182 bcdebits |= x << logsize; 13183 13184 inst.instruction = 0xe000b10; 13185 do_vfp_cond_or_thumb (); 13186 inst.instruction |= LOW4 (dn) << 16; 13187 inst.instruction |= HI1 (dn) << 7; 13188 inst.instruction |= inst.operands[1].reg << 12; 13189 inst.instruction |= (bcdebits & 3) << 5; 13190 inst.instruction |= (bcdebits >> 2) << 21; 13191 } 13192 break; 13193 13194 case NS_DRR: /* case 5 (fmdrr). */ 13195 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), 13196 _(BAD_FPU)); 13197 13198 inst.instruction = 0xc400b10; 13199 do_vfp_cond_or_thumb (); 13200 inst.instruction |= LOW4 (inst.operands[0].reg); 13201 inst.instruction |= HI1 (inst.operands[0].reg) << 5; 13202 inst.instruction |= inst.operands[1].reg << 12; 13203 inst.instruction |= inst.operands[2].reg << 16; 13204 break; 13205 13206 case NS_RS: /* case 6. */ 13207 { 13208 struct neon_type_el et = neon_check_type (2, NS_NULL, 13209 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); 13210 unsigned logsize = neon_logbits (et.size); 13211 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); 13212 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); 13213 unsigned abcdebits = 0; 13214 13215 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), 13216 _(BAD_FPU)); 13217 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) 13218 && et.size != 32, _(BAD_FPU)); 13219 constraint (et.type == NT_invtype, _("bad type for scalar")); 13220 constraint (x >= 64 / et.size, _("scalar index out of range")); 13221 13222 switch (et.size) 13223 { 13224 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; 13225 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; 13226 case 32: abcdebits = 0x00; break; 13227 default: ; 13228 } 13229 13230 abcdebits |= x << logsize; 13231 inst.instruction = 0xe100b10; 13232 do_vfp_cond_or_thumb (); 13233 inst.instruction |= LOW4 (dn) << 16; 13234 inst.instruction |= HI1 (dn) << 7; 13235 inst.instruction |= inst.operands[0].reg << 12; 13236 inst.instruction |= (abcdebits & 3) << 5; 13237 inst.instruction |= (abcdebits >> 2) << 21; 13238 } 13239 break; 13240 13241 case NS_RRD: /* case 7 (fmrrd). */ 13242 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), 13243 _(BAD_FPU)); 13244 13245 inst.instruction = 0xc500b10; 13246 do_vfp_cond_or_thumb (); 13247 inst.instruction |= inst.operands[0].reg << 12; 13248 inst.instruction |= inst.operands[1].reg << 16; 13249 inst.instruction |= LOW4 (inst.operands[2].reg); 13250 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 13251 break; 13252 13253 case NS_FF: /* case 8 (fcpys). */ 13254 do_vfp_nsyn_opcode ("fcpys"); 13255 break; 13256 13257 case NS_FI: /* case 10 (fconsts). */ 13258 ldconst = "fconsts"; 13259 encode_fconstd: 13260 if (is_quarter_float (inst.operands[1].imm)) 13261 { 13262 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); 13263 do_vfp_nsyn_opcode (ldconst); 13264 } 13265 else 13266 first_error (_("immediate out of range")); 13267 break; 13268 13269 case NS_RF: /* case 12 (fmrs). */ 13270 do_vfp_nsyn_opcode ("fmrs"); 13271 break; 13272 13273 case NS_FR: /* case 13 (fmsr). */ 13274 do_vfp_nsyn_opcode ("fmsr"); 13275 break; 13276 13277 /* The encoders for the fmrrs and fmsrr instructions expect three operands 13278 (one of which is a list), but we have parsed four. Do some fiddling to 13279 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 13280 expect. */ 13281 case NS_RRFF: /* case 14 (fmrrs). */ 13282 constraint (inst.operands[3].reg != inst.operands[2].reg + 1, 13283 _("VFP registers must be adjacent")); 13284 inst.operands[2].imm = 2; 13285 memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); 13286 do_vfp_nsyn_opcode ("fmrrs"); 13287 break; 13288 13289 case NS_FFRR: /* case 15 (fmsrr). */ 13290 constraint (inst.operands[1].reg != inst.operands[0].reg + 1, 13291 _("VFP registers must be adjacent")); 13292 inst.operands[1] = inst.operands[2]; 13293 inst.operands[2] = inst.operands[3]; 13294 inst.operands[0].imm = 2; 13295 memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); 13296 do_vfp_nsyn_opcode ("fmsrr"); 13297 break; 13298 13299 default: 13300 abort (); 13301 } 13302} 13303 13304static void 13305do_neon_rshift_round_imm (void) 13306{ 13307 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 13308 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); 13309 int imm = inst.operands[2].imm; 13310 13311 /* imm == 0 case is encoded as VMOV for V{R}SHR. */ 13312 if (imm == 0) 13313 { 13314 inst.operands[2].present = 0; 13315 do_neon_mov (); 13316 return; 13317 } 13318 13319 constraint (imm < 1 || (unsigned)imm > et.size, 13320 _("immediate out of range for shift")); 13321 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, 13322 et.size - imm); 13323} 13324 13325static void 13326do_neon_movl (void) 13327{ 13328 struct neon_type_el et = neon_check_type (2, NS_QD, 13329 N_EQK | N_DBL, N_SU_32 | N_KEY); 13330 unsigned sizebits = et.size >> 3; 13331 inst.instruction |= sizebits << 19; 13332 neon_two_same (0, et.type == NT_unsigned, -1); 13333} 13334 13335static void 13336do_neon_trn (void) 13337{ 13338 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13339 struct neon_type_el et = neon_check_type (2, rs, 13340 N_EQK, N_8 | N_16 | N_32 | N_KEY); 13341 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 13342 neon_two_same (neon_quad (rs), 1, et.size); 13343} 13344 13345static void 13346do_neon_zip_uzp (void) 13347{ 13348 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13349 struct neon_type_el et = neon_check_type (2, rs, 13350 N_EQK, N_8 | N_16 | N_32 | N_KEY); 13351 if (rs == NS_DD && et.size == 32) 13352 { 13353 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ 13354 inst.instruction = N_MNEM_vtrn; 13355 do_neon_trn (); 13356 return; 13357 } 13358 neon_two_same (neon_quad (rs), 1, et.size); 13359} 13360 13361static void 13362do_neon_sat_abs_neg (void) 13363{ 13364 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13365 struct neon_type_el et = neon_check_type (2, rs, 13366 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); 13367 neon_two_same (neon_quad (rs), 1, et.size); 13368} 13369 13370static void 13371do_neon_pair_long (void) 13372{ 13373 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13374 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); 13375 /* Unsigned is encoded in OP field (bit 7) for these instruction. */ 13376 inst.instruction |= (et.type == NT_unsigned) << 7; 13377 neon_two_same (neon_quad (rs), 1, et.size); 13378} 13379 13380static void 13381do_neon_recip_est (void) 13382{ 13383 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13384 struct neon_type_el et = neon_check_type (2, rs, 13385 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); 13386 inst.instruction |= (et.type == NT_float) << 8; 13387 neon_two_same (neon_quad (rs), 1, et.size); 13388} 13389 13390static void 13391do_neon_cls (void) 13392{ 13393 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13394 struct neon_type_el et = neon_check_type (2, rs, 13395 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); 13396 neon_two_same (neon_quad (rs), 1, et.size); 13397} 13398 13399static void 13400do_neon_clz (void) 13401{ 13402 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13403 struct neon_type_el et = neon_check_type (2, rs, 13404 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); 13405 neon_two_same (neon_quad (rs), 1, et.size); 13406} 13407 13408static void 13409do_neon_cnt (void) 13410{ 13411 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13412 struct neon_type_el et = neon_check_type (2, rs, 13413 N_EQK | N_INT, N_8 | N_KEY); 13414 neon_two_same (neon_quad (rs), 1, et.size); 13415} 13416 13417static void 13418do_neon_swp (void) 13419{ 13420 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13421 neon_two_same (neon_quad (rs), 1, -1); 13422} 13423 13424static void 13425do_neon_tbl_tbx (void) 13426{ 13427 unsigned listlenbits; 13428 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); 13429 13430 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) 13431 { 13432 first_error (_("bad list length for table lookup")); 13433 return; 13434 } 13435 13436 listlenbits = inst.operands[1].imm - 1; 13437 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13438 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13439 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 13440 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 13441 inst.instruction |= LOW4 (inst.operands[2].reg); 13442 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 13443 inst.instruction |= listlenbits << 8; 13444 13445 inst.instruction = neon_dp_fixup (inst.instruction); 13446} 13447 13448static void 13449do_neon_ldm_stm (void) 13450{ 13451 /* P, U and L bits are part of bitmask. */ 13452 int is_dbmode = (inst.instruction & (1 << 24)) != 0; 13453 unsigned offsetbits = inst.operands[1].imm * 2; 13454 13455 if (inst.operands[1].issingle) 13456 { 13457 do_vfp_nsyn_ldm_stm (is_dbmode); 13458 return; 13459 } 13460 13461 constraint (is_dbmode && !inst.operands[0].writeback, 13462 _("writeback (!) must be used for VLDMDB and VSTMDB")); 13463 13464 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, 13465 _("register list must contain at least 1 and at most 16 " 13466 "registers")); 13467 13468 inst.instruction |= inst.operands[0].reg << 16; 13469 inst.instruction |= inst.operands[0].writeback << 21; 13470 inst.instruction |= LOW4 (inst.operands[1].reg) << 12; 13471 inst.instruction |= HI1 (inst.operands[1].reg) << 22; 13472 13473 inst.instruction |= offsetbits; 13474 13475 do_vfp_cond_or_thumb (); 13476} 13477 13478static void 13479do_neon_ldr_str (void) 13480{ 13481 int is_ldr = (inst.instruction & (1 << 20)) != 0; 13482 13483 if (inst.operands[0].issingle) 13484 { 13485 if (is_ldr) 13486 do_vfp_nsyn_opcode ("flds"); 13487 else 13488 do_vfp_nsyn_opcode ("fsts"); 13489 } 13490 else 13491 { 13492 if (is_ldr) 13493 do_vfp_nsyn_opcode ("fldd"); 13494 else 13495 do_vfp_nsyn_opcode ("fstd"); 13496 } 13497} 13498 13499/* "interleave" version also handles non-interleaving register VLD1/VST1 13500 instructions. */ 13501 13502static void 13503do_neon_ld_st_interleave (void) 13504{ 13505 struct neon_type_el et = neon_check_type (1, NS_NULL, 13506 N_8 | N_16 | N_32 | N_64); 13507 unsigned alignbits = 0; 13508 unsigned idx; 13509 /* The bits in this table go: 13510 0: register stride of one (0) or two (1) 13511 1,2: register list length, minus one (1, 2, 3, 4). 13512 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). 13513 We use -1 for invalid entries. */ 13514 const int typetable[] = 13515 { 13516 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ 13517 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ 13518 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ 13519 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ 13520 }; 13521 int typebits; 13522 13523 if (et.type == NT_invtype) 13524 return; 13525 13526 if (inst.operands[1].immisalign) 13527 switch (inst.operands[1].imm >> 8) 13528 { 13529 case 64: alignbits = 1; break; 13530 case 128: 13531 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3) 13532 goto bad_alignment; 13533 alignbits = 2; 13534 break; 13535 case 256: 13536 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3) 13537 goto bad_alignment; 13538 alignbits = 3; 13539 break; 13540 default: 13541 bad_alignment: 13542 first_error (_("bad alignment")); 13543 return; 13544 } 13545 13546 inst.instruction |= alignbits << 4; 13547 inst.instruction |= neon_logbits (et.size) << 6; 13548 13549 /* Bits [4:6] of the immediate in a list specifier encode register stride 13550 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of 13551 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look 13552 up the right value for "type" in a table based on this value and the given 13553 list style, then stick it back. */ 13554 idx = ((inst.operands[0].imm >> 4) & 7) 13555 | (((inst.instruction >> 8) & 3) << 3); 13556 13557 typebits = typetable[idx]; 13558 13559 constraint (typebits == -1, _("bad list type for instruction")); 13560 13561 inst.instruction &= ~0xf00; 13562 inst.instruction |= typebits << 8; 13563} 13564 13565/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. 13566 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 13567 otherwise. The variable arguments are a list of pairs of legal (size, align) 13568 values, terminated with -1. */ 13569 13570static int 13571neon_alignment_bit (int size, int align, int *do_align, ...) 13572{ 13573 va_list ap; 13574 int result = FAIL, thissize, thisalign; 13575 13576 if (!inst.operands[1].immisalign) 13577 { 13578 *do_align = 0; 13579 return SUCCESS; 13580 } 13581 13582 va_start (ap, do_align); 13583 13584 do 13585 { 13586 thissize = va_arg (ap, int); 13587 if (thissize == -1) 13588 break; 13589 thisalign = va_arg (ap, int); 13590 13591 if (size == thissize && align == thisalign) 13592 result = SUCCESS; 13593 } 13594 while (result != SUCCESS); 13595 13596 va_end (ap); 13597 13598 if (result == SUCCESS) 13599 *do_align = 1; 13600 else 13601 first_error (_("unsupported alignment for instruction")); 13602 13603 return result; 13604} 13605 13606static void 13607do_neon_ld_st_lane (void) 13608{ 13609 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); 13610 int align_good, do_align = 0; 13611 int logsize = neon_logbits (et.size); 13612 int align = inst.operands[1].imm >> 8; 13613 int n = (inst.instruction >> 8) & 3; 13614 int max_el = 64 / et.size; 13615 13616 if (et.type == NT_invtype) 13617 return; 13618 13619 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, 13620 _("bad list length")); 13621 constraint (NEON_LANE (inst.operands[0].imm) >= max_el, 13622 _("scalar index out of range")); 13623 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 13624 && et.size == 8, 13625 _("stride of 2 unavailable when element size is 8")); 13626 13627 switch (n) 13628 { 13629 case 0: /* VLD1 / VST1. */ 13630 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, 13631 32, 32, -1); 13632 if (align_good == FAIL) 13633 return; 13634 if (do_align) 13635 { 13636 unsigned alignbits = 0; 13637 switch (et.size) 13638 { 13639 case 16: alignbits = 0x1; break; 13640 case 32: alignbits = 0x3; break; 13641 default: ; 13642 } 13643 inst.instruction |= alignbits << 4; 13644 } 13645 break; 13646 13647 case 1: /* VLD2 / VST2. */ 13648 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, 13649 32, 64, -1); 13650 if (align_good == FAIL) 13651 return; 13652 if (do_align) 13653 inst.instruction |= 1 << 4; 13654 break; 13655 13656 case 2: /* VLD3 / VST3. */ 13657 constraint (inst.operands[1].immisalign, 13658 _("can't use alignment with this instruction")); 13659 break; 13660 13661 case 3: /* VLD4 / VST4. */ 13662 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, 13663 16, 64, 32, 64, 32, 128, -1); 13664 if (align_good == FAIL) 13665 return; 13666 if (do_align) 13667 { 13668 unsigned alignbits = 0; 13669 switch (et.size) 13670 { 13671 case 8: alignbits = 0x1; break; 13672 case 16: alignbits = 0x1; break; 13673 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; 13674 default: ; 13675 } 13676 inst.instruction |= alignbits << 4; 13677 } 13678 break; 13679 13680 default: ; 13681 } 13682 13683 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ 13684 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13685 inst.instruction |= 1 << (4 + logsize); 13686 13687 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); 13688 inst.instruction |= logsize << 10; 13689} 13690 13691/* Encode single n-element structure to all lanes VLD<n> instructions. */ 13692 13693static void 13694do_neon_ld_dup (void) 13695{ 13696 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); 13697 int align_good, do_align = 0; 13698 13699 if (et.type == NT_invtype) 13700 return; 13701 13702 switch ((inst.instruction >> 8) & 3) 13703 { 13704 case 0: /* VLD1. */ 13705 assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); 13706 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, 13707 &do_align, 16, 16, 32, 32, -1); 13708 if (align_good == FAIL) 13709 return; 13710 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) 13711 { 13712 case 1: break; 13713 case 2: inst.instruction |= 1 << 5; break; 13714 default: first_error (_("bad list length")); return; 13715 } 13716 inst.instruction |= neon_logbits (et.size) << 6; 13717 break; 13718 13719 case 1: /* VLD2. */ 13720 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, 13721 &do_align, 8, 16, 16, 32, 32, 64, -1); 13722 if (align_good == FAIL) 13723 return; 13724 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, 13725 _("bad list length")); 13726 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13727 inst.instruction |= 1 << 5; 13728 inst.instruction |= neon_logbits (et.size) << 6; 13729 break; 13730 13731 case 2: /* VLD3. */ 13732 constraint (inst.operands[1].immisalign, 13733 _("can't use alignment with this instruction")); 13734 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, 13735 _("bad list length")); 13736 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13737 inst.instruction |= 1 << 5; 13738 inst.instruction |= neon_logbits (et.size) << 6; 13739 break; 13740 13741 case 3: /* VLD4. */ 13742 { 13743 int align = inst.operands[1].imm >> 8; 13744 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, 13745 16, 64, 32, 64, 32, 128, -1); 13746 if (align_good == FAIL) 13747 return; 13748 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, 13749 _("bad list length")); 13750 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13751 inst.instruction |= 1 << 5; 13752 if (et.size == 32 && align == 128) 13753 inst.instruction |= 0x3 << 6; 13754 else 13755 inst.instruction |= neon_logbits (et.size) << 6; 13756 } 13757 break; 13758 13759 default: ; 13760 } 13761 13762 inst.instruction |= do_align << 4; 13763} 13764 13765/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those 13766 apart from bits [11:4]. */ 13767 13768static void 13769do_neon_ldx_stx (void) 13770{ 13771 switch (NEON_LANE (inst.operands[0].imm)) 13772 { 13773 case NEON_INTERLEAVE_LANES: 13774 inst.instruction = NEON_ENC_INTERLV (inst.instruction); 13775 do_neon_ld_st_interleave (); 13776 break; 13777 13778 case NEON_ALL_LANES: 13779 inst.instruction = NEON_ENC_DUP (inst.instruction); 13780 do_neon_ld_dup (); 13781 break; 13782 13783 default: 13784 inst.instruction = NEON_ENC_LANE (inst.instruction); 13785 do_neon_ld_st_lane (); 13786 } 13787 13788 /* L bit comes from bit mask. */ 13789 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13790 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13791 inst.instruction |= inst.operands[1].reg << 16; 13792 13793 if (inst.operands[1].postind) 13794 { 13795 int postreg = inst.operands[1].imm & 0xf; 13796 constraint (!inst.operands[1].immisreg, 13797 _("post-index must be a register")); 13798 constraint (postreg == 0xd || postreg == 0xf, 13799 _("bad register for post-index")); 13800 inst.instruction |= postreg; 13801 } 13802 else if (inst.operands[1].writeback) 13803 { 13804 inst.instruction |= 0xd; 13805 } 13806 else 13807 inst.instruction |= 0xf; 13808 13809 if (thumb_mode) 13810 inst.instruction |= 0xf9000000; 13811 else 13812 inst.instruction |= 0xf4000000; 13813} 13814 13815 13816/* Overall per-instruction processing. */ 13817 13818/* We need to be able to fix up arbitrary expressions in some statements. 13819 This is so that we can handle symbols that are an arbitrary distance from 13820 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), 13821 which returns part of an address in a form which will be valid for 13822 a data instruction. We do this by pushing the expression into a symbol 13823 in the expr_section, and creating a fix for that. */ 13824 13825static void 13826fix_new_arm (fragS * frag, 13827 int where, 13828 short int size, 13829 expressionS * exp, 13830 int pc_rel, 13831 int reloc) 13832{ 13833 fixS * new_fix; 13834 13835 switch (exp->X_op) 13836 { 13837 case O_constant: 13838 case O_symbol: 13839 case O_add: 13840 case O_subtract: 13841 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc); 13842 break; 13843 13844 default: 13845 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0, 13846 pc_rel, reloc); 13847 break; 13848 } 13849 13850 /* Mark whether the fix is to a THUMB instruction, or an ARM 13851 instruction. */ 13852 new_fix->tc_fix_data = thumb_mode; 13853} 13854 13855/* Create a frg for an instruction requiring relaxation. */ 13856static void 13857output_relax_insn (void) 13858{ 13859 char * to; 13860 symbolS *sym; 13861 int offset; 13862 13863 /* The size of the instruction is unknown, so tie the debug info to the 13864 start of the instruction. */ 13865 dwarf2_emit_insn (0); 13866 13867 switch (inst.reloc.exp.X_op) 13868 { 13869 case O_symbol: 13870 sym = inst.reloc.exp.X_add_symbol; 13871 offset = inst.reloc.exp.X_add_number; 13872 break; 13873 case O_constant: 13874 sym = NULL; 13875 offset = inst.reloc.exp.X_add_number; 13876 break; 13877 default: 13878 sym = make_expr_symbol (&inst.reloc.exp); 13879 offset = 0; 13880 break; 13881 } 13882 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, 13883 inst.relax, sym, offset, NULL/*offset, opcode*/); 13884 md_number_to_chars (to, inst.instruction, THUMB_SIZE); 13885} 13886 13887/* Write a 32-bit thumb instruction to buf. */ 13888static void 13889put_thumb32_insn (char * buf, unsigned long insn) 13890{ 13891 md_number_to_chars (buf, insn >> 16, THUMB_SIZE); 13892 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); 13893} 13894 13895static void 13896output_inst (const char * str) 13897{ 13898 char * to = NULL; 13899 13900 if (inst.error) 13901 { 13902 as_bad ("%s -- `%s'", inst.error, str); 13903 return; 13904 } 13905 if (inst.relax) { 13906 output_relax_insn(); 13907 return; 13908 } 13909 if (inst.size == 0) 13910 return; 13911 13912 to = frag_more (inst.size); 13913 13914 if (thumb_mode && (inst.size > THUMB_SIZE)) 13915 { 13916 assert (inst.size == (2 * THUMB_SIZE)); 13917 put_thumb32_insn (to, inst.instruction); 13918 } 13919 else if (inst.size > INSN_SIZE) 13920 { 13921 assert (inst.size == (2 * INSN_SIZE)); 13922 md_number_to_chars (to, inst.instruction, INSN_SIZE); 13923 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); 13924 } 13925 else 13926 md_number_to_chars (to, inst.instruction, inst.size); 13927 13928 if (inst.reloc.type != BFD_RELOC_UNUSED) 13929 fix_new_arm (frag_now, to - frag_now->fr_literal, 13930 inst.size, & inst.reloc.exp, inst.reloc.pc_rel, 13931 inst.reloc.type); 13932 13933 dwarf2_emit_insn (inst.size); 13934} 13935 13936/* Tag values used in struct asm_opcode's tag field. */ 13937enum opcode_tag 13938{ 13939 OT_unconditional, /* Instruction cannot be conditionalized. 13940 The ARM condition field is still 0xE. */ 13941 OT_unconditionalF, /* Instruction cannot be conditionalized 13942 and carries 0xF in its ARM condition field. */ 13943 OT_csuffix, /* Instruction takes a conditional suffix. */ 13944 OT_csuffixF, /* Some forms of the instruction take a conditional 13945 suffix, others place 0xF where the condition field 13946 would be. */ 13947 OT_cinfix3, /* Instruction takes a conditional infix, 13948 beginning at character index 3. (In 13949 unified mode, it becomes a suffix.) */ 13950 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for 13951 tsts, cmps, cmns, and teqs. */ 13952 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at 13953 character index 3, even in unified mode. Used for 13954 legacy instructions where suffix and infix forms 13955 may be ambiguous. */ 13956 OT_csuf_or_in3, /* Instruction takes either a conditional 13957 suffix or an infix at character index 3. */ 13958 OT_odd_infix_unc, /* This is the unconditional variant of an 13959 instruction that takes a conditional infix 13960 at an unusual position. In unified mode, 13961 this variant will accept a suffix. */ 13962 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 13963 are the conditional variants of instructions that 13964 take conditional infixes in unusual positions. 13965 The infix appears at character index 13966 (tag - OT_odd_infix_0). These are not accepted 13967 in unified mode. */ 13968}; 13969 13970/* Subroutine of md_assemble, responsible for looking up the primary 13971 opcode from the mnemonic the user wrote. STR points to the 13972 beginning of the mnemonic. 13973 13974 This is not simply a hash table lookup, because of conditional 13975 variants. Most instructions have conditional variants, which are 13976 expressed with a _conditional affix_ to the mnemonic. If we were 13977 to encode each conditional variant as a literal string in the opcode 13978 table, it would have approximately 20,000 entries. 13979 13980 Most mnemonics take this affix as a suffix, and in unified syntax, 13981 'most' is upgraded to 'all'. However, in the divided syntax, some 13982 instructions take the affix as an infix, notably the s-variants of 13983 the arithmetic instructions. Of those instructions, all but six 13984 have the infix appear after the third character of the mnemonic. 13985 13986 Accordingly, the algorithm for looking up primary opcodes given 13987 an identifier is: 13988 13989 1. Look up the identifier in the opcode table. 13990 If we find a match, go to step U. 13991 13992 2. Look up the last two characters of the identifier in the 13993 conditions table. If we find a match, look up the first N-2 13994 characters of the identifier in the opcode table. If we 13995 find a match, go to step CE. 13996 13997 3. Look up the fourth and fifth characters of the identifier in 13998 the conditions table. If we find a match, extract those 13999 characters from the identifier, and look up the remaining 14000 characters in the opcode table. If we find a match, go 14001 to step CM. 14002 14003 4. Fail. 14004 14005 U. Examine the tag field of the opcode structure, in case this is 14006 one of the six instructions with its conditional infix in an 14007 unusual place. If it is, the tag tells us where to find the 14008 infix; look it up in the conditions table and set inst.cond 14009 accordingly. Otherwise, this is an unconditional instruction. 14010 Again set inst.cond accordingly. Return the opcode structure. 14011 14012 CE. Examine the tag field to make sure this is an instruction that 14013 should receive a conditional suffix. If it is not, fail. 14014 Otherwise, set inst.cond from the suffix we already looked up, 14015 and return the opcode structure. 14016 14017 CM. Examine the tag field to make sure this is an instruction that 14018 should receive a conditional infix after the third character. 14019 If it is not, fail. Otherwise, undo the edits to the current 14020 line of input and proceed as for case CE. */ 14021 14022static const struct asm_opcode * 14023opcode_lookup (char **str) 14024{ 14025 char *end, *base; 14026 char *affix; 14027 const struct asm_opcode *opcode; 14028 const struct asm_cond *cond; 14029 char save[2]; 14030 bfd_boolean neon_supported; 14031 14032 neon_supported = ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1); 14033 14034 /* Scan up to the end of the mnemonic, which must end in white space, 14035 '.' (in unified mode, or for Neon instructions), or end of string. */ 14036 for (base = end = *str; *end != '\0'; end++) 14037 if (*end == ' ' || ((unified_syntax || neon_supported) && *end == '.')) 14038 break; 14039 14040 if (end == base) 14041 return 0; 14042 14043 /* Handle a possible width suffix and/or Neon type suffix. */ 14044 if (end[0] == '.') 14045 { 14046 int offset = 2; 14047 14048 /* The .w and .n suffixes are only valid if the unified syntax is in 14049 use. */ 14050 if (unified_syntax && end[1] == 'w') 14051 inst.size_req = 4; 14052 else if (unified_syntax && end[1] == 'n') 14053 inst.size_req = 2; 14054 else 14055 offset = 0; 14056 14057 inst.vectype.elems = 0; 14058 14059 *str = end + offset; 14060 14061 if (end[offset] == '.') 14062 { 14063 /* See if we have a Neon type suffix (possible in either unified or 14064 non-unified ARM syntax mode). */ 14065 if (parse_neon_type (&inst.vectype, str) == FAIL) 14066 return 0; 14067 } 14068 else if (end[offset] != '\0' && end[offset] != ' ') 14069 return 0; 14070 } 14071 else 14072 *str = end; 14073 14074 /* Look for unaffixed or special-case affixed mnemonic. */ 14075 opcode = hash_find_n (arm_ops_hsh, base, end - base); 14076 if (opcode) 14077 { 14078 /* step U */ 14079 if (opcode->tag < OT_odd_infix_0) 14080 { 14081 inst.cond = COND_ALWAYS; 14082 return opcode; 14083 } 14084 14085 if (unified_syntax) 14086 as_warn (_("conditional infixes are deprecated in unified syntax")); 14087 affix = base + (opcode->tag - OT_odd_infix_0); 14088 cond = hash_find_n (arm_cond_hsh, affix, 2); 14089 assert (cond); 14090 14091 inst.cond = cond->value; 14092 return opcode; 14093 } 14094 14095 /* Cannot have a conditional suffix on a mnemonic of less than two 14096 characters. */ 14097 if (end - base < 3) 14098 return 0; 14099 14100 /* Look for suffixed mnemonic. */ 14101 affix = end - 2; 14102 cond = hash_find_n (arm_cond_hsh, affix, 2); 14103 opcode = hash_find_n (arm_ops_hsh, base, affix - base); 14104 if (opcode && cond) 14105 { 14106 /* step CE */ 14107 switch (opcode->tag) 14108 { 14109 case OT_cinfix3_legacy: 14110 /* Ignore conditional suffixes matched on infix only mnemonics. */ 14111 break; 14112 14113 case OT_cinfix3: 14114 case OT_cinfix3_deprecated: 14115 case OT_odd_infix_unc: 14116 if (!unified_syntax) 14117 return 0; 14118 /* else fall through */ 14119 14120 case OT_csuffix: 14121 case OT_csuffixF: 14122 case OT_csuf_or_in3: 14123 inst.cond = cond->value; 14124 return opcode; 14125 14126 case OT_unconditional: 14127 case OT_unconditionalF: 14128 if (thumb_mode) 14129 { 14130 inst.cond = cond->value; 14131 } 14132 else 14133 { 14134 /* delayed diagnostic */ 14135 inst.error = BAD_COND; 14136 inst.cond = COND_ALWAYS; 14137 } 14138 return opcode; 14139 14140 default: 14141 return 0; 14142 } 14143 } 14144 14145 /* Cannot have a usual-position infix on a mnemonic of less than 14146 six characters (five would be a suffix). */ 14147 if (end - base < 6) 14148 return 0; 14149 14150 /* Look for infixed mnemonic in the usual position. */ 14151 affix = base + 3; 14152 cond = hash_find_n (arm_cond_hsh, affix, 2); 14153 if (!cond) 14154 return 0; 14155 14156 memcpy (save, affix, 2); 14157 memmove (affix, affix + 2, (end - affix) - 2); 14158 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2); 14159 memmove (affix + 2, affix, (end - affix) - 2); 14160 memcpy (affix, save, 2); 14161 14162 if (opcode 14163 && (opcode->tag == OT_cinfix3 14164 || opcode->tag == OT_cinfix3_deprecated 14165 || opcode->tag == OT_csuf_or_in3 14166 || opcode->tag == OT_cinfix3_legacy)) 14167 { 14168 /* step CM */ 14169 if (unified_syntax 14170 && (opcode->tag == OT_cinfix3 14171 || opcode->tag == OT_cinfix3_deprecated)) 14172 as_warn (_("conditional infixes are deprecated in unified syntax")); 14173 14174 inst.cond = cond->value; 14175 return opcode; 14176 } 14177 14178 return 0; 14179} 14180 14181void 14182md_assemble (char *str) 14183{ 14184 char *p = str; 14185 const struct asm_opcode * opcode; 14186 14187 /* Align the previous label if needed. */ 14188 if (last_label_seen != NULL) 14189 { 14190 symbol_set_frag (last_label_seen, frag_now); 14191 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); 14192 S_SET_SEGMENT (last_label_seen, now_seg); 14193 } 14194 14195 memset (&inst, '\0', sizeof (inst)); 14196 inst.reloc.type = BFD_RELOC_UNUSED; 14197 14198 opcode = opcode_lookup (&p); 14199 if (!opcode) 14200 { 14201 /* It wasn't an instruction, but it might be a register alias of 14202 the form alias .req reg, or a Neon .dn/.qn directive. */ 14203 if (!create_register_alias (str, p) 14204 && !create_neon_reg_alias (str, p)) 14205 as_bad (_("bad instruction `%s'"), str); 14206 14207 return; 14208 } 14209 14210 if (opcode->tag == OT_cinfix3_deprecated) 14211 as_warn (_("s suffix on comparison instruction is deprecated")); 14212 14213 /* The value which unconditional instructions should have in place of the 14214 condition field. */ 14215 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; 14216 14217 if (thumb_mode) 14218 { 14219 arm_feature_set variant; 14220 14221 variant = cpu_variant; 14222 /* Only allow coprocessor instructions on Thumb-2 capable devices. */ 14223 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) 14224 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); 14225 /* Check that this instruction is supported for this CPU. */ 14226 if (!opcode->tvariant 14227 || (thumb_mode == 1 14228 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) 14229 { 14230 as_bad (_("selected processor does not support `%s'"), str); 14231 return; 14232 } 14233 if (inst.cond != COND_ALWAYS && !unified_syntax 14234 && opcode->tencode != do_t_branch) 14235 { 14236 as_bad (_("Thumb does not support conditional execution")); 14237 return; 14238 } 14239 14240 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) && !inst.size_req) 14241 { 14242 /* Implicit require narrow instructions on Thumb-1. This avoids 14243 relaxation accidentally introducing Thumb-2 instructions. */ 14244 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23) 14245 inst.size_req = 2; 14246 } 14247 14248 /* Check conditional suffixes. */ 14249 if (current_it_mask) 14250 { 14251 int cond; 14252 cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1; 14253 current_it_mask <<= 1; 14254 current_it_mask &= 0x1f; 14255 /* The BKPT instruction is unconditional even in an IT block. */ 14256 if (!inst.error 14257 && cond != inst.cond && opcode->tencode != do_t_bkpt) 14258 { 14259 as_bad (_("incorrect condition in IT block")); 14260 return; 14261 } 14262 } 14263 else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch) 14264 { 14265 as_bad (_("thumb conditional instrunction not in IT block")); 14266 return; 14267 } 14268 14269 mapping_state (MAP_THUMB); 14270 inst.instruction = opcode->tvalue; 14271 14272 if (!parse_operands (p, opcode->operands)) 14273 opcode->tencode (); 14274 14275 /* Clear current_it_mask at the end of an IT block. */ 14276 if (current_it_mask == 0x10) 14277 current_it_mask = 0; 14278 14279 if (!(inst.error || inst.relax)) 14280 { 14281 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); 14282 inst.size = (inst.instruction > 0xffff ? 4 : 2); 14283 if (inst.size_req && inst.size_req != inst.size) 14284 { 14285 as_bad (_("cannot honor width suffix -- `%s'"), str); 14286 return; 14287 } 14288 } 14289 14290 /* Something has gone badly wrong if we try to relax a fixed size 14291 instruction. */ 14292 assert (inst.size_req == 0 || !inst.relax); 14293 14294 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 14295 *opcode->tvariant); 14296 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly 14297 set those bits when Thumb-2 32-bit instructions are seen. ie. 14298 anything other than bl/blx. 14299 This is overly pessimistic for relaxable instructions. */ 14300 if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) 14301 || inst.relax) 14302 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 14303 arm_ext_v6t2); 14304 } 14305 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 14306 { 14307 /* Check that this instruction is supported for this CPU. */ 14308 if (!opcode->avariant || 14309 !ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)) 14310 { 14311 as_bad (_("selected processor does not support `%s'"), str); 14312 return; 14313 } 14314 if (inst.size_req) 14315 { 14316 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); 14317 return; 14318 } 14319 14320 mapping_state (MAP_ARM); 14321 inst.instruction = opcode->avalue; 14322 if (opcode->tag == OT_unconditionalF) 14323 inst.instruction |= 0xF << 28; 14324 else 14325 inst.instruction |= inst.cond << 28; 14326 inst.size = INSN_SIZE; 14327 if (!parse_operands (p, opcode->operands)) 14328 opcode->aencode (); 14329 /* Arm mode bx is marked as both v4T and v5 because it's still required 14330 on a hypothetical non-thumb v5 core. */ 14331 if (ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v4t) 14332 || ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v5)) 14333 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); 14334 else 14335 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 14336 *opcode->avariant); 14337 } 14338 else 14339 { 14340 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " 14341 "-- `%s'"), str); 14342 return; 14343 } 14344 output_inst (str); 14345} 14346 14347/* Various frobbings of labels and their addresses. */ 14348 14349void 14350arm_start_line_hook (void) 14351{ 14352 last_label_seen = NULL; 14353} 14354 14355void 14356arm_frob_label (symbolS * sym) 14357{ 14358 last_label_seen = sym; 14359 14360 ARM_SET_THUMB (sym, thumb_mode); 14361 14362#if defined OBJ_COFF || defined OBJ_ELF 14363 ARM_SET_INTERWORK (sym, support_interwork); 14364#endif 14365 14366 /* Note - do not allow local symbols (.Lxxx) to be labeled 14367 as Thumb functions. This is because these labels, whilst 14368 they exist inside Thumb code, are not the entry points for 14369 possible ARM->Thumb calls. Also, these labels can be used 14370 as part of a computed goto or switch statement. eg gcc 14371 can generate code that looks like this: 14372 14373 ldr r2, [pc, .Laaa] 14374 lsl r3, r3, #2 14375 ldr r2, [r3, r2] 14376 mov pc, r2 14377 14378 .Lbbb: .word .Lxxx 14379 .Lccc: .word .Lyyy 14380 ..etc... 14381 .Laaa: .word Lbbb 14382 14383 The first instruction loads the address of the jump table. 14384 The second instruction converts a table index into a byte offset. 14385 The third instruction gets the jump address out of the table. 14386 The fourth instruction performs the jump. 14387 14388 If the address stored at .Laaa is that of a symbol which has the 14389 Thumb_Func bit set, then the linker will arrange for this address 14390 to have the bottom bit set, which in turn would mean that the 14391 address computation performed by the third instruction would end 14392 up with the bottom bit set. Since the ARM is capable of unaligned 14393 word loads, the instruction would then load the incorrect address 14394 out of the jump table, and chaos would ensue. */ 14395 if (label_is_thumb_function_name 14396 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') 14397 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) 14398 { 14399 /* When the address of a Thumb function is taken the bottom 14400 bit of that address should be set. This will allow 14401 interworking between Arm and Thumb functions to work 14402 correctly. */ 14403 14404 THUMB_SET_FUNC (sym, 1); 14405 14406 label_is_thumb_function_name = FALSE; 14407 } 14408 14409 dwarf2_emit_label (sym); 14410} 14411 14412int 14413arm_data_in_code (void) 14414{ 14415 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) 14416 { 14417 *input_line_pointer = '/'; 14418 input_line_pointer += 5; 14419 *input_line_pointer = 0; 14420 return 1; 14421 } 14422 14423 return 0; 14424} 14425 14426char * 14427arm_canonicalize_symbol_name (char * name) 14428{ 14429 int len; 14430 14431 if (thumb_mode && (len = strlen (name)) > 5 14432 && streq (name + len - 5, "/data")) 14433 *(name + len - 5) = 0; 14434 14435 return name; 14436} 14437 14438/* Table of all register names defined by default. The user can 14439 define additional names with .req. Note that all register names 14440 should appear in both upper and lowercase variants. Some registers 14441 also have mixed-case names. */ 14442 14443#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } 14444#define REGNUM(p,n,t) REGDEF(p##n, n, t) 14445#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) 14446#define REGSET(p,t) \ 14447 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ 14448 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ 14449 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ 14450 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) 14451#define REGSETH(p,t) \ 14452 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ 14453 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ 14454 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ 14455 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) 14456#define REGSET2(p,t) \ 14457 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ 14458 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ 14459 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ 14460 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) 14461 14462static const struct reg_entry reg_names[] = 14463{ 14464 /* ARM integer registers. */ 14465 REGSET(r, RN), REGSET(R, RN), 14466 14467 /* ATPCS synonyms. */ 14468 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), 14469 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), 14470 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), 14471 14472 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), 14473 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), 14474 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), 14475 14476 /* Well-known aliases. */ 14477 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), 14478 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), 14479 14480 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), 14481 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), 14482 14483 /* Coprocessor numbers. */ 14484 REGSET(p, CP), REGSET(P, CP), 14485 14486 /* Coprocessor register numbers. The "cr" variants are for backward 14487 compatibility. */ 14488 REGSET(c, CN), REGSET(C, CN), 14489 REGSET(cr, CN), REGSET(CR, CN), 14490 14491 /* FPA registers. */ 14492 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), 14493 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), 14494 14495 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), 14496 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), 14497 14498 /* VFP SP registers. */ 14499 REGSET(s,VFS), REGSET(S,VFS), 14500 REGSETH(s,VFS), REGSETH(S,VFS), 14501 14502 /* VFP DP Registers. */ 14503 REGSET(d,VFD), REGSET(D,VFD), 14504 /* Extra Neon DP registers. */ 14505 REGSETH(d,VFD), REGSETH(D,VFD), 14506 14507 /* Neon QP registers. */ 14508 REGSET2(q,NQ), REGSET2(Q,NQ), 14509 14510 /* VFP control registers. */ 14511 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), 14512 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), 14513 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), 14514 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), 14515 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), 14516 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), 14517 14518 /* Maverick DSP coprocessor registers. */ 14519 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), 14520 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), 14521 14522 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), 14523 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), 14524 REGDEF(dspsc,0,DSPSC), 14525 14526 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), 14527 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), 14528 REGDEF(DSPSC,0,DSPSC), 14529 14530 /* iWMMXt data registers - p0, c0-15. */ 14531 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), 14532 14533 /* iWMMXt control registers - p1, c0-3. */ 14534 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), 14535 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), 14536 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), 14537 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), 14538 14539 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ 14540 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), 14541 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), 14542 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), 14543 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), 14544 14545 /* XScale accumulator registers. */ 14546 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), 14547}; 14548#undef REGDEF 14549#undef REGNUM 14550#undef REGSET 14551 14552/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled 14553 within psr_required_here. */ 14554static const struct asm_psr psrs[] = 14555{ 14556 /* Backward compatibility notation. Note that "all" is no longer 14557 truly all possible PSR bits. */ 14558 {"all", PSR_c | PSR_f}, 14559 {"flg", PSR_f}, 14560 {"ctl", PSR_c}, 14561 14562 /* Individual flags. */ 14563 {"f", PSR_f}, 14564 {"c", PSR_c}, 14565 {"x", PSR_x}, 14566 {"s", PSR_s}, 14567 /* Combinations of flags. */ 14568 {"fs", PSR_f | PSR_s}, 14569 {"fx", PSR_f | PSR_x}, 14570 {"fc", PSR_f | PSR_c}, 14571 {"sf", PSR_s | PSR_f}, 14572 {"sx", PSR_s | PSR_x}, 14573 {"sc", PSR_s | PSR_c}, 14574 {"xf", PSR_x | PSR_f}, 14575 {"xs", PSR_x | PSR_s}, 14576 {"xc", PSR_x | PSR_c}, 14577 {"cf", PSR_c | PSR_f}, 14578 {"cs", PSR_c | PSR_s}, 14579 {"cx", PSR_c | PSR_x}, 14580 {"fsx", PSR_f | PSR_s | PSR_x}, 14581 {"fsc", PSR_f | PSR_s | PSR_c}, 14582 {"fxs", PSR_f | PSR_x | PSR_s}, 14583 {"fxc", PSR_f | PSR_x | PSR_c}, 14584 {"fcs", PSR_f | PSR_c | PSR_s}, 14585 {"fcx", PSR_f | PSR_c | PSR_x}, 14586 {"sfx", PSR_s | PSR_f | PSR_x}, 14587 {"sfc", PSR_s | PSR_f | PSR_c}, 14588 {"sxf", PSR_s | PSR_x | PSR_f}, 14589 {"sxc", PSR_s | PSR_x | PSR_c}, 14590 {"scf", PSR_s | PSR_c | PSR_f}, 14591 {"scx", PSR_s | PSR_c | PSR_x}, 14592 {"xfs", PSR_x | PSR_f | PSR_s}, 14593 {"xfc", PSR_x | PSR_f | PSR_c}, 14594 {"xsf", PSR_x | PSR_s | PSR_f}, 14595 {"xsc", PSR_x | PSR_s | PSR_c}, 14596 {"xcf", PSR_x | PSR_c | PSR_f}, 14597 {"xcs", PSR_x | PSR_c | PSR_s}, 14598 {"cfs", PSR_c | PSR_f | PSR_s}, 14599 {"cfx", PSR_c | PSR_f | PSR_x}, 14600 {"csf", PSR_c | PSR_s | PSR_f}, 14601 {"csx", PSR_c | PSR_s | PSR_x}, 14602 {"cxf", PSR_c | PSR_x | PSR_f}, 14603 {"cxs", PSR_c | PSR_x | PSR_s}, 14604 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, 14605 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, 14606 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, 14607 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, 14608 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, 14609 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, 14610 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, 14611 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, 14612 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, 14613 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, 14614 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, 14615 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, 14616 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, 14617 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, 14618 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, 14619 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, 14620 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, 14621 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, 14622 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, 14623 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, 14624 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, 14625 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, 14626 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, 14627 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, 14628}; 14629 14630/* Table of V7M psr names. */ 14631static const struct asm_psr v7m_psrs[] = 14632{ 14633 {"apsr", 0 }, {"APSR", 0 }, 14634 {"iapsr", 1 }, {"IAPSR", 1 }, 14635 {"eapsr", 2 }, {"EAPSR", 2 }, 14636 {"psr", 3 }, {"PSR", 3 }, 14637 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, 14638 {"ipsr", 5 }, {"IPSR", 5 }, 14639 {"epsr", 6 }, {"EPSR", 6 }, 14640 {"iepsr", 7 }, {"IEPSR", 7 }, 14641 {"msp", 8 }, {"MSP", 8 }, 14642 {"psp", 9 }, {"PSP", 9 }, 14643 {"primask", 16}, {"PRIMASK", 16}, 14644 {"basepri", 17}, {"BASEPRI", 17}, 14645 {"basepri_max", 18}, {"BASEPRI_MAX", 18}, 14646 {"faultmask", 19}, {"FAULTMASK", 19}, 14647 {"control", 20}, {"CONTROL", 20} 14648}; 14649 14650/* Table of all shift-in-operand names. */ 14651static const struct asm_shift_name shift_names [] = 14652{ 14653 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, 14654 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, 14655 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, 14656 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, 14657 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, 14658 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } 14659}; 14660 14661/* Table of all explicit relocation names. */ 14662#ifdef OBJ_ELF 14663static struct reloc_entry reloc_names[] = 14664{ 14665 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, 14666 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, 14667 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, 14668 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, 14669 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, 14670 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, 14671 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, 14672 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, 14673 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, 14674 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, 14675 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32} 14676}; 14677#endif 14678 14679/* Table of all conditional affixes. 0xF is not defined as a condition code. */ 14680static const struct asm_cond conds[] = 14681{ 14682 {"eq", 0x0}, 14683 {"ne", 0x1}, 14684 {"cs", 0x2}, {"hs", 0x2}, 14685 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, 14686 {"mi", 0x4}, 14687 {"pl", 0x5}, 14688 {"vs", 0x6}, 14689 {"vc", 0x7}, 14690 {"hi", 0x8}, 14691 {"ls", 0x9}, 14692 {"ge", 0xa}, 14693 {"lt", 0xb}, 14694 {"gt", 0xc}, 14695 {"le", 0xd}, 14696 {"al", 0xe} 14697}; 14698 14699static struct asm_barrier_opt barrier_opt_names[] = 14700{ 14701 { "sy", 0xf }, 14702 { "un", 0x7 }, 14703 { "st", 0xe }, 14704 { "unst", 0x6 } 14705}; 14706 14707/* Table of ARM-format instructions. */ 14708 14709/* Macros for gluing together operand strings. N.B. In all cases 14710 other than OPS0, the trailing OP_stop comes from default 14711 zero-initialization of the unspecified elements of the array. */ 14712#define OPS0() { OP_stop, } 14713#define OPS1(a) { OP_##a, } 14714#define OPS2(a,b) { OP_##a,OP_##b, } 14715#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } 14716#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } 14717#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } 14718#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } 14719 14720/* These macros abstract out the exact format of the mnemonic table and 14721 save some repeated characters. */ 14722 14723/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ 14724#define TxCE(mnem, op, top, nops, ops, ae, te) \ 14725 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ 14726 THUMB_VARIANT, do_##ae, do_##te } 14727 14728/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for 14729 a T_MNEM_xyz enumerator. */ 14730#define TCE(mnem, aop, top, nops, ops, ae, te) \ 14731 TxCE(mnem, aop, 0x##top, nops, ops, ae, te) 14732#define tCE(mnem, aop, top, nops, ops, ae, te) \ 14733 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te) 14734 14735/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional 14736 infix after the third character. */ 14737#define TxC3(mnem, op, top, nops, ops, ae, te) \ 14738 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ 14739 THUMB_VARIANT, do_##ae, do_##te } 14740#define TxC3w(mnem, op, top, nops, ops, ae, te) \ 14741 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ 14742 THUMB_VARIANT, do_##ae, do_##te } 14743#define TC3(mnem, aop, top, nops, ops, ae, te) \ 14744 TxC3(mnem, aop, 0x##top, nops, ops, ae, te) 14745#define TC3w(mnem, aop, top, nops, ops, ae, te) \ 14746 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te) 14747#define tC3(mnem, aop, top, nops, ops, ae, te) \ 14748 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te) 14749#define tC3w(mnem, aop, top, nops, ops, ae, te) \ 14750 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te) 14751 14752/* Mnemonic with a conditional infix in an unusual place. Each and every variant has to 14753 appear in the condition table. */ 14754#define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ 14755 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ 14756 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } 14757 14758#define TxCM(m1, m2, op, top, nops, ops, ae, te) \ 14759 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \ 14760 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \ 14761 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \ 14762 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \ 14763 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \ 14764 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \ 14765 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \ 14766 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \ 14767 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \ 14768 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \ 14769 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \ 14770 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \ 14771 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \ 14772 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \ 14773 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \ 14774 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \ 14775 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \ 14776 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \ 14777 TxCM_(m1, al, m2, op, top, nops, ops, ae, te) 14778 14779#define TCM(m1,m2, aop, top, nops, ops, ae, te) \ 14780 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te) 14781#define tCM(m1,m2, aop, top, nops, ops, ae, te) \ 14782 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te) 14783 14784/* Mnemonic that cannot be conditionalized. The ARM condition-code 14785 field is still 0xE. Many of the Thumb variants can be executed 14786 conditionally, so this is checked separately. */ 14787#define TUE(mnem, op, top, nops, ops, ae, te) \ 14788 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ 14789 THUMB_VARIANT, do_##ae, do_##te } 14790 14791/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM 14792 condition code field. */ 14793#define TUF(mnem, op, top, nops, ops, ae, te) \ 14794 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ 14795 THUMB_VARIANT, do_##ae, do_##te } 14796 14797/* ARM-only variants of all the above. */ 14798#define CE(mnem, op, nops, ops, ae) \ 14799 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14800 14801#define C3(mnem, op, nops, ops, ae) \ 14802 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14803 14804/* Legacy mnemonics that always have conditional infix after the third 14805 character. */ 14806#define CL(mnem, op, nops, ops, ae) \ 14807 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ 14808 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14809 14810/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ 14811#define cCE(mnem, op, nops, ops, ae) \ 14812 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 14813 14814/* Legacy coprocessor instructions where conditional infix and conditional 14815 suffix are ambiguous. For consistency this includes all FPA instructions, 14816 not just the potentially ambiguous ones. */ 14817#define cCL(mnem, op, nops, ops, ae) \ 14818 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ 14819 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 14820 14821/* Coprocessor, takes either a suffix or a position-3 infix 14822 (for an FPA corner case). */ 14823#define C3E(mnem, op, nops, ops, ae) \ 14824 { #mnem, OPS##nops ops, OT_csuf_or_in3, \ 14825 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 14826 14827#define xCM_(m1, m2, m3, op, nops, ops, ae) \ 14828 { #m1 #m2 #m3, OPS##nops ops, \ 14829 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ 14830 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14831 14832#define CM(m1, m2, op, nops, ops, ae) \ 14833 xCM_(m1, , m2, op, nops, ops, ae), \ 14834 xCM_(m1, eq, m2, op, nops, ops, ae), \ 14835 xCM_(m1, ne, m2, op, nops, ops, ae), \ 14836 xCM_(m1, cs, m2, op, nops, ops, ae), \ 14837 xCM_(m1, hs, m2, op, nops, ops, ae), \ 14838 xCM_(m1, cc, m2, op, nops, ops, ae), \ 14839 xCM_(m1, ul, m2, op, nops, ops, ae), \ 14840 xCM_(m1, lo, m2, op, nops, ops, ae), \ 14841 xCM_(m1, mi, m2, op, nops, ops, ae), \ 14842 xCM_(m1, pl, m2, op, nops, ops, ae), \ 14843 xCM_(m1, vs, m2, op, nops, ops, ae), \ 14844 xCM_(m1, vc, m2, op, nops, ops, ae), \ 14845 xCM_(m1, hi, m2, op, nops, ops, ae), \ 14846 xCM_(m1, ls, m2, op, nops, ops, ae), \ 14847 xCM_(m1, ge, m2, op, nops, ops, ae), \ 14848 xCM_(m1, lt, m2, op, nops, ops, ae), \ 14849 xCM_(m1, gt, m2, op, nops, ops, ae), \ 14850 xCM_(m1, le, m2, op, nops, ops, ae), \ 14851 xCM_(m1, al, m2, op, nops, ops, ae) 14852 14853#define UE(mnem, op, nops, ops, ae) \ 14854 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } 14855 14856#define UF(mnem, op, nops, ops, ae) \ 14857 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } 14858 14859/* Neon data-processing. ARM versions are unconditional with cond=0xf. 14860 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we 14861 use the same encoding function for each. */ 14862#define NUF(mnem, op, nops, ops, enc) \ 14863 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ 14864 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 14865 14866/* Neon data processing, version which indirects through neon_enc_tab for 14867 the various overloaded versions of opcodes. */ 14868#define nUF(mnem, op, nops, ops, enc) \ 14869 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \ 14870 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 14871 14872/* Neon insn with conditional suffix for the ARM version, non-overloaded 14873 version. */ 14874#define NCE_tag(mnem, op, nops, ops, enc, tag) \ 14875 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ 14876 THUMB_VARIANT, do_##enc, do_##enc } 14877 14878#define NCE(mnem, op, nops, ops, enc) \ 14879 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix) 14880 14881#define NCEF(mnem, op, nops, ops, enc) \ 14882 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF) 14883 14884/* Neon insn with conditional suffix for the ARM version, overloaded types. */ 14885#define nCE_tag(mnem, op, nops, ops, enc, tag) \ 14886 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \ 14887 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 14888 14889#define nCE(mnem, op, nops, ops, enc) \ 14890 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix) 14891 14892#define nCEF(mnem, op, nops, ops, enc) \ 14893 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF) 14894 14895#define do_0 0 14896 14897/* Thumb-only, unconditional. */ 14898#define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te) 14899 14900static const struct asm_opcode insns[] = 14901{ 14902#define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */ 14903#define THUMB_VARIANT &arm_ext_v4t 14904 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c), 14905 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c), 14906 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c), 14907 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c), 14908 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub), 14909 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub), 14910 tCE(add, 0800000, add, 3, (RR, oRR, SHG), arit, t_add_sub), 14911 tC3(adds, 0900000, adds, 3, (RR, oRR, SHG), arit, t_add_sub), 14912 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c), 14913 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c), 14914 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3), 14915 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3), 14916 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c), 14917 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c), 14918 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3), 14919 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3), 14920 14921 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism 14922 for setting PSR flag bits. They are obsolete in V6 and do not 14923 have Thumb equivalents. */ 14924 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), 14925 tC3w(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), 14926 CL(tstp, 110f000, 2, (RR, SH), cmp), 14927 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), 14928 tC3w(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), 14929 CL(cmpp, 150f000, 2, (RR, SH), cmp), 14930 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), 14931 tC3w(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), 14932 CL(cmnp, 170f000, 2, (RR, SH), cmp), 14933 14934 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp), 14935 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp), 14936 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst), 14937 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst), 14938 14939 tCE(ldr, 4100000, ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), 14940 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDRGLDR),ldst, t_ldst), 14941 tCE(str, 4000000, str, 2, (RR, ADDRGLDR),ldst, t_ldst), 14942 tC3(strb, 4400000, strb, 2, (RR, ADDRGLDR),ldst, t_ldst), 14943 14944 tCE(stm, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14945 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14946 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14947 tCE(ldm, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14948 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14949 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14950 14951 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi), 14952 TCE(svc, f000000, df00, 1, (EXPi), swi, t_swi), 14953 tCE(b, a000000, b, 1, (EXPr), branch, t_branch), 14954 TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23), 14955 14956 /* Pseudo ops. */ 14957 tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr), 14958 C3(adrl, 28f0000, 2, (RR, EXP), adrl), 14959 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop), 14960 14961 /* Thumb-compatibility pseudo ops. */ 14962 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift), 14963 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift), 14964 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift), 14965 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift), 14966 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift), 14967 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift), 14968 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift), 14969 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift), 14970 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg), 14971 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg), 14972 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop), 14973 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop), 14974 14975 /* These may simplify to neg. */ 14976 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), 14977 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), 14978 14979 TCE(rrx, 1a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rd_rm), 14980 TCE(rrxs, 1b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rd_rm), 14981 14982#undef THUMB_VARIANT 14983#define THUMB_VARIANT &arm_ext_v6 14984 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), 14985 14986 /* V1 instructions with no Thumb analogue prior to V6T2. */ 14987#undef THUMB_VARIANT 14988#define THUMB_VARIANT &arm_ext_v6t2 14989 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), 14990 TC3w(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), 14991 CL(teqp, 130f000, 2, (RR, SH), cmp), 14992 14993 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt), 14994 TC3(ldrbt, 4700000, f8100e00, 2, (RR, ADDR), ldstt, t_ldstt), 14995 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt), 14996 TC3(strbt, 4600000, f8000e00, 2, (RR, ADDR), ldstt, t_ldstt), 14997 14998 TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14999 TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 15000 15001 TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 15002 TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 15003 15004 /* V1 instructions with no Thumb analogue at all. */ 15005 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit), 15006 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), 15007 15008 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), 15009 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), 15010 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), 15011 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), 15012 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), 15013 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), 15014 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), 15015 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), 15016 15017#undef ARM_VARIANT 15018#define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */ 15019#undef THUMB_VARIANT 15020#define THUMB_VARIANT &arm_ext_v4t 15021 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), 15022 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), 15023 15024#undef THUMB_VARIANT 15025#define THUMB_VARIANT &arm_ext_v6t2 15026 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), 15027 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), 15028 15029 /* Generic coprocessor instructions. */ 15030 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), 15031 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15032 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15033 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15034 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15035 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 15036 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), 15037 15038#undef ARM_VARIANT 15039#define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */ 15040 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), 15041 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), 15042 15043#undef ARM_VARIANT 15044#define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */ 15045 TCE(mrs, 10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs), 15046 TCE(msr, 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr), 15047 15048#undef ARM_VARIANT 15049#define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */ 15050 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 15051 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 15052 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 15053 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 15054 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 15055 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 15056 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 15057 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 15058 15059#undef ARM_VARIANT 15060#define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */ 15061#undef THUMB_VARIANT 15062#define THUMB_VARIANT &arm_ext_v4t 15063 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15064 tC3(strh, 00000b0, strh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15065 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15066 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15067 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15068 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15069 15070#undef ARM_VARIANT 15071#define ARM_VARIANT &arm_ext_v4t_5 15072 /* ARM Architecture 4T. */ 15073 /* Note: bx (and blx) are required on V5, even if the processor does 15074 not support Thumb. */ 15075 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx), 15076 15077#undef ARM_VARIANT 15078#define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */ 15079#undef THUMB_VARIANT 15080#define THUMB_VARIANT &arm_ext_v5t 15081 /* Note: blx has 2 variants; the .value coded here is for 15082 BLX(2). Only this variant has conditional execution. */ 15083 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx), 15084 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), 15085 15086#undef THUMB_VARIANT 15087#define THUMB_VARIANT &arm_ext_v6t2 15088 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), 15089 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15090 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15091 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15092 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15093 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), 15094 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 15095 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), 15096 15097#undef ARM_VARIANT 15098#define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */ 15099 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15100 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15101 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15102 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15103 15104 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15105 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15106 15107 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15108 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15109 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15110 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15111 15112 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15113 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15114 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15115 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15116 15117 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15118 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15119 15120 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15121 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15122 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15123 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15124 15125#undef ARM_VARIANT 15126#define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */ 15127 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld), 15128 TC3(ldrd, 00000d0, e8500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), 15129 TC3(strd, 00000f0, e8400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), 15130 15131 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15132 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15133 15134#undef ARM_VARIANT 15135#define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */ 15136 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), 15137 15138#undef ARM_VARIANT 15139#define ARM_VARIANT &arm_ext_v6 /* ARM V6. */ 15140#undef THUMB_VARIANT 15141#define THUMB_VARIANT &arm_ext_v6 15142 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), 15143 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), 15144 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), 15145 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), 15146 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), 15147 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15148 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15149 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15150 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15151 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend), 15152 15153#undef THUMB_VARIANT 15154#define THUMB_VARIANT &arm_ext_v6t2 15155 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex), 15156 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex), 15157 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15158 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15159 15160 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), 15161 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), 15162 15163/* ARM V6 not included in V7M (eg. integer SIMD). */ 15164#undef THUMB_VARIANT 15165#define THUMB_VARIANT &arm_ext_v6_notm 15166 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, t_cps), 15167 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), 15168 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), 15169 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15170 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15171 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15172 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15173 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15174 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15175 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15176 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15177 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15178 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15179 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15180 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15181 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15182 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15183 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15184 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15185 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15186 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15187 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15188 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15189 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15190 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15191 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15192 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15193 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15194 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15195 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15196 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15197 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15198 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15199 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15200 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15201 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15202 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15203 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15204 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15205 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe), 15206 UF(rfeib, 9900a00, 1, (RRw), rfe), 15207 UF(rfeda, 8100a00, 1, (RRw), rfe), 15208 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe), 15209 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe), 15210 UF(rfefa, 9900a00, 1, (RRw), rfe), 15211 UF(rfeea, 8100a00, 1, (RRw), rfe), 15212 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe), 15213 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15214 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15215 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15216 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15217 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15218 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15219 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15220 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15221 TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15222 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15223 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15224 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15225 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15226 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15227 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15228 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15229 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15230 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15231 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15232 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15233 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15234 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15235 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15236 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15237 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15238 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15239 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15240 TUF(srsia, 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), 15241 UF(srsib, 9c00500, 2, (oRRw, I31w), srs), 15242 UF(srsda, 8400500, 2, (oRRw, I31w), srs), 15243 TUF(srsdb, 9400500, e800c000, 2, (oRRw, I31w), srs, srs), 15244 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), 15245 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), 15246 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15247 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15248 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), 15249 15250#undef ARM_VARIANT 15251#define ARM_VARIANT &arm_ext_v6k 15252#undef THUMB_VARIANT 15253#define THUMB_VARIANT &arm_ext_v6k 15254 tCE(yield, 320f001, yield, 0, (), noargs, t_hint), 15255 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint), 15256 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint), 15257 tCE(sev, 320f004, sev, 0, (), noargs, t_hint), 15258 15259#undef THUMB_VARIANT 15260#define THUMB_VARIANT &arm_ext_v6_notm 15261 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd), 15262 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd), 15263 15264#undef THUMB_VARIANT 15265#define THUMB_VARIANT &arm_ext_v6t2 15266 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), 15267 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), 15268 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), 15269 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), 15270 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs), 15271 15272#undef ARM_VARIANT 15273#define ARM_VARIANT &arm_ext_v6z 15274 TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc), 15275 15276#undef ARM_VARIANT 15277#define ARM_VARIANT &arm_ext_v6t2 15278 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), 15279 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), 15280 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), 15281 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), 15282 15283 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), 15284 TCE(movw, 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), 15285 TCE(movt, 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), 15286 TCE(rbit, 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), 15287 15288 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15289 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15290 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15291 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15292 15293 UT(cbnz, b900, 2, (RR, EXP), t_cbz), 15294 UT(cbz, b100, 2, (RR, EXP), t_cbz), 15295 /* ARM does not really have an IT instruction, so always allow it. */ 15296#undef ARM_VARIANT 15297#define ARM_VARIANT &arm_ext_v1 15298 TUE(it, 0, bf08, 1, (COND), it, t_it), 15299 TUE(itt, 0, bf0c, 1, (COND), it, t_it), 15300 TUE(ite, 0, bf04, 1, (COND), it, t_it), 15301 TUE(ittt, 0, bf0e, 1, (COND), it, t_it), 15302 TUE(itet, 0, bf06, 1, (COND), it, t_it), 15303 TUE(itte, 0, bf0a, 1, (COND), it, t_it), 15304 TUE(itee, 0, bf02, 1, (COND), it, t_it), 15305 TUE(itttt, 0, bf0f, 1, (COND), it, t_it), 15306 TUE(itett, 0, bf07, 1, (COND), it, t_it), 15307 TUE(ittet, 0, bf0b, 1, (COND), it, t_it), 15308 TUE(iteet, 0, bf03, 1, (COND), it, t_it), 15309 TUE(ittte, 0, bf0d, 1, (COND), it, t_it), 15310 TUE(itete, 0, bf05, 1, (COND), it, t_it), 15311 TUE(ittee, 0, bf09, 1, (COND), it, t_it), 15312 TUE(iteee, 0, bf01, 1, (COND), it, t_it), 15313 15314 /* Thumb2 only instructions. */ 15315#undef ARM_VARIANT 15316#define ARM_VARIANT NULL 15317 15318 TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), 15319 TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), 15320 TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb), 15321 TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb), 15322 15323 /* Thumb-2 hardware division instructions (R and M profiles only). */ 15324#undef THUMB_VARIANT 15325#define THUMB_VARIANT &arm_ext_div 15326 TCE(sdiv, 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div), 15327 TCE(udiv, 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div), 15328 15329 /* ARM V7 instructions. */ 15330#undef ARM_VARIANT 15331#define ARM_VARIANT &arm_ext_v7 15332#undef THUMB_VARIANT 15333#define THUMB_VARIANT &arm_ext_v7 15334 TUF(pli, 450f000, f910f000, 1, (ADDR), pli, t_pld), 15335 TCE(dbg, 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), 15336 TUF(dmb, 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier), 15337 TUF(dsb, 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier), 15338 TUF(isb, 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier), 15339 15340#undef ARM_VARIANT 15341#define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ 15342 cCE(wfs, e200110, 1, (RR), rd), 15343 cCE(rfs, e300110, 1, (RR), rd), 15344 cCE(wfc, e400110, 1, (RR), rd), 15345 cCE(rfc, e500110, 1, (RR), rd), 15346 15347 cCL(ldfs, c100100, 2, (RF, ADDRGLDC), rd_cpaddr), 15348 cCL(ldfd, c108100, 2, (RF, ADDRGLDC), rd_cpaddr), 15349 cCL(ldfe, c500100, 2, (RF, ADDRGLDC), rd_cpaddr), 15350 cCL(ldfp, c508100, 2, (RF, ADDRGLDC), rd_cpaddr), 15351 15352 cCL(stfs, c000100, 2, (RF, ADDRGLDC), rd_cpaddr), 15353 cCL(stfd, c008100, 2, (RF, ADDRGLDC), rd_cpaddr), 15354 cCL(stfe, c400100, 2, (RF, ADDRGLDC), rd_cpaddr), 15355 cCL(stfp, c408100, 2, (RF, ADDRGLDC), rd_cpaddr), 15356 15357 cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm), 15358 cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm), 15359 cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm), 15360 cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm), 15361 cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm), 15362 cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm), 15363 cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm), 15364 cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm), 15365 cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm), 15366 cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm), 15367 cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm), 15368 cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm), 15369 15370 cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm), 15371 cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm), 15372 cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm), 15373 cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm), 15374 cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm), 15375 cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm), 15376 cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm), 15377 cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm), 15378 cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm), 15379 cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm), 15380 cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm), 15381 cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm), 15382 15383 cCL(abss, e208100, 2, (RF, RF_IF), rd_rm), 15384 cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm), 15385 cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm), 15386 cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm), 15387 cCL(absd, e208180, 2, (RF, RF_IF), rd_rm), 15388 cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm), 15389 cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm), 15390 cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm), 15391 cCL(abse, e288100, 2, (RF, RF_IF), rd_rm), 15392 cCL(absep, e288120, 2, (RF, RF_IF), rd_rm), 15393 cCL(absem, e288140, 2, (RF, RF_IF), rd_rm), 15394 cCL(absez, e288160, 2, (RF, RF_IF), rd_rm), 15395 15396 cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm), 15397 cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm), 15398 cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm), 15399 cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm), 15400 cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm), 15401 cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm), 15402 cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm), 15403 cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm), 15404 cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm), 15405 cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm), 15406 cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm), 15407 cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm), 15408 15409 cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm), 15410 cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm), 15411 cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm), 15412 cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm), 15413 cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm), 15414 cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm), 15415 cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm), 15416 cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm), 15417 cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm), 15418 cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm), 15419 cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm), 15420 cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm), 15421 15422 cCL(logs, e508100, 2, (RF, RF_IF), rd_rm), 15423 cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm), 15424 cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm), 15425 cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm), 15426 cCL(logd, e508180, 2, (RF, RF_IF), rd_rm), 15427 cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm), 15428 cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm), 15429 cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm), 15430 cCL(loge, e588100, 2, (RF, RF_IF), rd_rm), 15431 cCL(logep, e588120, 2, (RF, RF_IF), rd_rm), 15432 cCL(logem, e588140, 2, (RF, RF_IF), rd_rm), 15433 cCL(logez, e588160, 2, (RF, RF_IF), rd_rm), 15434 15435 cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm), 15436 cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm), 15437 cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm), 15438 cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm), 15439 cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm), 15440 cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm), 15441 cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm), 15442 cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm), 15443 cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm), 15444 cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm), 15445 cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm), 15446 cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm), 15447 15448 cCL(exps, e708100, 2, (RF, RF_IF), rd_rm), 15449 cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm), 15450 cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm), 15451 cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm), 15452 cCL(expd, e708180, 2, (RF, RF_IF), rd_rm), 15453 cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm), 15454 cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm), 15455 cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm), 15456 cCL(expe, e788100, 2, (RF, RF_IF), rd_rm), 15457 cCL(expep, e788120, 2, (RF, RF_IF), rd_rm), 15458 cCL(expem, e788140, 2, (RF, RF_IF), rd_rm), 15459 cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm), 15460 15461 cCL(sins, e808100, 2, (RF, RF_IF), rd_rm), 15462 cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm), 15463 cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm), 15464 cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm), 15465 cCL(sind, e808180, 2, (RF, RF_IF), rd_rm), 15466 cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm), 15467 cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm), 15468 cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm), 15469 cCL(sine, e888100, 2, (RF, RF_IF), rd_rm), 15470 cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm), 15471 cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm), 15472 cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm), 15473 15474 cCL(coss, e908100, 2, (RF, RF_IF), rd_rm), 15475 cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm), 15476 cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm), 15477 cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm), 15478 cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm), 15479 cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm), 15480 cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm), 15481 cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm), 15482 cCL(cose, e988100, 2, (RF, RF_IF), rd_rm), 15483 cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm), 15484 cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm), 15485 cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm), 15486 15487 cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm), 15488 cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm), 15489 cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm), 15490 cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm), 15491 cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm), 15492 cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm), 15493 cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm), 15494 cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm), 15495 cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm), 15496 cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm), 15497 cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm), 15498 cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm), 15499 15500 cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm), 15501 cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm), 15502 cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm), 15503 cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm), 15504 cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm), 15505 cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm), 15506 cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm), 15507 cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm), 15508 cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm), 15509 cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm), 15510 cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm), 15511 cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm), 15512 15513 cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm), 15514 cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm), 15515 cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm), 15516 cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm), 15517 cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm), 15518 cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm), 15519 cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm), 15520 cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm), 15521 cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm), 15522 cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm), 15523 cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm), 15524 cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm), 15525 15526 cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm), 15527 cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm), 15528 cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm), 15529 cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm), 15530 cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm), 15531 cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm), 15532 cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm), 15533 cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm), 15534 cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm), 15535 cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm), 15536 cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm), 15537 cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm), 15538 15539 cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm), 15540 cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm), 15541 cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm), 15542 cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm), 15543 cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm), 15544 cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm), 15545 cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm), 15546 cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm), 15547 cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm), 15548 cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm), 15549 cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm), 15550 cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm), 15551 15552 cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm), 15553 cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm), 15554 cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm), 15555 cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm), 15556 cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm), 15557 cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm), 15558 cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm), 15559 cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm), 15560 cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm), 15561 cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm), 15562 cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm), 15563 cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm), 15564 15565 cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm), 15566 cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm), 15567 cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm), 15568 cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm), 15569 cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm), 15570 cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15571 cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15572 cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15573 cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm), 15574 cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm), 15575 cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm), 15576 cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm), 15577 15578 cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm), 15579 cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm), 15580 cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm), 15581 cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm), 15582 cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm), 15583 cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15584 cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15585 cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15586 cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm), 15587 cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm), 15588 cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm), 15589 cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm), 15590 15591 cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm), 15592 cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm), 15593 cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm), 15594 cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm), 15595 cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm), 15596 cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15597 cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15598 cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15599 cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm), 15600 cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm), 15601 cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm), 15602 cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm), 15603 15604 cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm), 15605 cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm), 15606 cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm), 15607 cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm), 15608 cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm), 15609 cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15610 cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15611 cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15612 cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm), 15613 cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm), 15614 cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm), 15615 cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm), 15616 15617 cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm), 15618 cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm), 15619 cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm), 15620 cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm), 15621 cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm), 15622 cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15623 cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15624 cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15625 cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm), 15626 cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm), 15627 cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm), 15628 cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm), 15629 15630 cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm), 15631 cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm), 15632 cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm), 15633 cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm), 15634 cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm), 15635 cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15636 cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15637 cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15638 cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm), 15639 cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm), 15640 cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm), 15641 cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm), 15642 15643 cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm), 15644 cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm), 15645 cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm), 15646 cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm), 15647 cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm), 15648 cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15649 cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15650 cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15651 cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm), 15652 cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm), 15653 cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm), 15654 cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm), 15655 15656 cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm), 15657 cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm), 15658 cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm), 15659 cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm), 15660 cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm), 15661 cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15662 cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15663 cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15664 cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm), 15665 cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm), 15666 cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm), 15667 cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm), 15668 15669 cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm), 15670 cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm), 15671 cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm), 15672 cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm), 15673 cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm), 15674 cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15675 cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15676 cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15677 cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm), 15678 cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm), 15679 cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm), 15680 cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm), 15681 15682 cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm), 15683 cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm), 15684 cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm), 15685 cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm), 15686 cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm), 15687 cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15688 cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15689 cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15690 cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm), 15691 cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm), 15692 cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm), 15693 cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm), 15694 15695 cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), 15696 cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), 15697 cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), 15698 cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), 15699 cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), 15700 cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15701 cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15702 cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15703 cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), 15704 cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), 15705 cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), 15706 cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), 15707 15708 cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), 15709 cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), 15710 cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), 15711 cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), 15712 cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), 15713 cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15714 cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15715 cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15716 cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), 15717 cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), 15718 cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), 15719 cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), 15720 15721 cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), 15722 cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), 15723 cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), 15724 cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), 15725 cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), 15726 cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15727 cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15728 cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15729 cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), 15730 cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), 15731 cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), 15732 cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), 15733 15734 cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp), 15735 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp), 15736 cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp), 15737 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp), 15738 15739 cCL(flts, e000110, 2, (RF, RR), rn_rd), 15740 cCL(fltsp, e000130, 2, (RF, RR), rn_rd), 15741 cCL(fltsm, e000150, 2, (RF, RR), rn_rd), 15742 cCL(fltsz, e000170, 2, (RF, RR), rn_rd), 15743 cCL(fltd, e000190, 2, (RF, RR), rn_rd), 15744 cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd), 15745 cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd), 15746 cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd), 15747 cCL(flte, e080110, 2, (RF, RR), rn_rd), 15748 cCL(fltep, e080130, 2, (RF, RR), rn_rd), 15749 cCL(fltem, e080150, 2, (RF, RR), rn_rd), 15750 cCL(fltez, e080170, 2, (RF, RR), rn_rd), 15751 15752 /* The implementation of the FIX instruction is broken on some 15753 assemblers, in that it accepts a precision specifier as well as a 15754 rounding specifier, despite the fact that this is meaningless. 15755 To be more compatible, we accept it as well, though of course it 15756 does not set any bits. */ 15757 cCE(fix, e100110, 2, (RR, RF), rd_rm), 15758 cCL(fixp, e100130, 2, (RR, RF), rd_rm), 15759 cCL(fixm, e100150, 2, (RR, RF), rd_rm), 15760 cCL(fixz, e100170, 2, (RR, RF), rd_rm), 15761 cCL(fixsp, e100130, 2, (RR, RF), rd_rm), 15762 cCL(fixsm, e100150, 2, (RR, RF), rd_rm), 15763 cCL(fixsz, e100170, 2, (RR, RF), rd_rm), 15764 cCL(fixdp, e100130, 2, (RR, RF), rd_rm), 15765 cCL(fixdm, e100150, 2, (RR, RF), rd_rm), 15766 cCL(fixdz, e100170, 2, (RR, RF), rd_rm), 15767 cCL(fixep, e100130, 2, (RR, RF), rd_rm), 15768 cCL(fixem, e100150, 2, (RR, RF), rd_rm), 15769 cCL(fixez, e100170, 2, (RR, RF), rd_rm), 15770 15771 /* Instructions that were new with the real FPA, call them V2. */ 15772#undef ARM_VARIANT 15773#define ARM_VARIANT &fpu_fpa_ext_v2 15774 cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15775 cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15776 cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15777 cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15778 cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15779 cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15780 15781#undef ARM_VARIANT 15782#define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ 15783 /* Moves and type conversions. */ 15784 cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic), 15785 cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp), 15786 cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg), 15787 cCE(fmstat, ef1fa10, 0, (), noargs), 15788 cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), 15789 cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic), 15790 cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), 15791 cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), 15792 cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), 15793 cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), 15794 cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn), 15795 cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd), 15796 cCE(vmrs, ef00a10, 2, (APSR_RR, RVC), vfp_vmrs), 15797 cCE(vmsr, ee00a10, 2, (RVC, RR), vfp_vmsr), 15798 15799 /* Memory operations. */ 15800 cCE(flds, d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), 15801 cCE(fsts, d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), 15802 cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15803 cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15804 cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15805 cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15806 cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15807 cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15808 cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15809 cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15810 cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15811 cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15812 cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15813 cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15814 cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15815 cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15816 cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15817 cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15818 15819 /* Monadic operations. */ 15820 cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), 15821 cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic), 15822 cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), 15823 15824 /* Dyadic operations. */ 15825 cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15826 cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15827 cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15828 cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15829 cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15830 cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15831 cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15832 cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15833 cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15834 15835 /* Comparisons. */ 15836 cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic), 15837 cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z), 15838 cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), 15839 cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z), 15840 15841#undef ARM_VARIANT 15842#define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ 15843 /* Moves and type conversions. */ 15844 cCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), 15845 cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), 15846 cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 15847 cCE(fmdhr, e200b10, 2, (RVD, RR), vfp_dp_rn_rd), 15848 cCE(fmdlr, e000b10, 2, (RVD, RR), vfp_dp_rn_rd), 15849 cCE(fmrdh, e300b10, 2, (RR, RVD), vfp_dp_rd_rn), 15850 cCE(fmrdl, e100b10, 2, (RR, RVD), vfp_dp_rd_rn), 15851 cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), 15852 cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), 15853 cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), 15854 cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 15855 cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), 15856 cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 15857 15858 /* Memory operations. */ 15859 cCE(fldd, d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), 15860 cCE(fstd, d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), 15861 cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15862 cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15863 cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15864 cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15865 cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15866 cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15867 cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15868 cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15869 15870 /* Monadic operations. */ 15871 cCE(fabsd, eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 15872 cCE(fnegd, eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), 15873 cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 15874 15875 /* Dyadic operations. */ 15876 cCE(faddd, e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15877 cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15878 cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15879 cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15880 cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15881 cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15882 cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15883 cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15884 cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15885 15886 /* Comparisons. */ 15887 cCE(fcmpd, eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), 15888 cCE(fcmpzd, eb50b40, 1, (RVD), vfp_dp_rd), 15889 cCE(fcmped, eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 15890 cCE(fcmpezd, eb50bc0, 1, (RVD), vfp_dp_rd), 15891 15892#undef ARM_VARIANT 15893#define ARM_VARIANT &fpu_vfp_ext_v2 15894 cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), 15895 cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), 15896 cCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), 15897 cCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), 15898 15899/* Instructions which may belong to either the Neon or VFP instruction sets. 15900 Individual encoder functions perform additional architecture checks. */ 15901#undef ARM_VARIANT 15902#define ARM_VARIANT &fpu_vfp_ext_v1xd 15903#undef THUMB_VARIANT 15904#define THUMB_VARIANT &fpu_vfp_ext_v1xd 15905 /* These mnemonics are unique to VFP. */ 15906 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), 15907 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), 15908 nCE(vnmul, vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 15909 nCE(vnmla, vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 15910 nCE(vnmls, vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 15911 nCE(vcmp, vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), 15912 nCE(vcmpe, vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), 15913 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), 15914 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), 15915 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), 15916 15917 /* Mnemonics shared by Neon and VFP. */ 15918 nCEF(vmul, vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), 15919 nCEF(vmla, vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), 15920 nCEF(vmls, vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), 15921 15922 nCEF(vadd, vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), 15923 nCEF(vsub, vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), 15924 15925 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), 15926 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), 15927 15928 NCE(vldm, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15929 NCE(vldmia, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15930 NCE(vldmdb, d100b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15931 NCE(vstm, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15932 NCE(vstmia, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15933 NCE(vstmdb, d000b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15934 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), 15935 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), 15936 15937 nCEF(vcvt, vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt), 15938 15939 /* NOTE: All VMOV encoding is special-cased! */ 15940 NCE(vmov, 0, 1, (VMOV), neon_mov), 15941 NCE(vmovq, 0, 1, (VMOV), neon_mov), 15942 15943#undef THUMB_VARIANT 15944#define THUMB_VARIANT &fpu_neon_ext_v1 15945#undef ARM_VARIANT 15946#define ARM_VARIANT &fpu_neon_ext_v1 15947 /* Data processing with three registers of the same length. */ 15948 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ 15949 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), 15950 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), 15951 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 15952 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 15953 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 15954 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 15955 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 15956 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 15957 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ 15958 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), 15959 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), 15960 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), 15961 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), 15962 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), 15963 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), 15964 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), 15965 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), 15966 /* If not immediate, fall back to neon_dyadic_i64_su. 15967 shl_imm should accept I8 I16 I32 I64, 15968 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ 15969 nUF(vshl, vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), 15970 nUF(vshlq, vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), 15971 nUF(vqshl, vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), 15972 nUF(vqshlq, vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), 15973 /* Logic ops, types optional & ignored. */ 15974 nUF(vand, vand, 2, (RNDQ, NILO), neon_logic), 15975 nUF(vandq, vand, 2, (RNQ, NILO), neon_logic), 15976 nUF(vbic, vbic, 2, (RNDQ, NILO), neon_logic), 15977 nUF(vbicq, vbic, 2, (RNQ, NILO), neon_logic), 15978 nUF(vorr, vorr, 2, (RNDQ, NILO), neon_logic), 15979 nUF(vorrq, vorr, 2, (RNQ, NILO), neon_logic), 15980 nUF(vorn, vorn, 2, (RNDQ, NILO), neon_logic), 15981 nUF(vornq, vorn, 2, (RNQ, NILO), neon_logic), 15982 nUF(veor, veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), 15983 nUF(veorq, veor, 3, (RNQ, oRNQ, RNQ), neon_logic), 15984 /* Bitfield ops, untyped. */ 15985 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 15986 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 15987 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 15988 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 15989 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 15990 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 15991 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ 15992 nUF(vabd, vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 15993 nUF(vabdq, vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 15994 nUF(vmax, vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 15995 nUF(vmaxq, vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 15996 nUF(vmin, vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 15997 nUF(vminq, vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 15998 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall 15999 back to neon_dyadic_if_su. */ 16000 nUF(vcge, vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), 16001 nUF(vcgeq, vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), 16002 nUF(vcgt, vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), 16003 nUF(vcgtq, vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), 16004 nUF(vclt, vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), 16005 nUF(vcltq, vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), 16006 nUF(vcle, vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), 16007 nUF(vcleq, vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), 16008 /* Comparison. Type I8 I16 I32 F32. */ 16009 nUF(vceq, vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), 16010 nUF(vceqq, vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), 16011 /* As above, D registers only. */ 16012 nUF(vpmax, vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), 16013 nUF(vpmin, vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), 16014 /* Int and float variants, signedness unimportant. */ 16015 nUF(vmlaq, vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), 16016 nUF(vmlsq, vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), 16017 nUF(vpadd, vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), 16018 /* Add/sub take types I8 I16 I32 I64 F32. */ 16019 nUF(vaddq, vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), 16020 nUF(vsubq, vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), 16021 /* vtst takes sizes 8, 16, 32. */ 16022 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), 16023 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), 16024 /* VMUL takes I8 I16 I32 F32 P8. */ 16025 nUF(vmulq, vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), 16026 /* VQD{R}MULH takes S16 S32. */ 16027 nUF(vqdmulh, vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), 16028 nUF(vqdmulhq, vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), 16029 nUF(vqrdmulh, vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), 16030 nUF(vqrdmulhq, vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), 16031 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), 16032 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), 16033 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), 16034 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), 16035 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), 16036 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), 16037 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), 16038 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), 16039 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), 16040 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), 16041 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), 16042 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), 16043 16044 /* Two address, int/float. Types S8 S16 S32 F32. */ 16045 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), 16046 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), 16047 16048 /* Data processing with two registers and a shift amount. */ 16049 /* Right shifts, and variants with rounding. 16050 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ 16051 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), 16052 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), 16053 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), 16054 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), 16055 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), 16056 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), 16057 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), 16058 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), 16059 /* Shift and insert. Sizes accepted 8 16 32 64. */ 16060 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), 16061 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), 16062 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), 16063 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), 16064 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ 16065 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), 16066 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), 16067 /* Right shift immediate, saturating & narrowing, with rounding variants. 16068 Types accepted S16 S32 S64 U16 U32 U64. */ 16069 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), 16070 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), 16071 /* As above, unsigned. Types accepted S16 S32 S64. */ 16072 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), 16073 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), 16074 /* Right shift narrowing. Types accepted I16 I32 I64. */ 16075 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), 16076 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), 16077 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ 16078 nUF(vshll, vshll, 3, (RNQ, RND, I32), neon_shll), 16079 /* CVT with optional immediate for fixed-point variant. */ 16080 nUF(vcvtq, vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), 16081 16082 nUF(vmvn, vmvn, 2, (RNDQ, RNDQ_IMVNb), neon_mvn), 16083 nUF(vmvnq, vmvn, 2, (RNQ, RNDQ_IMVNb), neon_mvn), 16084 16085 /* Data processing, three registers of different lengths. */ 16086 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ 16087 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), 16088 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), 16089 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), 16090 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), 16091 /* If not scalar, fall back to neon_dyadic_long. 16092 Vector types as above, scalar types S16 S32 U16 U32. */ 16093 nUF(vmlal, vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), 16094 nUF(vmlsl, vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), 16095 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ 16096 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), 16097 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), 16098 /* Dyadic, narrowing insns. Types I16 I32 I64. */ 16099 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16100 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16101 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16102 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16103 /* Saturating doubling multiplies. Types S16 S32. */ 16104 nUF(vqdmlal, vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 16105 nUF(vqdmlsl, vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 16106 nUF(vqdmull, vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 16107 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types 16108 S16 S32 U16 U32. */ 16109 nUF(vmull, vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), 16110 16111 /* Extract. Size 8. */ 16112 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), 16113 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), 16114 16115 /* Two registers, miscellaneous. */ 16116 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ 16117 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), 16118 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), 16119 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), 16120 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), 16121 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), 16122 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), 16123 /* Vector replicate. Sizes 8 16 32. */ 16124 nCE(vdup, vdup, 2, (RNDQ, RR_RNSC), neon_dup), 16125 nCE(vdupq, vdup, 2, (RNQ, RR_RNSC), neon_dup), 16126 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ 16127 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), 16128 /* VMOVN. Types I16 I32 I64. */ 16129 nUF(vmovn, vmovn, 2, (RND, RNQ), neon_movn), 16130 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ 16131 nUF(vqmovn, vqmovn, 2, (RND, RNQ), neon_qmovn), 16132 /* VQMOVUN. Types S16 S32 S64. */ 16133 nUF(vqmovun, vqmovun, 2, (RND, RNQ), neon_qmovun), 16134 /* VZIP / VUZP. Sizes 8 16 32. */ 16135 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), 16136 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), 16137 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), 16138 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), 16139 /* VQABS / VQNEG. Types S8 S16 S32. */ 16140 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), 16141 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), 16142 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), 16143 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), 16144 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ 16145 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), 16146 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), 16147 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), 16148 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), 16149 /* Reciprocal estimates. Types U32 F32. */ 16150 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), 16151 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), 16152 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), 16153 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), 16154 /* VCLS. Types S8 S16 S32. */ 16155 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), 16156 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), 16157 /* VCLZ. Types I8 I16 I32. */ 16158 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), 16159 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), 16160 /* VCNT. Size 8. */ 16161 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), 16162 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), 16163 /* Two address, untyped. */ 16164 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), 16165 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), 16166 /* VTRN. Sizes 8 16 32. */ 16167 nUF(vtrn, vtrn, 2, (RNDQ, RNDQ), neon_trn), 16168 nUF(vtrnq, vtrn, 2, (RNQ, RNQ), neon_trn), 16169 16170 /* Table lookup. Size 8. */ 16171 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), 16172 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), 16173 16174#undef THUMB_VARIANT 16175#define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext 16176#undef ARM_VARIANT 16177#define ARM_VARIANT &fpu_vfp_v3_or_neon_ext 16178 /* Neon element/structure load/store. */ 16179 nUF(vld1, vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), 16180 nUF(vst1, vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), 16181 nUF(vld2, vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), 16182 nUF(vst2, vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), 16183 nUF(vld3, vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), 16184 nUF(vst3, vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), 16185 nUF(vld4, vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), 16186 nUF(vst4, vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), 16187 16188#undef THUMB_VARIANT 16189#define THUMB_VARIANT &fpu_vfp_ext_v3 16190#undef ARM_VARIANT 16191#define ARM_VARIANT &fpu_vfp_ext_v3 16192 cCE(fconsts, eb00a00, 2, (RVS, I255), vfp_sp_const), 16193 cCE(fconstd, eb00b00, 2, (RVD, I255), vfp_dp_const), 16194 cCE(fshtos, eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16195 cCE(fshtod, eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16196 cCE(fsltos, eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16197 cCE(fsltod, eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16198 cCE(fuhtos, ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16199 cCE(fuhtod, ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16200 cCE(fultos, ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16201 cCE(fultod, ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16202 cCE(ftoshs, ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16203 cCE(ftoshd, ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16204 cCE(ftosls, ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16205 cCE(ftosld, ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16206 cCE(ftouhs, ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16207 cCE(ftouhd, ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16208 cCE(ftouls, ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16209 cCE(ftould, ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16210 16211#undef THUMB_VARIANT 16212#undef ARM_VARIANT 16213#define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */ 16214 cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16215 cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16216 cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16217 cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16218 cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16219 cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16220 cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), 16221 cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), 16222 16223#undef ARM_VARIANT 16224#define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */ 16225 cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc), 16226 cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc), 16227 cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc), 16228 cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd), 16229 cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd), 16230 cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd), 16231 cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc), 16232 cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc), 16233 cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc), 16234 cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), 16235 cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), 16236 cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), 16237 cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), 16238 cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), 16239 cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), 16240 cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), 16241 cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), 16242 cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), 16243 cCE(tmcr, e000110, 2, (RIWC_RIWG, RR), rn_rd), 16244 cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn), 16245 cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16246 cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16247 cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16248 cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16249 cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16250 cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16251 cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn), 16252 cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn), 16253 cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn), 16254 cCE(tmrc, e100110, 2, (RR, RIWC_RIWG), rd_rn), 16255 cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm), 16256 cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc), 16257 cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc), 16258 cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc), 16259 cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn), 16260 cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn), 16261 cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn), 16262 cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16263 cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16264 cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16265 cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16266 cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16267 cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16268 cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16269 cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16270 cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16271 cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), 16272 cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16273 cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16274 cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16275 cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16276 cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16277 cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16278 cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16279 cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16280 cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16281 cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16282 cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16283 cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16284 cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16285 cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16286 cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16287 cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16288 cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16289 cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16290 cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16291 cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16292 cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16293 cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), 16294 cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), 16295 cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16296 cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16297 cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16298 cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16299 cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16300 cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16301 cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16302 cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16303 cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16304 cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16305 cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16306 cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16307 cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16308 cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16309 cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16310 cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16311 cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16312 cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16313 cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov), 16314 cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16315 cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16316 cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16317 cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16318 cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16319 cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16320 cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16321 cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16322 cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16323 cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16324 cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16325 cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16326 cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16327 cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16328 cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16329 cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16330 cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16331 cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16332 cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16333 cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16334 cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16335 cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), 16336 cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16337 cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16338 cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16339 cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16340 cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16341 cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16342 cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16343 cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16344 cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16345 cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16346 cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16347 cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16348 cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16349 cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16350 cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16351 cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16352 cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16353 cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16354 cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16355 cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16356 cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), 16357 cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), 16358 cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16359 cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16360 cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16361 cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16362 cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16363 cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16364 cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16365 cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16366 cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16367 cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn), 16368 cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn), 16369 cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn), 16370 cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn), 16371 cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn), 16372 cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn), 16373 cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16374 cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16375 cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16376 cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn), 16377 cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn), 16378 cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn), 16379 cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn), 16380 cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn), 16381 cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn), 16382 cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16383 cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16384 cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16385 cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16386 cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero), 16387 16388#undef ARM_VARIANT 16389#define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ 16390 cCE(torvscb, e13f190, 1, (RR), iwmmxt_tandorc), 16391 cCE(torvsch, e53f190, 1, (RR), iwmmxt_tandorc), 16392 cCE(torvscw, e93f190, 1, (RR), iwmmxt_tandorc), 16393 cCE(wabsb, e2001c0, 2, (RIWR, RIWR), rd_rn), 16394 cCE(wabsh, e6001c0, 2, (RIWR, RIWR), rd_rn), 16395 cCE(wabsw, ea001c0, 2, (RIWR, RIWR), rd_rn), 16396 cCE(wabsdiffb, e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16397 cCE(wabsdiffh, e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16398 cCE(wabsdiffw, e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16399 cCE(waddbhusl, e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16400 cCE(waddbhusm, e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16401 cCE(waddhc, e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16402 cCE(waddwc, ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16403 cCE(waddsubhx, ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16404 cCE(wavg4, e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16405 cCE(wavg4r, e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16406 cCE(wmaddsn, ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16407 cCE(wmaddsx, eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16408 cCE(wmaddun, ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16409 cCE(wmaddux, e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16410 cCE(wmerge, e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), 16411 cCE(wmiabb, e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16412 cCE(wmiabt, e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16413 cCE(wmiatb, e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16414 cCE(wmiatt, e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16415 cCE(wmiabbn, e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16416 cCE(wmiabtn, e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16417 cCE(wmiatbn, e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16418 cCE(wmiattn, e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16419 cCE(wmiawbb, e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16420 cCE(wmiawbt, e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16421 cCE(wmiawtb, ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16422 cCE(wmiawtt, eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16423 cCE(wmiawbbn, ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16424 cCE(wmiawbtn, ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16425 cCE(wmiawtbn, ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16426 cCE(wmiawttn, ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16427 cCE(wmulsmr, ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16428 cCE(wmulumr, ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16429 cCE(wmulwumr, ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16430 cCE(wmulwsmr, ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16431 cCE(wmulwum, ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16432 cCE(wmulwsm, ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16433 cCE(wmulwl, eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16434 cCE(wqmiabb, e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16435 cCE(wqmiabt, e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16436 cCE(wqmiatb, ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16437 cCE(wqmiatt, eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16438 cCE(wqmiabbn, ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16439 cCE(wqmiabtn, ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16440 cCE(wqmiatbn, ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16441 cCE(wqmiattn, ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16442 cCE(wqmulm, e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16443 cCE(wqmulmr, e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16444 cCE(wqmulwm, ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16445 cCE(wqmulwmr, ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16446 cCE(wsubaddhx, ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16447 16448#undef ARM_VARIANT 16449#define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */ 16450 cCE(cfldrs, c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), 16451 cCE(cfldrd, c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), 16452 cCE(cfldr32, c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), 16453 cCE(cfldr64, c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), 16454 cCE(cfstrs, c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), 16455 cCE(cfstrd, c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), 16456 cCE(cfstr32, c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), 16457 cCE(cfstr64, c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), 16458 cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd), 16459 cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn), 16460 cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd), 16461 cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn), 16462 cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd), 16463 cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn), 16464 cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd), 16465 cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn), 16466 cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd), 16467 cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn), 16468 cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn), 16469 cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn), 16470 cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn), 16471 cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn), 16472 cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn), 16473 cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn), 16474 cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn), 16475 cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn), 16476 cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn), 16477 cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn), 16478 cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc), 16479 cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd), 16480 cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn), 16481 cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn), 16482 cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn), 16483 cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn), 16484 cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn), 16485 cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn), 16486 cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn), 16487 cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn), 16488 cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn), 16489 cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn), 16490 cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn), 16491 cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn), 16492 cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple), 16493 cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple), 16494 cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift), 16495 cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift), 16496 cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm), 16497 cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), 16498 cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), 16499 cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), 16500 cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn), 16501 cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn), 16502 cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn), 16503 cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn), 16504 cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm), 16505 cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), 16506 cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), 16507 cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), 16508 cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm), 16509 cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm), 16510 cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn), 16511 cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn), 16512 cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn), 16513 cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn), 16514 cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16515 cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 16516 cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16517 cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 16518 cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16519 cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 16520 cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16521 cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16522 cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), 16523 cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), 16524 cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), 16525 cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), 16526}; 16527#undef ARM_VARIANT 16528#undef THUMB_VARIANT 16529#undef TCE 16530#undef TCM 16531#undef TUE 16532#undef TUF 16533#undef TCC 16534#undef cCE 16535#undef cCL 16536#undef C3E 16537#undef CE 16538#undef CM 16539#undef UE 16540#undef UF 16541#undef UT 16542#undef NUF 16543#undef nUF 16544#undef NCE 16545#undef nCE 16546#undef OPS0 16547#undef OPS1 16548#undef OPS2 16549#undef OPS3 16550#undef OPS4 16551#undef OPS5 16552#undef OPS6 16553#undef do_0 16554 16555/* MD interface: bits in the object file. */ 16556 16557/* Turn an integer of n bytes (in val) into a stream of bytes appropriate 16558 for use in the a.out file, and stores them in the array pointed to by buf. 16559 This knows about the endian-ness of the target machine and does 16560 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) 16561 2 (short) and 4 (long) Floating numbers are put out as a series of 16562 LITTLENUMS (shorts, here at least). */ 16563 16564void 16565md_number_to_chars (char * buf, valueT val, int n) 16566{ 16567 if (target_big_endian) 16568 number_to_chars_bigendian (buf, val, n); 16569 else 16570 number_to_chars_littleendian (buf, val, n); 16571} 16572 16573static valueT 16574md_chars_to_number (char * buf, int n) 16575{ 16576 valueT result = 0; 16577 unsigned char * where = (unsigned char *) buf; 16578 16579 if (target_big_endian) 16580 { 16581 while (n--) 16582 { 16583 result <<= 8; 16584 result |= (*where++ & 255); 16585 } 16586 } 16587 else 16588 { 16589 while (n--) 16590 { 16591 result <<= 8; 16592 result |= (where[n] & 255); 16593 } 16594 } 16595 16596 return result; 16597} 16598 16599/* MD interface: Sections. */ 16600 16601/* Estimate the size of a frag before relaxing. Assume everything fits in 16602 2 bytes. */ 16603 16604int 16605md_estimate_size_before_relax (fragS * fragp, 16606 segT segtype ATTRIBUTE_UNUSED) 16607{ 16608 fragp->fr_var = 2; 16609 return 2; 16610} 16611 16612/* Convert a machine dependent frag. */ 16613 16614void 16615md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) 16616{ 16617 unsigned long insn; 16618 unsigned long old_op; 16619 char *buf; 16620 expressionS exp; 16621 fixS *fixp; 16622 int reloc_type; 16623 int pc_rel; 16624 int opcode; 16625 16626 buf = fragp->fr_literal + fragp->fr_fix; 16627 16628 old_op = bfd_get_16(abfd, buf); 16629 if (fragp->fr_symbol) { 16630 exp.X_op = O_symbol; 16631 exp.X_add_symbol = fragp->fr_symbol; 16632 } else { 16633 exp.X_op = O_constant; 16634 } 16635 exp.X_add_number = fragp->fr_offset; 16636 opcode = fragp->fr_subtype; 16637 switch (opcode) 16638 { 16639 case T_MNEM_ldr_pc: 16640 case T_MNEM_ldr_pc2: 16641 case T_MNEM_ldr_sp: 16642 case T_MNEM_str_sp: 16643 case T_MNEM_ldr: 16644 case T_MNEM_ldrb: 16645 case T_MNEM_ldrh: 16646 case T_MNEM_str: 16647 case T_MNEM_strb: 16648 case T_MNEM_strh: 16649 if (fragp->fr_var == 4) 16650 { 16651 insn = THUMB_OP32(opcode); 16652 if ((old_op >> 12) == 4 || (old_op >> 12) == 9) 16653 { 16654 insn |= (old_op & 0x700) << 4; 16655 } 16656 else 16657 { 16658 insn |= (old_op & 7) << 12; 16659 insn |= (old_op & 0x38) << 13; 16660 } 16661 insn |= 0x00000c00; 16662 put_thumb32_insn (buf, insn); 16663 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; 16664 } 16665 else 16666 { 16667 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; 16668 } 16669 pc_rel = (opcode == T_MNEM_ldr_pc2); 16670 break; 16671 case T_MNEM_adr: 16672 if (fragp->fr_var == 4) 16673 { 16674 insn = THUMB_OP32 (opcode); 16675 insn |= (old_op & 0xf0) << 4; 16676 put_thumb32_insn (buf, insn); 16677 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; 16678 } 16679 else 16680 { 16681 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 16682 exp.X_add_number -= 4; 16683 } 16684 pc_rel = 1; 16685 break; 16686 case T_MNEM_mov: 16687 case T_MNEM_movs: 16688 case T_MNEM_cmp: 16689 case T_MNEM_cmn: 16690 if (fragp->fr_var == 4) 16691 { 16692 int r0off = (opcode == T_MNEM_mov 16693 || opcode == T_MNEM_movs) ? 0 : 8; 16694 insn = THUMB_OP32 (opcode); 16695 insn = (insn & 0xe1ffffff) | 0x10000000; 16696 insn |= (old_op & 0x700) << r0off; 16697 put_thumb32_insn (buf, insn); 16698 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; 16699 } 16700 else 16701 { 16702 reloc_type = BFD_RELOC_ARM_THUMB_IMM; 16703 } 16704 pc_rel = 0; 16705 break; 16706 case T_MNEM_b: 16707 if (fragp->fr_var == 4) 16708 { 16709 insn = THUMB_OP32(opcode); 16710 put_thumb32_insn (buf, insn); 16711 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; 16712 } 16713 else 16714 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; 16715 pc_rel = 1; 16716 break; 16717 case T_MNEM_bcond: 16718 if (fragp->fr_var == 4) 16719 { 16720 insn = THUMB_OP32(opcode); 16721 insn |= (old_op & 0xf00) << 14; 16722 put_thumb32_insn (buf, insn); 16723 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; 16724 } 16725 else 16726 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; 16727 pc_rel = 1; 16728 break; 16729 case T_MNEM_add_sp: 16730 case T_MNEM_add_pc: 16731 case T_MNEM_inc_sp: 16732 case T_MNEM_dec_sp: 16733 if (fragp->fr_var == 4) 16734 { 16735 /* ??? Choose between add and addw. */ 16736 insn = THUMB_OP32 (opcode); 16737 insn |= (old_op & 0xf0) << 4; 16738 put_thumb32_insn (buf, insn); 16739 if (opcode == T_MNEM_add_pc) 16740 reloc_type = BFD_RELOC_ARM_T32_IMM12; 16741 else 16742 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; 16743 } 16744 else 16745 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 16746 pc_rel = 0; 16747 break; 16748 16749 case T_MNEM_addi: 16750 case T_MNEM_addis: 16751 case T_MNEM_subi: 16752 case T_MNEM_subis: 16753 if (fragp->fr_var == 4) 16754 { 16755 insn = THUMB_OP32 (opcode); 16756 insn |= (old_op & 0xf0) << 4; 16757 insn |= (old_op & 0xf) << 16; 16758 put_thumb32_insn (buf, insn); 16759 if (insn & (1 << 20)) 16760 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; 16761 else 16762 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; 16763 } 16764 else 16765 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 16766 pc_rel = 0; 16767 break; 16768 default: 16769 abort(); 16770 } 16771 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, 16772 reloc_type); 16773 fixp->fx_file = fragp->fr_file; 16774 fixp->fx_line = fragp->fr_line; 16775 fragp->fr_fix += fragp->fr_var; 16776} 16777 16778/* Return the size of a relaxable immediate operand instruction. 16779 SHIFT and SIZE specify the form of the allowable immediate. */ 16780static int 16781relax_immediate (fragS *fragp, int size, int shift) 16782{ 16783 offsetT offset; 16784 offsetT mask; 16785 offsetT low; 16786 16787 /* ??? Should be able to do better than this. */ 16788 if (fragp->fr_symbol) 16789 return 4; 16790 16791 low = (1 << shift) - 1; 16792 mask = (1 << (shift + size)) - (1 << shift); 16793 offset = fragp->fr_offset; 16794 /* Force misaligned offsets to 32-bit variant. */ 16795 if (offset & low) 16796 return 4; 16797 if (offset & ~mask) 16798 return 4; 16799 return 2; 16800} 16801 16802/* Get the address of a symbol during relaxation. */ 16803static addressT 16804relaxed_symbol_addr(fragS *fragp, long stretch) 16805{ 16806 fragS *sym_frag; 16807 addressT addr; 16808 symbolS *sym; 16809 16810 sym = fragp->fr_symbol; 16811 sym_frag = symbol_get_frag (sym); 16812 know (S_GET_SEGMENT (sym) != absolute_section 16813 || sym_frag == &zero_address_frag); 16814 addr = S_GET_VALUE (sym) + fragp->fr_offset; 16815 16816 /* If frag has yet to be reached on this pass, assume it will 16817 move by STRETCH just as we did. If this is not so, it will 16818 be because some frag between grows, and that will force 16819 another pass. */ 16820 16821 if (stretch != 0 16822 && sym_frag->relax_marker != fragp->relax_marker) 16823 addr += stretch; 16824 16825 return addr; 16826} 16827 16828/* Return the size of a relaxable adr pseudo-instruction or PC-relative 16829 load. */ 16830static int 16831relax_adr (fragS *fragp, asection *sec, long stretch) 16832{ 16833 addressT addr; 16834 offsetT val; 16835 16836 /* Assume worst case for symbols not known to be in the same section. */ 16837 if (!S_IS_DEFINED(fragp->fr_symbol) 16838 || sec != S_GET_SEGMENT (fragp->fr_symbol)) 16839 return 4; 16840 16841 val = relaxed_symbol_addr(fragp, stretch); 16842 addr = fragp->fr_address + fragp->fr_fix; 16843 addr = (addr + 4) & ~3; 16844 /* Force misaligned targets to 32-bit variant. */ 16845 if (val & 3) 16846 return 4; 16847 val -= addr; 16848 if (val < 0 || val > 1020) 16849 return 4; 16850 return 2; 16851} 16852 16853/* Return the size of a relaxable add/sub immediate instruction. */ 16854static int 16855relax_addsub (fragS *fragp, asection *sec) 16856{ 16857 char *buf; 16858 int op; 16859 16860 buf = fragp->fr_literal + fragp->fr_fix; 16861 op = bfd_get_16(sec->owner, buf); 16862 if ((op & 0xf) == ((op >> 4) & 0xf)) 16863 return relax_immediate (fragp, 8, 0); 16864 else 16865 return relax_immediate (fragp, 3, 0); 16866} 16867 16868 16869/* Return the size of a relaxable branch instruction. BITS is the 16870 size of the offset field in the narrow instruction. */ 16871 16872static int 16873relax_branch (fragS *fragp, asection *sec, int bits, long stretch) 16874{ 16875 addressT addr; 16876 offsetT val; 16877 offsetT limit; 16878 16879 /* Assume worst case for symbols not known to be in the same section. */ 16880 if (!S_IS_DEFINED(fragp->fr_symbol) 16881 || sec != S_GET_SEGMENT (fragp->fr_symbol)) 16882 return 4; 16883 16884 val = relaxed_symbol_addr(fragp, stretch); 16885 addr = fragp->fr_address + fragp->fr_fix + 4; 16886 val -= addr; 16887 16888 /* Offset is a signed value *2 */ 16889 limit = 1 << bits; 16890 if (val >= limit || val < -limit) 16891 return 4; 16892 return 2; 16893} 16894 16895 16896/* Relax a machine dependent frag. This returns the amount by which 16897 the current size of the frag should change. */ 16898 16899int 16900arm_relax_frag (asection *sec, fragS *fragp, long stretch) 16901{ 16902 int oldsize; 16903 int newsize; 16904 16905 oldsize = fragp->fr_var; 16906 switch (fragp->fr_subtype) 16907 { 16908 case T_MNEM_ldr_pc2: 16909 newsize = relax_adr(fragp, sec, stretch); 16910 break; 16911 case T_MNEM_ldr_pc: 16912 case T_MNEM_ldr_sp: 16913 case T_MNEM_str_sp: 16914 newsize = relax_immediate(fragp, 8, 2); 16915 break; 16916 case T_MNEM_ldr: 16917 case T_MNEM_str: 16918 newsize = relax_immediate(fragp, 5, 2); 16919 break; 16920 case T_MNEM_ldrh: 16921 case T_MNEM_strh: 16922 newsize = relax_immediate(fragp, 5, 1); 16923 break; 16924 case T_MNEM_ldrb: 16925 case T_MNEM_strb: 16926 newsize = relax_immediate(fragp, 5, 0); 16927 break; 16928 case T_MNEM_adr: 16929 newsize = relax_adr(fragp, sec, stretch); 16930 break; 16931 case T_MNEM_mov: 16932 case T_MNEM_movs: 16933 case T_MNEM_cmp: 16934 case T_MNEM_cmn: 16935 newsize = relax_immediate(fragp, 8, 0); 16936 break; 16937 case T_MNEM_b: 16938 newsize = relax_branch(fragp, sec, 11, stretch); 16939 break; 16940 case T_MNEM_bcond: 16941 newsize = relax_branch(fragp, sec, 8, stretch); 16942 break; 16943 case T_MNEM_add_sp: 16944 case T_MNEM_add_pc: 16945 newsize = relax_immediate (fragp, 8, 2); 16946 break; 16947 case T_MNEM_inc_sp: 16948 case T_MNEM_dec_sp: 16949 newsize = relax_immediate (fragp, 7, 2); 16950 break; 16951 case T_MNEM_addi: 16952 case T_MNEM_addis: 16953 case T_MNEM_subi: 16954 case T_MNEM_subis: 16955 newsize = relax_addsub (fragp, sec); 16956 break; 16957 default: 16958 abort(); 16959 } 16960 16961 fragp->fr_var = newsize; 16962 /* Freeze wide instructions that are at or before the same location as 16963 in the previous pass. This avoids infinite loops. 16964 Don't freeze them unconditionally because targets may be artificialy 16965 misaligned by the expansion of preceeding frags. */ 16966 if (stretch <= 0 && newsize > 2) 16967 { 16968 md_convert_frag (sec->owner, sec, fragp); 16969 frag_wane(fragp); 16970 } 16971 16972 return newsize - oldsize; 16973} 16974 16975/* Round up a section size to the appropriate boundary. */ 16976 16977valueT 16978md_section_align (segT segment ATTRIBUTE_UNUSED, 16979 valueT size) 16980{ 16981#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 16982 if (OUTPUT_FLAVOR == bfd_target_aout_flavour) 16983 { 16984 /* For a.out, force the section size to be aligned. If we don't do 16985 this, BFD will align it for us, but it will not write out the 16986 final bytes of the section. This may be a bug in BFD, but it is 16987 easier to fix it here since that is how the other a.out targets 16988 work. */ 16989 int align; 16990 16991 align = bfd_get_section_alignment (stdoutput, segment); 16992 size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); 16993 } 16994#endif 16995 16996 return size; 16997} 16998 16999/* This is called from HANDLE_ALIGN in write.c. Fill in the contents 17000 of an rs_align_code fragment. */ 17001 17002void 17003arm_handle_align (fragS * fragP) 17004{ 17005 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 }; 17006 static char const thumb_noop[2] = { 0xc0, 0x46 }; 17007 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 }; 17008 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 }; 17009 17010 int bytes, fix, noop_size; 17011 char * p; 17012 const char * noop; 17013 17014 if (fragP->fr_type != rs_align_code) 17015 return; 17016 17017 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; 17018 p = fragP->fr_literal + fragP->fr_fix; 17019 fix = 0; 17020 17021 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) 17022 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; 17023 17024 if (fragP->tc_frag_data) 17025 { 17026 if (target_big_endian) 17027 noop = thumb_bigend_noop; 17028 else 17029 noop = thumb_noop; 17030 noop_size = sizeof (thumb_noop); 17031 } 17032 else 17033 { 17034 if (target_big_endian) 17035 noop = arm_bigend_noop; 17036 else 17037 noop = arm_noop; 17038 noop_size = sizeof (arm_noop); 17039 } 17040 17041 if (bytes & (noop_size - 1)) 17042 { 17043 fix = bytes & (noop_size - 1); 17044 memset (p, 0, fix); 17045 p += fix; 17046 bytes -= fix; 17047 } 17048 17049 while (bytes >= noop_size) 17050 { 17051 memcpy (p, noop, noop_size); 17052 p += noop_size; 17053 bytes -= noop_size; 17054 fix += noop_size; 17055 } 17056 17057 fragP->fr_fix += fix; 17058 fragP->fr_var = noop_size; 17059} 17060 17061/* Called from md_do_align. Used to create an alignment 17062 frag in a code section. */ 17063 17064void 17065arm_frag_align_code (int n, int max) 17066{ 17067 char * p; 17068 17069 /* We assume that there will never be a requirement 17070 to support alignments greater than 32 bytes. */ 17071 if (max > MAX_MEM_FOR_RS_ALIGN_CODE) 17072 as_fatal (_("alignments greater than 32 bytes not supported in .text sections.")); 17073 17074 p = frag_var (rs_align_code, 17075 MAX_MEM_FOR_RS_ALIGN_CODE, 17076 1, 17077 (relax_substateT) max, 17078 (symbolS *) NULL, 17079 (offsetT) n, 17080 (char *) NULL); 17081 *p = 0; 17082} 17083 17084/* Perform target specific initialisation of a frag. */ 17085 17086void 17087arm_init_frag (fragS * fragP) 17088{ 17089 /* Record whether this frag is in an ARM or a THUMB area. */ 17090 fragP->tc_frag_data = thumb_mode; 17091} 17092 17093#ifdef OBJ_ELF 17094/* When we change sections we need to issue a new mapping symbol. */ 17095 17096void 17097arm_elf_change_section (void) 17098{ 17099 flagword flags; 17100 segment_info_type *seginfo; 17101 17102 /* Link an unlinked unwind index table section to the .text section. */ 17103 if (elf_section_type (now_seg) == SHT_ARM_EXIDX 17104 && elf_linked_to_section (now_seg) == NULL) 17105 elf_linked_to_section (now_seg) = text_section; 17106 17107 if (!SEG_NORMAL (now_seg)) 17108 return; 17109 17110 flags = bfd_get_section_flags (stdoutput, now_seg); 17111 17112 /* We can ignore sections that only contain debug info. */ 17113 if ((flags & SEC_ALLOC) == 0) 17114 return; 17115 17116 seginfo = seg_info (now_seg); 17117 mapstate = seginfo->tc_segment_info_data.mapstate; 17118 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency; 17119} 17120 17121int 17122arm_elf_section_type (const char * str, size_t len) 17123{ 17124 if (len == 5 && strncmp (str, "exidx", 5) == 0) 17125 return SHT_ARM_EXIDX; 17126 17127 return -1; 17128} 17129 17130/* Code to deal with unwinding tables. */ 17131 17132static void add_unwind_adjustsp (offsetT); 17133 17134/* Cenerate and deferred unwind frame offset. */ 17135 17136static void 17137flush_pending_unwind (void) 17138{ 17139 offsetT offset; 17140 17141 offset = unwind.pending_offset; 17142 unwind.pending_offset = 0; 17143 if (offset != 0) 17144 add_unwind_adjustsp (offset); 17145} 17146 17147/* Add an opcode to this list for this function. Two-byte opcodes should 17148 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse 17149 order. */ 17150 17151static void 17152add_unwind_opcode (valueT op, int length) 17153{ 17154 /* Add any deferred stack adjustment. */ 17155 if (unwind.pending_offset) 17156 flush_pending_unwind (); 17157 17158 unwind.sp_restored = 0; 17159 17160 if (unwind.opcode_count + length > unwind.opcode_alloc) 17161 { 17162 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; 17163 if (unwind.opcodes) 17164 unwind.opcodes = xrealloc (unwind.opcodes, 17165 unwind.opcode_alloc); 17166 else 17167 unwind.opcodes = xmalloc (unwind.opcode_alloc); 17168 } 17169 while (length > 0) 17170 { 17171 length--; 17172 unwind.opcodes[unwind.opcode_count] = op & 0xff; 17173 op >>= 8; 17174 unwind.opcode_count++; 17175 } 17176} 17177 17178/* Add unwind opcodes to adjust the stack pointer. */ 17179 17180static void 17181add_unwind_adjustsp (offsetT offset) 17182{ 17183 valueT op; 17184 17185 if (offset > 0x200) 17186 { 17187 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ 17188 char bytes[5]; 17189 int n; 17190 valueT o; 17191 17192 /* Long form: 0xb2, uleb128. */ 17193 /* This might not fit in a word so add the individual bytes, 17194 remembering the list is built in reverse order. */ 17195 o = (valueT) ((offset - 0x204) >> 2); 17196 if (o == 0) 17197 add_unwind_opcode (0, 1); 17198 17199 /* Calculate the uleb128 encoding of the offset. */ 17200 n = 0; 17201 while (o) 17202 { 17203 bytes[n] = o & 0x7f; 17204 o >>= 7; 17205 if (o) 17206 bytes[n] |= 0x80; 17207 n++; 17208 } 17209 /* Add the insn. */ 17210 for (; n; n--) 17211 add_unwind_opcode (bytes[n - 1], 1); 17212 add_unwind_opcode (0xb2, 1); 17213 } 17214 else if (offset > 0x100) 17215 { 17216 /* Two short opcodes. */ 17217 add_unwind_opcode (0x3f, 1); 17218 op = (offset - 0x104) >> 2; 17219 add_unwind_opcode (op, 1); 17220 } 17221 else if (offset > 0) 17222 { 17223 /* Short opcode. */ 17224 op = (offset - 4) >> 2; 17225 add_unwind_opcode (op, 1); 17226 } 17227 else if (offset < 0) 17228 { 17229 offset = -offset; 17230 while (offset > 0x100) 17231 { 17232 add_unwind_opcode (0x7f, 1); 17233 offset -= 0x100; 17234 } 17235 op = ((offset - 4) >> 2) | 0x40; 17236 add_unwind_opcode (op, 1); 17237 } 17238} 17239 17240/* Finish the list of unwind opcodes for this function. */ 17241static void 17242finish_unwind_opcodes (void) 17243{ 17244 valueT op; 17245 17246 if (unwind.fp_used) 17247 { 17248 /* Adjust sp as necessary. */ 17249 unwind.pending_offset += unwind.fp_offset - unwind.frame_size; 17250 flush_pending_unwind (); 17251 17252 /* After restoring sp from the frame pointer. */ 17253 op = 0x90 | unwind.fp_reg; 17254 add_unwind_opcode (op, 1); 17255 } 17256 else 17257 flush_pending_unwind (); 17258} 17259 17260 17261/* Start an exception table entry. If idx is nonzero this is an index table 17262 entry. */ 17263 17264static void 17265start_unwind_section (const segT text_seg, int idx) 17266{ 17267 const char * text_name; 17268 const char * prefix; 17269 const char * prefix_once; 17270 const char * group_name; 17271 size_t prefix_len; 17272 size_t text_len; 17273 char * sec_name; 17274 size_t sec_name_len; 17275 int type; 17276 int flags; 17277 int linkonce; 17278 17279 if (idx) 17280 { 17281 prefix = ELF_STRING_ARM_unwind; 17282 prefix_once = ELF_STRING_ARM_unwind_once; 17283 type = SHT_ARM_EXIDX; 17284 } 17285 else 17286 { 17287 prefix = ELF_STRING_ARM_unwind_info; 17288 prefix_once = ELF_STRING_ARM_unwind_info_once; 17289 type = SHT_PROGBITS; 17290 } 17291 17292 text_name = segment_name (text_seg); 17293 if (streq (text_name, ".text")) 17294 text_name = ""; 17295 17296 if (strncmp (text_name, ".gnu.linkonce.t.", 17297 strlen (".gnu.linkonce.t.")) == 0) 17298 { 17299 prefix = prefix_once; 17300 text_name += strlen (".gnu.linkonce.t."); 17301 } 17302 17303 prefix_len = strlen (prefix); 17304 text_len = strlen (text_name); 17305 sec_name_len = prefix_len + text_len; 17306 sec_name = xmalloc (sec_name_len + 1); 17307 memcpy (sec_name, prefix, prefix_len); 17308 memcpy (sec_name + prefix_len, text_name, text_len); 17309 sec_name[prefix_len + text_len] = '\0'; 17310 17311 flags = SHF_ALLOC; 17312 linkonce = 0; 17313 group_name = 0; 17314 17315 /* Handle COMDAT group. */ 17316 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) 17317 { 17318 group_name = elf_group_name (text_seg); 17319 if (group_name == NULL) 17320 { 17321 as_bad ("Group section `%s' has no group signature", 17322 segment_name (text_seg)); 17323 ignore_rest_of_line (); 17324 return; 17325 } 17326 flags |= SHF_GROUP; 17327 linkonce = 1; 17328 } 17329 17330 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); 17331 17332 /* Set the setion link for index tables. */ 17333 if (idx) 17334 elf_linked_to_section (now_seg) = text_seg; 17335} 17336 17337 17338/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional 17339 personality routine data. Returns zero, or the index table value for 17340 and inline entry. */ 17341 17342static valueT 17343create_unwind_entry (int have_data) 17344{ 17345 int size; 17346 addressT where; 17347 char *ptr; 17348 /* The current word of data. */ 17349 valueT data; 17350 /* The number of bytes left in this word. */ 17351 int n; 17352 17353 finish_unwind_opcodes (); 17354 17355 /* Remember the current text section. */ 17356 unwind.saved_seg = now_seg; 17357 unwind.saved_subseg = now_subseg; 17358 17359 start_unwind_section (now_seg, 0); 17360 17361 if (unwind.personality_routine == NULL) 17362 { 17363 if (unwind.personality_index == -2) 17364 { 17365 if (have_data) 17366 as_bad (_("handerdata in cantunwind frame")); 17367 return 1; /* EXIDX_CANTUNWIND. */ 17368 } 17369 17370 /* Use a default personality routine if none is specified. */ 17371 if (unwind.personality_index == -1) 17372 { 17373 if (unwind.opcode_count > 3) 17374 unwind.personality_index = 1; 17375 else 17376 unwind.personality_index = 0; 17377 } 17378 17379 /* Space for the personality routine entry. */ 17380 if (unwind.personality_index == 0) 17381 { 17382 if (unwind.opcode_count > 3) 17383 as_bad (_("too many unwind opcodes for personality routine 0")); 17384 17385 if (!have_data) 17386 { 17387 /* All the data is inline in the index table. */ 17388 data = 0x80; 17389 n = 3; 17390 while (unwind.opcode_count > 0) 17391 { 17392 unwind.opcode_count--; 17393 data = (data << 8) | unwind.opcodes[unwind.opcode_count]; 17394 n--; 17395 } 17396 17397 /* Pad with "finish" opcodes. */ 17398 while (n--) 17399 data = (data << 8) | 0xb0; 17400 17401 return data; 17402 } 17403 size = 0; 17404 } 17405 else 17406 /* We get two opcodes "free" in the first word. */ 17407 size = unwind.opcode_count - 2; 17408 } 17409 else 17410 /* An extra byte is required for the opcode count. */ 17411 size = unwind.opcode_count + 1; 17412 17413 size = (size + 3) >> 2; 17414 if (size > 0xff) 17415 as_bad (_("too many unwind opcodes")); 17416 17417 frag_align (2, 0, 0); 17418 record_alignment (now_seg, 2); 17419 unwind.table_entry = expr_build_dot (); 17420 17421 /* Allocate the table entry. */ 17422 ptr = frag_more ((size << 2) + 4); 17423 memset(ptr, 0, (size << 2) + 4); 17424 where = frag_now_fix () - ((size << 2) + 4); 17425 17426 switch (unwind.personality_index) 17427 { 17428 case -1: 17429 /* ??? Should this be a PLT generating relocation? */ 17430 /* Custom personality routine. */ 17431 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, 17432 BFD_RELOC_ARM_PREL31); 17433 17434 where += 4; 17435 ptr += 4; 17436 17437 /* Set the first byte to the number of additional words. */ 17438 data = size - 1; 17439 n = 3; 17440 break; 17441 17442 /* ABI defined personality routines. */ 17443 case 0: 17444 /* Three opcodes bytes are packed into the first word. */ 17445 data = 0x80; 17446 n = 3; 17447 break; 17448 17449 case 1: 17450 case 2: 17451 /* The size and first two opcode bytes go in the first word. */ 17452 data = ((0x80 + unwind.personality_index) << 8) | size; 17453 n = 2; 17454 break; 17455 17456 default: 17457 /* Should never happen. */ 17458 abort (); 17459 } 17460 17461 /* Pack the opcodes into words (MSB first), reversing the list at the same 17462 time. */ 17463 while (unwind.opcode_count > 0) 17464 { 17465 if (n == 0) 17466 { 17467 md_number_to_chars (ptr, data, 4); 17468 ptr += 4; 17469 n = 4; 17470 data = 0; 17471 } 17472 unwind.opcode_count--; 17473 n--; 17474 data = (data << 8) | unwind.opcodes[unwind.opcode_count]; 17475 } 17476 17477 /* Finish off the last word. */ 17478 if (n < 4) 17479 { 17480 /* Pad with "finish" opcodes. */ 17481 while (n--) 17482 data = (data << 8) | 0xb0; 17483 17484 md_number_to_chars (ptr, data, 4); 17485 } 17486 17487 if (!have_data) 17488 { 17489 /* Add an empty descriptor if there is no user-specified data. */ 17490 ptr = frag_more (4); 17491 md_number_to_chars (ptr, 0, 4); 17492 } 17493 17494 return 0; 17495} 17496 17497 17498/* Initialize the DWARF-2 unwind information for this procedure. */ 17499 17500void 17501tc_arm_frame_initial_instructions (void) 17502{ 17503 cfi_add_CFA_def_cfa (REG_SP, 0); 17504} 17505#endif /* OBJ_ELF */ 17506 17507/* Convert REGNAME to a DWARF-2 register number. */ 17508 17509int 17510tc_arm_regname_to_dw2regnum (char *regname) 17511{ 17512 int reg = arm_reg_parse (®name, REG_TYPE_RN); 17513 17514 if (reg == FAIL) 17515 return -1; 17516 17517 return reg; 17518} 17519 17520#ifdef TE_PE 17521void 17522tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) 17523{ 17524 expressionS expr; 17525 17526 expr.X_op = O_secrel; 17527 expr.X_add_symbol = symbol; 17528 expr.X_add_number = 0; 17529 emit_expr (&expr, size); 17530} 17531#endif 17532 17533/* MD interface: Symbol and relocation handling. */ 17534 17535/* Return the address within the segment that a PC-relative fixup is 17536 relative to. For ARM, PC-relative fixups applied to instructions 17537 are generally relative to the location of the fixup plus 8 bytes. 17538 Thumb branches are offset by 4, and Thumb loads relative to PC 17539 require special handling. */ 17540 17541long 17542md_pcrel_from_section (fixS * fixP, segT seg) 17543{ 17544 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; 17545 17546 /* If this is pc-relative and we are going to emit a relocation 17547 then we just want to put out any pipeline compensation that the linker 17548 will need. Otherwise we want to use the calculated base. 17549 For WinCE we skip the bias for externals as well, since this 17550 is how the MS ARM-CE assembler behaves and we want to be compatible. */ 17551 if (fixP->fx_pcrel 17552 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) 17553 || (arm_force_relocation (fixP) 17554#ifdef TE_WINCE 17555 && !S_IS_EXTERNAL (fixP->fx_addsy) 17556#endif 17557 ))) 17558 base = 0; 17559 17560 switch (fixP->fx_r_type) 17561 { 17562 /* PC relative addressing on the Thumb is slightly odd as the 17563 bottom two bits of the PC are forced to zero for the 17564 calculation. This happens *after* application of the 17565 pipeline offset. However, Thumb adrl already adjusts for 17566 this, so we need not do it again. */ 17567 case BFD_RELOC_ARM_THUMB_ADD: 17568 return base & ~3; 17569 17570 case BFD_RELOC_ARM_THUMB_OFFSET: 17571 case BFD_RELOC_ARM_T32_OFFSET_IMM: 17572 case BFD_RELOC_ARM_T32_ADD_PC12: 17573 case BFD_RELOC_ARM_T32_CP_OFF_IMM: 17574 return (base + 4) & ~3; 17575 17576 /* Thumb branches are simply offset by +4. */ 17577 case BFD_RELOC_THUMB_PCREL_BRANCH7: 17578 case BFD_RELOC_THUMB_PCREL_BRANCH9: 17579 case BFD_RELOC_THUMB_PCREL_BRANCH12: 17580 case BFD_RELOC_THUMB_PCREL_BRANCH20: 17581 case BFD_RELOC_THUMB_PCREL_BRANCH23: 17582 case BFD_RELOC_THUMB_PCREL_BRANCH25: 17583 case BFD_RELOC_THUMB_PCREL_BLX: 17584 return base + 4; 17585 17586 /* ARM mode branches are offset by +8. However, the Windows CE 17587 loader expects the relocation not to take this into account. */ 17588 case BFD_RELOC_ARM_PCREL_BRANCH: 17589 case BFD_RELOC_ARM_PCREL_CALL: 17590 case BFD_RELOC_ARM_PCREL_JUMP: 17591 case BFD_RELOC_ARM_PCREL_BLX: 17592 case BFD_RELOC_ARM_PLT32: 17593#ifdef TE_WINCE 17594 /* When handling fixups immediately, because we have already 17595 discovered the value of a symbol, or the address of the frag involved 17596 we must account for the offset by +8, as the OS loader will never see the reloc. 17597 see fixup_segment() in write.c 17598 The S_IS_EXTERNAL test handles the case of global symbols. 17599 Those need the calculated base, not just the pipe compensation the linker will need. */ 17600 if (fixP->fx_pcrel 17601 && fixP->fx_addsy != NULL 17602 && (S_GET_SEGMENT (fixP->fx_addsy) == seg) 17603 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) 17604 return base + 8; 17605 return base; 17606#else 17607 return base + 8; 17608#endif 17609 17610 /* ARM mode loads relative to PC are also offset by +8. Unlike 17611 branches, the Windows CE loader *does* expect the relocation 17612 to take this into account. */ 17613 case BFD_RELOC_ARM_OFFSET_IMM: 17614 case BFD_RELOC_ARM_OFFSET_IMM8: 17615 case BFD_RELOC_ARM_HWLITERAL: 17616 case BFD_RELOC_ARM_LITERAL: 17617 case BFD_RELOC_ARM_CP_OFF_IMM: 17618 return base + 8; 17619 17620 17621 /* Other PC-relative relocations are un-offset. */ 17622 default: 17623 return base; 17624 } 17625} 17626 17627/* Under ELF we need to default _GLOBAL_OFFSET_TABLE. 17628 Otherwise we have no need to default values of symbols. */ 17629 17630symbolS * 17631md_undefined_symbol (char * name ATTRIBUTE_UNUSED) 17632{ 17633#ifdef OBJ_ELF 17634 if (name[0] == '_' && name[1] == 'G' 17635 && streq (name, GLOBAL_OFFSET_TABLE_NAME)) 17636 { 17637 if (!GOT_symbol) 17638 { 17639 if (symbol_find (name)) 17640 as_bad ("GOT already in the symbol table"); 17641 17642 GOT_symbol = symbol_new (name, undefined_section, 17643 (valueT) 0, & zero_address_frag); 17644 } 17645 17646 return GOT_symbol; 17647 } 17648#endif 17649 17650 return 0; 17651} 17652 17653/* Subroutine of md_apply_fix. Check to see if an immediate can be 17654 computed as two separate immediate values, added together. We 17655 already know that this value cannot be computed by just one ARM 17656 instruction. */ 17657 17658static unsigned int 17659validate_immediate_twopart (unsigned int val, 17660 unsigned int * highpart) 17661{ 17662 unsigned int a; 17663 unsigned int i; 17664 17665 for (i = 0; i < 32; i += 2) 17666 if (((a = rotate_left (val, i)) & 0xff) != 0) 17667 { 17668 if (a & 0xff00) 17669 { 17670 if (a & ~ 0xffff) 17671 continue; 17672 * highpart = (a >> 8) | ((i + 24) << 7); 17673 } 17674 else if (a & 0xff0000) 17675 { 17676 if (a & 0xff000000) 17677 continue; 17678 * highpart = (a >> 16) | ((i + 16) << 7); 17679 } 17680 else 17681 { 17682 assert (a & 0xff000000); 17683 * highpart = (a >> 24) | ((i + 8) << 7); 17684 } 17685 17686 return (a & 0xff) | (i << 7); 17687 } 17688 17689 return FAIL; 17690} 17691 17692static int 17693validate_offset_imm (unsigned int val, int hwse) 17694{ 17695 if ((hwse && val > 255) || val > 4095) 17696 return FAIL; 17697 return val; 17698} 17699 17700/* Subroutine of md_apply_fix. Do those data_ops which can take a 17701 negative immediate constant by altering the instruction. A bit of 17702 a hack really. 17703 MOV <-> MVN 17704 AND <-> BIC 17705 ADC <-> SBC 17706 by inverting the second operand, and 17707 ADD <-> SUB 17708 CMP <-> CMN 17709 by negating the second operand. */ 17710 17711static int 17712negate_data_op (unsigned long * instruction, 17713 unsigned long value) 17714{ 17715 int op, new_inst; 17716 unsigned long negated, inverted; 17717 17718 negated = encode_arm_immediate (-value); 17719 inverted = encode_arm_immediate (~value); 17720 17721 op = (*instruction >> DATA_OP_SHIFT) & 0xf; 17722 switch (op) 17723 { 17724 /* First negates. */ 17725 case OPCODE_SUB: /* ADD <-> SUB */ 17726 new_inst = OPCODE_ADD; 17727 value = negated; 17728 break; 17729 17730 case OPCODE_ADD: 17731 new_inst = OPCODE_SUB; 17732 value = negated; 17733 break; 17734 17735 case OPCODE_CMP: /* CMP <-> CMN */ 17736 new_inst = OPCODE_CMN; 17737 value = negated; 17738 break; 17739 17740 case OPCODE_CMN: 17741 new_inst = OPCODE_CMP; 17742 value = negated; 17743 break; 17744 17745 /* Now Inverted ops. */ 17746 case OPCODE_MOV: /* MOV <-> MVN */ 17747 new_inst = OPCODE_MVN; 17748 value = inverted; 17749 break; 17750 17751 case OPCODE_MVN: 17752 new_inst = OPCODE_MOV; 17753 value = inverted; 17754 break; 17755 17756 case OPCODE_AND: /* AND <-> BIC */ 17757 new_inst = OPCODE_BIC; 17758 value = inverted; 17759 break; 17760 17761 case OPCODE_BIC: 17762 new_inst = OPCODE_AND; 17763 value = inverted; 17764 break; 17765 17766 case OPCODE_ADC: /* ADC <-> SBC */ 17767 new_inst = OPCODE_SBC; 17768 value = inverted; 17769 break; 17770 17771 case OPCODE_SBC: 17772 new_inst = OPCODE_ADC; 17773 value = inverted; 17774 break; 17775 17776 /* We cannot do anything. */ 17777 default: 17778 return FAIL; 17779 } 17780 17781 if (value == (unsigned) FAIL) 17782 return FAIL; 17783 17784 *instruction &= OPCODE_MASK; 17785 *instruction |= new_inst << DATA_OP_SHIFT; 17786 return value; 17787} 17788 17789/* Like negate_data_op, but for Thumb-2. */ 17790 17791static unsigned int 17792thumb32_negate_data_op (offsetT *instruction, unsigned int value) 17793{ 17794 int op, new_inst; 17795 int rd; 17796 unsigned int negated, inverted; 17797 17798 negated = encode_thumb32_immediate (-value); 17799 inverted = encode_thumb32_immediate (~value); 17800 17801 rd = (*instruction >> 8) & 0xf; 17802 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; 17803 switch (op) 17804 { 17805 /* ADD <-> SUB. Includes CMP <-> CMN. */ 17806 case T2_OPCODE_SUB: 17807 new_inst = T2_OPCODE_ADD; 17808 value = negated; 17809 break; 17810 17811 case T2_OPCODE_ADD: 17812 new_inst = T2_OPCODE_SUB; 17813 value = negated; 17814 break; 17815 17816 /* ORR <-> ORN. Includes MOV <-> MVN. */ 17817 case T2_OPCODE_ORR: 17818 new_inst = T2_OPCODE_ORN; 17819 value = inverted; 17820 break; 17821 17822 case T2_OPCODE_ORN: 17823 new_inst = T2_OPCODE_ORR; 17824 value = inverted; 17825 break; 17826 17827 /* AND <-> BIC. TST has no inverted equivalent. */ 17828 case T2_OPCODE_AND: 17829 new_inst = T2_OPCODE_BIC; 17830 if (rd == 15) 17831 value = FAIL; 17832 else 17833 value = inverted; 17834 break; 17835 17836 case T2_OPCODE_BIC: 17837 new_inst = T2_OPCODE_AND; 17838 value = inverted; 17839 break; 17840 17841 /* ADC <-> SBC */ 17842 case T2_OPCODE_ADC: 17843 new_inst = T2_OPCODE_SBC; 17844 value = inverted; 17845 break; 17846 17847 case T2_OPCODE_SBC: 17848 new_inst = T2_OPCODE_ADC; 17849 value = inverted; 17850 break; 17851 17852 /* We cannot do anything. */ 17853 default: 17854 return FAIL; 17855 } 17856 17857 if (value == (unsigned int)FAIL) 17858 return FAIL; 17859 17860 *instruction &= T2_OPCODE_MASK; 17861 *instruction |= new_inst << T2_DATA_OP_SHIFT; 17862 return value; 17863} 17864 17865/* Read a 32-bit thumb instruction from buf. */ 17866static unsigned long 17867get_thumb32_insn (char * buf) 17868{ 17869 unsigned long insn; 17870 insn = md_chars_to_number (buf, THUMB_SIZE) << 16; 17871 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 17872 17873 return insn; 17874} 17875 17876 17877/* We usually want to set the low bit on the address of thumb function 17878 symbols. In particular .word foo - . should have the low bit set. 17879 Generic code tries to fold the difference of two symbols to 17880 a constant. Prevent this and force a relocation when the first symbols 17881 is a thumb function. */ 17882int 17883arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) 17884{ 17885 if (op == O_subtract 17886 && l->X_op == O_symbol 17887 && r->X_op == O_symbol 17888 && THUMB_IS_FUNC (l->X_add_symbol)) 17889 { 17890 l->X_op = O_subtract; 17891 l->X_op_symbol = r->X_add_symbol; 17892 l->X_add_number -= r->X_add_number; 17893 return 1; 17894 } 17895 /* Process as normal. */ 17896 return 0; 17897} 17898 17899void 17900md_apply_fix (fixS * fixP, 17901 valueT * valP, 17902 segT seg) 17903{ 17904 offsetT value = * valP; 17905 offsetT newval; 17906 unsigned int newimm; 17907 unsigned long temp; 17908 int sign; 17909 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; 17910 17911 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); 17912 17913 /* Note whether this will delete the relocation. */ 17914 17915 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 17916 fixP->fx_done = 1; 17917 17918 /* On a 64-bit host, silently truncate 'value' to 32 bits for 17919 consistency with the behavior on 32-bit hosts. Remember value 17920 for emit_reloc. */ 17921 value &= 0xffffffff; 17922 value ^= 0x80000000; 17923 value -= 0x80000000; 17924 17925 *valP = value; 17926 fixP->fx_addnumber = value; 17927 17928 /* Same treatment for fixP->fx_offset. */ 17929 fixP->fx_offset &= 0xffffffff; 17930 fixP->fx_offset ^= 0x80000000; 17931 fixP->fx_offset -= 0x80000000; 17932 17933 switch (fixP->fx_r_type) 17934 { 17935 case BFD_RELOC_NONE: 17936 /* This will need to go in the object file. */ 17937 fixP->fx_done = 0; 17938 break; 17939 17940 case BFD_RELOC_ARM_IMMEDIATE: 17941 /* We claim that this fixup has been processed here, 17942 even if in fact we generate an error because we do 17943 not have a reloc for it, so tc_gen_reloc will reject it. */ 17944 fixP->fx_done = 1; 17945 17946 if (fixP->fx_addsy 17947 && ! S_IS_DEFINED (fixP->fx_addsy)) 17948 { 17949 as_bad_where (fixP->fx_file, fixP->fx_line, 17950 _("undefined symbol %s used as an immediate value"), 17951 S_GET_NAME (fixP->fx_addsy)); 17952 break; 17953 } 17954 17955 newimm = encode_arm_immediate (value); 17956 temp = md_chars_to_number (buf, INSN_SIZE); 17957 17958 /* If the instruction will fail, see if we can fix things up by 17959 changing the opcode. */ 17960 if (newimm == (unsigned int) FAIL 17961 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) 17962 { 17963 as_bad_where (fixP->fx_file, fixP->fx_line, 17964 _("invalid constant (%lx) after fixup"), 17965 (unsigned long) value); 17966 break; 17967 } 17968 17969 newimm |= (temp & 0xfffff000); 17970 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); 17971 break; 17972 17973 case BFD_RELOC_ARM_ADRL_IMMEDIATE: 17974 { 17975 unsigned int highpart = 0; 17976 unsigned int newinsn = 0xe1a00000; /* nop. */ 17977 17978 newimm = encode_arm_immediate (value); 17979 temp = md_chars_to_number (buf, INSN_SIZE); 17980 17981 /* If the instruction will fail, see if we can fix things up by 17982 changing the opcode. */ 17983 if (newimm == (unsigned int) FAIL 17984 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) 17985 { 17986 /* No ? OK - try using two ADD instructions to generate 17987 the value. */ 17988 newimm = validate_immediate_twopart (value, & highpart); 17989 17990 /* Yes - then make sure that the second instruction is 17991 also an add. */ 17992 if (newimm != (unsigned int) FAIL) 17993 newinsn = temp; 17994 /* Still No ? Try using a negated value. */ 17995 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) 17996 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; 17997 /* Otherwise - give up. */ 17998 else 17999 { 18000 as_bad_where (fixP->fx_file, fixP->fx_line, 18001 _("unable to compute ADRL instructions for PC offset of 0x%lx"), 18002 (long) value); 18003 break; 18004 } 18005 18006 /* Replace the first operand in the 2nd instruction (which 18007 is the PC) with the destination register. We have 18008 already added in the PC in the first instruction and we 18009 do not want to do it again. */ 18010 newinsn &= ~ 0xf0000; 18011 newinsn |= ((newinsn & 0x0f000) << 4); 18012 } 18013 18014 newimm |= (temp & 0xfffff000); 18015 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); 18016 18017 highpart |= (newinsn & 0xfffff000); 18018 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); 18019 } 18020 break; 18021 18022 case BFD_RELOC_ARM_OFFSET_IMM: 18023 if (!fixP->fx_done && seg->use_rela_p) 18024 value = 0; 18025 18026 case BFD_RELOC_ARM_LITERAL: 18027 sign = value >= 0; 18028 18029 if (value < 0) 18030 value = - value; 18031 18032 if (validate_offset_imm (value, 0) == FAIL) 18033 { 18034 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) 18035 as_bad_where (fixP->fx_file, fixP->fx_line, 18036 _("invalid literal constant: pool needs to be closer")); 18037 else 18038 as_bad_where (fixP->fx_file, fixP->fx_line, 18039 _("bad immediate value for offset (%ld)"), 18040 (long) value); 18041 break; 18042 } 18043 18044 newval = md_chars_to_number (buf, INSN_SIZE); 18045 newval &= 0xff7ff000; 18046 newval |= value | (sign ? INDEX_UP : 0); 18047 md_number_to_chars (buf, newval, INSN_SIZE); 18048 break; 18049 18050 case BFD_RELOC_ARM_OFFSET_IMM8: 18051 case BFD_RELOC_ARM_HWLITERAL: 18052 sign = value >= 0; 18053 18054 if (value < 0) 18055 value = - value; 18056 18057 if (validate_offset_imm (value, 1) == FAIL) 18058 { 18059 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) 18060 as_bad_where (fixP->fx_file, fixP->fx_line, 18061 _("invalid literal constant: pool needs to be closer")); 18062 else 18063 as_bad (_("bad immediate value for 8-bit offset (%ld)"), 18064 (long) value); 18065 break; 18066 } 18067 18068 newval = md_chars_to_number (buf, INSN_SIZE); 18069 newval &= 0xff7ff0f0; 18070 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); 18071 md_number_to_chars (buf, newval, INSN_SIZE); 18072 break; 18073 18074 case BFD_RELOC_ARM_T32_OFFSET_U8: 18075 if (value < 0 || value > 1020 || value % 4 != 0) 18076 as_bad_where (fixP->fx_file, fixP->fx_line, 18077 _("bad immediate value for offset (%ld)"), (long) value); 18078 value /= 4; 18079 18080 newval = md_chars_to_number (buf+2, THUMB_SIZE); 18081 newval |= value; 18082 md_number_to_chars (buf+2, newval, THUMB_SIZE); 18083 break; 18084 18085 case BFD_RELOC_ARM_T32_OFFSET_IMM: 18086 /* This is a complicated relocation used for all varieties of Thumb32 18087 load/store instruction with immediate offset: 18088 18089 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, 18090 *4, optional writeback(W) 18091 (doubleword load/store) 18092 18093 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel 18094 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit 18095 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) 18096 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit 18097 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit 18098 18099 Uppercase letters indicate bits that are already encoded at 18100 this point. Lowercase letters are our problem. For the 18101 second block of instructions, the secondary opcode nybble 18102 (bits 8..11) is present, and bit 23 is zero, even if this is 18103 a PC-relative operation. */ 18104 newval = md_chars_to_number (buf, THUMB_SIZE); 18105 newval <<= 16; 18106 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); 18107 18108 if ((newval & 0xf0000000) == 0xe0000000) 18109 { 18110 /* Doubleword load/store: 8-bit offset, scaled by 4. */ 18111 if (value >= 0) 18112 newval |= (1 << 23); 18113 else 18114 value = -value; 18115 if (value % 4 != 0) 18116 { 18117 as_bad_where (fixP->fx_file, fixP->fx_line, 18118 _("offset not a multiple of 4")); 18119 break; 18120 } 18121 value /= 4; 18122 if (value > 0xff) 18123 { 18124 as_bad_where (fixP->fx_file, fixP->fx_line, 18125 _("offset out of range")); 18126 break; 18127 } 18128 newval &= ~0xff; 18129 } 18130 else if ((newval & 0x000f0000) == 0x000f0000) 18131 { 18132 /* PC-relative, 12-bit offset. */ 18133 if (value >= 0) 18134 newval |= (1 << 23); 18135 else 18136 value = -value; 18137 if (value > 0xfff) 18138 { 18139 as_bad_where (fixP->fx_file, fixP->fx_line, 18140 _("offset out of range")); 18141 break; 18142 } 18143 newval &= ~0xfff; 18144 } 18145 else if ((newval & 0x00000100) == 0x00000100) 18146 { 18147 /* Writeback: 8-bit, +/- offset. */ 18148 if (value >= 0) 18149 newval |= (1 << 9); 18150 else 18151 value = -value; 18152 if (value > 0xff) 18153 { 18154 as_bad_where (fixP->fx_file, fixP->fx_line, 18155 _("offset out of range")); 18156 break; 18157 } 18158 newval &= ~0xff; 18159 } 18160 else if ((newval & 0x00000f00) == 0x00000e00) 18161 { 18162 /* T-instruction: positive 8-bit offset. */ 18163 if (value < 0 || value > 0xff) 18164 { 18165 as_bad_where (fixP->fx_file, fixP->fx_line, 18166 _("offset out of range")); 18167 break; 18168 } 18169 newval &= ~0xff; 18170 newval |= value; 18171 } 18172 else 18173 { 18174 /* Positive 12-bit or negative 8-bit offset. */ 18175 int limit; 18176 if (value >= 0) 18177 { 18178 newval |= (1 << 23); 18179 limit = 0xfff; 18180 } 18181 else 18182 { 18183 value = -value; 18184 limit = 0xff; 18185 } 18186 if (value > limit) 18187 { 18188 as_bad_where (fixP->fx_file, fixP->fx_line, 18189 _("offset out of range")); 18190 break; 18191 } 18192 newval &= ~limit; 18193 } 18194 18195 newval |= value; 18196 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); 18197 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); 18198 break; 18199 18200 case BFD_RELOC_ARM_SHIFT_IMM: 18201 newval = md_chars_to_number (buf, INSN_SIZE); 18202 if (((unsigned long) value) > 32 18203 || (value == 32 18204 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) 18205 { 18206 as_bad_where (fixP->fx_file, fixP->fx_line, 18207 _("shift expression is too large")); 18208 break; 18209 } 18210 18211 if (value == 0) 18212 /* Shifts of zero must be done as lsl. */ 18213 newval &= ~0x60; 18214 else if (value == 32) 18215 value = 0; 18216 newval &= 0xfffff07f; 18217 newval |= (value & 0x1f) << 7; 18218 md_number_to_chars (buf, newval, INSN_SIZE); 18219 break; 18220 18221 case BFD_RELOC_ARM_T32_IMMEDIATE: 18222 case BFD_RELOC_ARM_T32_ADD_IMM: 18223 case BFD_RELOC_ARM_T32_IMM12: 18224 case BFD_RELOC_ARM_T32_ADD_PC12: 18225 /* We claim that this fixup has been processed here, 18226 even if in fact we generate an error because we do 18227 not have a reloc for it, so tc_gen_reloc will reject it. */ 18228 fixP->fx_done = 1; 18229 18230 if (fixP->fx_addsy 18231 && ! S_IS_DEFINED (fixP->fx_addsy)) 18232 { 18233 as_bad_where (fixP->fx_file, fixP->fx_line, 18234 _("undefined symbol %s used as an immediate value"), 18235 S_GET_NAME (fixP->fx_addsy)); 18236 break; 18237 } 18238 18239 newval = md_chars_to_number (buf, THUMB_SIZE); 18240 newval <<= 16; 18241 newval |= md_chars_to_number (buf+2, THUMB_SIZE); 18242 18243 newimm = FAIL; 18244 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE 18245 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) 18246 { 18247 newimm = encode_thumb32_immediate (value); 18248 if (newimm == (unsigned int) FAIL) 18249 newimm = thumb32_negate_data_op (&newval, value); 18250 } 18251 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE 18252 && newimm == (unsigned int) FAIL) 18253 { 18254 /* Turn add/sum into addw/subw. */ 18255 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) 18256 newval = (newval & 0xfeffffff) | 0x02000000; 18257 18258 /* 12 bit immediate for addw/subw. */ 18259 if (value < 0) 18260 { 18261 value = -value; 18262 newval ^= 0x00a00000; 18263 } 18264 if (value > 0xfff) 18265 newimm = (unsigned int) FAIL; 18266 else 18267 newimm = value; 18268 } 18269 18270 if (newimm == (unsigned int)FAIL) 18271 { 18272 as_bad_where (fixP->fx_file, fixP->fx_line, 18273 _("invalid constant (%lx) after fixup"), 18274 (unsigned long) value); 18275 break; 18276 } 18277 18278 newval |= (newimm & 0x800) << 15; 18279 newval |= (newimm & 0x700) << 4; 18280 newval |= (newimm & 0x0ff); 18281 18282 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); 18283 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); 18284 break; 18285 18286 case BFD_RELOC_ARM_SMC: 18287 if (((unsigned long) value) > 0xffff) 18288 as_bad_where (fixP->fx_file, fixP->fx_line, 18289 _("invalid smc expression")); 18290 newval = md_chars_to_number (buf, INSN_SIZE); 18291 newval |= (value & 0xf) | ((value & 0xfff0) << 4); 18292 md_number_to_chars (buf, newval, INSN_SIZE); 18293 break; 18294 18295 case BFD_RELOC_ARM_SWI: 18296 if (fixP->tc_fix_data != 0) 18297 { 18298 if (((unsigned long) value) > 0xff) 18299 as_bad_where (fixP->fx_file, fixP->fx_line, 18300 _("invalid swi expression")); 18301 newval = md_chars_to_number (buf, THUMB_SIZE); 18302 newval |= value; 18303 md_number_to_chars (buf, newval, THUMB_SIZE); 18304 } 18305 else 18306 { 18307 if (((unsigned long) value) > 0x00ffffff) 18308 as_bad_where (fixP->fx_file, fixP->fx_line, 18309 _("invalid swi expression")); 18310 newval = md_chars_to_number (buf, INSN_SIZE); 18311 newval |= value; 18312 md_number_to_chars (buf, newval, INSN_SIZE); 18313 } 18314 break; 18315 18316 case BFD_RELOC_ARM_MULTI: 18317 if (((unsigned long) value) > 0xffff) 18318 as_bad_where (fixP->fx_file, fixP->fx_line, 18319 _("invalid expression in load/store multiple")); 18320 newval = value | md_chars_to_number (buf, INSN_SIZE); 18321 md_number_to_chars (buf, newval, INSN_SIZE); 18322 break; 18323 18324#ifdef OBJ_ELF 18325 case BFD_RELOC_ARM_PCREL_CALL: 18326 newval = md_chars_to_number (buf, INSN_SIZE); 18327 if ((newval & 0xf0000000) == 0xf0000000) 18328 temp = 1; 18329 else 18330 temp = 3; 18331 goto arm_branch_common; 18332 18333 case BFD_RELOC_ARM_PCREL_JUMP: 18334 case BFD_RELOC_ARM_PLT32: 18335#endif 18336 case BFD_RELOC_ARM_PCREL_BRANCH: 18337 temp = 3; 18338 goto arm_branch_common; 18339 18340 case BFD_RELOC_ARM_PCREL_BLX: 18341 temp = 1; 18342 arm_branch_common: 18343 /* We are going to store value (shifted right by two) in the 18344 instruction, in a 24 bit, signed field. Bits 26 through 32 either 18345 all clear or all set and bit 0 must be clear. For B/BL bit 1 must 18346 also be be clear. */ 18347 if (value & temp) 18348 as_bad_where (fixP->fx_file, fixP->fx_line, 18349 _("misaligned branch destination")); 18350 if ((value & (offsetT)0xfe000000) != (offsetT)0 18351 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) 18352 as_bad_where (fixP->fx_file, fixP->fx_line, 18353 _("branch out of range")); 18354 18355 if (fixP->fx_done || !seg->use_rela_p) 18356 { 18357 newval = md_chars_to_number (buf, INSN_SIZE); 18358 newval |= (value >> 2) & 0x00ffffff; 18359 /* Set the H bit on BLX instructions. */ 18360 if (temp == 1) 18361 { 18362 if (value & 2) 18363 newval |= 0x01000000; 18364 else 18365 newval &= ~0x01000000; 18366 } 18367 md_number_to_chars (buf, newval, INSN_SIZE); 18368 } 18369 break; 18370 18371 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ 18372 /* CBZ can only branch forward. */ 18373 18374 /* Attempts to use CBZ to branch to the next instruction 18375 (which, strictly speaking, are prohibited) will be turned into 18376 no-ops. 18377 18378 FIXME: It may be better to remove the instruction completely and 18379 perform relaxation. */ 18380 if (value == -2) 18381 { 18382 newval = md_chars_to_number (buf, THUMB_SIZE); 18383 newval = 0xbf00; /* NOP encoding T1 */ 18384 md_number_to_chars (buf, newval, THUMB_SIZE); 18385 } 18386 else 18387 { 18388 if (value & ~0x7e) 18389 as_bad_where (fixP->fx_file, fixP->fx_line, 18390 _("branch out of range")); 18391 18392 if (fixP->fx_done || !seg->use_rela_p) 18393 { 18394 newval = md_chars_to_number (buf, THUMB_SIZE); 18395 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); 18396 md_number_to_chars (buf, newval, THUMB_SIZE); 18397 } 18398 } 18399 break; 18400 18401 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ 18402 if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) 18403 as_bad_where (fixP->fx_file, fixP->fx_line, 18404 _("branch out of range")); 18405 18406 if (fixP->fx_done || !seg->use_rela_p) 18407 { 18408 newval = md_chars_to_number (buf, THUMB_SIZE); 18409 newval |= (value & 0x1ff) >> 1; 18410 md_number_to_chars (buf, newval, THUMB_SIZE); 18411 } 18412 break; 18413 18414 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ 18415 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) 18416 as_bad_where (fixP->fx_file, fixP->fx_line, 18417 _("branch out of range")); 18418 18419 if (fixP->fx_done || !seg->use_rela_p) 18420 { 18421 newval = md_chars_to_number (buf, THUMB_SIZE); 18422 newval |= (value & 0xfff) >> 1; 18423 md_number_to_chars (buf, newval, THUMB_SIZE); 18424 } 18425 break; 18426 18427 case BFD_RELOC_THUMB_PCREL_BRANCH20: 18428 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) 18429 as_bad_where (fixP->fx_file, fixP->fx_line, 18430 _("conditional branch out of range")); 18431 18432 if (fixP->fx_done || !seg->use_rela_p) 18433 { 18434 offsetT newval2; 18435 addressT S, J1, J2, lo, hi; 18436 18437 S = (value & 0x00100000) >> 20; 18438 J2 = (value & 0x00080000) >> 19; 18439 J1 = (value & 0x00040000) >> 18; 18440 hi = (value & 0x0003f000) >> 12; 18441 lo = (value & 0x00000ffe) >> 1; 18442 18443 newval = md_chars_to_number (buf, THUMB_SIZE); 18444 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 18445 newval |= (S << 10) | hi; 18446 newval2 |= (J1 << 13) | (J2 << 11) | lo; 18447 md_number_to_chars (buf, newval, THUMB_SIZE); 18448 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); 18449 } 18450 break; 18451 18452 case BFD_RELOC_THUMB_PCREL_BLX: 18453 case BFD_RELOC_THUMB_PCREL_BRANCH23: 18454 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) 18455 as_bad_where (fixP->fx_file, fixP->fx_line, 18456 _("branch out of range")); 18457 18458 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) 18459 /* For a BLX instruction, make sure that the relocation is rounded up 18460 to a word boundary. This follows the semantics of the instruction 18461 which specifies that bit 1 of the target address will come from bit 18462 1 of the base address. */ 18463 value = (value + 1) & ~ 1; 18464 18465 if (fixP->fx_done || !seg->use_rela_p) 18466 { 18467 offsetT newval2; 18468 18469 newval = md_chars_to_number (buf, THUMB_SIZE); 18470 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 18471 newval |= (value & 0x7fffff) >> 12; 18472 newval2 |= (value & 0xfff) >> 1; 18473 md_number_to_chars (buf, newval, THUMB_SIZE); 18474 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); 18475 } 18476 break; 18477 18478 case BFD_RELOC_THUMB_PCREL_BRANCH25: 18479 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) 18480 as_bad_where (fixP->fx_file, fixP->fx_line, 18481 _("branch out of range")); 18482 18483 if (fixP->fx_done || !seg->use_rela_p) 18484 { 18485 offsetT newval2; 18486 addressT S, I1, I2, lo, hi; 18487 18488 S = (value & 0x01000000) >> 24; 18489 I1 = (value & 0x00800000) >> 23; 18490 I2 = (value & 0x00400000) >> 22; 18491 hi = (value & 0x003ff000) >> 12; 18492 lo = (value & 0x00000ffe) >> 1; 18493 18494 I1 = !(I1 ^ S); 18495 I2 = !(I2 ^ S); 18496 18497 newval = md_chars_to_number (buf, THUMB_SIZE); 18498 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 18499 newval |= (S << 10) | hi; 18500 newval2 |= (I1 << 13) | (I2 << 11) | lo; 18501 md_number_to_chars (buf, newval, THUMB_SIZE); 18502 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); 18503 } 18504 break; 18505 18506 case BFD_RELOC_8: 18507 if (fixP->fx_done || !seg->use_rela_p) 18508 md_number_to_chars (buf, value, 1); 18509 break; 18510 18511 case BFD_RELOC_16: 18512 if (fixP->fx_done || !seg->use_rela_p) 18513 md_number_to_chars (buf, value, 2); 18514 break; 18515 18516#ifdef OBJ_ELF 18517 case BFD_RELOC_ARM_TLS_GD32: 18518 case BFD_RELOC_ARM_TLS_LE32: 18519 case BFD_RELOC_ARM_TLS_IE32: 18520 case BFD_RELOC_ARM_TLS_LDM32: 18521 case BFD_RELOC_ARM_TLS_LDO32: 18522 S_SET_THREAD_LOCAL (fixP->fx_addsy); 18523 /* fall through */ 18524 18525 case BFD_RELOC_ARM_GOT32: 18526 case BFD_RELOC_ARM_GOTOFF: 18527 case BFD_RELOC_ARM_TARGET2: 18528 if (fixP->fx_done || !seg->use_rela_p) 18529 md_number_to_chars (buf, 0, 4); 18530 break; 18531#endif 18532 18533 case BFD_RELOC_RVA: 18534 case BFD_RELOC_32: 18535 case BFD_RELOC_ARM_TARGET1: 18536 case BFD_RELOC_ARM_ROSEGREL32: 18537 case BFD_RELOC_ARM_SBREL32: 18538 case BFD_RELOC_32_PCREL: 18539#ifdef TE_PE 18540 case BFD_RELOC_32_SECREL: 18541#endif 18542 if (fixP->fx_done || !seg->use_rela_p) 18543#ifdef TE_WINCE 18544 /* For WinCE we only do this for pcrel fixups. */ 18545 if (fixP->fx_done || fixP->fx_pcrel) 18546#endif 18547 md_number_to_chars (buf, value, 4); 18548 break; 18549 18550#ifdef OBJ_ELF 18551 case BFD_RELOC_ARM_PREL31: 18552 if (fixP->fx_done || !seg->use_rela_p) 18553 { 18554 newval = md_chars_to_number (buf, 4) & 0x80000000; 18555 if ((value ^ (value >> 1)) & 0x40000000) 18556 { 18557 as_bad_where (fixP->fx_file, fixP->fx_line, 18558 _("rel31 relocation overflow")); 18559 } 18560 newval |= value & 0x7fffffff; 18561 md_number_to_chars (buf, newval, 4); 18562 } 18563 break; 18564#endif 18565 18566 case BFD_RELOC_ARM_CP_OFF_IMM: 18567 case BFD_RELOC_ARM_T32_CP_OFF_IMM: 18568 if (value < -1023 || value > 1023 || (value & 3)) 18569 as_bad_where (fixP->fx_file, fixP->fx_line, 18570 _("co-processor offset out of range")); 18571 cp_off_common: 18572 sign = value >= 0; 18573 if (value < 0) 18574 value = -value; 18575 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM 18576 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) 18577 newval = md_chars_to_number (buf, INSN_SIZE); 18578 else 18579 newval = get_thumb32_insn (buf); 18580 newval &= 0xff7fff00; 18581 newval |= (value >> 2) | (sign ? INDEX_UP : 0); 18582 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM 18583 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) 18584 md_number_to_chars (buf, newval, INSN_SIZE); 18585 else 18586 put_thumb32_insn (buf, newval); 18587 break; 18588 18589 case BFD_RELOC_ARM_CP_OFF_IMM_S2: 18590 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: 18591 if (value < -255 || value > 255) 18592 as_bad_where (fixP->fx_file, fixP->fx_line, 18593 _("co-processor offset out of range")); 18594 value *= 4; 18595 goto cp_off_common; 18596 18597 case BFD_RELOC_ARM_THUMB_OFFSET: 18598 newval = md_chars_to_number (buf, THUMB_SIZE); 18599 /* Exactly what ranges, and where the offset is inserted depends 18600 on the type of instruction, we can establish this from the 18601 top 4 bits. */ 18602 switch (newval >> 12) 18603 { 18604 case 4: /* PC load. */ 18605 /* Thumb PC loads are somewhat odd, bit 1 of the PC is 18606 forced to zero for these loads; md_pcrel_from has already 18607 compensated for this. */ 18608 if (value & 3) 18609 as_bad_where (fixP->fx_file, fixP->fx_line, 18610 _("invalid offset, target not word aligned (0x%08lX)"), 18611 (((unsigned long) fixP->fx_frag->fr_address 18612 + (unsigned long) fixP->fx_where) & ~3) 18613 + (unsigned long) value); 18614 18615 if (value & ~0x3fc) 18616 as_bad_where (fixP->fx_file, fixP->fx_line, 18617 _("invalid offset, value too big (0x%08lX)"), 18618 (long) value); 18619 18620 newval |= value >> 2; 18621 break; 18622 18623 case 9: /* SP load/store. */ 18624 if (value & ~0x3fc) 18625 as_bad_where (fixP->fx_file, fixP->fx_line, 18626 _("invalid offset, value too big (0x%08lX)"), 18627 (long) value); 18628 newval |= value >> 2; 18629 break; 18630 18631 case 6: /* Word load/store. */ 18632 if (value & ~0x7c) 18633 as_bad_where (fixP->fx_file, fixP->fx_line, 18634 _("invalid offset, value too big (0x%08lX)"), 18635 (long) value); 18636 newval |= value << 4; /* 6 - 2. */ 18637 break; 18638 18639 case 7: /* Byte load/store. */ 18640 if (value & ~0x1f) 18641 as_bad_where (fixP->fx_file, fixP->fx_line, 18642 _("invalid offset, value too big (0x%08lX)"), 18643 (long) value); 18644 newval |= value << 6; 18645 break; 18646 18647 case 8: /* Halfword load/store. */ 18648 if (value & ~0x3e) 18649 as_bad_where (fixP->fx_file, fixP->fx_line, 18650 _("invalid offset, value too big (0x%08lX)"), 18651 (long) value); 18652 newval |= value << 5; /* 6 - 1. */ 18653 break; 18654 18655 default: 18656 as_bad_where (fixP->fx_file, fixP->fx_line, 18657 "Unable to process relocation for thumb opcode: %lx", 18658 (unsigned long) newval); 18659 break; 18660 } 18661 md_number_to_chars (buf, newval, THUMB_SIZE); 18662 break; 18663 18664 case BFD_RELOC_ARM_THUMB_ADD: 18665 /* This is a complicated relocation, since we use it for all of 18666 the following immediate relocations: 18667 18668 3bit ADD/SUB 18669 8bit ADD/SUB 18670 9bit ADD/SUB SP word-aligned 18671 10bit ADD PC/SP word-aligned 18672 18673 The type of instruction being processed is encoded in the 18674 instruction field: 18675 18676 0x8000 SUB 18677 0x00F0 Rd 18678 0x000F Rs 18679 */ 18680 newval = md_chars_to_number (buf, THUMB_SIZE); 18681 { 18682 int rd = (newval >> 4) & 0xf; 18683 int rs = newval & 0xf; 18684 int subtract = !!(newval & 0x8000); 18685 18686 /* Check for HI regs, only very restricted cases allowed: 18687 Adjusting SP, and using PC or SP to get an address. */ 18688 if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) 18689 || (rs > 7 && rs != REG_SP && rs != REG_PC)) 18690 as_bad_where (fixP->fx_file, fixP->fx_line, 18691 _("invalid Hi register with immediate")); 18692 18693 /* If value is negative, choose the opposite instruction. */ 18694 if (value < 0) 18695 { 18696 value = -value; 18697 subtract = !subtract; 18698 if (value < 0) 18699 as_bad_where (fixP->fx_file, fixP->fx_line, 18700 _("immediate value out of range")); 18701 } 18702 18703 if (rd == REG_SP) 18704 { 18705 if (value & ~0x1fc) 18706 as_bad_where (fixP->fx_file, fixP->fx_line, 18707 _("invalid immediate for stack address calculation")); 18708 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; 18709 newval |= value >> 2; 18710 } 18711 else if (rs == REG_PC || rs == REG_SP) 18712 { 18713 if (subtract || value & ~0x3fc) 18714 as_bad_where (fixP->fx_file, fixP->fx_line, 18715 _("invalid immediate for address calculation (value = 0x%08lX)"), 18716 (unsigned long) value); 18717 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); 18718 newval |= rd << 8; 18719 newval |= value >> 2; 18720 } 18721 else if (rs == rd) 18722 { 18723 if (value & ~0xff) 18724 as_bad_where (fixP->fx_file, fixP->fx_line, 18725 _("immediate value out of range")); 18726 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; 18727 newval |= (rd << 8) | value; 18728 } 18729 else 18730 { 18731 if (value & ~0x7) 18732 as_bad_where (fixP->fx_file, fixP->fx_line, 18733 _("immediate value out of range")); 18734 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; 18735 newval |= rd | (rs << 3) | (value << 6); 18736 } 18737 } 18738 md_number_to_chars (buf, newval, THUMB_SIZE); 18739 break; 18740 18741 case BFD_RELOC_ARM_THUMB_IMM: 18742 newval = md_chars_to_number (buf, THUMB_SIZE); 18743 if (value < 0 || value > 255) 18744 as_bad_where (fixP->fx_file, fixP->fx_line, 18745 _("invalid immediate: %ld is too large"), 18746 (long) value); 18747 newval |= value; 18748 md_number_to_chars (buf, newval, THUMB_SIZE); 18749 break; 18750 18751 case BFD_RELOC_ARM_THUMB_SHIFT: 18752 /* 5bit shift value (0..32). LSL cannot take 32. */ 18753 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; 18754 temp = newval & 0xf800; 18755 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) 18756 as_bad_where (fixP->fx_file, fixP->fx_line, 18757 _("invalid shift value: %ld"), (long) value); 18758 /* Shifts of zero must be encoded as LSL. */ 18759 if (value == 0) 18760 newval = (newval & 0x003f) | T_OPCODE_LSL_I; 18761 /* Shifts of 32 are encoded as zero. */ 18762 else if (value == 32) 18763 value = 0; 18764 newval |= value << 6; 18765 md_number_to_chars (buf, newval, THUMB_SIZE); 18766 break; 18767 18768 case BFD_RELOC_VTABLE_INHERIT: 18769 case BFD_RELOC_VTABLE_ENTRY: 18770 fixP->fx_done = 0; 18771 return; 18772 18773 case BFD_RELOC_ARM_MOVW: 18774 case BFD_RELOC_ARM_MOVT: 18775 case BFD_RELOC_ARM_THUMB_MOVW: 18776 case BFD_RELOC_ARM_THUMB_MOVT: 18777 if (fixP->fx_done || !seg->use_rela_p) 18778 { 18779 /* REL format relocations are limited to a 16-bit addend. */ 18780 if (!fixP->fx_done) 18781 { 18782 if (value < -0x1000 || value > 0xffff) 18783 as_bad_where (fixP->fx_file, fixP->fx_line, 18784 _("offset too big")); 18785 } 18786 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT 18787 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) 18788 { 18789 value >>= 16; 18790 } 18791 18792 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW 18793 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) 18794 { 18795 newval = get_thumb32_insn (buf); 18796 newval &= 0xfbf08f00; 18797 newval |= (value & 0xf000) << 4; 18798 newval |= (value & 0x0800) << 15; 18799 newval |= (value & 0x0700) << 4; 18800 newval |= (value & 0x00ff); 18801 put_thumb32_insn (buf, newval); 18802 } 18803 else 18804 { 18805 newval = md_chars_to_number (buf, 4); 18806 newval &= 0xfff0f000; 18807 newval |= value & 0x0fff; 18808 newval |= (value & 0xf000) << 4; 18809 md_number_to_chars (buf, newval, 4); 18810 } 18811 } 18812 return; 18813 18814 case BFD_RELOC_ARM_ALU_PC_G0_NC: 18815 case BFD_RELOC_ARM_ALU_PC_G0: 18816 case BFD_RELOC_ARM_ALU_PC_G1_NC: 18817 case BFD_RELOC_ARM_ALU_PC_G1: 18818 case BFD_RELOC_ARM_ALU_PC_G2: 18819 case BFD_RELOC_ARM_ALU_SB_G0_NC: 18820 case BFD_RELOC_ARM_ALU_SB_G0: 18821 case BFD_RELOC_ARM_ALU_SB_G1_NC: 18822 case BFD_RELOC_ARM_ALU_SB_G1: 18823 case BFD_RELOC_ARM_ALU_SB_G2: 18824 assert (!fixP->fx_done); 18825 if (!seg->use_rela_p) 18826 { 18827 bfd_vma insn; 18828 bfd_vma encoded_addend; 18829 bfd_vma addend_abs = abs (value); 18830 18831 /* Check that the absolute value of the addend can be 18832 expressed as an 8-bit constant plus a rotation. */ 18833 encoded_addend = encode_arm_immediate (addend_abs); 18834 if (encoded_addend == (unsigned int) FAIL) 18835 as_bad_where (fixP->fx_file, fixP->fx_line, 18836 _("the offset 0x%08lX is not representable"), 18837 (unsigned long) addend_abs); 18838 18839 /* Extract the instruction. */ 18840 insn = md_chars_to_number (buf, INSN_SIZE); 18841 18842 /* If the addend is positive, use an ADD instruction. 18843 Otherwise use a SUB. Take care not to destroy the S bit. */ 18844 insn &= 0xff1fffff; 18845 if (value < 0) 18846 insn |= 1 << 22; 18847 else 18848 insn |= 1 << 23; 18849 18850 /* Place the encoded addend into the first 12 bits of the 18851 instruction. */ 18852 insn &= 0xfffff000; 18853 insn |= encoded_addend; 18854 18855 /* Update the instruction. */ 18856 md_number_to_chars (buf, insn, INSN_SIZE); 18857 } 18858 break; 18859 18860 case BFD_RELOC_ARM_LDR_PC_G0: 18861 case BFD_RELOC_ARM_LDR_PC_G1: 18862 case BFD_RELOC_ARM_LDR_PC_G2: 18863 case BFD_RELOC_ARM_LDR_SB_G0: 18864 case BFD_RELOC_ARM_LDR_SB_G1: 18865 case BFD_RELOC_ARM_LDR_SB_G2: 18866 assert (!fixP->fx_done); 18867 if (!seg->use_rela_p) 18868 { 18869 bfd_vma insn; 18870 bfd_vma addend_abs = abs (value); 18871 18872 /* Check that the absolute value of the addend can be 18873 encoded in 12 bits. */ 18874 if (addend_abs >= 0x1000) 18875 as_bad_where (fixP->fx_file, fixP->fx_line, 18876 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), 18877 (unsigned long) addend_abs); 18878 18879 /* Extract the instruction. */ 18880 insn = md_chars_to_number (buf, INSN_SIZE); 18881 18882 /* If the addend is negative, clear bit 23 of the instruction. 18883 Otherwise set it. */ 18884 if (value < 0) 18885 insn &= ~(1 << 23); 18886 else 18887 insn |= 1 << 23; 18888 18889 /* Place the absolute value of the addend into the first 12 bits 18890 of the instruction. */ 18891 insn &= 0xfffff000; 18892 insn |= addend_abs; 18893 18894 /* Update the instruction. */ 18895 md_number_to_chars (buf, insn, INSN_SIZE); 18896 } 18897 break; 18898 18899 case BFD_RELOC_ARM_LDRS_PC_G0: 18900 case BFD_RELOC_ARM_LDRS_PC_G1: 18901 case BFD_RELOC_ARM_LDRS_PC_G2: 18902 case BFD_RELOC_ARM_LDRS_SB_G0: 18903 case BFD_RELOC_ARM_LDRS_SB_G1: 18904 case BFD_RELOC_ARM_LDRS_SB_G2: 18905 assert (!fixP->fx_done); 18906 if (!seg->use_rela_p) 18907 { 18908 bfd_vma insn; 18909 bfd_vma addend_abs = abs (value); 18910 18911 /* Check that the absolute value of the addend can be 18912 encoded in 8 bits. */ 18913 if (addend_abs >= 0x100) 18914 as_bad_where (fixP->fx_file, fixP->fx_line, 18915 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), 18916 (unsigned long) addend_abs); 18917 18918 /* Extract the instruction. */ 18919 insn = md_chars_to_number (buf, INSN_SIZE); 18920 18921 /* If the addend is negative, clear bit 23 of the instruction. 18922 Otherwise set it. */ 18923 if (value < 0) 18924 insn &= ~(1 << 23); 18925 else 18926 insn |= 1 << 23; 18927 18928 /* Place the first four bits of the absolute value of the addend 18929 into the first 4 bits of the instruction, and the remaining 18930 four into bits 8 .. 11. */ 18931 insn &= 0xfffff0f0; 18932 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); 18933 18934 /* Update the instruction. */ 18935 md_number_to_chars (buf, insn, INSN_SIZE); 18936 } 18937 break; 18938 18939 case BFD_RELOC_ARM_LDC_PC_G0: 18940 case BFD_RELOC_ARM_LDC_PC_G1: 18941 case BFD_RELOC_ARM_LDC_PC_G2: 18942 case BFD_RELOC_ARM_LDC_SB_G0: 18943 case BFD_RELOC_ARM_LDC_SB_G1: 18944 case BFD_RELOC_ARM_LDC_SB_G2: 18945 assert (!fixP->fx_done); 18946 if (!seg->use_rela_p) 18947 { 18948 bfd_vma insn; 18949 bfd_vma addend_abs = abs (value); 18950 18951 /* Check that the absolute value of the addend is a multiple of 18952 four and, when divided by four, fits in 8 bits. */ 18953 if (addend_abs & 0x3) 18954 as_bad_where (fixP->fx_file, fixP->fx_line, 18955 _("bad offset 0x%08lX (must be word-aligned)"), 18956 (unsigned long) addend_abs); 18957 18958 if ((addend_abs >> 2) > 0xff) 18959 as_bad_where (fixP->fx_file, fixP->fx_line, 18960 _("bad offset 0x%08lX (must be an 8-bit number of words)"), 18961 (unsigned long) addend_abs); 18962 18963 /* Extract the instruction. */ 18964 insn = md_chars_to_number (buf, INSN_SIZE); 18965 18966 /* If the addend is negative, clear bit 23 of the instruction. 18967 Otherwise set it. */ 18968 if (value < 0) 18969 insn &= ~(1 << 23); 18970 else 18971 insn |= 1 << 23; 18972 18973 /* Place the addend (divided by four) into the first eight 18974 bits of the instruction. */ 18975 insn &= 0xfffffff0; 18976 insn |= addend_abs >> 2; 18977 18978 /* Update the instruction. */ 18979 md_number_to_chars (buf, insn, INSN_SIZE); 18980 } 18981 break; 18982 18983 case BFD_RELOC_UNUSED: 18984 default: 18985 as_bad_where (fixP->fx_file, fixP->fx_line, 18986 _("bad relocation fixup type (%d)"), fixP->fx_r_type); 18987 } 18988} 18989 18990/* Translate internal representation of relocation info to BFD target 18991 format. */ 18992 18993arelent * 18994tc_gen_reloc (asection *section, fixS *fixp) 18995{ 18996 arelent * reloc; 18997 bfd_reloc_code_real_type code; 18998 18999 reloc = xmalloc (sizeof (arelent)); 19000 19001 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); 19002 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 19003 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 19004 19005 if (fixp->fx_pcrel) 19006 { 19007 if (section->use_rela_p) 19008 fixp->fx_offset -= md_pcrel_from_section (fixp, section); 19009 else 19010 fixp->fx_offset = reloc->address; 19011 } 19012 reloc->addend = fixp->fx_offset; 19013 19014 switch (fixp->fx_r_type) 19015 { 19016 case BFD_RELOC_8: 19017 if (fixp->fx_pcrel) 19018 { 19019 code = BFD_RELOC_8_PCREL; 19020 break; 19021 } 19022 19023 case BFD_RELOC_16: 19024 if (fixp->fx_pcrel) 19025 { 19026 code = BFD_RELOC_16_PCREL; 19027 break; 19028 } 19029 19030 case BFD_RELOC_32: 19031 if (fixp->fx_pcrel) 19032 { 19033 code = BFD_RELOC_32_PCREL; 19034 break; 19035 } 19036 19037 case BFD_RELOC_ARM_MOVW: 19038 if (fixp->fx_pcrel) 19039 { 19040 code = BFD_RELOC_ARM_MOVW_PCREL; 19041 break; 19042 } 19043 19044 case BFD_RELOC_ARM_MOVT: 19045 if (fixp->fx_pcrel) 19046 { 19047 code = BFD_RELOC_ARM_MOVT_PCREL; 19048 break; 19049 } 19050 19051 case BFD_RELOC_ARM_THUMB_MOVW: 19052 if (fixp->fx_pcrel) 19053 { 19054 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; 19055 break; 19056 } 19057 19058 case BFD_RELOC_ARM_THUMB_MOVT: 19059 if (fixp->fx_pcrel) 19060 { 19061 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; 19062 break; 19063 } 19064 19065 case BFD_RELOC_NONE: 19066 case BFD_RELOC_ARM_PCREL_BRANCH: 19067 case BFD_RELOC_ARM_PCREL_BLX: 19068 case BFD_RELOC_RVA: 19069 case BFD_RELOC_THUMB_PCREL_BRANCH7: 19070 case BFD_RELOC_THUMB_PCREL_BRANCH9: 19071 case BFD_RELOC_THUMB_PCREL_BRANCH12: 19072 case BFD_RELOC_THUMB_PCREL_BRANCH20: 19073 case BFD_RELOC_THUMB_PCREL_BRANCH23: 19074 case BFD_RELOC_THUMB_PCREL_BRANCH25: 19075 case BFD_RELOC_THUMB_PCREL_BLX: 19076 case BFD_RELOC_VTABLE_ENTRY: 19077 case BFD_RELOC_VTABLE_INHERIT: 19078#ifdef TE_PE 19079 case BFD_RELOC_32_SECREL: 19080#endif 19081 code = fixp->fx_r_type; 19082 break; 19083 19084 case BFD_RELOC_ARM_LITERAL: 19085 case BFD_RELOC_ARM_HWLITERAL: 19086 /* If this is called then the a literal has 19087 been referenced across a section boundary. */ 19088 as_bad_where (fixp->fx_file, fixp->fx_line, 19089 _("literal referenced across section boundary")); 19090 return NULL; 19091 19092#ifdef OBJ_ELF 19093 case BFD_RELOC_ARM_GOT32: 19094 case BFD_RELOC_ARM_GOTOFF: 19095 case BFD_RELOC_ARM_PLT32: 19096 case BFD_RELOC_ARM_TARGET1: 19097 case BFD_RELOC_ARM_ROSEGREL32: 19098 case BFD_RELOC_ARM_SBREL32: 19099 case BFD_RELOC_ARM_PREL31: 19100 case BFD_RELOC_ARM_TARGET2: 19101 case BFD_RELOC_ARM_TLS_LE32: 19102 case BFD_RELOC_ARM_TLS_LDO32: 19103 case BFD_RELOC_ARM_PCREL_CALL: 19104 case BFD_RELOC_ARM_PCREL_JUMP: 19105 case BFD_RELOC_ARM_ALU_PC_G0_NC: 19106 case BFD_RELOC_ARM_ALU_PC_G0: 19107 case BFD_RELOC_ARM_ALU_PC_G1_NC: 19108 case BFD_RELOC_ARM_ALU_PC_G1: 19109 case BFD_RELOC_ARM_ALU_PC_G2: 19110 case BFD_RELOC_ARM_LDR_PC_G0: 19111 case BFD_RELOC_ARM_LDR_PC_G1: 19112 case BFD_RELOC_ARM_LDR_PC_G2: 19113 case BFD_RELOC_ARM_LDRS_PC_G0: 19114 case BFD_RELOC_ARM_LDRS_PC_G1: 19115 case BFD_RELOC_ARM_LDRS_PC_G2: 19116 case BFD_RELOC_ARM_LDC_PC_G0: 19117 case BFD_RELOC_ARM_LDC_PC_G1: 19118 case BFD_RELOC_ARM_LDC_PC_G2: 19119 case BFD_RELOC_ARM_ALU_SB_G0_NC: 19120 case BFD_RELOC_ARM_ALU_SB_G0: 19121 case BFD_RELOC_ARM_ALU_SB_G1_NC: 19122 case BFD_RELOC_ARM_ALU_SB_G1: 19123 case BFD_RELOC_ARM_ALU_SB_G2: 19124 case BFD_RELOC_ARM_LDR_SB_G0: 19125 case BFD_RELOC_ARM_LDR_SB_G1: 19126 case BFD_RELOC_ARM_LDR_SB_G2: 19127 case BFD_RELOC_ARM_LDRS_SB_G0: 19128 case BFD_RELOC_ARM_LDRS_SB_G1: 19129 case BFD_RELOC_ARM_LDRS_SB_G2: 19130 case BFD_RELOC_ARM_LDC_SB_G0: 19131 case BFD_RELOC_ARM_LDC_SB_G1: 19132 case BFD_RELOC_ARM_LDC_SB_G2: 19133 code = fixp->fx_r_type; 19134 break; 19135 19136 case BFD_RELOC_ARM_TLS_GD32: 19137 case BFD_RELOC_ARM_TLS_IE32: 19138 case BFD_RELOC_ARM_TLS_LDM32: 19139 /* BFD will include the symbol's address in the addend. 19140 But we don't want that, so subtract it out again here. */ 19141 if (!S_IS_COMMON (fixp->fx_addsy)) 19142 reloc->addend -= (*reloc->sym_ptr_ptr)->value; 19143 code = fixp->fx_r_type; 19144 break; 19145#endif 19146 19147 case BFD_RELOC_ARM_IMMEDIATE: 19148 as_bad_where (fixp->fx_file, fixp->fx_line, 19149 _("internal relocation (type: IMMEDIATE) not fixed up")); 19150 return NULL; 19151 19152 case BFD_RELOC_ARM_ADRL_IMMEDIATE: 19153 as_bad_where (fixp->fx_file, fixp->fx_line, 19154 _("ADRL used for a symbol not defined in the same file")); 19155 return NULL; 19156 19157 case BFD_RELOC_ARM_OFFSET_IMM: 19158 if (section->use_rela_p) 19159 { 19160 code = fixp->fx_r_type; 19161 break; 19162 } 19163 19164 if (fixp->fx_addsy != NULL 19165 && !S_IS_DEFINED (fixp->fx_addsy) 19166 && S_IS_LOCAL (fixp->fx_addsy)) 19167 { 19168 as_bad_where (fixp->fx_file, fixp->fx_line, 19169 _("undefined local label `%s'"), 19170 S_GET_NAME (fixp->fx_addsy)); 19171 return NULL; 19172 } 19173 19174 as_bad_where (fixp->fx_file, fixp->fx_line, 19175 _("internal_relocation (type: OFFSET_IMM) not fixed up")); 19176 return NULL; 19177 19178 default: 19179 { 19180 char * type; 19181 19182 switch (fixp->fx_r_type) 19183 { 19184 case BFD_RELOC_NONE: type = "NONE"; break; 19185 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; 19186 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; 19187 case BFD_RELOC_ARM_SMC: type = "SMC"; break; 19188 case BFD_RELOC_ARM_SWI: type = "SWI"; break; 19189 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; 19190 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; 19191 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; 19192 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; 19193 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; 19194 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; 19195 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; 19196 default: type = _("<unknown>"); break; 19197 } 19198 as_bad_where (fixp->fx_file, fixp->fx_line, 19199 _("cannot represent %s relocation in this object file format"), 19200 type); 19201 return NULL; 19202 } 19203 } 19204 19205#ifdef OBJ_ELF 19206 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) 19207 && GOT_symbol 19208 && fixp->fx_addsy == GOT_symbol) 19209 { 19210 code = BFD_RELOC_ARM_GOTPC; 19211 reloc->addend = fixp->fx_offset = reloc->address; 19212 } 19213#endif 19214 19215 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 19216 19217 if (reloc->howto == NULL) 19218 { 19219 as_bad_where (fixp->fx_file, fixp->fx_line, 19220 _("cannot represent %s relocation in this object file format"), 19221 bfd_get_reloc_code_name (code)); 19222 return NULL; 19223 } 19224 19225 /* HACK: Since arm ELF uses Rel instead of Rela, encode the 19226 vtable entry to be used in the relocation's section offset. */ 19227 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 19228 reloc->address = fixp->fx_offset; 19229 19230 return reloc; 19231} 19232 19233/* This fix_new is called by cons via TC_CONS_FIX_NEW. */ 19234 19235void 19236cons_fix_new_arm (fragS * frag, 19237 int where, 19238 int size, 19239 expressionS * exp) 19240{ 19241 bfd_reloc_code_real_type type; 19242 int pcrel = 0; 19243 19244 /* Pick a reloc. 19245 FIXME: @@ Should look at CPU word size. */ 19246 switch (size) 19247 { 19248 case 1: 19249 type = BFD_RELOC_8; 19250 break; 19251 case 2: 19252 type = BFD_RELOC_16; 19253 break; 19254 case 4: 19255 default: 19256 type = BFD_RELOC_32; 19257 break; 19258 case 8: 19259 type = BFD_RELOC_64; 19260 break; 19261 } 19262 19263#ifdef TE_PE 19264 if (exp->X_op == O_secrel) 19265 { 19266 exp->X_op = O_symbol; 19267 type = BFD_RELOC_32_SECREL; 19268 } 19269#endif 19270 19271 fix_new_exp (frag, where, (int) size, exp, pcrel, type); 19272} 19273 19274#if defined OBJ_COFF || defined OBJ_ELF 19275void 19276arm_validate_fix (fixS * fixP) 19277{ 19278 /* If the destination of the branch is a defined symbol which does not have 19279 the THUMB_FUNC attribute, then we must be calling a function which has 19280 the (interfacearm) attribute. We look for the Thumb entry point to that 19281 function and change the branch to refer to that function instead. */ 19282 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 19283 && fixP->fx_addsy != NULL 19284 && S_IS_DEFINED (fixP->fx_addsy) 19285 && ! THUMB_IS_FUNC (fixP->fx_addsy)) 19286 { 19287 fixP->fx_addsy = find_real_start (fixP->fx_addsy); 19288 } 19289} 19290#endif 19291 19292int 19293arm_force_relocation (struct fix * fixp) 19294{ 19295#if defined (OBJ_COFF) && defined (TE_PE) 19296 if (fixp->fx_r_type == BFD_RELOC_RVA) 19297 return 1; 19298#endif 19299 19300 /* Resolve these relocations even if the symbol is extern or weak. */ 19301 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE 19302 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM 19303 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE 19304 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM 19305 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE 19306 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 19307 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12) 19308 return 0; 19309 19310 /* Always leave these relocations for the linker. */ 19311 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC 19312 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) 19313 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) 19314 return 1; 19315 19316 /* Always generate relocations against function symbols. */ 19317 if (fixp->fx_r_type == BFD_RELOC_32 19318 && fixp->fx_addsy 19319 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) 19320 return 1; 19321 19322 return generic_force_reloc (fixp); 19323} 19324 19325#if defined (OBJ_ELF) || defined (OBJ_COFF) 19326/* Relocations against function names must be left unadjusted, 19327 so that the linker can use this information to generate interworking 19328 stubs. The MIPS version of this function 19329 also prevents relocations that are mips-16 specific, but I do not 19330 know why it does this. 19331 19332 FIXME: 19333 There is one other problem that ought to be addressed here, but 19334 which currently is not: Taking the address of a label (rather 19335 than a function) and then later jumping to that address. Such 19336 addresses also ought to have their bottom bit set (assuming that 19337 they reside in Thumb code), but at the moment they will not. */ 19338 19339bfd_boolean 19340arm_fix_adjustable (fixS * fixP) 19341{ 19342 if (fixP->fx_addsy == NULL) 19343 return 1; 19344 19345 /* Preserve relocations against symbols with function type. */ 19346 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) 19347 return 0; 19348 19349 if (THUMB_IS_FUNC (fixP->fx_addsy) 19350 && fixP->fx_subsy == NULL) 19351 return 0; 19352 19353 /* We need the symbol name for the VTABLE entries. */ 19354 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 19355 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 19356 return 0; 19357 19358 /* Don't allow symbols to be discarded on GOT related relocs. */ 19359 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 19360 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 19361 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF 19362 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 19363 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 19364 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 19365 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 19366 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 19367 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) 19368 return 0; 19369 19370 /* Similarly for group relocations. */ 19371 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC 19372 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) 19373 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) 19374 return 0; 19375 19376 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW 19377 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT 19378 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW 19379 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) 19380 return 0; 19381 19382 return 1; 19383} 19384#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ 19385 19386#ifdef OBJ_ELF 19387 19388const char * 19389elf32_arm_target_format (void) 19390{ 19391#ifdef TE_SYMBIAN 19392 return (target_big_endian 19393 ? "elf32-bigarm-symbian" 19394 : "elf32-littlearm-symbian"); 19395#elif defined (TE_VXWORKS) 19396 return (target_big_endian 19397 ? "elf32-bigarm-vxworks" 19398 : "elf32-littlearm-vxworks"); 19399#else 19400 if (target_big_endian) 19401 return "elf32-bigarm"; 19402 else 19403 return "elf32-littlearm"; 19404#endif 19405} 19406 19407void 19408armelf_frob_symbol (symbolS * symp, 19409 int * puntp) 19410{ 19411 elf_frob_symbol (symp, puntp); 19412} 19413#endif 19414 19415/* MD interface: Finalization. */ 19416 19417/* A good place to do this, although this was probably not intended 19418 for this kind of use. We need to dump the literal pool before 19419 references are made to a null symbol pointer. */ 19420 19421void 19422arm_cleanup (void) 19423{ 19424 literal_pool * pool; 19425 19426 for (pool = list_of_pools; pool; pool = pool->next) 19427 { 19428 /* Put it at the end of the relevent section. */ 19429 subseg_set (pool->section, pool->sub_section); 19430#ifdef OBJ_ELF 19431 arm_elf_change_section (); 19432#endif 19433 s_ltorg (0); 19434 } 19435} 19436 19437/* Adjust the symbol table. This marks Thumb symbols as distinct from 19438 ARM ones. */ 19439 19440void 19441arm_adjust_symtab (void) 19442{ 19443#ifdef OBJ_COFF 19444 symbolS * sym; 19445 19446 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 19447 { 19448 if (ARM_IS_THUMB (sym)) 19449 { 19450 if (THUMB_IS_FUNC (sym)) 19451 { 19452 /* Mark the symbol as a Thumb function. */ 19453 if ( S_GET_STORAGE_CLASS (sym) == C_STAT 19454 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ 19455 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); 19456 19457 else if (S_GET_STORAGE_CLASS (sym) == C_EXT) 19458 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); 19459 else 19460 as_bad (_("%s: unexpected function type: %d"), 19461 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); 19462 } 19463 else switch (S_GET_STORAGE_CLASS (sym)) 19464 { 19465 case C_EXT: 19466 S_SET_STORAGE_CLASS (sym, C_THUMBEXT); 19467 break; 19468 case C_STAT: 19469 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); 19470 break; 19471 case C_LABEL: 19472 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); 19473 break; 19474 default: 19475 /* Do nothing. */ 19476 break; 19477 } 19478 } 19479 19480 if (ARM_IS_INTERWORK (sym)) 19481 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; 19482 } 19483#endif 19484#ifdef OBJ_ELF 19485 symbolS * sym; 19486 char bind; 19487 19488 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 19489 { 19490 if (ARM_IS_THUMB (sym)) 19491 { 19492 elf_symbol_type * elf_sym; 19493 19494 elf_sym = elf_symbol (symbol_get_bfdsym (sym)); 19495 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); 19496 19497 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, 19498 BFD_ARM_SPECIAL_SYM_TYPE_ANY)) 19499 { 19500 /* If it's a .thumb_func, declare it as so, 19501 otherwise tag label as .code 16. */ 19502 if (THUMB_IS_FUNC (sym)) 19503 elf_sym->internal_elf_sym.st_info = 19504 ELF_ST_INFO (bind, STT_ARM_TFUNC); 19505 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) 19506 elf_sym->internal_elf_sym.st_info = 19507 ELF_ST_INFO (bind, STT_ARM_16BIT); 19508 } 19509 } 19510 } 19511#endif 19512} 19513 19514/* MD interface: Initialization. */ 19515 19516static void 19517set_constant_flonums (void) 19518{ 19519 int i; 19520 19521 for (i = 0; i < NUM_FLOAT_VALS; i++) 19522 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) 19523 abort (); 19524} 19525 19526/* Auto-select Thumb mode if it's the only available instruction set for the 19527 given architecture. */ 19528 19529static void 19530autoselect_thumb_from_cpu_variant (void) 19531{ 19532 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 19533 opcode_select (16); 19534} 19535 19536void 19537md_begin (void) 19538{ 19539 unsigned mach; 19540 unsigned int i; 19541 19542 if ( (arm_ops_hsh = hash_new ()) == NULL 19543 || (arm_cond_hsh = hash_new ()) == NULL 19544 || (arm_shift_hsh = hash_new ()) == NULL 19545 || (arm_psr_hsh = hash_new ()) == NULL 19546 || (arm_v7m_psr_hsh = hash_new ()) == NULL 19547 || (arm_reg_hsh = hash_new ()) == NULL 19548 || (arm_reloc_hsh = hash_new ()) == NULL 19549 || (arm_barrier_opt_hsh = hash_new ()) == NULL) 19550 as_fatal (_("virtual memory exhausted")); 19551 19552 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) 19553 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i)); 19554 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) 19555 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i)); 19556 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) 19557 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i)); 19558 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) 19559 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i)); 19560 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) 19561 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template, (PTR) (v7m_psrs + i)); 19562 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) 19563 hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i)); 19564 for (i = 0; 19565 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); 19566 i++) 19567 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template, 19568 (PTR) (barrier_opt_names + i)); 19569#ifdef OBJ_ELF 19570 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++) 19571 hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i)); 19572#endif 19573 19574 set_constant_flonums (); 19575 19576 /* Set the cpu variant based on the command-line options. We prefer 19577 -mcpu= over -march= if both are set (as for GCC); and we prefer 19578 -mfpu= over any other way of setting the floating point unit. 19579 Use of legacy options with new options are faulted. */ 19580 if (legacy_cpu) 19581 { 19582 if (mcpu_cpu_opt || march_cpu_opt) 19583 as_bad (_("use of old and new-style options to set CPU type")); 19584 19585 mcpu_cpu_opt = legacy_cpu; 19586 } 19587 else if (!mcpu_cpu_opt) 19588 mcpu_cpu_opt = march_cpu_opt; 19589 19590 if (legacy_fpu) 19591 { 19592 if (mfpu_opt) 19593 as_bad (_("use of old and new-style options to set FPU type")); 19594 19595 mfpu_opt = legacy_fpu; 19596 } 19597 else if (!mfpu_opt) 19598 { 19599#if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS)) 19600 /* Some environments specify a default FPU. If they don't, infer it 19601 from the processor. */ 19602 if (mcpu_fpu_opt) 19603 mfpu_opt = mcpu_fpu_opt; 19604 else 19605 mfpu_opt = march_fpu_opt; 19606#else 19607 mfpu_opt = &fpu_default; 19608#endif 19609 } 19610 19611 if (!mfpu_opt) 19612 { 19613 if (mcpu_cpu_opt != NULL) 19614 mfpu_opt = &fpu_default; 19615 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) 19616 mfpu_opt = &fpu_arch_vfp_v2; 19617 else 19618 mfpu_opt = &fpu_arch_fpa; 19619 } 19620 19621#ifdef CPU_DEFAULT 19622 if (!mcpu_cpu_opt) 19623 { 19624 mcpu_cpu_opt = &cpu_default; 19625 selected_cpu = cpu_default; 19626 } 19627#else 19628 if (mcpu_cpu_opt) 19629 selected_cpu = *mcpu_cpu_opt; 19630 else 19631 mcpu_cpu_opt = &arm_arch_any; 19632#endif 19633 19634 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 19635 19636 autoselect_thumb_from_cpu_variant (); 19637 19638 arm_arch_used = thumb_arch_used = arm_arch_none; 19639 19640#if defined OBJ_COFF || defined OBJ_ELF 19641 { 19642 unsigned int flags = 0; 19643 19644#if defined OBJ_ELF 19645 flags = meabi_flags; 19646 19647 switch (meabi_flags) 19648 { 19649 case EF_ARM_EABI_UNKNOWN: 19650#endif 19651 /* Set the flags in the private structure. */ 19652 if (uses_apcs_26) flags |= F_APCS26; 19653 if (support_interwork) flags |= F_INTERWORK; 19654 if (uses_apcs_float) flags |= F_APCS_FLOAT; 19655 if (pic_code) flags |= F_PIC; 19656 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) 19657 flags |= F_SOFT_FLOAT; 19658 19659 switch (mfloat_abi_opt) 19660 { 19661 case ARM_FLOAT_ABI_SOFT: 19662 case ARM_FLOAT_ABI_SOFTFP: 19663 flags |= F_SOFT_FLOAT; 19664 break; 19665 19666 case ARM_FLOAT_ABI_HARD: 19667 if (flags & F_SOFT_FLOAT) 19668 as_bad (_("hard-float conflicts with specified fpu")); 19669 break; 19670 } 19671 19672 /* Using pure-endian doubles (even if soft-float). */ 19673 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) 19674 flags |= F_VFP_FLOAT; 19675 19676#if defined OBJ_ELF 19677 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) 19678 flags |= EF_ARM_MAVERICK_FLOAT; 19679 break; 19680 19681 case EF_ARM_EABI_VER4: 19682 case EF_ARM_EABI_VER5: 19683 /* No additional flags to set. */ 19684 break; 19685 19686 default: 19687 abort (); 19688 } 19689#endif 19690 bfd_set_private_flags (stdoutput, flags); 19691 19692 /* We have run out flags in the COFF header to encode the 19693 status of ATPCS support, so instead we create a dummy, 19694 empty, debug section called .arm.atpcs. */ 19695 if (atpcs) 19696 { 19697 asection * sec; 19698 19699 sec = bfd_make_section (stdoutput, ".arm.atpcs"); 19700 19701 if (sec != NULL) 19702 { 19703 bfd_set_section_flags 19704 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); 19705 bfd_set_section_size (stdoutput, sec, 0); 19706 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); 19707 } 19708 } 19709 } 19710#endif 19711 19712 /* Record the CPU type as well. */ 19713 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) 19714 mach = bfd_mach_arm_iWMMXt2; 19715 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) 19716 mach = bfd_mach_arm_iWMMXt; 19717 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) 19718 mach = bfd_mach_arm_XScale; 19719 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) 19720 mach = bfd_mach_arm_ep9312; 19721 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) 19722 mach = bfd_mach_arm_5TE; 19723 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) 19724 { 19725 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 19726 mach = bfd_mach_arm_5T; 19727 else 19728 mach = bfd_mach_arm_5; 19729 } 19730 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) 19731 { 19732 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 19733 mach = bfd_mach_arm_4T; 19734 else 19735 mach = bfd_mach_arm_4; 19736 } 19737 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) 19738 mach = bfd_mach_arm_3M; 19739 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) 19740 mach = bfd_mach_arm_3; 19741 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) 19742 mach = bfd_mach_arm_2a; 19743 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) 19744 mach = bfd_mach_arm_2; 19745 else 19746 mach = bfd_mach_arm_unknown; 19747 19748 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); 19749} 19750 19751/* Command line processing. */ 19752 19753/* md_parse_option 19754 Invocation line includes a switch not recognized by the base assembler. 19755 See if it's a processor-specific option. 19756 19757 This routine is somewhat complicated by the need for backwards 19758 compatibility (since older releases of gcc can't be changed). 19759 The new options try to make the interface as compatible as 19760 possible with GCC. 19761 19762 New options (supported) are: 19763 19764 -mcpu=<cpu name> Assemble for selected processor 19765 -march=<architecture name> Assemble for selected architecture 19766 -mfpu=<fpu architecture> Assemble for selected FPU. 19767 -EB/-mbig-endian Big-endian 19768 -EL/-mlittle-endian Little-endian 19769 -k Generate PIC code 19770 -mthumb Start in Thumb mode 19771 -mthumb-interwork Code supports ARM/Thumb interworking 19772 19773 For now we will also provide support for: 19774 19775 -mapcs-32 32-bit Program counter 19776 -mapcs-26 26-bit Program counter 19777 -macps-float Floats passed in FP registers 19778 -mapcs-reentrant Reentrant code 19779 -matpcs 19780 (sometime these will probably be replaced with -mapcs=<list of options> 19781 and -matpcs=<list of options>) 19782 19783 The remaining options are only supported for back-wards compatibility. 19784 Cpu variants, the arm part is optional: 19785 -m[arm]1 Currently not supported. 19786 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor 19787 -m[arm]3 Arm 3 processor 19788 -m[arm]6[xx], Arm 6 processors 19789 -m[arm]7[xx][t][[d]m] Arm 7 processors 19790 -m[arm]8[10] Arm 8 processors 19791 -m[arm]9[20][tdmi] Arm 9 processors 19792 -mstrongarm[110[0]] StrongARM processors 19793 -mxscale XScale processors 19794 -m[arm]v[2345[t[e]]] Arm architectures 19795 -mall All (except the ARM1) 19796 FP variants: 19797 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions 19798 -mfpe-old (No float load/store multiples) 19799 -mvfpxd VFP Single precision 19800 -mvfp All VFP 19801 -mno-fpu Disable all floating point instructions 19802 19803 The following CPU names are recognized: 19804 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, 19805 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, 19806 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, 19807 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, 19808 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, 19809 arm10t arm10e, arm1020t, arm1020e, arm10200e, 19810 strongarm, strongarm110, strongarm1100, strongarm1110, xscale. 19811 19812 */ 19813 19814const char * md_shortopts = "m:k"; 19815 19816#ifdef ARM_BI_ENDIAN 19817#define OPTION_EB (OPTION_MD_BASE + 0) 19818#define OPTION_EL (OPTION_MD_BASE + 1) 19819#else 19820#if TARGET_BYTES_BIG_ENDIAN 19821#define OPTION_EB (OPTION_MD_BASE + 0) 19822#else 19823#define OPTION_EL (OPTION_MD_BASE + 1) 19824#endif 19825#endif 19826 19827struct option md_longopts[] = 19828{ 19829#ifdef OPTION_EB 19830 {"EB", no_argument, NULL, OPTION_EB}, 19831#endif 19832#ifdef OPTION_EL 19833 {"EL", no_argument, NULL, OPTION_EL}, 19834#endif 19835 {NULL, no_argument, NULL, 0} 19836}; 19837 19838size_t md_longopts_size = sizeof (md_longopts); 19839 19840struct arm_option_table 19841{ 19842 char *option; /* Option name to match. */ 19843 char *help; /* Help information. */ 19844 int *var; /* Variable to change. */ 19845 int value; /* What to change it to. */ 19846 char *deprecated; /* If non-null, print this message. */ 19847}; 19848 19849struct arm_option_table arm_opts[] = 19850{ 19851 {"k", N_("generate PIC code"), &pic_code, 1, NULL}, 19852 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, 19853 {"mthumb-interwork", N_("support ARM/Thumb interworking"), 19854 &support_interwork, 1, NULL}, 19855 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, 19856 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, 19857 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, 19858 1, NULL}, 19859 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, 19860 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, 19861 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, 19862 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, 19863 NULL}, 19864 19865 /* These are recognized by the assembler, but have no affect on code. */ 19866 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, 19867 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, 19868 {NULL, NULL, NULL, 0, NULL} 19869}; 19870 19871struct arm_legacy_option_table 19872{ 19873 char *option; /* Option name to match. */ 19874 const arm_feature_set **var; /* Variable to change. */ 19875 const arm_feature_set value; /* What to change it to. */ 19876 char *deprecated; /* If non-null, print this message. */ 19877}; 19878 19879const struct arm_legacy_option_table arm_legacy_opts[] = 19880{ 19881 /* DON'T add any new processors to this list -- we want the whole list 19882 to go away... Add them to the processors table instead. */ 19883 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, 19884 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, 19885 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, 19886 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, 19887 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, 19888 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, 19889 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, 19890 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, 19891 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, 19892 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, 19893 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, 19894 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, 19895 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, 19896 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, 19897 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, 19898 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, 19899 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, 19900 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, 19901 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, 19902 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, 19903 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, 19904 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, 19905 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, 19906 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, 19907 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, 19908 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, 19909 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, 19910 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, 19911 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, 19912 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, 19913 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, 19914 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, 19915 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, 19916 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, 19917 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, 19918 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, 19919 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, 19920 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, 19921 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, 19922 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, 19923 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, 19924 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, 19925 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, 19926 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, 19927 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, 19928 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, 19929 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19930 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19931 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19932 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19933 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, 19934 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, 19935 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, 19936 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, 19937 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, 19938 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, 19939 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, 19940 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, 19941 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, 19942 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, 19943 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, 19944 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, 19945 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, 19946 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, 19947 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, 19948 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, 19949 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, 19950 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, 19951 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, 19952 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, 19953 N_("use -mcpu=strongarm110")}, 19954 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, 19955 N_("use -mcpu=strongarm1100")}, 19956 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, 19957 N_("use -mcpu=strongarm1110")}, 19958 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, 19959 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, 19960 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, 19961 19962 /* Architecture variants -- don't add any more to this list either. */ 19963 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, 19964 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, 19965 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, 19966 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, 19967 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, 19968 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, 19969 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, 19970 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, 19971 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, 19972 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, 19973 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, 19974 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, 19975 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, 19976 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, 19977 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, 19978 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, 19979 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, 19980 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, 19981 19982 /* Floating point variants -- don't add any more to this list either. */ 19983 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, 19984 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, 19985 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, 19986 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, 19987 N_("use either -mfpu=softfpa or -mfpu=softvfp")}, 19988 19989 {NULL, NULL, ARM_ARCH_NONE, NULL} 19990}; 19991 19992struct arm_cpu_option_table 19993{ 19994 char *name; 19995 const arm_feature_set value; 19996 /* For some CPUs we assume an FPU unless the user explicitly sets 19997 -mfpu=... */ 19998 const arm_feature_set default_fpu; 19999 /* The canonical name of the CPU, or NULL to use NAME converted to upper 20000 case. */ 20001 const char *canonical_name; 20002}; 20003 20004/* This list should, at a minimum, contain all the cpu names 20005 recognized by GCC. */ 20006static const struct arm_cpu_option_table arm_cpus[] = 20007{ 20008 {"all", ARM_ANY, FPU_ARCH_FPA, NULL}, 20009 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL}, 20010 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL}, 20011 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, 20012 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, 20013 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20014 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20015 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20016 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20017 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20018 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20019 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 20020 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20021 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 20022 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20023 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 20024 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20025 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20026 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20027 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20028 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20029 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20030 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20031 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20032 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20033 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20034 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20035 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20036 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20037 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20038 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20039 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20040 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20041 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20042 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20043 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20044 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20045 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20046 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20047 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"}, 20048 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20049 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20050 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20051 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20052 /* For V5 or later processors we default to using VFP; but the user 20053 should really set the FPU type explicitly. */ 20054 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 20055 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20056 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, 20057 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, 20058 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, 20059 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 20060 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"}, 20061 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20062 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 20063 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"}, 20064 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20065 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20066 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 20067 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 20068 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20069 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"}, 20070 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 20071 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20072 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20073 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"}, 20074 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, 20075 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"}, 20076 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL}, 20077 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"}, 20078 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL}, 20079 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL}, 20080 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL}, 20081 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL}, 20082 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL}, 20083 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL}, 20084 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL}, 20085 {"cortex-a8", ARM_ARCH_V7A, ARM_FEATURE(0, FPU_VFP_V3 20086 | FPU_NEON_EXT_V1), 20087 NULL}, 20088 {"cortex-a9", ARM_ARCH_V7A, ARM_FEATURE(0, FPU_VFP_V3 20089 | FPU_NEON_EXT_V1), 20090 NULL}, 20091 {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, NULL}, 20092 {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, NULL}, 20093 /* ??? XSCALE is really an architecture. */ 20094 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, 20095 /* ??? iwmmxt is not a processor. */ 20096 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL}, 20097 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL}, 20098 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, 20099 /* Maverick */ 20100 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"}, 20101 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL} 20102}; 20103 20104struct arm_arch_option_table 20105{ 20106 char *name; 20107 const arm_feature_set value; 20108 const arm_feature_set default_fpu; 20109}; 20110 20111/* This list should, at a minimum, contain all the architecture names 20112 recognized by GCC. */ 20113static const struct arm_arch_option_table arm_archs[] = 20114{ 20115 {"all", ARM_ANY, FPU_ARCH_FPA}, 20116 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA}, 20117 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA}, 20118 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA}, 20119 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA}, 20120 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA}, 20121 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA}, 20122 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA}, 20123 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA}, 20124 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA}, 20125 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA}, 20126 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP}, 20127 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP}, 20128 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP}, 20129 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP}, 20130 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP}, 20131 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP}, 20132 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP}, 20133 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP}, 20134 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP}, 20135 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP}, 20136 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP}, 20137 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP}, 20138 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP}, 20139 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP}, 20140 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP}, 20141 {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP}, 20142 /* The official spelling of the ARMv7 profile variants is the dashed form. 20143 Accept the non-dashed form for compatibility with old toolchains. */ 20144 {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP}, 20145 {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP}, 20146 {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP}, 20147 {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP}, 20148 {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP}, 20149 {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP}, 20150 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP}, 20151 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP}, 20152 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP}, 20153 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE} 20154}; 20155 20156/* ISA extensions in the co-processor space. */ 20157struct arm_option_cpu_value_table 20158{ 20159 char *name; 20160 const arm_feature_set value; 20161}; 20162 20163static const struct arm_option_cpu_value_table arm_extensions[] = 20164{ 20165 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)}, 20166 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)}, 20167 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)}, 20168 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2)}, 20169 {"sec", ARM_FEATURE (ARM_EXT_V6Z, 0)}, 20170 {NULL, ARM_ARCH_NONE} 20171}; 20172 20173/* This list should, at a minimum, contain all the fpu names 20174 recognized by GCC. */ 20175static const struct arm_option_cpu_value_table arm_fpus[] = 20176{ 20177 {"softfpa", FPU_NONE}, 20178 {"fpe", FPU_ARCH_FPE}, 20179 {"fpe2", FPU_ARCH_FPE}, 20180 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ 20181 {"fpa", FPU_ARCH_FPA}, 20182 {"fpa10", FPU_ARCH_FPA}, 20183 {"fpa11", FPU_ARCH_FPA}, 20184 {"arm7500fe", FPU_ARCH_FPA}, 20185 {"softvfp", FPU_ARCH_VFP}, 20186 {"softvfp+vfp", FPU_ARCH_VFP_V2}, 20187 {"vfp", FPU_ARCH_VFP_V2}, 20188 {"vfpv2", FPU_ARCH_VFP_V2}, 20189 {"vfp9", FPU_ARCH_VFP_V2}, 20190 {"vfp3", FPU_ARCH_VFP_V3}, 20191 {"vfpv3", FPU_ARCH_VFP_V3}, 20192 {"vfp10", FPU_ARCH_VFP_V2}, 20193 {"vfp10-r0", FPU_ARCH_VFP_V1}, 20194 {"vfpxd", FPU_ARCH_VFP_V1xD}, 20195 {"arm1020t", FPU_ARCH_VFP_V1}, 20196 {"arm1020e", FPU_ARCH_VFP_V2}, 20197 {"arm1136jfs", FPU_ARCH_VFP_V2}, 20198 {"arm1136jf-s", FPU_ARCH_VFP_V2}, 20199 {"maverick", FPU_ARCH_MAVERICK}, 20200 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, 20201 {NULL, ARM_ARCH_NONE} 20202}; 20203 20204struct arm_option_value_table 20205{ 20206 char *name; 20207 long value; 20208}; 20209 20210static const struct arm_option_value_table arm_float_abis[] = 20211{ 20212 {"hard", ARM_FLOAT_ABI_HARD}, 20213 {"softfp", ARM_FLOAT_ABI_SOFTFP}, 20214 {"soft", ARM_FLOAT_ABI_SOFT}, 20215 {NULL, 0} 20216}; 20217 20218#ifdef OBJ_ELF 20219/* We only know how to output GNU and ver 4/5 (AAELF) formats. */ 20220static const struct arm_option_value_table arm_eabis[] = 20221{ 20222 {"gnu", EF_ARM_EABI_UNKNOWN}, 20223 {"4", EF_ARM_EABI_VER4}, 20224 {"5", EF_ARM_EABI_VER5}, 20225 {NULL, 0} 20226}; 20227#endif 20228 20229struct arm_long_option_table 20230{ 20231 char * option; /* Substring to match. */ 20232 char * help; /* Help information. */ 20233 int (* func) (char * subopt); /* Function to decode sub-option. */ 20234 char * deprecated; /* If non-null, print this message. */ 20235}; 20236 20237static int 20238arm_parse_extension (char * str, const arm_feature_set **opt_p) 20239{ 20240 arm_feature_set *ext_set = xmalloc (sizeof (arm_feature_set)); 20241 20242 /* Copy the feature set, so that we can modify it. */ 20243 *ext_set = **opt_p; 20244 *opt_p = ext_set; 20245 20246 while (str != NULL && *str != 0) 20247 { 20248 const struct arm_option_cpu_value_table * opt; 20249 char * ext; 20250 int optlen; 20251 20252 if (*str != '+') 20253 { 20254 as_bad (_("invalid architectural extension")); 20255 return 0; 20256 } 20257 20258 str++; 20259 ext = strchr (str, '+'); 20260 20261 if (ext != NULL) 20262 optlen = ext - str; 20263 else 20264 optlen = strlen (str); 20265 20266 if (optlen == 0) 20267 { 20268 as_bad (_("missing architectural extension")); 20269 return 0; 20270 } 20271 20272 for (opt = arm_extensions; opt->name != NULL; opt++) 20273 if (strncmp (opt->name, str, optlen) == 0) 20274 { 20275 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); 20276 break; 20277 } 20278 20279 if (opt->name == NULL) 20280 { 20281 as_bad (_("unknown architectural extnsion `%s'"), str); 20282 return 0; 20283 } 20284 20285 str = ext; 20286 }; 20287 20288 return 1; 20289} 20290 20291static int 20292arm_parse_cpu (char * str) 20293{ 20294 const struct arm_cpu_option_table * opt; 20295 char * ext = strchr (str, '+'); 20296 int optlen; 20297 20298 if (ext != NULL) 20299 optlen = ext - str; 20300 else 20301 optlen = strlen (str); 20302 20303 if (optlen == 0) 20304 { 20305 as_bad (_("missing cpu name `%s'"), str); 20306 return 0; 20307 } 20308 20309 for (opt = arm_cpus; opt->name != NULL; opt++) 20310 if (strncmp (opt->name, str, optlen) == 0) 20311 { 20312 mcpu_cpu_opt = &opt->value; 20313 mcpu_fpu_opt = &opt->default_fpu; 20314 if (opt->canonical_name) 20315 strcpy(selected_cpu_name, opt->canonical_name); 20316 else 20317 { 20318 int i; 20319 for (i = 0; i < optlen; i++) 20320 selected_cpu_name[i] = TOUPPER (opt->name[i]); 20321 selected_cpu_name[i] = 0; 20322 } 20323 20324 if (ext != NULL) 20325 return arm_parse_extension (ext, &mcpu_cpu_opt); 20326 20327 return 1; 20328 } 20329 20330 as_bad (_("unknown cpu `%s'"), str); 20331 return 0; 20332} 20333 20334static int 20335arm_parse_arch (char * str) 20336{ 20337 const struct arm_arch_option_table *opt; 20338 char *ext = strchr (str, '+'); 20339 int optlen; 20340 20341 if (ext != NULL) 20342 optlen = ext - str; 20343 else 20344 optlen = strlen (str); 20345 20346 if (optlen == 0) 20347 { 20348 as_bad (_("missing architecture name `%s'"), str); 20349 return 0; 20350 } 20351 20352 for (opt = arm_archs; opt->name != NULL; opt++) 20353 if (strncmp (opt->name, str, optlen) == 0) 20354 { 20355 march_cpu_opt = &opt->value; 20356 march_fpu_opt = &opt->default_fpu; 20357 strcpy(selected_cpu_name, opt->name); 20358 20359 if (ext != NULL) 20360 return arm_parse_extension (ext, &march_cpu_opt); 20361 20362 return 1; 20363 } 20364 20365 as_bad (_("unknown architecture `%s'\n"), str); 20366 return 0; 20367} 20368 20369static int 20370arm_parse_fpu (char * str) 20371{ 20372 const struct arm_option_cpu_value_table * opt; 20373 20374 for (opt = arm_fpus; opt->name != NULL; opt++) 20375 if (streq (opt->name, str)) 20376 { 20377 mfpu_opt = &opt->value; 20378 return 1; 20379 } 20380 20381 as_bad (_("unknown floating point format `%s'\n"), str); 20382 return 0; 20383} 20384 20385static int 20386arm_parse_float_abi (char * str) 20387{ 20388 const struct arm_option_value_table * opt; 20389 20390 for (opt = arm_float_abis; opt->name != NULL; opt++) 20391 if (streq (opt->name, str)) 20392 { 20393 mfloat_abi_opt = opt->value; 20394 return 1; 20395 } 20396 20397 as_bad (_("unknown floating point abi `%s'\n"), str); 20398 return 0; 20399} 20400 20401#ifdef OBJ_ELF 20402static int 20403arm_parse_eabi (char * str) 20404{ 20405 const struct arm_option_value_table *opt; 20406 20407 for (opt = arm_eabis; opt->name != NULL; opt++) 20408 if (streq (opt->name, str)) 20409 { 20410 meabi_flags = opt->value; 20411 return 1; 20412 } 20413 as_bad (_("unknown EABI `%s'\n"), str); 20414 return 0; 20415} 20416#endif 20417 20418struct arm_long_option_table arm_long_opts[] = 20419{ 20420 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), 20421 arm_parse_cpu, NULL}, 20422 {"march=", N_("<arch name>\t assemble for architecture <arch name>"), 20423 arm_parse_arch, NULL}, 20424 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), 20425 arm_parse_fpu, NULL}, 20426 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), 20427 arm_parse_float_abi, NULL}, 20428#ifdef OBJ_ELF 20429 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"), 20430 arm_parse_eabi, NULL}, 20431#endif 20432 {NULL, NULL, 0, NULL} 20433}; 20434 20435int 20436md_parse_option (int c, char * arg) 20437{ 20438 struct arm_option_table *opt; 20439 const struct arm_legacy_option_table *fopt; 20440 struct arm_long_option_table *lopt; 20441 20442 switch (c) 20443 { 20444#ifdef OPTION_EB 20445 case OPTION_EB: 20446 target_big_endian = 1; 20447 break; 20448#endif 20449 20450#ifdef OPTION_EL 20451 case OPTION_EL: 20452 target_big_endian = 0; 20453 break; 20454#endif 20455 20456 case 'a': 20457 /* Listing option. Just ignore these, we don't support additional 20458 ones. */ 20459 return 0; 20460 20461 default: 20462 for (opt = arm_opts; opt->option != NULL; opt++) 20463 { 20464 if (c == opt->option[0] 20465 && ((arg == NULL && opt->option[1] == 0) 20466 || streq (arg, opt->option + 1))) 20467 { 20468#if WARN_DEPRECATED 20469 /* If the option is deprecated, tell the user. */ 20470 if (opt->deprecated != NULL) 20471 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, 20472 arg ? arg : "", _(opt->deprecated)); 20473#endif 20474 20475 if (opt->var != NULL) 20476 *opt->var = opt->value; 20477 20478 return 1; 20479 } 20480 } 20481 20482 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) 20483 { 20484 if (c == fopt->option[0] 20485 && ((arg == NULL && fopt->option[1] == 0) 20486 || streq (arg, fopt->option + 1))) 20487 { 20488#if WARN_DEPRECATED 20489 /* If the option is deprecated, tell the user. */ 20490 if (fopt->deprecated != NULL) 20491 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, 20492 arg ? arg : "", _(fopt->deprecated)); 20493#endif 20494 20495 if (fopt->var != NULL) 20496 *fopt->var = &fopt->value; 20497 20498 return 1; 20499 } 20500 } 20501 20502 for (lopt = arm_long_opts; lopt->option != NULL; lopt++) 20503 { 20504 /* These options are expected to have an argument. */ 20505 if (c == lopt->option[0] 20506 && arg != NULL 20507 && strncmp (arg, lopt->option + 1, 20508 strlen (lopt->option + 1)) == 0) 20509 { 20510#if WARN_DEPRECATED 20511 /* If the option is deprecated, tell the user. */ 20512 if (lopt->deprecated != NULL) 20513 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, 20514 _(lopt->deprecated)); 20515#endif 20516 20517 /* Call the sup-option parser. */ 20518 return lopt->func (arg + strlen (lopt->option) - 1); 20519 } 20520 } 20521 20522 return 0; 20523 } 20524 20525 return 1; 20526} 20527 20528void 20529md_show_usage (FILE * fp) 20530{ 20531 struct arm_option_table *opt; 20532 struct arm_long_option_table *lopt; 20533 20534 fprintf (fp, _(" ARM-specific assembler options:\n")); 20535 20536 for (opt = arm_opts; opt->option != NULL; opt++) 20537 if (opt->help != NULL) 20538 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); 20539 20540 for (lopt = arm_long_opts; lopt->option != NULL; lopt++) 20541 if (lopt->help != NULL) 20542 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); 20543 20544#ifdef OPTION_EB 20545 fprintf (fp, _("\ 20546 -EB assemble code for a big-endian cpu\n")); 20547#endif 20548 20549#ifdef OPTION_EL 20550 fprintf (fp, _("\ 20551 -EL assemble code for a little-endian cpu\n")); 20552#endif 20553} 20554 20555 20556#ifdef OBJ_ELF 20557typedef struct 20558{ 20559 int val; 20560 arm_feature_set flags; 20561} cpu_arch_ver_table; 20562 20563/* Mapping from CPU features to EABI CPU arch values. Table must be sorted 20564 least features first. */ 20565static const cpu_arch_ver_table cpu_arch_ver[] = 20566{ 20567 {1, ARM_ARCH_V4}, 20568 {2, ARM_ARCH_V4T}, 20569 {3, ARM_ARCH_V5}, 20570 {4, ARM_ARCH_V5TE}, 20571 {5, ARM_ARCH_V5TEJ}, 20572 {6, ARM_ARCH_V6}, 20573 {7, ARM_ARCH_V6Z}, 20574 {8, ARM_ARCH_V6K}, 20575 {9, ARM_ARCH_V6T2}, 20576 {10, ARM_ARCH_V7A}, 20577 {10, ARM_ARCH_V7R}, 20578 {10, ARM_ARCH_V7M}, 20579 {0, ARM_ARCH_NONE} 20580}; 20581 20582/* Set the public EABI object attributes. */ 20583static void 20584aeabi_set_public_attributes (void) 20585{ 20586 int arch; 20587 arm_feature_set flags; 20588 arm_feature_set tmp; 20589 const cpu_arch_ver_table *p; 20590 20591 /* Choose the architecture based on the capabilities of the requested cpu 20592 (if any) and/or the instructions actually used. */ 20593 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); 20594 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); 20595 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); 20596 /*Allow the user to override the reported architecture. */ 20597 if (object_arch) 20598 { 20599 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); 20600 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); 20601 } 20602 20603 tmp = flags; 20604 arch = 0; 20605 for (p = cpu_arch_ver; p->val; p++) 20606 { 20607 if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) 20608 { 20609 arch = p->val; 20610 ARM_CLEAR_FEATURE (tmp, tmp, p->flags); 20611 } 20612 } 20613 20614 /* Tag_CPU_name. */ 20615 if (selected_cpu_name[0]) 20616 { 20617 char *p; 20618 20619 p = selected_cpu_name; 20620 if (strncmp(p, "armv", 4) == 0) 20621 { 20622 int i; 20623 20624 p += 4; 20625 for (i = 0; p[i]; i++) 20626 p[i] = TOUPPER (p[i]); 20627 } 20628 bfd_elf_add_proc_attr_string (stdoutput, 5, p); 20629 } 20630 /* Tag_CPU_arch. */ 20631 bfd_elf_add_proc_attr_int (stdoutput, 6, arch); 20632 /* Tag_CPU_arch_profile. */ 20633 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) 20634 bfd_elf_add_proc_attr_int (stdoutput, 7, 'A'); 20635 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) 20636 bfd_elf_add_proc_attr_int (stdoutput, 7, 'R'); 20637 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)) 20638 bfd_elf_add_proc_attr_int (stdoutput, 7, 'M'); 20639 /* Tag_ARM_ISA_use. */ 20640 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full)) 20641 bfd_elf_add_proc_attr_int (stdoutput, 8, 1); 20642 /* Tag_THUMB_ISA_use. */ 20643 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full)) 20644 bfd_elf_add_proc_attr_int (stdoutput, 9, 20645 ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1); 20646 /* Tag_VFP_arch. */ 20647 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v3) 20648 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v3)) 20649 bfd_elf_add_proc_attr_int (stdoutput, 10, 3); 20650 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v2) 20651 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v2)) 20652 bfd_elf_add_proc_attr_int (stdoutput, 10, 2); 20653 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1) 20654 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1) 20655 || ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1xd) 20656 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1xd)) 20657 bfd_elf_add_proc_attr_int (stdoutput, 10, 1); 20658 /* Tag_WMMX_arch. */ 20659 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt) 20660 || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt)) 20661 bfd_elf_add_proc_attr_int (stdoutput, 11, 1); 20662 /* Tag_NEON_arch. */ 20663 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_neon_ext_v1) 20664 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_neon_ext_v1)) 20665 bfd_elf_add_proc_attr_int (stdoutput, 12, 1); 20666} 20667 20668/* Add the default contents for the .ARM.attributes section. */ 20669void 20670arm_md_end (void) 20671{ 20672 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) 20673 return; 20674 20675 aeabi_set_public_attributes (); 20676} 20677#endif /* OBJ_ELF */ 20678 20679 20680/* Parse a .cpu directive. */ 20681 20682static void 20683s_arm_cpu (int ignored ATTRIBUTE_UNUSED) 20684{ 20685 const struct arm_cpu_option_table *opt; 20686 char *name; 20687 char saved_char; 20688 20689 name = input_line_pointer; 20690 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20691 input_line_pointer++; 20692 saved_char = *input_line_pointer; 20693 *input_line_pointer = 0; 20694 20695 /* Skip the first "all" entry. */ 20696 for (opt = arm_cpus + 1; opt->name != NULL; opt++) 20697 if (streq (opt->name, name)) 20698 { 20699 mcpu_cpu_opt = &opt->value; 20700 selected_cpu = opt->value; 20701 if (opt->canonical_name) 20702 strcpy(selected_cpu_name, opt->canonical_name); 20703 else 20704 { 20705 int i; 20706 for (i = 0; opt->name[i]; i++) 20707 selected_cpu_name[i] = TOUPPER (opt->name[i]); 20708 selected_cpu_name[i] = 0; 20709 } 20710 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 20711 *input_line_pointer = saved_char; 20712 demand_empty_rest_of_line (); 20713 return; 20714 } 20715 as_bad (_("unknown cpu `%s'"), name); 20716 *input_line_pointer = saved_char; 20717 ignore_rest_of_line (); 20718} 20719 20720 20721/* Parse a .arch directive. */ 20722 20723static void 20724s_arm_arch (int ignored ATTRIBUTE_UNUSED) 20725{ 20726 const struct arm_arch_option_table *opt; 20727 char saved_char; 20728 char *name; 20729 20730 name = input_line_pointer; 20731 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20732 input_line_pointer++; 20733 saved_char = *input_line_pointer; 20734 *input_line_pointer = 0; 20735 20736 /* Skip the first "all" entry. */ 20737 for (opt = arm_archs + 1; opt->name != NULL; opt++) 20738 if (streq (opt->name, name)) 20739 { 20740 mcpu_cpu_opt = &opt->value; 20741 selected_cpu = opt->value; 20742 strcpy(selected_cpu_name, opt->name); 20743 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 20744 *input_line_pointer = saved_char; 20745 demand_empty_rest_of_line (); 20746 return; 20747 } 20748 20749 as_bad (_("unknown architecture `%s'\n"), name); 20750 *input_line_pointer = saved_char; 20751 ignore_rest_of_line (); 20752} 20753 20754/* Parse a .arch_extension directive. */ 20755 20756static void 20757s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED) 20758{ 20759 const struct arm_option_cpu_value_table *opt; 20760 char saved_char; 20761 char *name; 20762 20763 name = input_line_pointer; 20764 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20765 input_line_pointer++; 20766 saved_char = *input_line_pointer; 20767 *input_line_pointer = 0; 20768 20769 for (opt = arm_extensions; opt->name != NULL; opt++) 20770 if (streq (opt->name, name)) 20771 { 20772 ARM_MERGE_FEATURE_SETS (cpu_variant, cpu_variant, opt->value); 20773 *input_line_pointer = saved_char; 20774 demand_empty_rest_of_line (); 20775 return; 20776 } 20777 20778 as_bad (_("unknown architecture `%s'\n"), name); 20779 *input_line_pointer = saved_char; 20780 ignore_rest_of_line (); 20781} 20782 20783/* Parse a .object_arch directive. */ 20784 20785static void 20786s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) 20787{ 20788 const struct arm_arch_option_table *opt; 20789 char saved_char; 20790 char *name; 20791 20792 name = input_line_pointer; 20793 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20794 input_line_pointer++; 20795 saved_char = *input_line_pointer; 20796 *input_line_pointer = 0; 20797 20798 /* Skip the first "all" entry. */ 20799 for (opt = arm_archs + 1; opt->name != NULL; opt++) 20800 if (streq (opt->name, name)) 20801 { 20802 object_arch = &opt->value; 20803 *input_line_pointer = saved_char; 20804 demand_empty_rest_of_line (); 20805 return; 20806 } 20807 20808 as_bad (_("unknown architecture `%s'\n"), name); 20809 *input_line_pointer = saved_char; 20810 ignore_rest_of_line (); 20811} 20812 20813 20814/* Parse a .fpu directive. */ 20815 20816static void 20817s_arm_fpu (int ignored ATTRIBUTE_UNUSED) 20818{ 20819 const struct arm_option_cpu_value_table *opt; 20820 char saved_char; 20821 char *name; 20822 20823 name = input_line_pointer; 20824 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20825 input_line_pointer++; 20826 saved_char = *input_line_pointer; 20827 *input_line_pointer = 0; 20828 20829 for (opt = arm_fpus; opt->name != NULL; opt++) 20830 if (streq (opt->name, name)) 20831 { 20832 mfpu_opt = &opt->value; 20833 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 20834 *input_line_pointer = saved_char; 20835 demand_empty_rest_of_line (); 20836 return; 20837 } 20838 20839 as_bad (_("unknown floating point format `%s'\n"), name); 20840 *input_line_pointer = saved_char; 20841 ignore_rest_of_line (); 20842} 20843 20844/* Copy symbol information. */ 20845void 20846arm_copy_symbol_attributes (symbolS *dest, symbolS *src) 20847{ 20848 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); 20849} 20850