tc-arm.c revision 269797
1/* tc-arm.c -- Assemble for the ARM 2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 3 2004, 2005, 2006 4 Free Software Foundation, Inc. 5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) 6 Modified by David Taylor (dtaylor@armltd.co.uk) 7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) 8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) 9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) 10 11 This file is part of GAS, the GNU Assembler. 12 13 GAS is free software; you can redistribute it and/or modify 14 it under the terms of the GNU General Public License as published by 15 the Free Software Foundation; either version 2, or (at your option) 16 any later version. 17 18 GAS is distributed in the hope that it will be useful, 19 but WITHOUT ANY WARRANTY; without even the implied warranty of 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 GNU General Public License for more details. 22 23 You should have received a copy of the GNU General Public License 24 along with GAS; see the file COPYING. If not, write to the Free 25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 26 02110-1301, USA. */ 27 28#include <limits.h> 29#include <stdarg.h> 30#define NO_RELOC 0 31#include "as.h" 32#include "safe-ctype.h" 33#include "subsegs.h" 34#include "obstack.h" 35 36#include "opcode/arm.h" 37 38#ifdef OBJ_ELF 39#include "elf/arm.h" 40#include "dw2gencfi.h" 41#endif 42 43#include "dwarf2dbg.h" 44 45#define WARN_DEPRECATED 1 46 47#ifdef OBJ_ELF 48/* Must be at least the size of the largest unwind opcode (currently two). */ 49#define ARM_OPCODE_CHUNK_SIZE 8 50 51/* This structure holds the unwinding state. */ 52 53static struct 54{ 55 symbolS * proc_start; 56 symbolS * table_entry; 57 symbolS * personality_routine; 58 int personality_index; 59 /* The segment containing the function. */ 60 segT saved_seg; 61 subsegT saved_subseg; 62 /* Opcodes generated from this function. */ 63 unsigned char * opcodes; 64 int opcode_count; 65 int opcode_alloc; 66 /* The number of bytes pushed to the stack. */ 67 offsetT frame_size; 68 /* We don't add stack adjustment opcodes immediately so that we can merge 69 multiple adjustments. We can also omit the final adjustment 70 when using a frame pointer. */ 71 offsetT pending_offset; 72 /* These two fields are set by both unwind_movsp and unwind_setfp. They 73 hold the reg+offset to use when restoring sp from a frame pointer. */ 74 offsetT fp_offset; 75 int fp_reg; 76 /* Nonzero if an unwind_setfp directive has been seen. */ 77 unsigned fp_used:1; 78 /* Nonzero if the last opcode restores sp from fp_reg. */ 79 unsigned sp_restored:1; 80} unwind; 81 82/* Bit N indicates that an R_ARM_NONE relocation has been output for 83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be 84 emitted only once per section, to save unnecessary bloat. */ 85static unsigned int marked_pr_dependency = 0; 86 87#endif /* OBJ_ELF */ 88 89/* Results from operand parsing worker functions. */ 90 91typedef enum 92{ 93 PARSE_OPERAND_SUCCESS, 94 PARSE_OPERAND_FAIL, 95 PARSE_OPERAND_FAIL_NO_BACKTRACK 96} parse_operand_result; 97 98enum arm_float_abi 99{ 100 ARM_FLOAT_ABI_HARD, 101 ARM_FLOAT_ABI_SOFTFP, 102 ARM_FLOAT_ABI_SOFT 103}; 104 105/* Types of processor to assemble for. */ 106#ifndef CPU_DEFAULT 107#if defined __XSCALE__ 108#define CPU_DEFAULT ARM_ARCH_XSCALE 109#else 110#if defined __thumb__ 111#define CPU_DEFAULT ARM_ARCH_V5T 112#endif 113#endif 114#endif 115 116#ifndef FPU_DEFAULT 117# ifdef TE_LINUX 118# define FPU_DEFAULT FPU_ARCH_FPA 119# elif defined (TE_NetBSD) 120# ifdef OBJ_ELF 121# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ 122# else 123 /* Legacy a.out format. */ 124# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ 125# endif 126# elif defined (TE_VXWORKS) 127# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ 128# else 129 /* For backwards compatibility, default to FPA. */ 130# define FPU_DEFAULT FPU_ARCH_FPA 131# endif 132#endif /* ifndef FPU_DEFAULT */ 133 134#define streq(a, b) (strcmp (a, b) == 0) 135 136static arm_feature_set cpu_variant; 137static arm_feature_set arm_arch_used; 138static arm_feature_set thumb_arch_used; 139 140/* Flags stored in private area of BFD structure. */ 141static int uses_apcs_26 = FALSE; 142static int atpcs = FALSE; 143static int support_interwork = FALSE; 144static int uses_apcs_float = FALSE; 145static int pic_code = FALSE; 146 147/* Variables that we set while parsing command-line options. Once all 148 options have been read we re-process these values to set the real 149 assembly flags. */ 150static const arm_feature_set *legacy_cpu = NULL; 151static const arm_feature_set *legacy_fpu = NULL; 152 153static const arm_feature_set *mcpu_cpu_opt = NULL; 154static const arm_feature_set *mcpu_fpu_opt = NULL; 155static const arm_feature_set *march_cpu_opt = NULL; 156static const arm_feature_set *march_fpu_opt = NULL; 157static const arm_feature_set *mfpu_opt = NULL; 158static const arm_feature_set *object_arch = NULL; 159 160/* Constants for known architecture features. */ 161static const arm_feature_set fpu_default = FPU_DEFAULT; 162static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; 163static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; 164static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; 165static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; 166static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; 167static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; 168static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; 169static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; 170 171#ifdef CPU_DEFAULT 172static const arm_feature_set cpu_default = CPU_DEFAULT; 173#endif 174 175static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); 176static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); 177static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); 178static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); 179static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); 180static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); 181static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); 182static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); 183static const arm_feature_set arm_ext_v4t_5 = 184 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); 185static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); 186static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); 187static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); 188static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); 189static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); 190static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); 191static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0); 192static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); 193static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); 194static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); 195static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); 196static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); 197static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); 198static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); 199 200static const arm_feature_set arm_arch_any = ARM_ANY; 201static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); 202static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; 203static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; 204 205static const arm_feature_set arm_cext_iwmmxt2 = 206 ARM_FEATURE (0, ARM_CEXT_IWMMXT2); 207static const arm_feature_set arm_cext_iwmmxt = 208 ARM_FEATURE (0, ARM_CEXT_IWMMXT); 209static const arm_feature_set arm_cext_xscale = 210 ARM_FEATURE (0, ARM_CEXT_XSCALE); 211static const arm_feature_set arm_cext_maverick = 212 ARM_FEATURE (0, ARM_CEXT_MAVERICK); 213static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); 214static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); 215static const arm_feature_set fpu_vfp_ext_v1xd = 216 ARM_FEATURE (0, FPU_VFP_EXT_V1xD); 217static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); 218static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); 219static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); 220static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); 221static const arm_feature_set fpu_vfp_v3_or_neon_ext = 222 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); 223 224static int mfloat_abi_opt = -1; 225/* Record user cpu selection for object attributes. */ 226static arm_feature_set selected_cpu = ARM_ARCH_NONE; 227/* Must be long enough to hold any of the names in arm_cpus. */ 228static char selected_cpu_name[16]; 229#ifdef OBJ_ELF 230# ifdef EABI_DEFAULT 231static int meabi_flags = EABI_DEFAULT; 232# else 233static int meabi_flags = EF_ARM_EABI_UNKNOWN; 234# endif 235 236bfd_boolean 237arm_is_eabi(void) 238{ 239 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); 240} 241#endif 242 243#ifdef OBJ_ELF 244/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ 245symbolS * GOT_symbol; 246#endif 247 248/* 0: assemble for ARM, 249 1: assemble for Thumb, 250 2: assemble for Thumb even though target CPU does not support thumb 251 instructions. */ 252static int thumb_mode = 0; 253 254/* If unified_syntax is true, we are processing the new unified 255 ARM/Thumb syntax. Important differences from the old ARM mode: 256 257 - Immediate operands do not require a # prefix. 258 - Conditional affixes always appear at the end of the 259 instruction. (For backward compatibility, those instructions 260 that formerly had them in the middle, continue to accept them 261 there.) 262 - The IT instruction may appear, and if it does is validated 263 against subsequent conditional affixes. It does not generate 264 machine code. 265 266 Important differences from the old Thumb mode: 267 268 - Immediate operands do not require a # prefix. 269 - Most of the V6T2 instructions are only available in unified mode. 270 - The .N and .W suffixes are recognized and honored (it is an error 271 if they cannot be honored). 272 - All instructions set the flags if and only if they have an 's' affix. 273 - Conditional affixes may be used. They are validated against 274 preceding IT instructions. Unlike ARM mode, you cannot use a 275 conditional affix except in the scope of an IT instruction. */ 276 277static bfd_boolean unified_syntax = FALSE; 278 279enum neon_el_type 280{ 281 NT_invtype, 282 NT_untyped, 283 NT_integer, 284 NT_float, 285 NT_poly, 286 NT_signed, 287 NT_unsigned 288}; 289 290struct neon_type_el 291{ 292 enum neon_el_type type; 293 unsigned size; 294}; 295 296#define NEON_MAX_TYPE_ELS 4 297 298struct neon_type 299{ 300 struct neon_type_el el[NEON_MAX_TYPE_ELS]; 301 unsigned elems; 302}; 303 304struct arm_it 305{ 306 const char * error; 307 unsigned long instruction; 308 int size; 309 int size_req; 310 int cond; 311 /* "uncond_value" is set to the value in place of the conditional field in 312 unconditional versions of the instruction, or -1 if nothing is 313 appropriate. */ 314 int uncond_value; 315 struct neon_type vectype; 316 /* Set to the opcode if the instruction needs relaxation. 317 Zero if the instruction is not relaxed. */ 318 unsigned long relax; 319 struct 320 { 321 bfd_reloc_code_real_type type; 322 expressionS exp; 323 int pc_rel; 324 } reloc; 325 326 struct 327 { 328 unsigned reg; 329 signed int imm; 330 struct neon_type_el vectype; 331 unsigned present : 1; /* Operand present. */ 332 unsigned isreg : 1; /* Operand was a register. */ 333 unsigned immisreg : 1; /* .imm field is a second register. */ 334 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ 335 unsigned immisalign : 1; /* Immediate is an alignment specifier. */ 336 unsigned immisfloat : 1; /* Immediate was parsed as a float. */ 337 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV 338 instructions. This allows us to disambiguate ARM <-> vector insns. */ 339 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ 340 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ 341 unsigned isquad : 1; /* Operand is Neon quad-precision register. */ 342 unsigned issingle : 1; /* Operand is VFP single-precision register. */ 343 unsigned hasreloc : 1; /* Operand has relocation suffix. */ 344 unsigned writeback : 1; /* Operand has trailing ! */ 345 unsigned preind : 1; /* Preindexed address. */ 346 unsigned postind : 1; /* Postindexed address. */ 347 unsigned negative : 1; /* Index register was negated. */ 348 unsigned shifted : 1; /* Shift applied to operation. */ 349 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ 350 } operands[6]; 351}; 352 353static struct arm_it inst; 354 355#define NUM_FLOAT_VALS 8 356 357const char * fp_const[] = 358{ 359 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 360}; 361 362/* Number of littlenums required to hold an extended precision number. */ 363#define MAX_LITTLENUMS 6 364 365LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; 366 367#define FAIL (-1) 368#define SUCCESS (0) 369 370#define SUFF_S 1 371#define SUFF_D 2 372#define SUFF_E 3 373#define SUFF_P 4 374 375#define CP_T_X 0x00008000 376#define CP_T_Y 0x00400000 377 378#define CONDS_BIT 0x00100000 379#define LOAD_BIT 0x00100000 380 381#define DOUBLE_LOAD_FLAG 0x00000001 382 383struct asm_cond 384{ 385 const char * template; 386 unsigned long value; 387}; 388 389#define COND_ALWAYS 0xE 390 391struct asm_psr 392{ 393 const char *template; 394 unsigned long field; 395}; 396 397struct asm_barrier_opt 398{ 399 const char *template; 400 unsigned long value; 401}; 402 403/* The bit that distinguishes CPSR and SPSR. */ 404#define SPSR_BIT (1 << 22) 405 406/* The individual PSR flag bits. */ 407#define PSR_c (1 << 16) 408#define PSR_x (1 << 17) 409#define PSR_s (1 << 18) 410#define PSR_f (1 << 19) 411 412struct reloc_entry 413{ 414 char *name; 415 bfd_reloc_code_real_type reloc; 416}; 417 418enum vfp_reg_pos 419{ 420 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, 421 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn 422}; 423 424enum vfp_ldstm_type 425{ 426 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX 427}; 428 429/* Bits for DEFINED field in neon_typed_alias. */ 430#define NTA_HASTYPE 1 431#define NTA_HASINDEX 2 432 433struct neon_typed_alias 434{ 435 unsigned char defined; 436 unsigned char index; 437 struct neon_type_el eltype; 438}; 439 440/* ARM register categories. This includes coprocessor numbers and various 441 architecture extensions' registers. */ 442enum arm_reg_type 443{ 444 REG_TYPE_RN, 445 REG_TYPE_CP, 446 REG_TYPE_CN, 447 REG_TYPE_FN, 448 REG_TYPE_VFS, 449 REG_TYPE_VFD, 450 REG_TYPE_NQ, 451 REG_TYPE_VFSD, 452 REG_TYPE_NDQ, 453 REG_TYPE_NSDQ, 454 REG_TYPE_VFC, 455 REG_TYPE_MVF, 456 REG_TYPE_MVD, 457 REG_TYPE_MVFX, 458 REG_TYPE_MVDX, 459 REG_TYPE_MVAX, 460 REG_TYPE_DSPSC, 461 REG_TYPE_MMXWR, 462 REG_TYPE_MMXWC, 463 REG_TYPE_MMXWCG, 464 REG_TYPE_XSCALE, 465}; 466 467/* Structure for a hash table entry for a register. 468 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra 469 information which states whether a vector type or index is specified (for a 470 register alias created with .dn or .qn). Otherwise NEON should be NULL. */ 471struct reg_entry 472{ 473 const char *name; 474 unsigned char number; 475 unsigned char type; 476 unsigned char builtin; 477 struct neon_typed_alias *neon; 478}; 479 480/* Diagnostics used when we don't get a register of the expected type. */ 481const char *const reg_expected_msgs[] = 482{ 483 N_("ARM register expected"), 484 N_("bad or missing co-processor number"), 485 N_("co-processor register expected"), 486 N_("FPA register expected"), 487 N_("VFP single precision register expected"), 488 N_("VFP/Neon double precision register expected"), 489 N_("Neon quad precision register expected"), 490 N_("VFP single or double precision register expected"), 491 N_("Neon double or quad precision register expected"), 492 N_("VFP single, double or Neon quad precision register expected"), 493 N_("VFP system register expected"), 494 N_("Maverick MVF register expected"), 495 N_("Maverick MVD register expected"), 496 N_("Maverick MVFX register expected"), 497 N_("Maverick MVDX register expected"), 498 N_("Maverick MVAX register expected"), 499 N_("Maverick DSPSC register expected"), 500 N_("iWMMXt data register expected"), 501 N_("iWMMXt control register expected"), 502 N_("iWMMXt scalar register expected"), 503 N_("XScale accumulator register expected"), 504}; 505 506/* Some well known registers that we refer to directly elsewhere. */ 507#define REG_SP 13 508#define REG_LR 14 509#define REG_PC 15 510 511/* ARM instructions take 4bytes in the object file, Thumb instructions 512 take 2: */ 513#define INSN_SIZE 4 514 515struct asm_opcode 516{ 517 /* Basic string to match. */ 518 const char *template; 519 520 /* Parameters to instruction. */ 521 unsigned char operands[8]; 522 523 /* Conditional tag - see opcode_lookup. */ 524 unsigned int tag : 4; 525 526 /* Basic instruction code. */ 527 unsigned int avalue : 28; 528 529 /* Thumb-format instruction code. */ 530 unsigned int tvalue; 531 532 /* Which architecture variant provides this instruction. */ 533 const arm_feature_set *avariant; 534 const arm_feature_set *tvariant; 535 536 /* Function to call to encode instruction in ARM format. */ 537 void (* aencode) (void); 538 539 /* Function to call to encode instruction in Thumb format. */ 540 void (* tencode) (void); 541}; 542 543/* Defines for various bits that we will want to toggle. */ 544#define INST_IMMEDIATE 0x02000000 545#define OFFSET_REG 0x02000000 546#define HWOFFSET_IMM 0x00400000 547#define SHIFT_BY_REG 0x00000010 548#define PRE_INDEX 0x01000000 549#define INDEX_UP 0x00800000 550#define WRITE_BACK 0x00200000 551#define LDM_TYPE_2_OR_3 0x00400000 552#define CPSI_MMOD 0x00020000 553 554#define LITERAL_MASK 0xf000f000 555#define OPCODE_MASK 0xfe1fffff 556#define V4_STR_BIT 0x00000020 557 558#define T2_SUBS_PC_LR 0xf3de8f00 559 560#define DATA_OP_SHIFT 21 561 562#define T2_OPCODE_MASK 0xfe1fffff 563#define T2_DATA_OP_SHIFT 21 564 565/* Codes to distinguish the arithmetic instructions. */ 566#define OPCODE_AND 0 567#define OPCODE_EOR 1 568#define OPCODE_SUB 2 569#define OPCODE_RSB 3 570#define OPCODE_ADD 4 571#define OPCODE_ADC 5 572#define OPCODE_SBC 6 573#define OPCODE_RSC 7 574#define OPCODE_TST 8 575#define OPCODE_TEQ 9 576#define OPCODE_CMP 10 577#define OPCODE_CMN 11 578#define OPCODE_ORR 12 579#define OPCODE_MOV 13 580#define OPCODE_BIC 14 581#define OPCODE_MVN 15 582 583#define T2_OPCODE_AND 0 584#define T2_OPCODE_BIC 1 585#define T2_OPCODE_ORR 2 586#define T2_OPCODE_ORN 3 587#define T2_OPCODE_EOR 4 588#define T2_OPCODE_ADD 8 589#define T2_OPCODE_ADC 10 590#define T2_OPCODE_SBC 11 591#define T2_OPCODE_SUB 13 592#define T2_OPCODE_RSB 14 593 594#define T_OPCODE_MUL 0x4340 595#define T_OPCODE_TST 0x4200 596#define T_OPCODE_CMN 0x42c0 597#define T_OPCODE_NEG 0x4240 598#define T_OPCODE_MVN 0x43c0 599 600#define T_OPCODE_ADD_R3 0x1800 601#define T_OPCODE_SUB_R3 0x1a00 602#define T_OPCODE_ADD_HI 0x4400 603#define T_OPCODE_ADD_ST 0xb000 604#define T_OPCODE_SUB_ST 0xb080 605#define T_OPCODE_ADD_SP 0xa800 606#define T_OPCODE_ADD_PC 0xa000 607#define T_OPCODE_ADD_I8 0x3000 608#define T_OPCODE_SUB_I8 0x3800 609#define T_OPCODE_ADD_I3 0x1c00 610#define T_OPCODE_SUB_I3 0x1e00 611 612#define T_OPCODE_ASR_R 0x4100 613#define T_OPCODE_LSL_R 0x4080 614#define T_OPCODE_LSR_R 0x40c0 615#define T_OPCODE_ROR_R 0x41c0 616#define T_OPCODE_ASR_I 0x1000 617#define T_OPCODE_LSL_I 0x0000 618#define T_OPCODE_LSR_I 0x0800 619 620#define T_OPCODE_MOV_I8 0x2000 621#define T_OPCODE_CMP_I8 0x2800 622#define T_OPCODE_CMP_LR 0x4280 623#define T_OPCODE_MOV_HR 0x4600 624#define T_OPCODE_CMP_HR 0x4500 625 626#define T_OPCODE_LDR_PC 0x4800 627#define T_OPCODE_LDR_SP 0x9800 628#define T_OPCODE_STR_SP 0x9000 629#define T_OPCODE_LDR_IW 0x6800 630#define T_OPCODE_STR_IW 0x6000 631#define T_OPCODE_LDR_IH 0x8800 632#define T_OPCODE_STR_IH 0x8000 633#define T_OPCODE_LDR_IB 0x7800 634#define T_OPCODE_STR_IB 0x7000 635#define T_OPCODE_LDR_RW 0x5800 636#define T_OPCODE_STR_RW 0x5000 637#define T_OPCODE_LDR_RH 0x5a00 638#define T_OPCODE_STR_RH 0x5200 639#define T_OPCODE_LDR_RB 0x5c00 640#define T_OPCODE_STR_RB 0x5400 641 642#define T_OPCODE_PUSH 0xb400 643#define T_OPCODE_POP 0xbc00 644 645#define T_OPCODE_BRANCH 0xe000 646 647#define THUMB_SIZE 2 /* Size of thumb instruction. */ 648#define THUMB_PP_PC_LR 0x0100 649#define THUMB_LOAD_BIT 0x0800 650#define THUMB2_LOAD_BIT 0x00100000 651 652#define BAD_ARGS _("bad arguments to instruction") 653#define BAD_PC _("r15 not allowed here") 654#define BAD_SP _("r13 not allowed here") 655#define BAD_COND _("instruction cannot be conditional") 656#define BAD_OVERLAP _("registers may not be the same") 657#define BAD_HIREG _("lo register required") 658#define BAD_THUMB32 _("instruction not supported in Thumb16 mode") 659#define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); 660#define BAD_BRANCH _("branch must be last instruction in IT block") 661#define BAD_NOT_IT _("instruction not allowed in IT block") 662#define BAD_FPU _("selected FPU does not support instruction") 663#define BAD_VMRS _("APSR_nzcv may only be used with fpscr") 664 665static struct hash_control *arm_ops_hsh; 666static struct hash_control *arm_cond_hsh; 667static struct hash_control *arm_shift_hsh; 668static struct hash_control *arm_psr_hsh; 669static struct hash_control *arm_v7m_psr_hsh; 670static struct hash_control *arm_reg_hsh; 671static struct hash_control *arm_reloc_hsh; 672static struct hash_control *arm_barrier_opt_hsh; 673 674/* Stuff needed to resolve the label ambiguity 675 As: 676 ... 677 label: <insn> 678 may differ from: 679 ... 680 label: 681 <insn> 682*/ 683 684symbolS * last_label_seen; 685static int label_is_thumb_function_name = FALSE; 686 687/* Literal pool structure. Held on a per-section 688 and per-sub-section basis. */ 689 690#define MAX_LITERAL_POOL_SIZE 1024 691typedef struct literal_pool 692{ 693 expressionS literals [MAX_LITERAL_POOL_SIZE]; 694 unsigned int next_free_entry; 695 unsigned int id; 696 symbolS * symbol; 697 segT section; 698 subsegT sub_section; 699 struct literal_pool * next; 700} literal_pool; 701 702/* Pointer to a linked list of literal pools. */ 703literal_pool * list_of_pools = NULL; 704 705/* State variables for IT block handling. */ 706static bfd_boolean current_it_mask = 0; 707static int current_cc; 708 709 710/* Pure syntax. */ 711 712/* This array holds the chars that always start a comment. If the 713 pre-processor is disabled, these aren't very useful. */ 714const char comment_chars[] = "@"; 715 716/* This array holds the chars that only start a comment at the beginning of 717 a line. If the line seems to have the form '# 123 filename' 718 .line and .file directives will appear in the pre-processed output. */ 719/* Note that input_file.c hand checks for '#' at the beginning of the 720 first line of the input file. This is because the compiler outputs 721 #NO_APP at the beginning of its output. */ 722/* Also note that comments like this one will always work. */ 723const char line_comment_chars[] = "#"; 724 725const char line_separator_chars[] = ";"; 726 727/* Chars that can be used to separate mant 728 from exp in floating point numbers. */ 729const char EXP_CHARS[] = "eE"; 730 731/* Chars that mean this number is a floating point constant. */ 732/* As in 0f12.456 */ 733/* or 0d1.2345e12 */ 734 735const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; 736 737/* Prefix characters that indicate the start of an immediate 738 value. */ 739#define is_immediate_prefix(C) ((C) == '#' || (C) == '$') 740 741/* Separator character handling. */ 742 743#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) 744 745static inline int 746skip_past_char (char ** str, char c) 747{ 748 if (**str == c) 749 { 750 (*str)++; 751 return SUCCESS; 752 } 753 else 754 return FAIL; 755} 756#define skip_past_comma(str) skip_past_char (str, ',') 757 758/* Arithmetic expressions (possibly involving symbols). */ 759 760/* Return TRUE if anything in the expression is a bignum. */ 761 762static int 763walk_no_bignums (symbolS * sp) 764{ 765 if (symbol_get_value_expression (sp)->X_op == O_big) 766 return 1; 767 768 if (symbol_get_value_expression (sp)->X_add_symbol) 769 { 770 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) 771 || (symbol_get_value_expression (sp)->X_op_symbol 772 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); 773 } 774 775 return 0; 776} 777 778static int in_my_get_expression = 0; 779 780/* Third argument to my_get_expression. */ 781#define GE_NO_PREFIX 0 782#define GE_IMM_PREFIX 1 783#define GE_OPT_PREFIX 2 784/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) 785 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ 786#define GE_OPT_PREFIX_BIG 3 787 788static int 789my_get_expression (expressionS * ep, char ** str, int prefix_mode) 790{ 791 char * save_in; 792 segT seg; 793 794 /* In unified syntax, all prefixes are optional. */ 795 if (unified_syntax) 796 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode 797 : GE_OPT_PREFIX; 798 799 switch (prefix_mode) 800 { 801 case GE_NO_PREFIX: break; 802 case GE_IMM_PREFIX: 803 if (!is_immediate_prefix (**str)) 804 { 805 inst.error = _("immediate expression requires a # prefix"); 806 return FAIL; 807 } 808 (*str)++; 809 break; 810 case GE_OPT_PREFIX: 811 case GE_OPT_PREFIX_BIG: 812 if (is_immediate_prefix (**str)) 813 (*str)++; 814 break; 815 default: abort (); 816 } 817 818 memset (ep, 0, sizeof (expressionS)); 819 820 save_in = input_line_pointer; 821 input_line_pointer = *str; 822 in_my_get_expression = 1; 823 seg = expression (ep); 824 in_my_get_expression = 0; 825 826 if (ep->X_op == O_illegal) 827 { 828 /* We found a bad expression in md_operand(). */ 829 *str = input_line_pointer; 830 input_line_pointer = save_in; 831 if (inst.error == NULL) 832 inst.error = _("bad expression"); 833 return 1; 834 } 835 836#ifdef OBJ_AOUT 837 if (seg != absolute_section 838 && seg != text_section 839 && seg != data_section 840 && seg != bss_section 841 && seg != undefined_section) 842 { 843 inst.error = _("bad segment"); 844 *str = input_line_pointer; 845 input_line_pointer = save_in; 846 return 1; 847 } 848#endif 849 850 /* Get rid of any bignums now, so that we don't generate an error for which 851 we can't establish a line number later on. Big numbers are never valid 852 in instructions, which is where this routine is always called. */ 853 if (prefix_mode != GE_OPT_PREFIX_BIG 854 && (ep->X_op == O_big 855 || (ep->X_add_symbol 856 && (walk_no_bignums (ep->X_add_symbol) 857 || (ep->X_op_symbol 858 && walk_no_bignums (ep->X_op_symbol)))))) 859 { 860 inst.error = _("invalid constant"); 861 *str = input_line_pointer; 862 input_line_pointer = save_in; 863 return 1; 864 } 865 866 *str = input_line_pointer; 867 input_line_pointer = save_in; 868 return 0; 869} 870 871/* Turn a string in input_line_pointer into a floating point constant 872 of type TYPE, and store the appropriate bytes in *LITP. The number 873 of LITTLENUMS emitted is stored in *SIZEP. An error message is 874 returned, or NULL on OK. 875 876 Note that fp constants aren't represent in the normal way on the ARM. 877 In big endian mode, things are as expected. However, in little endian 878 mode fp constants are big-endian word-wise, and little-endian byte-wise 879 within the words. For example, (double) 1.1 in big endian mode is 880 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is 881 the byte sequence 99 99 f1 3f 9a 99 99 99. 882 883 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ 884 885char * 886md_atof (int type, char * litP, int * sizeP) 887{ 888 int prec; 889 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 890 char *t; 891 int i; 892 893 switch (type) 894 { 895 case 'f': 896 case 'F': 897 case 's': 898 case 'S': 899 prec = 2; 900 break; 901 902 case 'd': 903 case 'D': 904 case 'r': 905 case 'R': 906 prec = 4; 907 break; 908 909 case 'x': 910 case 'X': 911 prec = 6; 912 break; 913 914 case 'p': 915 case 'P': 916 prec = 6; 917 break; 918 919 default: 920 *sizeP = 0; 921 return _("bad call to MD_ATOF()"); 922 } 923 924 t = atof_ieee (input_line_pointer, type, words); 925 if (t) 926 input_line_pointer = t; 927 *sizeP = prec * 2; 928 929 if (target_big_endian) 930 { 931 for (i = 0; i < prec; i++) 932 { 933 md_number_to_chars (litP, (valueT) words[i], 2); 934 litP += 2; 935 } 936 } 937 else 938 { 939 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) 940 for (i = prec - 1; i >= 0; i--) 941 { 942 md_number_to_chars (litP, (valueT) words[i], 2); 943 litP += 2; 944 } 945 else 946 /* For a 4 byte float the order of elements in `words' is 1 0. 947 For an 8 byte float the order is 1 0 3 2. */ 948 for (i = 0; i < prec; i += 2) 949 { 950 md_number_to_chars (litP, (valueT) words[i + 1], 2); 951 md_number_to_chars (litP + 2, (valueT) words[i], 2); 952 litP += 4; 953 } 954 } 955 956 return 0; 957} 958 959/* We handle all bad expressions here, so that we can report the faulty 960 instruction in the error message. */ 961void 962md_operand (expressionS * expr) 963{ 964 if (in_my_get_expression) 965 expr->X_op = O_illegal; 966} 967 968/* Immediate values. */ 969 970/* Generic immediate-value read function for use in directives. 971 Accepts anything that 'expression' can fold to a constant. 972 *val receives the number. */ 973#ifdef OBJ_ELF 974static int 975immediate_for_directive (int *val) 976{ 977 expressionS exp; 978 exp.X_op = O_illegal; 979 980 if (is_immediate_prefix (*input_line_pointer)) 981 { 982 input_line_pointer++; 983 expression (&exp); 984 } 985 986 if (exp.X_op != O_constant) 987 { 988 as_bad (_("expected #constant")); 989 ignore_rest_of_line (); 990 return FAIL; 991 } 992 *val = exp.X_add_number; 993 return SUCCESS; 994} 995#endif 996 997/* Register parsing. */ 998 999/* Generic register parser. CCP points to what should be the 1000 beginning of a register name. If it is indeed a valid register 1001 name, advance CCP over it and return the reg_entry structure; 1002 otherwise return NULL. Does not issue diagnostics. */ 1003 1004static struct reg_entry * 1005arm_reg_parse_multi (char **ccp) 1006{ 1007 char *start = *ccp; 1008 char *p; 1009 struct reg_entry *reg; 1010 1011#ifdef REGISTER_PREFIX 1012 if (*start != REGISTER_PREFIX) 1013 return NULL; 1014 start++; 1015#endif 1016#ifdef OPTIONAL_REGISTER_PREFIX 1017 if (*start == OPTIONAL_REGISTER_PREFIX) 1018 start++; 1019#endif 1020 1021 p = start; 1022 if (!ISALPHA (*p) || !is_name_beginner (*p)) 1023 return NULL; 1024 1025 do 1026 p++; 1027 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); 1028 1029 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); 1030 1031 if (!reg) 1032 return NULL; 1033 1034 *ccp = p; 1035 return reg; 1036} 1037 1038static int 1039arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, 1040 enum arm_reg_type type) 1041{ 1042 /* Alternative syntaxes are accepted for a few register classes. */ 1043 switch (type) 1044 { 1045 case REG_TYPE_MVF: 1046 case REG_TYPE_MVD: 1047 case REG_TYPE_MVFX: 1048 case REG_TYPE_MVDX: 1049 /* Generic coprocessor register names are allowed for these. */ 1050 if (reg && reg->type == REG_TYPE_CN) 1051 return reg->number; 1052 break; 1053 1054 case REG_TYPE_CP: 1055 /* For backward compatibility, a bare number is valid here. */ 1056 { 1057 unsigned long processor = strtoul (start, ccp, 10); 1058 if (*ccp != start && processor <= 15) 1059 return processor; 1060 } 1061 1062 case REG_TYPE_MMXWC: 1063 /* WC includes WCG. ??? I'm not sure this is true for all 1064 instructions that take WC registers. */ 1065 if (reg && reg->type == REG_TYPE_MMXWCG) 1066 return reg->number; 1067 break; 1068 1069 default: 1070 break; 1071 } 1072 1073 return FAIL; 1074} 1075 1076/* As arm_reg_parse_multi, but the register must be of type TYPE, and the 1077 return value is the register number or FAIL. */ 1078 1079static int 1080arm_reg_parse (char **ccp, enum arm_reg_type type) 1081{ 1082 char *start = *ccp; 1083 struct reg_entry *reg = arm_reg_parse_multi (ccp); 1084 int ret; 1085 1086 /* Do not allow a scalar (reg+index) to parse as a register. */ 1087 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) 1088 return FAIL; 1089 1090 if (reg && reg->type == type) 1091 return reg->number; 1092 1093 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) 1094 return ret; 1095 1096 *ccp = start; 1097 return FAIL; 1098} 1099 1100/* Parse a Neon type specifier. *STR should point at the leading '.' 1101 character. Does no verification at this stage that the type fits the opcode 1102 properly. E.g., 1103 1104 .i32.i32.s16 1105 .s32.f32 1106 .u16 1107 1108 Can all be legally parsed by this function. 1109 1110 Fills in neon_type struct pointer with parsed information, and updates STR 1111 to point after the parsed type specifier. Returns SUCCESS if this was a legal 1112 type, FAIL if not. */ 1113 1114static int 1115parse_neon_type (struct neon_type *type, char **str) 1116{ 1117 char *ptr = *str; 1118 1119 if (type) 1120 type->elems = 0; 1121 1122 while (type->elems < NEON_MAX_TYPE_ELS) 1123 { 1124 enum neon_el_type thistype = NT_untyped; 1125 unsigned thissize = -1u; 1126 1127 if (*ptr != '.') 1128 break; 1129 1130 ptr++; 1131 1132 /* Just a size without an explicit type. */ 1133 if (ISDIGIT (*ptr)) 1134 goto parsesize; 1135 1136 switch (TOLOWER (*ptr)) 1137 { 1138 case 'i': thistype = NT_integer; break; 1139 case 'f': thistype = NT_float; break; 1140 case 'p': thistype = NT_poly; break; 1141 case 's': thistype = NT_signed; break; 1142 case 'u': thistype = NT_unsigned; break; 1143 case 'd': 1144 thistype = NT_float; 1145 thissize = 64; 1146 ptr++; 1147 goto done; 1148 default: 1149 as_bad (_("unexpected character `%c' in type specifier"), *ptr); 1150 return FAIL; 1151 } 1152 1153 ptr++; 1154 1155 /* .f is an abbreviation for .f32. */ 1156 if (thistype == NT_float && !ISDIGIT (*ptr)) 1157 thissize = 32; 1158 else 1159 { 1160 parsesize: 1161 thissize = strtoul (ptr, &ptr, 10); 1162 1163 if (thissize != 8 && thissize != 16 && thissize != 32 1164 && thissize != 64) 1165 { 1166 as_bad (_("bad size %d in type specifier"), thissize); 1167 return FAIL; 1168 } 1169 } 1170 1171 done: 1172 if (type) 1173 { 1174 type->el[type->elems].type = thistype; 1175 type->el[type->elems].size = thissize; 1176 type->elems++; 1177 } 1178 } 1179 1180 /* Empty/missing type is not a successful parse. */ 1181 if (type->elems == 0) 1182 return FAIL; 1183 1184 *str = ptr; 1185 1186 return SUCCESS; 1187} 1188 1189/* Errors may be set multiple times during parsing or bit encoding 1190 (particularly in the Neon bits), but usually the earliest error which is set 1191 will be the most meaningful. Avoid overwriting it with later (cascading) 1192 errors by calling this function. */ 1193 1194static void 1195first_error (const char *err) 1196{ 1197 if (!inst.error) 1198 inst.error = err; 1199} 1200 1201/* Parse a single type, e.g. ".s32", leading period included. */ 1202static int 1203parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) 1204{ 1205 char *str = *ccp; 1206 struct neon_type optype; 1207 1208 if (*str == '.') 1209 { 1210 if (parse_neon_type (&optype, &str) == SUCCESS) 1211 { 1212 if (optype.elems == 1) 1213 *vectype = optype.el[0]; 1214 else 1215 { 1216 first_error (_("only one type should be specified for operand")); 1217 return FAIL; 1218 } 1219 } 1220 else 1221 { 1222 first_error (_("vector type expected")); 1223 return FAIL; 1224 } 1225 } 1226 else 1227 return FAIL; 1228 1229 *ccp = str; 1230 1231 return SUCCESS; 1232} 1233 1234/* Special meanings for indices (which have a range of 0-7), which will fit into 1235 a 4-bit integer. */ 1236 1237#define NEON_ALL_LANES 15 1238#define NEON_INTERLEAVE_LANES 14 1239 1240/* Parse either a register or a scalar, with an optional type. Return the 1241 register number, and optionally fill in the actual type of the register 1242 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and 1243 type/index information in *TYPEINFO. */ 1244 1245static int 1246parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, 1247 enum arm_reg_type *rtype, 1248 struct neon_typed_alias *typeinfo) 1249{ 1250 char *str = *ccp; 1251 struct reg_entry *reg = arm_reg_parse_multi (&str); 1252 struct neon_typed_alias atype; 1253 struct neon_type_el parsetype; 1254 1255 atype.defined = 0; 1256 atype.index = -1; 1257 atype.eltype.type = NT_invtype; 1258 atype.eltype.size = -1; 1259 1260 /* Try alternate syntax for some types of register. Note these are mutually 1261 exclusive with the Neon syntax extensions. */ 1262 if (reg == NULL) 1263 { 1264 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); 1265 if (altreg != FAIL) 1266 *ccp = str; 1267 if (typeinfo) 1268 *typeinfo = atype; 1269 return altreg; 1270 } 1271 1272 /* Undo polymorphism when a set of register types may be accepted. */ 1273 if ((type == REG_TYPE_NDQ 1274 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) 1275 || (type == REG_TYPE_VFSD 1276 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) 1277 || (type == REG_TYPE_NSDQ 1278 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD 1279 || reg->type == REG_TYPE_NQ)) 1280 || (type == REG_TYPE_MMXWC 1281 && (reg->type == REG_TYPE_MMXWCG))) 1282 type = reg->type; 1283 1284 if (type != reg->type) 1285 return FAIL; 1286 1287 if (reg->neon) 1288 atype = *reg->neon; 1289 1290 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) 1291 { 1292 if ((atype.defined & NTA_HASTYPE) != 0) 1293 { 1294 first_error (_("can't redefine type for operand")); 1295 return FAIL; 1296 } 1297 atype.defined |= NTA_HASTYPE; 1298 atype.eltype = parsetype; 1299 } 1300 1301 if (skip_past_char (&str, '[') == SUCCESS) 1302 { 1303 if (type != REG_TYPE_VFD) 1304 { 1305 first_error (_("only D registers may be indexed")); 1306 return FAIL; 1307 } 1308 1309 if ((atype.defined & NTA_HASINDEX) != 0) 1310 { 1311 first_error (_("can't change index for operand")); 1312 return FAIL; 1313 } 1314 1315 atype.defined |= NTA_HASINDEX; 1316 1317 if (skip_past_char (&str, ']') == SUCCESS) 1318 atype.index = NEON_ALL_LANES; 1319 else 1320 { 1321 expressionS exp; 1322 1323 my_get_expression (&exp, &str, GE_NO_PREFIX); 1324 1325 if (exp.X_op != O_constant) 1326 { 1327 first_error (_("constant expression required")); 1328 return FAIL; 1329 } 1330 1331 if (skip_past_char (&str, ']') == FAIL) 1332 return FAIL; 1333 1334 atype.index = exp.X_add_number; 1335 } 1336 } 1337 1338 if (typeinfo) 1339 *typeinfo = atype; 1340 1341 if (rtype) 1342 *rtype = type; 1343 1344 *ccp = str; 1345 1346 return reg->number; 1347} 1348 1349/* Like arm_reg_parse, but allow allow the following extra features: 1350 - If RTYPE is non-zero, return the (possibly restricted) type of the 1351 register (e.g. Neon double or quad reg when either has been requested). 1352 - If this is a Neon vector type with additional type information, fill 1353 in the struct pointed to by VECTYPE (if non-NULL). 1354 This function will fault on encountering a scalar. 1355*/ 1356 1357static int 1358arm_typed_reg_parse (char **ccp, enum arm_reg_type type, 1359 enum arm_reg_type *rtype, struct neon_type_el *vectype) 1360{ 1361 struct neon_typed_alias atype; 1362 char *str = *ccp; 1363 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); 1364 1365 if (reg == FAIL) 1366 return FAIL; 1367 1368 /* Do not allow a scalar (reg+index) to parse as a register. */ 1369 if ((atype.defined & NTA_HASINDEX) != 0) 1370 { 1371 first_error (_("register operand expected, but got scalar")); 1372 return FAIL; 1373 } 1374 1375 if (vectype) 1376 *vectype = atype.eltype; 1377 1378 *ccp = str; 1379 1380 return reg; 1381} 1382 1383#define NEON_SCALAR_REG(X) ((X) >> 4) 1384#define NEON_SCALAR_INDEX(X) ((X) & 15) 1385 1386/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't 1387 have enough information to be able to do a good job bounds-checking. So, we 1388 just do easy checks here, and do further checks later. */ 1389 1390static int 1391parse_scalar (char **ccp, int elsize, struct neon_type_el *type) 1392{ 1393 int reg; 1394 char *str = *ccp; 1395 struct neon_typed_alias atype; 1396 1397 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); 1398 1399 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) 1400 return FAIL; 1401 1402 if (atype.index == NEON_ALL_LANES) 1403 { 1404 first_error (_("scalar must have an index")); 1405 return FAIL; 1406 } 1407 else if (atype.index >= 64 / elsize) 1408 { 1409 first_error (_("scalar index out of range")); 1410 return FAIL; 1411 } 1412 1413 if (type) 1414 *type = atype.eltype; 1415 1416 *ccp = str; 1417 1418 return reg * 16 + atype.index; 1419} 1420 1421/* Parse an ARM register list. Returns the bitmask, or FAIL. */ 1422static long 1423parse_reg_list (char ** strp) 1424{ 1425 char * str = * strp; 1426 long range = 0; 1427 int another_range; 1428 1429 /* We come back here if we get ranges concatenated by '+' or '|'. */ 1430 do 1431 { 1432 another_range = 0; 1433 1434 if (*str == '{') 1435 { 1436 int in_range = 0; 1437 int cur_reg = -1; 1438 1439 str++; 1440 do 1441 { 1442 int reg; 1443 1444 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) 1445 { 1446 first_error (_(reg_expected_msgs[REG_TYPE_RN])); 1447 return FAIL; 1448 } 1449 1450 if (in_range) 1451 { 1452 int i; 1453 1454 if (reg <= cur_reg) 1455 { 1456 first_error (_("bad range in register list")); 1457 return FAIL; 1458 } 1459 1460 for (i = cur_reg + 1; i < reg; i++) 1461 { 1462 if (range & (1 << i)) 1463 as_tsktsk 1464 (_("Warning: duplicated register (r%d) in register list"), 1465 i); 1466 else 1467 range |= 1 << i; 1468 } 1469 in_range = 0; 1470 } 1471 1472 if (range & (1 << reg)) 1473 as_tsktsk (_("Warning: duplicated register (r%d) in register list"), 1474 reg); 1475 else if (reg <= cur_reg) 1476 as_tsktsk (_("Warning: register range not in ascending order")); 1477 1478 range |= 1 << reg; 1479 cur_reg = reg; 1480 } 1481 while (skip_past_comma (&str) != FAIL 1482 || (in_range = 1, *str++ == '-')); 1483 str--; 1484 1485 if (*str++ != '}') 1486 { 1487 first_error (_("missing `}'")); 1488 return FAIL; 1489 } 1490 } 1491 else 1492 { 1493 expressionS expr; 1494 1495 if (my_get_expression (&expr, &str, GE_NO_PREFIX)) 1496 return FAIL; 1497 1498 if (expr.X_op == O_constant) 1499 { 1500 if (expr.X_add_number 1501 != (expr.X_add_number & 0x0000ffff)) 1502 { 1503 inst.error = _("invalid register mask"); 1504 return FAIL; 1505 } 1506 1507 if ((range & expr.X_add_number) != 0) 1508 { 1509 int regno = range & expr.X_add_number; 1510 1511 regno &= -regno; 1512 regno = (1 << regno) - 1; 1513 as_tsktsk 1514 (_("Warning: duplicated register (r%d) in register list"), 1515 regno); 1516 } 1517 1518 range |= expr.X_add_number; 1519 } 1520 else 1521 { 1522 if (inst.reloc.type != 0) 1523 { 1524 inst.error = _("expression too complex"); 1525 return FAIL; 1526 } 1527 1528 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS)); 1529 inst.reloc.type = BFD_RELOC_ARM_MULTI; 1530 inst.reloc.pc_rel = 0; 1531 } 1532 } 1533 1534 if (*str == '|' || *str == '+') 1535 { 1536 str++; 1537 another_range = 1; 1538 } 1539 } 1540 while (another_range); 1541 1542 *strp = str; 1543 return range; 1544} 1545 1546/* Types of registers in a list. */ 1547 1548enum reg_list_els 1549{ 1550 REGLIST_VFP_S, 1551 REGLIST_VFP_D, 1552 REGLIST_NEON_D 1553}; 1554 1555/* Parse a VFP register list. If the string is invalid return FAIL. 1556 Otherwise return the number of registers, and set PBASE to the first 1557 register. Parses registers of type ETYPE. 1558 If REGLIST_NEON_D is used, several syntax enhancements are enabled: 1559 - Q registers can be used to specify pairs of D registers 1560 - { } can be omitted from around a singleton register list 1561 FIXME: This is not implemented, as it would require backtracking in 1562 some cases, e.g.: 1563 vtbl.8 d3,d4,d5 1564 This could be done (the meaning isn't really ambiguous), but doesn't 1565 fit in well with the current parsing framework. 1566 - 32 D registers may be used (also true for VFPv3). 1567 FIXME: Types are ignored in these register lists, which is probably a 1568 bug. */ 1569 1570static int 1571parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) 1572{ 1573 char *str = *ccp; 1574 int base_reg; 1575 int new_base; 1576 enum arm_reg_type regtype = 0; 1577 int max_regs = 0; 1578 int count = 0; 1579 int warned = 0; 1580 unsigned long mask = 0; 1581 int i; 1582 1583 if (*str != '{') 1584 { 1585 inst.error = _("expecting {"); 1586 return FAIL; 1587 } 1588 1589 str++; 1590 1591 switch (etype) 1592 { 1593 case REGLIST_VFP_S: 1594 regtype = REG_TYPE_VFS; 1595 max_regs = 32; 1596 break; 1597 1598 case REGLIST_VFP_D: 1599 regtype = REG_TYPE_VFD; 1600 break; 1601 1602 case REGLIST_NEON_D: 1603 regtype = REG_TYPE_NDQ; 1604 break; 1605 } 1606 1607 if (etype != REGLIST_VFP_S) 1608 { 1609 /* VFPv3 allows 32 D registers. */ 1610 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3)) 1611 { 1612 max_regs = 32; 1613 if (thumb_mode) 1614 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 1615 fpu_vfp_ext_v3); 1616 else 1617 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 1618 fpu_vfp_ext_v3); 1619 } 1620 else 1621 max_regs = 16; 1622 } 1623 1624 base_reg = max_regs; 1625 1626 do 1627 { 1628 int setmask = 1, addregs = 1; 1629 1630 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); 1631 1632 if (new_base == FAIL) 1633 { 1634 first_error (_(reg_expected_msgs[regtype])); 1635 return FAIL; 1636 } 1637 1638 if (new_base >= max_regs) 1639 { 1640 first_error (_("register out of range in list")); 1641 return FAIL; 1642 } 1643 1644 /* Note: a value of 2 * n is returned for the register Q<n>. */ 1645 if (regtype == REG_TYPE_NQ) 1646 { 1647 setmask = 3; 1648 addregs = 2; 1649 } 1650 1651 if (new_base < base_reg) 1652 base_reg = new_base; 1653 1654 if (mask & (setmask << new_base)) 1655 { 1656 first_error (_("invalid register list")); 1657 return FAIL; 1658 } 1659 1660 if ((mask >> new_base) != 0 && ! warned) 1661 { 1662 as_tsktsk (_("register list not in ascending order")); 1663 warned = 1; 1664 } 1665 1666 mask |= setmask << new_base; 1667 count += addregs; 1668 1669 if (*str == '-') /* We have the start of a range expression */ 1670 { 1671 int high_range; 1672 1673 str++; 1674 1675 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) 1676 == FAIL) 1677 { 1678 inst.error = gettext (reg_expected_msgs[regtype]); 1679 return FAIL; 1680 } 1681 1682 if (high_range >= max_regs) 1683 { 1684 first_error (_("register out of range in list")); 1685 return FAIL; 1686 } 1687 1688 if (regtype == REG_TYPE_NQ) 1689 high_range = high_range + 1; 1690 1691 if (high_range <= new_base) 1692 { 1693 inst.error = _("register range not in ascending order"); 1694 return FAIL; 1695 } 1696 1697 for (new_base += addregs; new_base <= high_range; new_base += addregs) 1698 { 1699 if (mask & (setmask << new_base)) 1700 { 1701 inst.error = _("invalid register list"); 1702 return FAIL; 1703 } 1704 1705 mask |= setmask << new_base; 1706 count += addregs; 1707 } 1708 } 1709 } 1710 while (skip_past_comma (&str) != FAIL); 1711 1712 str++; 1713 1714 /* Sanity check -- should have raised a parse error above. */ 1715 if (count == 0 || count > max_regs) 1716 abort (); 1717 1718 *pbase = base_reg; 1719 1720 /* Final test -- the registers must be consecutive. */ 1721 mask >>= base_reg; 1722 for (i = 0; i < count; i++) 1723 { 1724 if ((mask & (1u << i)) == 0) 1725 { 1726 inst.error = _("non-contiguous register range"); 1727 return FAIL; 1728 } 1729 } 1730 1731 *ccp = str; 1732 1733 return count; 1734} 1735 1736/* True if two alias types are the same. */ 1737 1738static int 1739neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) 1740{ 1741 if (!a && !b) 1742 return 1; 1743 1744 if (!a || !b) 1745 return 0; 1746 1747 if (a->defined != b->defined) 1748 return 0; 1749 1750 if ((a->defined & NTA_HASTYPE) != 0 1751 && (a->eltype.type != b->eltype.type 1752 || a->eltype.size != b->eltype.size)) 1753 return 0; 1754 1755 if ((a->defined & NTA_HASINDEX) != 0 1756 && (a->index != b->index)) 1757 return 0; 1758 1759 return 1; 1760} 1761 1762/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. 1763 The base register is put in *PBASE. 1764 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of 1765 the return value. 1766 The register stride (minus one) is put in bit 4 of the return value. 1767 Bits [6:5] encode the list length (minus one). 1768 The type of the list elements is put in *ELTYPE, if non-NULL. */ 1769 1770#define NEON_LANE(X) ((X) & 0xf) 1771#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) 1772#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) 1773 1774static int 1775parse_neon_el_struct_list (char **str, unsigned *pbase, 1776 struct neon_type_el *eltype) 1777{ 1778 char *ptr = *str; 1779 int base_reg = -1; 1780 int reg_incr = -1; 1781 int count = 0; 1782 int lane = -1; 1783 int leading_brace = 0; 1784 enum arm_reg_type rtype = REG_TYPE_NDQ; 1785 int addregs = 1; 1786 const char *const incr_error = "register stride must be 1 or 2"; 1787 const char *const type_error = "mismatched element/structure types in list"; 1788 struct neon_typed_alias firsttype; 1789 1790 if (skip_past_char (&ptr, '{') == SUCCESS) 1791 leading_brace = 1; 1792 1793 do 1794 { 1795 struct neon_typed_alias atype; 1796 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); 1797 1798 if (getreg == FAIL) 1799 { 1800 first_error (_(reg_expected_msgs[rtype])); 1801 return FAIL; 1802 } 1803 1804 if (base_reg == -1) 1805 { 1806 base_reg = getreg; 1807 if (rtype == REG_TYPE_NQ) 1808 { 1809 reg_incr = 1; 1810 addregs = 2; 1811 } 1812 firsttype = atype; 1813 } 1814 else if (reg_incr == -1) 1815 { 1816 reg_incr = getreg - base_reg; 1817 if (reg_incr < 1 || reg_incr > 2) 1818 { 1819 first_error (_(incr_error)); 1820 return FAIL; 1821 } 1822 } 1823 else if (getreg != base_reg + reg_incr * count) 1824 { 1825 first_error (_(incr_error)); 1826 return FAIL; 1827 } 1828 1829 if (!neon_alias_types_same (&atype, &firsttype)) 1830 { 1831 first_error (_(type_error)); 1832 return FAIL; 1833 } 1834 1835 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list 1836 modes. */ 1837 if (ptr[0] == '-') 1838 { 1839 struct neon_typed_alias htype; 1840 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; 1841 if (lane == -1) 1842 lane = NEON_INTERLEAVE_LANES; 1843 else if (lane != NEON_INTERLEAVE_LANES) 1844 { 1845 first_error (_(type_error)); 1846 return FAIL; 1847 } 1848 if (reg_incr == -1) 1849 reg_incr = 1; 1850 else if (reg_incr != 1) 1851 { 1852 first_error (_("don't use Rn-Rm syntax with non-unit stride")); 1853 return FAIL; 1854 } 1855 ptr++; 1856 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); 1857 if (hireg == FAIL) 1858 { 1859 first_error (_(reg_expected_msgs[rtype])); 1860 return FAIL; 1861 } 1862 if (!neon_alias_types_same (&htype, &firsttype)) 1863 { 1864 first_error (_(type_error)); 1865 return FAIL; 1866 } 1867 count += hireg + dregs - getreg; 1868 continue; 1869 } 1870 1871 /* If we're using Q registers, we can't use [] or [n] syntax. */ 1872 if (rtype == REG_TYPE_NQ) 1873 { 1874 count += 2; 1875 continue; 1876 } 1877 1878 if ((atype.defined & NTA_HASINDEX) != 0) 1879 { 1880 if (lane == -1) 1881 lane = atype.index; 1882 else if (lane != atype.index) 1883 { 1884 first_error (_(type_error)); 1885 return FAIL; 1886 } 1887 } 1888 else if (lane == -1) 1889 lane = NEON_INTERLEAVE_LANES; 1890 else if (lane != NEON_INTERLEAVE_LANES) 1891 { 1892 first_error (_(type_error)); 1893 return FAIL; 1894 } 1895 count++; 1896 } 1897 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); 1898 1899 /* No lane set by [x]. We must be interleaving structures. */ 1900 if (lane == -1) 1901 lane = NEON_INTERLEAVE_LANES; 1902 1903 /* Sanity check. */ 1904 if (lane == -1 || base_reg == -1 || count < 1 || count > 4 1905 || (count > 1 && reg_incr == -1)) 1906 { 1907 first_error (_("error parsing element/structure list")); 1908 return FAIL; 1909 } 1910 1911 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) 1912 { 1913 first_error (_("expected }")); 1914 return FAIL; 1915 } 1916 1917 if (reg_incr == -1) 1918 reg_incr = 1; 1919 1920 if (eltype) 1921 *eltype = firsttype.eltype; 1922 1923 *pbase = base_reg; 1924 *str = ptr; 1925 1926 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); 1927} 1928 1929/* Parse an explicit relocation suffix on an expression. This is 1930 either nothing, or a word in parentheses. Note that if !OBJ_ELF, 1931 arm_reloc_hsh contains no entries, so this function can only 1932 succeed if there is no () after the word. Returns -1 on error, 1933 BFD_RELOC_UNUSED if there wasn't any suffix. */ 1934static int 1935parse_reloc (char **str) 1936{ 1937 struct reloc_entry *r; 1938 char *p, *q; 1939 1940 if (**str != '(') 1941 return BFD_RELOC_UNUSED; 1942 1943 p = *str + 1; 1944 q = p; 1945 1946 while (*q && *q != ')' && *q != ',') 1947 q++; 1948 if (*q != ')') 1949 return -1; 1950 1951 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) 1952 return -1; 1953 1954 *str = q + 1; 1955 return r->reloc; 1956} 1957 1958/* Directives: register aliases. */ 1959 1960static struct reg_entry * 1961insert_reg_alias (char *str, int number, int type) 1962{ 1963 struct reg_entry *new; 1964 const char *name; 1965 1966 if ((new = hash_find (arm_reg_hsh, str)) != 0) 1967 { 1968 if (new->builtin) 1969 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); 1970 1971 /* Only warn about a redefinition if it's not defined as the 1972 same register. */ 1973 else if (new->number != number || new->type != type) 1974 as_warn (_("ignoring redefinition of register alias '%s'"), str); 1975 1976 return 0; 1977 } 1978 1979 name = xstrdup (str); 1980 new = xmalloc (sizeof (struct reg_entry)); 1981 1982 new->name = name; 1983 new->number = number; 1984 new->type = type; 1985 new->builtin = FALSE; 1986 new->neon = NULL; 1987 1988 if (hash_insert (arm_reg_hsh, name, (PTR) new)) 1989 abort (); 1990 1991 return new; 1992} 1993 1994static void 1995insert_neon_reg_alias (char *str, int number, int type, 1996 struct neon_typed_alias *atype) 1997{ 1998 struct reg_entry *reg = insert_reg_alias (str, number, type); 1999 2000 if (!reg) 2001 { 2002 first_error (_("attempt to redefine typed alias")); 2003 return; 2004 } 2005 2006 if (atype) 2007 { 2008 reg->neon = xmalloc (sizeof (struct neon_typed_alias)); 2009 *reg->neon = *atype; 2010 } 2011} 2012 2013/* Look for the .req directive. This is of the form: 2014 2015 new_register_name .req existing_register_name 2016 2017 If we find one, or if it looks sufficiently like one that we want to 2018 handle any error here, return non-zero. Otherwise return zero. */ 2019 2020static int 2021create_register_alias (char * newname, char *p) 2022{ 2023 struct reg_entry *old; 2024 char *oldname, *nbuf; 2025 size_t nlen; 2026 2027 /* The input scrubber ensures that whitespace after the mnemonic is 2028 collapsed to single spaces. */ 2029 oldname = p; 2030 if (strncmp (oldname, " .req ", 6) != 0) 2031 return 0; 2032 2033 oldname += 6; 2034 if (*oldname == '\0') 2035 return 0; 2036 2037 old = hash_find (arm_reg_hsh, oldname); 2038 if (!old) 2039 { 2040 as_warn (_("unknown register '%s' -- .req ignored"), oldname); 2041 return 1; 2042 } 2043 2044 /* If TC_CASE_SENSITIVE is defined, then newname already points to 2045 the desired alias name, and p points to its end. If not, then 2046 the desired alias name is in the global original_case_string. */ 2047#ifdef TC_CASE_SENSITIVE 2048 nlen = p - newname; 2049#else 2050 newname = original_case_string; 2051 nlen = strlen (newname); 2052#endif 2053 2054 nbuf = alloca (nlen + 1); 2055 memcpy (nbuf, newname, nlen); 2056 nbuf[nlen] = '\0'; 2057 2058 /* Create aliases under the new name as stated; an all-lowercase 2059 version of the new name; and an all-uppercase version of the new 2060 name. */ 2061 insert_reg_alias (nbuf, old->number, old->type); 2062 2063 for (p = nbuf; *p; p++) 2064 *p = TOUPPER (*p); 2065 2066 if (strncmp (nbuf, newname, nlen)) 2067 insert_reg_alias (nbuf, old->number, old->type); 2068 2069 for (p = nbuf; *p; p++) 2070 *p = TOLOWER (*p); 2071 2072 if (strncmp (nbuf, newname, nlen)) 2073 insert_reg_alias (nbuf, old->number, old->type); 2074 2075 return 1; 2076} 2077 2078/* Create a Neon typed/indexed register alias using directives, e.g.: 2079 X .dn d5.s32[1] 2080 Y .qn 6.s16 2081 Z .dn d7 2082 T .dn Z[0] 2083 These typed registers can be used instead of the types specified after the 2084 Neon mnemonic, so long as all operands given have types. Types can also be 2085 specified directly, e.g.: 2086 vadd d0.s32, d1.s32, d2.s32 2087*/ 2088 2089static int 2090create_neon_reg_alias (char *newname, char *p) 2091{ 2092 enum arm_reg_type basetype; 2093 struct reg_entry *basereg; 2094 struct reg_entry mybasereg; 2095 struct neon_type ntype; 2096 struct neon_typed_alias typeinfo; 2097 char *namebuf, *nameend; 2098 int namelen; 2099 2100 typeinfo.defined = 0; 2101 typeinfo.eltype.type = NT_invtype; 2102 typeinfo.eltype.size = -1; 2103 typeinfo.index = -1; 2104 2105 nameend = p; 2106 2107 if (strncmp (p, " .dn ", 5) == 0) 2108 basetype = REG_TYPE_VFD; 2109 else if (strncmp (p, " .qn ", 5) == 0) 2110 basetype = REG_TYPE_NQ; 2111 else 2112 return 0; 2113 2114 p += 5; 2115 2116 if (*p == '\0') 2117 return 0; 2118 2119 basereg = arm_reg_parse_multi (&p); 2120 2121 if (basereg && basereg->type != basetype) 2122 { 2123 as_bad (_("bad type for register")); 2124 return 0; 2125 } 2126 2127 if (basereg == NULL) 2128 { 2129 expressionS exp; 2130 /* Try parsing as an integer. */ 2131 my_get_expression (&exp, &p, GE_NO_PREFIX); 2132 if (exp.X_op != O_constant) 2133 { 2134 as_bad (_("expression must be constant")); 2135 return 0; 2136 } 2137 basereg = &mybasereg; 2138 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 2139 : exp.X_add_number; 2140 basereg->neon = 0; 2141 } 2142 2143 if (basereg->neon) 2144 typeinfo = *basereg->neon; 2145 2146 if (parse_neon_type (&ntype, &p) == SUCCESS) 2147 { 2148 /* We got a type. */ 2149 if (typeinfo.defined & NTA_HASTYPE) 2150 { 2151 as_bad (_("can't redefine the type of a register alias")); 2152 return 0; 2153 } 2154 2155 typeinfo.defined |= NTA_HASTYPE; 2156 if (ntype.elems != 1) 2157 { 2158 as_bad (_("you must specify a single type only")); 2159 return 0; 2160 } 2161 typeinfo.eltype = ntype.el[0]; 2162 } 2163 2164 if (skip_past_char (&p, '[') == SUCCESS) 2165 { 2166 expressionS exp; 2167 /* We got a scalar index. */ 2168 2169 if (typeinfo.defined & NTA_HASINDEX) 2170 { 2171 as_bad (_("can't redefine the index of a scalar alias")); 2172 return 0; 2173 } 2174 2175 my_get_expression (&exp, &p, GE_NO_PREFIX); 2176 2177 if (exp.X_op != O_constant) 2178 { 2179 as_bad (_("scalar index must be constant")); 2180 return 0; 2181 } 2182 2183 typeinfo.defined |= NTA_HASINDEX; 2184 typeinfo.index = exp.X_add_number; 2185 2186 if (skip_past_char (&p, ']') == FAIL) 2187 { 2188 as_bad (_("expecting ]")); 2189 return 0; 2190 } 2191 } 2192 2193 namelen = nameend - newname; 2194 namebuf = alloca (namelen + 1); 2195 strncpy (namebuf, newname, namelen); 2196 namebuf[namelen] = '\0'; 2197 2198 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2199 typeinfo.defined != 0 ? &typeinfo : NULL); 2200 2201 /* Insert name in all uppercase. */ 2202 for (p = namebuf; *p; p++) 2203 *p = TOUPPER (*p); 2204 2205 if (strncmp (namebuf, newname, namelen)) 2206 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2207 typeinfo.defined != 0 ? &typeinfo : NULL); 2208 2209 /* Insert name in all lowercase. */ 2210 for (p = namebuf; *p; p++) 2211 *p = TOLOWER (*p); 2212 2213 if (strncmp (namebuf, newname, namelen)) 2214 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2215 typeinfo.defined != 0 ? &typeinfo : NULL); 2216 2217 return 1; 2218} 2219 2220/* Should never be called, as .req goes between the alias and the 2221 register name, not at the beginning of the line. */ 2222static void 2223s_req (int a ATTRIBUTE_UNUSED) 2224{ 2225 as_bad (_("invalid syntax for .req directive")); 2226} 2227 2228static void 2229s_dn (int a ATTRIBUTE_UNUSED) 2230{ 2231 as_bad (_("invalid syntax for .dn directive")); 2232} 2233 2234static void 2235s_qn (int a ATTRIBUTE_UNUSED) 2236{ 2237 as_bad (_("invalid syntax for .qn directive")); 2238} 2239 2240/* The .unreq directive deletes an alias which was previously defined 2241 by .req. For example: 2242 2243 my_alias .req r11 2244 .unreq my_alias */ 2245 2246static void 2247s_unreq (int a ATTRIBUTE_UNUSED) 2248{ 2249 char * name; 2250 char saved_char; 2251 2252 name = input_line_pointer; 2253 2254 while (*input_line_pointer != 0 2255 && *input_line_pointer != ' ' 2256 && *input_line_pointer != '\n') 2257 ++input_line_pointer; 2258 2259 saved_char = *input_line_pointer; 2260 *input_line_pointer = 0; 2261 2262 if (!*name) 2263 as_bad (_("invalid syntax for .unreq directive")); 2264 else 2265 { 2266 struct reg_entry *reg = hash_find (arm_reg_hsh, name); 2267 2268 if (!reg) 2269 as_bad (_("unknown register alias '%s'"), name); 2270 else if (reg->builtin) 2271 as_warn (_("ignoring attempt to undefine built-in register '%s'"), 2272 name); 2273 else 2274 { 2275 hash_delete (arm_reg_hsh, name); 2276 free ((char *) reg->name); 2277 if (reg->neon) 2278 free (reg->neon); 2279 free (reg); 2280 } 2281 } 2282 2283 *input_line_pointer = saved_char; 2284 demand_empty_rest_of_line (); 2285} 2286 2287/* Directives: Instruction set selection. */ 2288 2289#ifdef OBJ_ELF 2290/* This code is to handle mapping symbols as defined in the ARM ELF spec. 2291 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). 2292 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), 2293 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ 2294 2295static enum mstate mapstate = MAP_UNDEFINED; 2296 2297void 2298mapping_state (enum mstate state) 2299{ 2300 symbolS * symbolP; 2301 const char * symname; 2302 int type; 2303 2304 if (mapstate == state) 2305 /* The mapping symbol has already been emitted. 2306 There is nothing else to do. */ 2307 return; 2308 2309 mapstate = state; 2310 2311 switch (state) 2312 { 2313 case MAP_DATA: 2314 symname = "$d"; 2315 type = BSF_NO_FLAGS; 2316 break; 2317 case MAP_ARM: 2318 symname = "$a"; 2319 type = BSF_NO_FLAGS; 2320 break; 2321 case MAP_THUMB: 2322 symname = "$t"; 2323 type = BSF_NO_FLAGS; 2324 break; 2325 case MAP_UNDEFINED: 2326 return; 2327 default: 2328 abort (); 2329 } 2330 2331 seg_info (now_seg)->tc_segment_info_data.mapstate = state; 2332 2333 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now); 2334 symbol_table_insert (symbolP); 2335 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; 2336 2337 switch (state) 2338 { 2339 case MAP_ARM: 2340 THUMB_SET_FUNC (symbolP, 0); 2341 ARM_SET_THUMB (symbolP, 0); 2342 ARM_SET_INTERWORK (symbolP, support_interwork); 2343 break; 2344 2345 case MAP_THUMB: 2346 THUMB_SET_FUNC (symbolP, 1); 2347 ARM_SET_THUMB (symbolP, 1); 2348 ARM_SET_INTERWORK (symbolP, support_interwork); 2349 break; 2350 2351 case MAP_DATA: 2352 default: 2353 return; 2354 } 2355} 2356#else 2357#define mapping_state(x) /* nothing */ 2358#endif 2359 2360/* Find the real, Thumb encoded start of a Thumb function. */ 2361 2362static symbolS * 2363find_real_start (symbolS * symbolP) 2364{ 2365 char * real_start; 2366 const char * name = S_GET_NAME (symbolP); 2367 symbolS * new_target; 2368 2369 /* This definition must agree with the one in gcc/config/arm/thumb.c. */ 2370#define STUB_NAME ".real_start_of" 2371 2372 if (name == NULL) 2373 abort (); 2374 2375 /* The compiler may generate BL instructions to local labels because 2376 it needs to perform a branch to a far away location. These labels 2377 do not have a corresponding ".real_start_of" label. We check 2378 both for S_IS_LOCAL and for a leading dot, to give a way to bypass 2379 the ".real_start_of" convention for nonlocal branches. */ 2380 if (S_IS_LOCAL (symbolP) || name[0] == '.') 2381 return symbolP; 2382 2383 real_start = ACONCAT ((STUB_NAME, name, NULL)); 2384 new_target = symbol_find (real_start); 2385 2386 if (new_target == NULL) 2387 { 2388 as_warn ("Failed to find real start of function: %s\n", name); 2389 new_target = symbolP; 2390 } 2391 2392 return new_target; 2393} 2394 2395static void 2396opcode_select (int width) 2397{ 2398 switch (width) 2399 { 2400 case 16: 2401 if (! thumb_mode) 2402 { 2403 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 2404 as_bad (_("selected processor does not support THUMB opcodes")); 2405 2406 thumb_mode = 1; 2407 /* No need to force the alignment, since we will have been 2408 coming from ARM mode, which is word-aligned. */ 2409 record_alignment (now_seg, 1); 2410 } 2411 mapping_state (MAP_THUMB); 2412 break; 2413 2414 case 32: 2415 if (thumb_mode) 2416 { 2417 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 2418 as_bad (_("selected processor does not support ARM opcodes")); 2419 2420 thumb_mode = 0; 2421 2422 if (!need_pass_2) 2423 frag_align (2, 0, 0); 2424 2425 record_alignment (now_seg, 1); 2426 } 2427 mapping_state (MAP_ARM); 2428 break; 2429 2430 default: 2431 as_bad (_("invalid instruction size selected (%d)"), width); 2432 } 2433} 2434 2435static void 2436s_arm (int ignore ATTRIBUTE_UNUSED) 2437{ 2438 opcode_select (32); 2439 demand_empty_rest_of_line (); 2440} 2441 2442static void 2443s_thumb (int ignore ATTRIBUTE_UNUSED) 2444{ 2445 opcode_select (16); 2446 demand_empty_rest_of_line (); 2447} 2448 2449static void 2450s_code (int unused ATTRIBUTE_UNUSED) 2451{ 2452 int temp; 2453 2454 temp = get_absolute_expression (); 2455 switch (temp) 2456 { 2457 case 16: 2458 case 32: 2459 opcode_select (temp); 2460 break; 2461 2462 default: 2463 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); 2464 } 2465} 2466 2467static void 2468s_force_thumb (int ignore ATTRIBUTE_UNUSED) 2469{ 2470 /* If we are not already in thumb mode go into it, EVEN if 2471 the target processor does not support thumb instructions. 2472 This is used by gcc/config/arm/lib1funcs.asm for example 2473 to compile interworking support functions even if the 2474 target processor should not support interworking. */ 2475 if (! thumb_mode) 2476 { 2477 thumb_mode = 2; 2478 record_alignment (now_seg, 1); 2479 } 2480 2481 demand_empty_rest_of_line (); 2482} 2483 2484static void 2485s_thumb_func (int ignore ATTRIBUTE_UNUSED) 2486{ 2487 s_thumb (0); 2488 2489 /* The following label is the name/address of the start of a Thumb function. 2490 We need to know this for the interworking support. */ 2491 label_is_thumb_function_name = TRUE; 2492} 2493 2494/* Perform a .set directive, but also mark the alias as 2495 being a thumb function. */ 2496 2497static void 2498s_thumb_set (int equiv) 2499{ 2500 /* XXX the following is a duplicate of the code for s_set() in read.c 2501 We cannot just call that code as we need to get at the symbol that 2502 is created. */ 2503 char * name; 2504 char delim; 2505 char * end_name; 2506 symbolS * symbolP; 2507 2508 /* Especial apologies for the random logic: 2509 This just grew, and could be parsed much more simply! 2510 Dean - in haste. */ 2511 name = input_line_pointer; 2512 delim = get_symbol_end (); 2513 end_name = input_line_pointer; 2514 *end_name = delim; 2515 2516 if (*input_line_pointer != ',') 2517 { 2518 *end_name = 0; 2519 as_bad (_("expected comma after name \"%s\""), name); 2520 *end_name = delim; 2521 ignore_rest_of_line (); 2522 return; 2523 } 2524 2525 input_line_pointer++; 2526 *end_name = 0; 2527 2528 if (name[0] == '.' && name[1] == '\0') 2529 { 2530 /* XXX - this should not happen to .thumb_set. */ 2531 abort (); 2532 } 2533 2534 if ((symbolP = symbol_find (name)) == NULL 2535 && (symbolP = md_undefined_symbol (name)) == NULL) 2536 { 2537#ifndef NO_LISTING 2538 /* When doing symbol listings, play games with dummy fragments living 2539 outside the normal fragment chain to record the file and line info 2540 for this symbol. */ 2541 if (listing & LISTING_SYMBOLS) 2542 { 2543 extern struct list_info_struct * listing_tail; 2544 fragS * dummy_frag = xmalloc (sizeof (fragS)); 2545 2546 memset (dummy_frag, 0, sizeof (fragS)); 2547 dummy_frag->fr_type = rs_fill; 2548 dummy_frag->line = listing_tail; 2549 symbolP = symbol_new (name, undefined_section, 0, dummy_frag); 2550 dummy_frag->fr_symbol = symbolP; 2551 } 2552 else 2553#endif 2554 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); 2555 2556#ifdef OBJ_COFF 2557 /* "set" symbols are local unless otherwise specified. */ 2558 SF_SET_LOCAL (symbolP); 2559#endif /* OBJ_COFF */ 2560 } /* Make a new symbol. */ 2561 2562 symbol_table_insert (symbolP); 2563 2564 * end_name = delim; 2565 2566 if (equiv 2567 && S_IS_DEFINED (symbolP) 2568 && S_GET_SEGMENT (symbolP) != reg_section) 2569 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); 2570 2571 pseudo_set (symbolP); 2572 2573 demand_empty_rest_of_line (); 2574 2575 /* XXX Now we come to the Thumb specific bit of code. */ 2576 2577 THUMB_SET_FUNC (symbolP, 1); 2578 ARM_SET_THUMB (symbolP, 1); 2579#if defined OBJ_ELF || defined OBJ_COFF 2580 ARM_SET_INTERWORK (symbolP, support_interwork); 2581#endif 2582} 2583 2584/* Directives: Mode selection. */ 2585 2586/* .syntax [unified|divided] - choose the new unified syntax 2587 (same for Arm and Thumb encoding, modulo slight differences in what 2588 can be represented) or the old divergent syntax for each mode. */ 2589static void 2590s_syntax (int unused ATTRIBUTE_UNUSED) 2591{ 2592 char *name, delim; 2593 2594 name = input_line_pointer; 2595 delim = get_symbol_end (); 2596 2597 if (!strcasecmp (name, "unified")) 2598 unified_syntax = TRUE; 2599 else if (!strcasecmp (name, "divided")) 2600 unified_syntax = FALSE; 2601 else 2602 { 2603 as_bad (_("unrecognized syntax mode \"%s\""), name); 2604 return; 2605 } 2606 *input_line_pointer = delim; 2607 demand_empty_rest_of_line (); 2608} 2609 2610/* Directives: sectioning and alignment. */ 2611 2612/* Same as s_align_ptwo but align 0 => align 2. */ 2613 2614static void 2615s_align (int unused ATTRIBUTE_UNUSED) 2616{ 2617 int temp; 2618 bfd_boolean fill_p; 2619 long temp_fill; 2620 long max_alignment = 15; 2621 2622 temp = get_absolute_expression (); 2623 if (temp > max_alignment) 2624 as_bad (_("alignment too large: %d assumed"), temp = max_alignment); 2625 else if (temp < 0) 2626 { 2627 as_bad (_("alignment negative. 0 assumed.")); 2628 temp = 0; 2629 } 2630 2631 if (*input_line_pointer == ',') 2632 { 2633 input_line_pointer++; 2634 temp_fill = get_absolute_expression (); 2635 fill_p = TRUE; 2636 } 2637 else 2638 { 2639 fill_p = FALSE; 2640 temp_fill = 0; 2641 } 2642 2643 if (!temp) 2644 temp = 2; 2645 2646 /* Only make a frag if we HAVE to. */ 2647 if (temp && !need_pass_2) 2648 { 2649 if (!fill_p && subseg_text_p (now_seg)) 2650 frag_align_code (temp, 0); 2651 else 2652 frag_align (temp, (int) temp_fill, 0); 2653 } 2654 demand_empty_rest_of_line (); 2655 2656 record_alignment (now_seg, temp); 2657} 2658 2659static void 2660s_bss (int ignore ATTRIBUTE_UNUSED) 2661{ 2662 /* We don't support putting frags in the BSS segment, we fake it by 2663 marking in_bss, then looking at s_skip for clues. */ 2664 subseg_set (bss_section, 0); 2665 demand_empty_rest_of_line (); 2666 mapping_state (MAP_DATA); 2667} 2668 2669static void 2670s_even (int ignore ATTRIBUTE_UNUSED) 2671{ 2672 /* Never make frag if expect extra pass. */ 2673 if (!need_pass_2) 2674 frag_align (1, 0, 0); 2675 2676 record_alignment (now_seg, 1); 2677 2678 demand_empty_rest_of_line (); 2679} 2680 2681/* Directives: Literal pools. */ 2682 2683static literal_pool * 2684find_literal_pool (void) 2685{ 2686 literal_pool * pool; 2687 2688 for (pool = list_of_pools; pool != NULL; pool = pool->next) 2689 { 2690 if (pool->section == now_seg 2691 && pool->sub_section == now_subseg) 2692 break; 2693 } 2694 2695 return pool; 2696} 2697 2698static literal_pool * 2699find_or_make_literal_pool (void) 2700{ 2701 /* Next literal pool ID number. */ 2702 static unsigned int latest_pool_num = 1; 2703 literal_pool * pool; 2704 2705 pool = find_literal_pool (); 2706 2707 if (pool == NULL) 2708 { 2709 /* Create a new pool. */ 2710 pool = xmalloc (sizeof (* pool)); 2711 if (! pool) 2712 return NULL; 2713 2714 pool->next_free_entry = 0; 2715 pool->section = now_seg; 2716 pool->sub_section = now_subseg; 2717 pool->next = list_of_pools; 2718 pool->symbol = NULL; 2719 2720 /* Add it to the list. */ 2721 list_of_pools = pool; 2722 } 2723 2724 /* New pools, and emptied pools, will have a NULL symbol. */ 2725 if (pool->symbol == NULL) 2726 { 2727 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, 2728 (valueT) 0, &zero_address_frag); 2729 pool->id = latest_pool_num ++; 2730 } 2731 2732 /* Done. */ 2733 return pool; 2734} 2735 2736/* Add the literal in the global 'inst' 2737 structure to the relevent literal pool. */ 2738 2739static int 2740add_to_lit_pool (void) 2741{ 2742 literal_pool * pool; 2743 unsigned int entry; 2744 2745 pool = find_or_make_literal_pool (); 2746 2747 /* Check if this literal value is already in the pool. */ 2748 for (entry = 0; entry < pool->next_free_entry; entry ++) 2749 { 2750 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) 2751 && (inst.reloc.exp.X_op == O_constant) 2752 && (pool->literals[entry].X_add_number 2753 == inst.reloc.exp.X_add_number) 2754 && (pool->literals[entry].X_unsigned 2755 == inst.reloc.exp.X_unsigned)) 2756 break; 2757 2758 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) 2759 && (inst.reloc.exp.X_op == O_symbol) 2760 && (pool->literals[entry].X_add_number 2761 == inst.reloc.exp.X_add_number) 2762 && (pool->literals[entry].X_add_symbol 2763 == inst.reloc.exp.X_add_symbol) 2764 && (pool->literals[entry].X_op_symbol 2765 == inst.reloc.exp.X_op_symbol)) 2766 break; 2767 } 2768 2769 /* Do we need to create a new entry? */ 2770 if (entry == pool->next_free_entry) 2771 { 2772 if (entry >= MAX_LITERAL_POOL_SIZE) 2773 { 2774 inst.error = _("literal pool overflow"); 2775 return FAIL; 2776 } 2777 2778 pool->literals[entry] = inst.reloc.exp; 2779 pool->next_free_entry += 1; 2780 } 2781 2782 inst.reloc.exp.X_op = O_symbol; 2783 inst.reloc.exp.X_add_number = ((int) entry) * 4; 2784 inst.reloc.exp.X_add_symbol = pool->symbol; 2785 2786 return SUCCESS; 2787} 2788 2789/* Can't use symbol_new here, so have to create a symbol and then at 2790 a later date assign it a value. Thats what these functions do. */ 2791 2792static void 2793symbol_locate (symbolS * symbolP, 2794 const char * name, /* It is copied, the caller can modify. */ 2795 segT segment, /* Segment identifier (SEG_<something>). */ 2796 valueT valu, /* Symbol value. */ 2797 fragS * frag) /* Associated fragment. */ 2798{ 2799 unsigned int name_length; 2800 char * preserved_copy_of_name; 2801 2802 name_length = strlen (name) + 1; /* +1 for \0. */ 2803 obstack_grow (¬es, name, name_length); 2804 preserved_copy_of_name = obstack_finish (¬es); 2805 2806#ifdef tc_canonicalize_symbol_name 2807 preserved_copy_of_name = 2808 tc_canonicalize_symbol_name (preserved_copy_of_name); 2809#endif 2810 2811 S_SET_NAME (symbolP, preserved_copy_of_name); 2812 2813 S_SET_SEGMENT (symbolP, segment); 2814 S_SET_VALUE (symbolP, valu); 2815 symbol_clear_list_pointers (symbolP); 2816 2817 symbol_set_frag (symbolP, frag); 2818 2819 /* Link to end of symbol chain. */ 2820 { 2821 extern int symbol_table_frozen; 2822 2823 if (symbol_table_frozen) 2824 abort (); 2825 } 2826 2827 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); 2828 2829 obj_symbol_new_hook (symbolP); 2830 2831#ifdef tc_symbol_new_hook 2832 tc_symbol_new_hook (symbolP); 2833#endif 2834 2835#ifdef DEBUG_SYMS 2836 verify_symbol_chain (symbol_rootP, symbol_lastP); 2837#endif /* DEBUG_SYMS */ 2838} 2839 2840 2841static void 2842s_ltorg (int ignored ATTRIBUTE_UNUSED) 2843{ 2844 unsigned int entry; 2845 literal_pool * pool; 2846 char sym_name[20]; 2847 2848 pool = find_literal_pool (); 2849 if (pool == NULL 2850 || pool->symbol == NULL 2851 || pool->next_free_entry == 0) 2852 return; 2853 2854 mapping_state (MAP_DATA); 2855 2856 /* Align pool as you have word accesses. 2857 Only make a frag if we have to. */ 2858 if (!need_pass_2) 2859 frag_align (2, 0, 0); 2860 2861 record_alignment (now_seg, 2); 2862 2863 sprintf (sym_name, "$$lit_\002%x", pool->id); 2864 2865 symbol_locate (pool->symbol, sym_name, now_seg, 2866 (valueT) frag_now_fix (), frag_now); 2867 symbol_table_insert (pool->symbol); 2868 2869 ARM_SET_THUMB (pool->symbol, thumb_mode); 2870 2871#if defined OBJ_COFF || defined OBJ_ELF 2872 ARM_SET_INTERWORK (pool->symbol, support_interwork); 2873#endif 2874 2875 for (entry = 0; entry < pool->next_free_entry; entry ++) 2876 /* First output the expression in the instruction to the pool. */ 2877 emit_expr (&(pool->literals[entry]), 4); /* .word */ 2878 2879 /* Mark the pool as empty. */ 2880 pool->next_free_entry = 0; 2881 pool->symbol = NULL; 2882} 2883 2884#ifdef OBJ_ELF 2885/* Forward declarations for functions below, in the MD interface 2886 section. */ 2887static void fix_new_arm (fragS *, int, short, expressionS *, int, int); 2888static valueT create_unwind_entry (int); 2889static void start_unwind_section (const segT, int); 2890static void add_unwind_opcode (valueT, int); 2891static void flush_pending_unwind (void); 2892 2893/* Directives: Data. */ 2894 2895static void 2896s_arm_elf_cons (int nbytes) 2897{ 2898 expressionS exp; 2899 2900#ifdef md_flush_pending_output 2901 md_flush_pending_output (); 2902#endif 2903 2904 if (is_it_end_of_statement ()) 2905 { 2906 demand_empty_rest_of_line (); 2907 return; 2908 } 2909 2910#ifdef md_cons_align 2911 md_cons_align (nbytes); 2912#endif 2913 2914 mapping_state (MAP_DATA); 2915 do 2916 { 2917 int reloc; 2918 char *base = input_line_pointer; 2919 2920 expression (& exp); 2921 2922 if (exp.X_op != O_symbol) 2923 emit_expr (&exp, (unsigned int) nbytes); 2924 else 2925 { 2926 char *before_reloc = input_line_pointer; 2927 reloc = parse_reloc (&input_line_pointer); 2928 if (reloc == -1) 2929 { 2930 as_bad (_("unrecognized relocation suffix")); 2931 ignore_rest_of_line (); 2932 return; 2933 } 2934 else if (reloc == BFD_RELOC_UNUSED) 2935 emit_expr (&exp, (unsigned int) nbytes); 2936 else 2937 { 2938 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc); 2939 int size = bfd_get_reloc_size (howto); 2940 2941 if (reloc == BFD_RELOC_ARM_PLT32) 2942 { 2943 as_bad (_("(plt) is only valid on branch targets")); 2944 reloc = BFD_RELOC_UNUSED; 2945 size = 0; 2946 } 2947 2948 if (size > nbytes) 2949 as_bad (_("%s relocations do not fit in %d bytes"), 2950 howto->name, nbytes); 2951 else 2952 { 2953 /* We've parsed an expression stopping at O_symbol. 2954 But there may be more expression left now that we 2955 have parsed the relocation marker. Parse it again. 2956 XXX Surely there is a cleaner way to do this. */ 2957 char *p = input_line_pointer; 2958 int offset; 2959 char *save_buf = alloca (input_line_pointer - base); 2960 memcpy (save_buf, base, input_line_pointer - base); 2961 memmove (base + (input_line_pointer - before_reloc), 2962 base, before_reloc - base); 2963 2964 input_line_pointer = base + (input_line_pointer-before_reloc); 2965 expression (&exp); 2966 memcpy (base, save_buf, p - base); 2967 2968 offset = nbytes - size; 2969 p = frag_more ((int) nbytes); 2970 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, 2971 size, &exp, 0, reloc); 2972 } 2973 } 2974 } 2975 } 2976 while (*input_line_pointer++ == ','); 2977 2978 /* Put terminator back into stream. */ 2979 input_line_pointer --; 2980 demand_empty_rest_of_line (); 2981} 2982 2983 2984/* Parse a .rel31 directive. */ 2985 2986static void 2987s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) 2988{ 2989 expressionS exp; 2990 char *p; 2991 valueT highbit; 2992 2993 highbit = 0; 2994 if (*input_line_pointer == '1') 2995 highbit = 0x80000000; 2996 else if (*input_line_pointer != '0') 2997 as_bad (_("expected 0 or 1")); 2998 2999 input_line_pointer++; 3000 if (*input_line_pointer != ',') 3001 as_bad (_("missing comma")); 3002 input_line_pointer++; 3003 3004#ifdef md_flush_pending_output 3005 md_flush_pending_output (); 3006#endif 3007 3008#ifdef md_cons_align 3009 md_cons_align (4); 3010#endif 3011 3012 mapping_state (MAP_DATA); 3013 3014 expression (&exp); 3015 3016 p = frag_more (4); 3017 md_number_to_chars (p, highbit, 4); 3018 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, 3019 BFD_RELOC_ARM_PREL31); 3020 3021 demand_empty_rest_of_line (); 3022} 3023 3024/* Directives: AEABI stack-unwind tables. */ 3025 3026/* Parse an unwind_fnstart directive. Simply records the current location. */ 3027 3028static void 3029s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) 3030{ 3031 demand_empty_rest_of_line (); 3032 /* Mark the start of the function. */ 3033 unwind.proc_start = expr_build_dot (); 3034 3035 /* Reset the rest of the unwind info. */ 3036 unwind.opcode_count = 0; 3037 unwind.table_entry = NULL; 3038 unwind.personality_routine = NULL; 3039 unwind.personality_index = -1; 3040 unwind.frame_size = 0; 3041 unwind.fp_offset = 0; 3042 unwind.fp_reg = 13; 3043 unwind.fp_used = 0; 3044 unwind.sp_restored = 0; 3045} 3046 3047 3048/* Parse a handlerdata directive. Creates the exception handling table entry 3049 for the function. */ 3050 3051static void 3052s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) 3053{ 3054 demand_empty_rest_of_line (); 3055 if (unwind.table_entry) 3056 as_bad (_("dupicate .handlerdata directive")); 3057 3058 create_unwind_entry (1); 3059} 3060 3061/* Parse an unwind_fnend directive. Generates the index table entry. */ 3062 3063static void 3064s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) 3065{ 3066 long where; 3067 char *ptr; 3068 valueT val; 3069 3070 demand_empty_rest_of_line (); 3071 3072 /* Add eh table entry. */ 3073 if (unwind.table_entry == NULL) 3074 val = create_unwind_entry (0); 3075 else 3076 val = 0; 3077 3078 /* Add index table entry. This is two words. */ 3079 start_unwind_section (unwind.saved_seg, 1); 3080 frag_align (2, 0, 0); 3081 record_alignment (now_seg, 2); 3082 3083 ptr = frag_more (8); 3084 memset(ptr, 0, 8); 3085 where = frag_now_fix () - 8; 3086 3087 /* Self relative offset of the function start. */ 3088 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, 3089 BFD_RELOC_ARM_PREL31); 3090 3091 /* Indicate dependency on EHABI-defined personality routines to the 3092 linker, if it hasn't been done already. */ 3093 if (unwind.personality_index >= 0 && unwind.personality_index < 3 3094 && !(marked_pr_dependency & (1 << unwind.personality_index))) 3095 { 3096 static const char *const name[] = { 3097 "__aeabi_unwind_cpp_pr0", 3098 "__aeabi_unwind_cpp_pr1", 3099 "__aeabi_unwind_cpp_pr2" 3100 }; 3101 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); 3102 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); 3103 marked_pr_dependency |= 1 << unwind.personality_index; 3104 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency 3105 = marked_pr_dependency; 3106 } 3107 3108 if (val) 3109 /* Inline exception table entry. */ 3110 md_number_to_chars (ptr + 4, val, 4); 3111 else 3112 /* Self relative offset of the table entry. */ 3113 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, 3114 BFD_RELOC_ARM_PREL31); 3115 3116 /* Restore the original section. */ 3117 subseg_set (unwind.saved_seg, unwind.saved_subseg); 3118} 3119 3120 3121/* Parse an unwind_cantunwind directive. */ 3122 3123static void 3124s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) 3125{ 3126 demand_empty_rest_of_line (); 3127 if (unwind.personality_routine || unwind.personality_index != -1) 3128 as_bad (_("personality routine specified for cantunwind frame")); 3129 3130 unwind.personality_index = -2; 3131} 3132 3133 3134/* Parse a personalityindex directive. */ 3135 3136static void 3137s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) 3138{ 3139 expressionS exp; 3140 3141 if (unwind.personality_routine || unwind.personality_index != -1) 3142 as_bad (_("duplicate .personalityindex directive")); 3143 3144 expression (&exp); 3145 3146 if (exp.X_op != O_constant 3147 || exp.X_add_number < 0 || exp.X_add_number > 15) 3148 { 3149 as_bad (_("bad personality routine number")); 3150 ignore_rest_of_line (); 3151 return; 3152 } 3153 3154 unwind.personality_index = exp.X_add_number; 3155 3156 demand_empty_rest_of_line (); 3157} 3158 3159 3160/* Parse a personality directive. */ 3161 3162static void 3163s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) 3164{ 3165 char *name, *p, c; 3166 3167 if (unwind.personality_routine || unwind.personality_index != -1) 3168 as_bad (_("duplicate .personality directive")); 3169 3170 name = input_line_pointer; 3171 c = get_symbol_end (); 3172 p = input_line_pointer; 3173 unwind.personality_routine = symbol_find_or_make (name); 3174 *p = c; 3175 demand_empty_rest_of_line (); 3176} 3177 3178 3179/* Parse a directive saving core registers. */ 3180 3181static void 3182s_arm_unwind_save_core (void) 3183{ 3184 valueT op; 3185 long range; 3186 int n; 3187 3188 range = parse_reg_list (&input_line_pointer); 3189 if (range == FAIL) 3190 { 3191 as_bad (_("expected register list")); 3192 ignore_rest_of_line (); 3193 return; 3194 } 3195 3196 demand_empty_rest_of_line (); 3197 3198 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} 3199 into .unwind_save {..., sp...}. We aren't bothered about the value of 3200 ip because it is clobbered by calls. */ 3201 if (unwind.sp_restored && unwind.fp_reg == 12 3202 && (range & 0x3000) == 0x1000) 3203 { 3204 unwind.opcode_count--; 3205 unwind.sp_restored = 0; 3206 range = (range | 0x2000) & ~0x1000; 3207 unwind.pending_offset = 0; 3208 } 3209 3210 /* Pop r4-r15. */ 3211 if (range & 0xfff0) 3212 { 3213 /* See if we can use the short opcodes. These pop a block of up to 8 3214 registers starting with r4, plus maybe r14. */ 3215 for (n = 0; n < 8; n++) 3216 { 3217 /* Break at the first non-saved register. */ 3218 if ((range & (1 << (n + 4))) == 0) 3219 break; 3220 } 3221 /* See if there are any other bits set. */ 3222 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) 3223 { 3224 /* Use the long form. */ 3225 op = 0x8000 | ((range >> 4) & 0xfff); 3226 add_unwind_opcode (op, 2); 3227 } 3228 else 3229 { 3230 /* Use the short form. */ 3231 if (range & 0x4000) 3232 op = 0xa8; /* Pop r14. */ 3233 else 3234 op = 0xa0; /* Do not pop r14. */ 3235 op |= (n - 1); 3236 add_unwind_opcode (op, 1); 3237 } 3238 } 3239 3240 /* Pop r0-r3. */ 3241 if (range & 0xf) 3242 { 3243 op = 0xb100 | (range & 0xf); 3244 add_unwind_opcode (op, 2); 3245 } 3246 3247 /* Record the number of bytes pushed. */ 3248 for (n = 0; n < 16; n++) 3249 { 3250 if (range & (1 << n)) 3251 unwind.frame_size += 4; 3252 } 3253} 3254 3255 3256/* Parse a directive saving FPA registers. */ 3257 3258static void 3259s_arm_unwind_save_fpa (int reg) 3260{ 3261 expressionS exp; 3262 int num_regs; 3263 valueT op; 3264 3265 /* Get Number of registers to transfer. */ 3266 if (skip_past_comma (&input_line_pointer) != FAIL) 3267 expression (&exp); 3268 else 3269 exp.X_op = O_illegal; 3270 3271 if (exp.X_op != O_constant) 3272 { 3273 as_bad (_("expected , <constant>")); 3274 ignore_rest_of_line (); 3275 return; 3276 } 3277 3278 num_regs = exp.X_add_number; 3279 3280 if (num_regs < 1 || num_regs > 4) 3281 { 3282 as_bad (_("number of registers must be in the range [1:4]")); 3283 ignore_rest_of_line (); 3284 return; 3285 } 3286 3287 demand_empty_rest_of_line (); 3288 3289 if (reg == 4) 3290 { 3291 /* Short form. */ 3292 op = 0xb4 | (num_regs - 1); 3293 add_unwind_opcode (op, 1); 3294 } 3295 else 3296 { 3297 /* Long form. */ 3298 op = 0xc800 | (reg << 4) | (num_regs - 1); 3299 add_unwind_opcode (op, 2); 3300 } 3301 unwind.frame_size += num_regs * 12; 3302} 3303 3304 3305/* Parse a directive saving VFP registers for ARMv6 and above. */ 3306 3307static void 3308s_arm_unwind_save_vfp_armv6 (void) 3309{ 3310 int count; 3311 unsigned int start; 3312 valueT op; 3313 int num_vfpv3_regs = 0; 3314 int num_regs_below_16; 3315 3316 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); 3317 if (count == FAIL) 3318 { 3319 as_bad (_("expected register list")); 3320 ignore_rest_of_line (); 3321 return; 3322 } 3323 3324 demand_empty_rest_of_line (); 3325 3326 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather 3327 than FSTMX/FLDMX-style ones). */ 3328 3329 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ 3330 if (start >= 16) 3331 num_vfpv3_regs = count; 3332 else if (start + count > 16) 3333 num_vfpv3_regs = start + count - 16; 3334 3335 if (num_vfpv3_regs > 0) 3336 { 3337 int start_offset = start > 16 ? start - 16 : 0; 3338 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); 3339 add_unwind_opcode (op, 2); 3340 } 3341 3342 /* Generate opcode for registers numbered in the range 0 .. 15. */ 3343 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; 3344 assert (num_regs_below_16 + num_vfpv3_regs == count); 3345 if (num_regs_below_16 > 0) 3346 { 3347 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); 3348 add_unwind_opcode (op, 2); 3349 } 3350 3351 unwind.frame_size += count * 8; 3352} 3353 3354 3355/* Parse a directive saving VFP registers for pre-ARMv6. */ 3356 3357static void 3358s_arm_unwind_save_vfp (void) 3359{ 3360 int count; 3361 unsigned int reg; 3362 valueT op; 3363 3364 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); 3365 if (count == FAIL) 3366 { 3367 as_bad (_("expected register list")); 3368 ignore_rest_of_line (); 3369 return; 3370 } 3371 3372 demand_empty_rest_of_line (); 3373 3374 if (reg == 8) 3375 { 3376 /* Short form. */ 3377 op = 0xb8 | (count - 1); 3378 add_unwind_opcode (op, 1); 3379 } 3380 else 3381 { 3382 /* Long form. */ 3383 op = 0xb300 | (reg << 4) | (count - 1); 3384 add_unwind_opcode (op, 2); 3385 } 3386 unwind.frame_size += count * 8 + 4; 3387} 3388 3389 3390/* Parse a directive saving iWMMXt data registers. */ 3391 3392static void 3393s_arm_unwind_save_mmxwr (void) 3394{ 3395 int reg; 3396 int hi_reg; 3397 int i; 3398 unsigned mask = 0; 3399 valueT op; 3400 3401 if (*input_line_pointer == '{') 3402 input_line_pointer++; 3403 3404 do 3405 { 3406 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); 3407 3408 if (reg == FAIL) 3409 { 3410 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); 3411 goto error; 3412 } 3413 3414 if (mask >> reg) 3415 as_tsktsk (_("register list not in ascending order")); 3416 mask |= 1 << reg; 3417 3418 if (*input_line_pointer == '-') 3419 { 3420 input_line_pointer++; 3421 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); 3422 if (hi_reg == FAIL) 3423 { 3424 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); 3425 goto error; 3426 } 3427 else if (reg >= hi_reg) 3428 { 3429 as_bad (_("bad register range")); 3430 goto error; 3431 } 3432 for (; reg < hi_reg; reg++) 3433 mask |= 1 << reg; 3434 } 3435 } 3436 while (skip_past_comma (&input_line_pointer) != FAIL); 3437 3438 if (*input_line_pointer == '}') 3439 input_line_pointer++; 3440 3441 demand_empty_rest_of_line (); 3442 3443 /* Generate any deferred opcodes because we're going to be looking at 3444 the list. */ 3445 flush_pending_unwind (); 3446 3447 for (i = 0; i < 16; i++) 3448 { 3449 if (mask & (1 << i)) 3450 unwind.frame_size += 8; 3451 } 3452 3453 /* Attempt to combine with a previous opcode. We do this because gcc 3454 likes to output separate unwind directives for a single block of 3455 registers. */ 3456 if (unwind.opcode_count > 0) 3457 { 3458 i = unwind.opcodes[unwind.opcode_count - 1]; 3459 if ((i & 0xf8) == 0xc0) 3460 { 3461 i &= 7; 3462 /* Only merge if the blocks are contiguous. */ 3463 if (i < 6) 3464 { 3465 if ((mask & 0xfe00) == (1 << 9)) 3466 { 3467 mask |= ((1 << (i + 11)) - 1) & 0xfc00; 3468 unwind.opcode_count--; 3469 } 3470 } 3471 else if (i == 6 && unwind.opcode_count >= 2) 3472 { 3473 i = unwind.opcodes[unwind.opcode_count - 2]; 3474 reg = i >> 4; 3475 i &= 0xf; 3476 3477 op = 0xffff << (reg - 1); 3478 if (reg > 0 3479 && ((mask & op) == (1u << (reg - 1)))) 3480 { 3481 op = (1 << (reg + i + 1)) - 1; 3482 op &= ~((1 << reg) - 1); 3483 mask |= op; 3484 unwind.opcode_count -= 2; 3485 } 3486 } 3487 } 3488 } 3489 3490 hi_reg = 15; 3491 /* We want to generate opcodes in the order the registers have been 3492 saved, ie. descending order. */ 3493 for (reg = 15; reg >= -1; reg--) 3494 { 3495 /* Save registers in blocks. */ 3496 if (reg < 0 3497 || !(mask & (1 << reg))) 3498 { 3499 /* We found an unsaved reg. Generate opcodes to save the 3500 preceeding block. */ 3501 if (reg != hi_reg) 3502 { 3503 if (reg == 9) 3504 { 3505 /* Short form. */ 3506 op = 0xc0 | (hi_reg - 10); 3507 add_unwind_opcode (op, 1); 3508 } 3509 else 3510 { 3511 /* Long form. */ 3512 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); 3513 add_unwind_opcode (op, 2); 3514 } 3515 } 3516 hi_reg = reg - 1; 3517 } 3518 } 3519 3520 return; 3521error: 3522 ignore_rest_of_line (); 3523} 3524 3525static void 3526s_arm_unwind_save_mmxwcg (void) 3527{ 3528 int reg; 3529 int hi_reg; 3530 unsigned mask = 0; 3531 valueT op; 3532 3533 if (*input_line_pointer == '{') 3534 input_line_pointer++; 3535 3536 do 3537 { 3538 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); 3539 3540 if (reg == FAIL) 3541 { 3542 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); 3543 goto error; 3544 } 3545 3546 reg -= 8; 3547 if (mask >> reg) 3548 as_tsktsk (_("register list not in ascending order")); 3549 mask |= 1 << reg; 3550 3551 if (*input_line_pointer == '-') 3552 { 3553 input_line_pointer++; 3554 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); 3555 if (hi_reg == FAIL) 3556 { 3557 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); 3558 goto error; 3559 } 3560 else if (reg >= hi_reg) 3561 { 3562 as_bad (_("bad register range")); 3563 goto error; 3564 } 3565 for (; reg < hi_reg; reg++) 3566 mask |= 1 << reg; 3567 } 3568 } 3569 while (skip_past_comma (&input_line_pointer) != FAIL); 3570 3571 if (*input_line_pointer == '}') 3572 input_line_pointer++; 3573 3574 demand_empty_rest_of_line (); 3575 3576 /* Generate any deferred opcodes because we're going to be looking at 3577 the list. */ 3578 flush_pending_unwind (); 3579 3580 for (reg = 0; reg < 16; reg++) 3581 { 3582 if (mask & (1 << reg)) 3583 unwind.frame_size += 4; 3584 } 3585 op = 0xc700 | mask; 3586 add_unwind_opcode (op, 2); 3587 return; 3588error: 3589 ignore_rest_of_line (); 3590} 3591 3592 3593/* Parse an unwind_save directive. 3594 If the argument is non-zero, this is a .vsave directive. */ 3595 3596static void 3597s_arm_unwind_save (int arch_v6) 3598{ 3599 char *peek; 3600 struct reg_entry *reg; 3601 bfd_boolean had_brace = FALSE; 3602 3603 /* Figure out what sort of save we have. */ 3604 peek = input_line_pointer; 3605 3606 if (*peek == '{') 3607 { 3608 had_brace = TRUE; 3609 peek++; 3610 } 3611 3612 reg = arm_reg_parse_multi (&peek); 3613 3614 if (!reg) 3615 { 3616 as_bad (_("register expected")); 3617 ignore_rest_of_line (); 3618 return; 3619 } 3620 3621 switch (reg->type) 3622 { 3623 case REG_TYPE_FN: 3624 if (had_brace) 3625 { 3626 as_bad (_("FPA .unwind_save does not take a register list")); 3627 ignore_rest_of_line (); 3628 return; 3629 } 3630 s_arm_unwind_save_fpa (reg->number); 3631 return; 3632 3633 case REG_TYPE_RN: s_arm_unwind_save_core (); return; 3634 case REG_TYPE_VFD: 3635 if (arch_v6) 3636 s_arm_unwind_save_vfp_armv6 (); 3637 else 3638 s_arm_unwind_save_vfp (); 3639 return; 3640 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; 3641 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; 3642 3643 default: 3644 as_bad (_(".unwind_save does not support this kind of register")); 3645 ignore_rest_of_line (); 3646 } 3647} 3648 3649 3650/* Parse an unwind_movsp directive. */ 3651 3652static void 3653s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) 3654{ 3655 int reg; 3656 valueT op; 3657 int offset; 3658 3659 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 3660 if (reg == FAIL) 3661 { 3662 as_bad (_(reg_expected_msgs[REG_TYPE_RN])); 3663 ignore_rest_of_line (); 3664 return; 3665 } 3666 3667 /* Optional constant. */ 3668 if (skip_past_comma (&input_line_pointer) != FAIL) 3669 { 3670 if (immediate_for_directive (&offset) == FAIL) 3671 return; 3672 } 3673 else 3674 offset = 0; 3675 3676 demand_empty_rest_of_line (); 3677 3678 if (reg == REG_SP || reg == REG_PC) 3679 { 3680 as_bad (_("SP and PC not permitted in .unwind_movsp directive")); 3681 return; 3682 } 3683 3684 if (unwind.fp_reg != REG_SP) 3685 as_bad (_("unexpected .unwind_movsp directive")); 3686 3687 /* Generate opcode to restore the value. */ 3688 op = 0x90 | reg; 3689 add_unwind_opcode (op, 1); 3690 3691 /* Record the information for later. */ 3692 unwind.fp_reg = reg; 3693 unwind.fp_offset = unwind.frame_size - offset; 3694 unwind.sp_restored = 1; 3695} 3696 3697/* Parse an unwind_pad directive. */ 3698 3699static void 3700s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) 3701{ 3702 int offset; 3703 3704 if (immediate_for_directive (&offset) == FAIL) 3705 return; 3706 3707 if (offset & 3) 3708 { 3709 as_bad (_("stack increment must be multiple of 4")); 3710 ignore_rest_of_line (); 3711 return; 3712 } 3713 3714 /* Don't generate any opcodes, just record the details for later. */ 3715 unwind.frame_size += offset; 3716 unwind.pending_offset += offset; 3717 3718 demand_empty_rest_of_line (); 3719} 3720 3721/* Parse an unwind_setfp directive. */ 3722 3723static void 3724s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) 3725{ 3726 int sp_reg; 3727 int fp_reg; 3728 int offset; 3729 3730 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 3731 if (skip_past_comma (&input_line_pointer) == FAIL) 3732 sp_reg = FAIL; 3733 else 3734 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 3735 3736 if (fp_reg == FAIL || sp_reg == FAIL) 3737 { 3738 as_bad (_("expected <reg>, <reg>")); 3739 ignore_rest_of_line (); 3740 return; 3741 } 3742 3743 /* Optional constant. */ 3744 if (skip_past_comma (&input_line_pointer) != FAIL) 3745 { 3746 if (immediate_for_directive (&offset) == FAIL) 3747 return; 3748 } 3749 else 3750 offset = 0; 3751 3752 demand_empty_rest_of_line (); 3753 3754 if (sp_reg != 13 && sp_reg != unwind.fp_reg) 3755 { 3756 as_bad (_("register must be either sp or set by a previous" 3757 "unwind_movsp directive")); 3758 return; 3759 } 3760 3761 /* Don't generate any opcodes, just record the information for later. */ 3762 unwind.fp_reg = fp_reg; 3763 unwind.fp_used = 1; 3764 if (sp_reg == 13) 3765 unwind.fp_offset = unwind.frame_size - offset; 3766 else 3767 unwind.fp_offset -= offset; 3768} 3769 3770/* Parse an unwind_raw directive. */ 3771 3772static void 3773s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) 3774{ 3775 expressionS exp; 3776 /* This is an arbitrary limit. */ 3777 unsigned char op[16]; 3778 int count; 3779 3780 expression (&exp); 3781 if (exp.X_op == O_constant 3782 && skip_past_comma (&input_line_pointer) != FAIL) 3783 { 3784 unwind.frame_size += exp.X_add_number; 3785 expression (&exp); 3786 } 3787 else 3788 exp.X_op = O_illegal; 3789 3790 if (exp.X_op != O_constant) 3791 { 3792 as_bad (_("expected <offset>, <opcode>")); 3793 ignore_rest_of_line (); 3794 return; 3795 } 3796 3797 count = 0; 3798 3799 /* Parse the opcode. */ 3800 for (;;) 3801 { 3802 if (count >= 16) 3803 { 3804 as_bad (_("unwind opcode too long")); 3805 ignore_rest_of_line (); 3806 } 3807 if (exp.X_op != O_constant || exp.X_add_number & ~0xff) 3808 { 3809 as_bad (_("invalid unwind opcode")); 3810 ignore_rest_of_line (); 3811 return; 3812 } 3813 op[count++] = exp.X_add_number; 3814 3815 /* Parse the next byte. */ 3816 if (skip_past_comma (&input_line_pointer) == FAIL) 3817 break; 3818 3819 expression (&exp); 3820 } 3821 3822 /* Add the opcode bytes in reverse order. */ 3823 while (count--) 3824 add_unwind_opcode (op[count], 1); 3825 3826 demand_empty_rest_of_line (); 3827} 3828 3829 3830/* Parse a .eabi_attribute directive. */ 3831 3832static void 3833s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) 3834{ 3835 s_vendor_attribute (OBJ_ATTR_PROC); 3836} 3837#endif /* OBJ_ELF */ 3838 3839static void s_arm_arch (int); 3840static void s_arm_arch_extension (int); 3841static void s_arm_object_arch (int); 3842static void s_arm_cpu (int); 3843static void s_arm_fpu (int); 3844 3845#ifdef TE_PE 3846 3847static void 3848pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) 3849{ 3850 expressionS exp; 3851 3852 do 3853 { 3854 expression (&exp); 3855 if (exp.X_op == O_symbol) 3856 exp.X_op = O_secrel; 3857 3858 emit_expr (&exp, 4); 3859 } 3860 while (*input_line_pointer++ == ','); 3861 3862 input_line_pointer--; 3863 demand_empty_rest_of_line (); 3864} 3865#endif /* TE_PE */ 3866 3867/* This table describes all the machine specific pseudo-ops the assembler 3868 has to support. The fields are: 3869 pseudo-op name without dot 3870 function to call to execute this pseudo-op 3871 Integer arg to pass to the function. */ 3872 3873const pseudo_typeS md_pseudo_table[] = 3874{ 3875 /* Never called because '.req' does not start a line. */ 3876 { "req", s_req, 0 }, 3877 /* Following two are likewise never called. */ 3878 { "dn", s_dn, 0 }, 3879 { "qn", s_qn, 0 }, 3880 { "unreq", s_unreq, 0 }, 3881 { "bss", s_bss, 0 }, 3882 { "align", s_align, 0 }, 3883 { "arm", s_arm, 0 }, 3884 { "thumb", s_thumb, 0 }, 3885 { "code", s_code, 0 }, 3886 { "force_thumb", s_force_thumb, 0 }, 3887 { "thumb_func", s_thumb_func, 0 }, 3888 { "thumb_set", s_thumb_set, 0 }, 3889 { "even", s_even, 0 }, 3890 { "ltorg", s_ltorg, 0 }, 3891 { "pool", s_ltorg, 0 }, 3892 { "syntax", s_syntax, 0 }, 3893 { "cpu", s_arm_cpu, 0 }, 3894 { "arch", s_arm_arch, 0 }, 3895 { "arch_extension", s_arm_arch_extension, 0 }, 3896 { "object_arch", s_arm_object_arch, 0 }, 3897 { "fpu", s_arm_fpu, 0 }, 3898#ifdef OBJ_ELF 3899 { "word", s_arm_elf_cons, 4 }, 3900 { "long", s_arm_elf_cons, 4 }, 3901 { "rel31", s_arm_rel31, 0 }, 3902 { "fnstart", s_arm_unwind_fnstart, 0 }, 3903 { "fnend", s_arm_unwind_fnend, 0 }, 3904 { "cantunwind", s_arm_unwind_cantunwind, 0 }, 3905 { "personality", s_arm_unwind_personality, 0 }, 3906 { "personalityindex", s_arm_unwind_personalityindex, 0 }, 3907 { "handlerdata", s_arm_unwind_handlerdata, 0 }, 3908 { "save", s_arm_unwind_save, 0 }, 3909 { "vsave", s_arm_unwind_save, 1 }, 3910 { "movsp", s_arm_unwind_movsp, 0 }, 3911 { "pad", s_arm_unwind_pad, 0 }, 3912 { "setfp", s_arm_unwind_setfp, 0 }, 3913 { "unwind_raw", s_arm_unwind_raw, 0 }, 3914 { "eabi_attribute", s_arm_eabi_attribute, 0 }, 3915#else 3916 { "word", cons, 4}, 3917 3918 /* These are used for dwarf. */ 3919 {"2byte", cons, 2}, 3920 {"4byte", cons, 4}, 3921 {"8byte", cons, 8}, 3922 /* These are used for dwarf2. */ 3923 { "file", (void (*) (int)) dwarf2_directive_file, 0 }, 3924 { "loc", dwarf2_directive_loc, 0 }, 3925 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, 3926#endif 3927 { "extend", float_cons, 'x' }, 3928 { "ldouble", float_cons, 'x' }, 3929 { "packed", float_cons, 'p' }, 3930#ifdef TE_PE 3931 {"secrel32", pe_directive_secrel, 0}, 3932#endif 3933 { 0, 0, 0 } 3934}; 3935 3936/* Parser functions used exclusively in instruction operands. */ 3937 3938/* Generic immediate-value read function for use in insn parsing. 3939 STR points to the beginning of the immediate (the leading #); 3940 VAL receives the value; if the value is outside [MIN, MAX] 3941 issue an error. PREFIX_OPT is true if the immediate prefix is 3942 optional. */ 3943 3944static int 3945parse_immediate (char **str, int *val, int min, int max, 3946 bfd_boolean prefix_opt) 3947{ 3948 expressionS exp; 3949 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); 3950 if (exp.X_op != O_constant) 3951 { 3952 inst.error = _("constant expression required"); 3953 return FAIL; 3954 } 3955 3956 if (exp.X_add_number < min || exp.X_add_number > max) 3957 { 3958 inst.error = _("immediate value out of range"); 3959 return FAIL; 3960 } 3961 3962 *val = exp.X_add_number; 3963 return SUCCESS; 3964} 3965 3966/* Less-generic immediate-value read function with the possibility of loading a 3967 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate 3968 instructions. Puts the result directly in inst.operands[i]. */ 3969 3970static int 3971parse_big_immediate (char **str, int i) 3972{ 3973 expressionS exp; 3974 char *ptr = *str; 3975 3976 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG); 3977 3978 if (exp.X_op == O_constant) 3979 { 3980 inst.operands[i].imm = exp.X_add_number & 0xffffffff; 3981 /* If we're on a 64-bit host, then a 64-bit number can be returned using 3982 O_constant. We have to be careful not to break compilation for 3983 32-bit X_add_number, though. */ 3984 if ((exp.X_add_number & ~0xffffffffl) != 0) 3985 { 3986 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */ 3987 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff; 3988 inst.operands[i].regisimm = 1; 3989 } 3990 } 3991 else if (exp.X_op == O_big 3992 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32 3993 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64) 3994 { 3995 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; 3996 /* Bignums have their least significant bits in 3997 generic_bignum[0]. Make sure we put 32 bits in imm and 3998 32 bits in reg, in a (hopefully) portable way. */ 3999 assert (parts != 0); 4000 inst.operands[i].imm = 0; 4001 for (j = 0; j < parts; j++, idx++) 4002 inst.operands[i].imm |= generic_bignum[idx] 4003 << (LITTLENUM_NUMBER_OF_BITS * j); 4004 inst.operands[i].reg = 0; 4005 for (j = 0; j < parts; j++, idx++) 4006 inst.operands[i].reg |= generic_bignum[idx] 4007 << (LITTLENUM_NUMBER_OF_BITS * j); 4008 inst.operands[i].regisimm = 1; 4009 } 4010 else 4011 return FAIL; 4012 4013 *str = ptr; 4014 4015 return SUCCESS; 4016} 4017 4018/* Returns the pseudo-register number of an FPA immediate constant, 4019 or FAIL if there isn't a valid constant here. */ 4020 4021static int 4022parse_fpa_immediate (char ** str) 4023{ 4024 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 4025 char * save_in; 4026 expressionS exp; 4027 int i; 4028 int j; 4029 4030 /* First try and match exact strings, this is to guarantee 4031 that some formats will work even for cross assembly. */ 4032 4033 for (i = 0; fp_const[i]; i++) 4034 { 4035 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) 4036 { 4037 char *start = *str; 4038 4039 *str += strlen (fp_const[i]); 4040 if (is_end_of_line[(unsigned char) **str]) 4041 return i + 8; 4042 *str = start; 4043 } 4044 } 4045 4046 /* Just because we didn't get a match doesn't mean that the constant 4047 isn't valid, just that it is in a format that we don't 4048 automatically recognize. Try parsing it with the standard 4049 expression routines. */ 4050 4051 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); 4052 4053 /* Look for a raw floating point number. */ 4054 if ((save_in = atof_ieee (*str, 'x', words)) != NULL 4055 && is_end_of_line[(unsigned char) *save_in]) 4056 { 4057 for (i = 0; i < NUM_FLOAT_VALS; i++) 4058 { 4059 for (j = 0; j < MAX_LITTLENUMS; j++) 4060 { 4061 if (words[j] != fp_values[i][j]) 4062 break; 4063 } 4064 4065 if (j == MAX_LITTLENUMS) 4066 { 4067 *str = save_in; 4068 return i + 8; 4069 } 4070 } 4071 } 4072 4073 /* Try and parse a more complex expression, this will probably fail 4074 unless the code uses a floating point prefix (eg "0f"). */ 4075 save_in = input_line_pointer; 4076 input_line_pointer = *str; 4077 if (expression (&exp) == absolute_section 4078 && exp.X_op == O_big 4079 && exp.X_add_number < 0) 4080 { 4081 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. 4082 Ditto for 15. */ 4083 if (gen_to_words (words, 5, (long) 15) == 0) 4084 { 4085 for (i = 0; i < NUM_FLOAT_VALS; i++) 4086 { 4087 for (j = 0; j < MAX_LITTLENUMS; j++) 4088 { 4089 if (words[j] != fp_values[i][j]) 4090 break; 4091 } 4092 4093 if (j == MAX_LITTLENUMS) 4094 { 4095 *str = input_line_pointer; 4096 input_line_pointer = save_in; 4097 return i + 8; 4098 } 4099 } 4100 } 4101 } 4102 4103 *str = input_line_pointer; 4104 input_line_pointer = save_in; 4105 inst.error = _("invalid FPA immediate expression"); 4106 return FAIL; 4107} 4108 4109/* Returns 1 if a number has "quarter-precision" float format 4110 0baBbbbbbc defgh000 00000000 00000000. */ 4111 4112static int 4113is_quarter_float (unsigned imm) 4114{ 4115 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; 4116 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; 4117} 4118 4119/* Parse an 8-bit "quarter-precision" floating point number of the form: 4120 0baBbbbbbc defgh000 00000000 00000000. 4121 The zero and minus-zero cases need special handling, since they can't be 4122 encoded in the "quarter-precision" float format, but can nonetheless be 4123 loaded as integer constants. */ 4124 4125static unsigned 4126parse_qfloat_immediate (char **ccp, int *immed) 4127{ 4128 char *str = *ccp; 4129 char *fpnum; 4130 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 4131 int found_fpchar = 0; 4132 4133 skip_past_char (&str, '#'); 4134 4135 /* We must not accidentally parse an integer as a floating-point number. Make 4136 sure that the value we parse is not an integer by checking for special 4137 characters '.' or 'e'. 4138 FIXME: This is a horrible hack, but doing better is tricky because type 4139 information isn't in a very usable state at parse time. */ 4140 fpnum = str; 4141 skip_whitespace (fpnum); 4142 4143 if (strncmp (fpnum, "0x", 2) == 0) 4144 return FAIL; 4145 else 4146 { 4147 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) 4148 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') 4149 { 4150 found_fpchar = 1; 4151 break; 4152 } 4153 4154 if (!found_fpchar) 4155 return FAIL; 4156 } 4157 4158 if ((str = atof_ieee (str, 's', words)) != NULL) 4159 { 4160 unsigned fpword = 0; 4161 int i; 4162 4163 /* Our FP word must be 32 bits (single-precision FP). */ 4164 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) 4165 { 4166 fpword <<= LITTLENUM_NUMBER_OF_BITS; 4167 fpword |= words[i]; 4168 } 4169 4170 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) 4171 *immed = fpword; 4172 else 4173 return FAIL; 4174 4175 *ccp = str; 4176 4177 return SUCCESS; 4178 } 4179 4180 return FAIL; 4181} 4182 4183/* Shift operands. */ 4184enum shift_kind 4185{ 4186 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX 4187}; 4188 4189struct asm_shift_name 4190{ 4191 const char *name; 4192 enum shift_kind kind; 4193}; 4194 4195/* Third argument to parse_shift. */ 4196enum parse_shift_mode 4197{ 4198 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ 4199 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ 4200 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ 4201 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ 4202 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ 4203}; 4204 4205/* Parse a <shift> specifier on an ARM data processing instruction. 4206 This has three forms: 4207 4208 (LSL|LSR|ASL|ASR|ROR) Rs 4209 (LSL|LSR|ASL|ASR|ROR) #imm 4210 RRX 4211 4212 Note that ASL is assimilated to LSL in the instruction encoding, and 4213 RRX to ROR #0 (which cannot be written as such). */ 4214 4215static int 4216parse_shift (char **str, int i, enum parse_shift_mode mode) 4217{ 4218 const struct asm_shift_name *shift_name; 4219 enum shift_kind shift; 4220 char *s = *str; 4221 char *p = s; 4222 int reg; 4223 4224 for (p = *str; ISALPHA (*p); p++) 4225 ; 4226 4227 if (p == *str) 4228 { 4229 inst.error = _("shift expression expected"); 4230 return FAIL; 4231 } 4232 4233 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str); 4234 4235 if (shift_name == NULL) 4236 { 4237 inst.error = _("shift expression expected"); 4238 return FAIL; 4239 } 4240 4241 shift = shift_name->kind; 4242 4243 switch (mode) 4244 { 4245 case NO_SHIFT_RESTRICT: 4246 case SHIFT_IMMEDIATE: break; 4247 4248 case SHIFT_LSL_OR_ASR_IMMEDIATE: 4249 if (shift != SHIFT_LSL && shift != SHIFT_ASR) 4250 { 4251 inst.error = _("'LSL' or 'ASR' required"); 4252 return FAIL; 4253 } 4254 break; 4255 4256 case SHIFT_LSL_IMMEDIATE: 4257 if (shift != SHIFT_LSL) 4258 { 4259 inst.error = _("'LSL' required"); 4260 return FAIL; 4261 } 4262 break; 4263 4264 case SHIFT_ASR_IMMEDIATE: 4265 if (shift != SHIFT_ASR) 4266 { 4267 inst.error = _("'ASR' required"); 4268 return FAIL; 4269 } 4270 break; 4271 4272 default: abort (); 4273 } 4274 4275 if (shift != SHIFT_RRX) 4276 { 4277 /* Whitespace can appear here if the next thing is a bare digit. */ 4278 skip_whitespace (p); 4279 4280 if (mode == NO_SHIFT_RESTRICT 4281 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 4282 { 4283 inst.operands[i].imm = reg; 4284 inst.operands[i].immisreg = 1; 4285 } 4286 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 4287 return FAIL; 4288 } 4289 inst.operands[i].shift_kind = shift; 4290 inst.operands[i].shifted = 1; 4291 *str = p; 4292 return SUCCESS; 4293} 4294 4295/* Parse a <shifter_operand> for an ARM data processing instruction: 4296 4297 #<immediate> 4298 #<immediate>, <rotate> 4299 <Rm> 4300 <Rm>, <shift> 4301 4302 where <shift> is defined by parse_shift above, and <rotate> is a 4303 multiple of 2 between 0 and 30. Validation of immediate operands 4304 is deferred to md_apply_fix. */ 4305 4306static int 4307parse_shifter_operand (char **str, int i) 4308{ 4309 int value; 4310 expressionS expr; 4311 4312 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) 4313 { 4314 inst.operands[i].reg = value; 4315 inst.operands[i].isreg = 1; 4316 4317 /* parse_shift will override this if appropriate */ 4318 inst.reloc.exp.X_op = O_constant; 4319 inst.reloc.exp.X_add_number = 0; 4320 4321 if (skip_past_comma (str) == FAIL) 4322 return SUCCESS; 4323 4324 /* Shift operation on register. */ 4325 return parse_shift (str, i, NO_SHIFT_RESTRICT); 4326 } 4327 4328 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) 4329 return FAIL; 4330 4331 if (skip_past_comma (str) == SUCCESS) 4332 { 4333 /* #x, y -- ie explicit rotation by Y. */ 4334 if (my_get_expression (&expr, str, GE_NO_PREFIX)) 4335 return FAIL; 4336 4337 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant) 4338 { 4339 inst.error = _("constant expression expected"); 4340 return FAIL; 4341 } 4342 4343 value = expr.X_add_number; 4344 if (value < 0 || value > 30 || value % 2 != 0) 4345 { 4346 inst.error = _("invalid rotation"); 4347 return FAIL; 4348 } 4349 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) 4350 { 4351 inst.error = _("invalid constant"); 4352 return FAIL; 4353 } 4354 4355 /* Convert to decoded value. md_apply_fix will put it back. */ 4356 inst.reloc.exp.X_add_number 4357 = (((inst.reloc.exp.X_add_number << (32 - value)) 4358 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff); 4359 } 4360 4361 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 4362 inst.reloc.pc_rel = 0; 4363 return SUCCESS; 4364} 4365 4366/* Group relocation information. Each entry in the table contains the 4367 textual name of the relocation as may appear in assembler source 4368 and must end with a colon. 4369 Along with this textual name are the relocation codes to be used if 4370 the corresponding instruction is an ALU instruction (ADD or SUB only), 4371 an LDR, an LDRS, or an LDC. */ 4372 4373struct group_reloc_table_entry 4374{ 4375 const char *name; 4376 int alu_code; 4377 int ldr_code; 4378 int ldrs_code; 4379 int ldc_code; 4380}; 4381 4382typedef enum 4383{ 4384 /* Varieties of non-ALU group relocation. */ 4385 4386 GROUP_LDR, 4387 GROUP_LDRS, 4388 GROUP_LDC 4389} group_reloc_type; 4390 4391static struct group_reloc_table_entry group_reloc_table[] = 4392 { /* Program counter relative: */ 4393 { "pc_g0_nc", 4394 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ 4395 0, /* LDR */ 4396 0, /* LDRS */ 4397 0 }, /* LDC */ 4398 { "pc_g0", 4399 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ 4400 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ 4401 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ 4402 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ 4403 { "pc_g1_nc", 4404 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ 4405 0, /* LDR */ 4406 0, /* LDRS */ 4407 0 }, /* LDC */ 4408 { "pc_g1", 4409 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ 4410 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ 4411 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ 4412 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ 4413 { "pc_g2", 4414 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ 4415 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ 4416 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ 4417 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ 4418 /* Section base relative */ 4419 { "sb_g0_nc", 4420 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ 4421 0, /* LDR */ 4422 0, /* LDRS */ 4423 0 }, /* LDC */ 4424 { "sb_g0", 4425 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ 4426 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ 4427 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ 4428 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ 4429 { "sb_g1_nc", 4430 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ 4431 0, /* LDR */ 4432 0, /* LDRS */ 4433 0 }, /* LDC */ 4434 { "sb_g1", 4435 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ 4436 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ 4437 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ 4438 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ 4439 { "sb_g2", 4440 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ 4441 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ 4442 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ 4443 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ 4444 4445/* Given the address of a pointer pointing to the textual name of a group 4446 relocation as may appear in assembler source, attempt to find its details 4447 in group_reloc_table. The pointer will be updated to the character after 4448 the trailing colon. On failure, FAIL will be returned; SUCCESS 4449 otherwise. On success, *entry will be updated to point at the relevant 4450 group_reloc_table entry. */ 4451 4452static int 4453find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) 4454{ 4455 unsigned int i; 4456 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) 4457 { 4458 int length = strlen (group_reloc_table[i].name); 4459 4460 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 && 4461 (*str)[length] == ':') 4462 { 4463 *out = &group_reloc_table[i]; 4464 *str += (length + 1); 4465 return SUCCESS; 4466 } 4467 } 4468 4469 return FAIL; 4470} 4471 4472/* Parse a <shifter_operand> for an ARM data processing instruction 4473 (as for parse_shifter_operand) where group relocations are allowed: 4474 4475 #<immediate> 4476 #<immediate>, <rotate> 4477 #:<group_reloc>:<expression> 4478 <Rm> 4479 <Rm>, <shift> 4480 4481 where <group_reloc> is one of the strings defined in group_reloc_table. 4482 The hashes are optional. 4483 4484 Everything else is as for parse_shifter_operand. */ 4485 4486static parse_operand_result 4487parse_shifter_operand_group_reloc (char **str, int i) 4488{ 4489 /* Determine if we have the sequence of characters #: or just : 4490 coming next. If we do, then we check for a group relocation. 4491 If we don't, punt the whole lot to parse_shifter_operand. */ 4492 4493 if (((*str)[0] == '#' && (*str)[1] == ':') 4494 || (*str)[0] == ':') 4495 { 4496 struct group_reloc_table_entry *entry; 4497 4498 if ((*str)[0] == '#') 4499 (*str) += 2; 4500 else 4501 (*str)++; 4502 4503 /* Try to parse a group relocation. Anything else is an error. */ 4504 if (find_group_reloc_table_entry (str, &entry) == FAIL) 4505 { 4506 inst.error = _("unknown group relocation"); 4507 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4508 } 4509 4510 /* We now have the group relocation table entry corresponding to 4511 the name in the assembler source. Next, we parse the expression. */ 4512 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) 4513 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4514 4515 /* Record the relocation type (always the ALU variant here). */ 4516 inst.reloc.type = entry->alu_code; 4517 assert (inst.reloc.type != 0); 4518 4519 return PARSE_OPERAND_SUCCESS; 4520 } 4521 else 4522 return parse_shifter_operand (str, i) == SUCCESS 4523 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; 4524 4525 /* Never reached. */ 4526} 4527 4528/* Parse all forms of an ARM address expression. Information is written 4529 to inst.operands[i] and/or inst.reloc. 4530 4531 Preindexed addressing (.preind=1): 4532 4533 [Rn, #offset] .reg=Rn .reloc.exp=offset 4534 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4535 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4536 .shift_kind=shift .reloc.exp=shift_imm 4537 4538 These three may have a trailing ! which causes .writeback to be set also. 4539 4540 Postindexed addressing (.postind=1, .writeback=1): 4541 4542 [Rn], #offset .reg=Rn .reloc.exp=offset 4543 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4544 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4545 .shift_kind=shift .reloc.exp=shift_imm 4546 4547 Unindexed addressing (.preind=0, .postind=0): 4548 4549 [Rn], {option} .reg=Rn .imm=option .immisreg=0 4550 4551 Other: 4552 4553 [Rn]{!} shorthand for [Rn,#0]{!} 4554 =immediate .isreg=0 .reloc.exp=immediate 4555 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label 4556 4557 It is the caller's responsibility to check for addressing modes not 4558 supported by the instruction, and to set inst.reloc.type. */ 4559 4560static parse_operand_result 4561parse_address_main (char **str, int i, int group_relocations, 4562 group_reloc_type group_type) 4563{ 4564 char *p = *str; 4565 int reg; 4566 4567 if (skip_past_char (&p, '[') == FAIL) 4568 { 4569 if (skip_past_char (&p, '=') == FAIL) 4570 { 4571 /* bare address - translate to PC-relative offset */ 4572 inst.reloc.pc_rel = 1; 4573 inst.operands[i].reg = REG_PC; 4574 inst.operands[i].isreg = 1; 4575 inst.operands[i].preind = 1; 4576 } 4577 /* else a load-constant pseudo op, no special treatment needed here */ 4578 4579 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 4580 return PARSE_OPERAND_FAIL; 4581 4582 *str = p; 4583 return PARSE_OPERAND_SUCCESS; 4584 } 4585 4586 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 4587 { 4588 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 4589 return PARSE_OPERAND_FAIL; 4590 } 4591 inst.operands[i].reg = reg; 4592 inst.operands[i].isreg = 1; 4593 4594 if (skip_past_comma (&p) == SUCCESS) 4595 { 4596 inst.operands[i].preind = 1; 4597 4598 if (*p == '+') p++; 4599 else if (*p == '-') p++, inst.operands[i].negative = 1; 4600 4601 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 4602 { 4603 inst.operands[i].imm = reg; 4604 inst.operands[i].immisreg = 1; 4605 4606 if (skip_past_comma (&p) == SUCCESS) 4607 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) 4608 return PARSE_OPERAND_FAIL; 4609 } 4610 else if (skip_past_char (&p, ':') == SUCCESS) 4611 { 4612 /* FIXME: '@' should be used here, but it's filtered out by generic 4613 code before we get to see it here. This may be subject to 4614 change. */ 4615 expressionS exp; 4616 my_get_expression (&exp, &p, GE_NO_PREFIX); 4617 if (exp.X_op != O_constant) 4618 { 4619 inst.error = _("alignment must be constant"); 4620 return PARSE_OPERAND_FAIL; 4621 } 4622 inst.operands[i].imm = exp.X_add_number << 8; 4623 inst.operands[i].immisalign = 1; 4624 /* Alignments are not pre-indexes. */ 4625 inst.operands[i].preind = 0; 4626 } 4627 else 4628 { 4629 if (inst.operands[i].negative) 4630 { 4631 inst.operands[i].negative = 0; 4632 p--; 4633 } 4634 4635 if (group_relocations && 4636 ((*p == '#' && *(p + 1) == ':') || *p == ':')) 4637 4638 { 4639 struct group_reloc_table_entry *entry; 4640 4641 /* Skip over the #: or : sequence. */ 4642 if (*p == '#') 4643 p += 2; 4644 else 4645 p++; 4646 4647 /* Try to parse a group relocation. Anything else is an 4648 error. */ 4649 if (find_group_reloc_table_entry (&p, &entry) == FAIL) 4650 { 4651 inst.error = _("unknown group relocation"); 4652 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4653 } 4654 4655 /* We now have the group relocation table entry corresponding to 4656 the name in the assembler source. Next, we parse the 4657 expression. */ 4658 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 4659 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4660 4661 /* Record the relocation type. */ 4662 switch (group_type) 4663 { 4664 case GROUP_LDR: 4665 inst.reloc.type = entry->ldr_code; 4666 break; 4667 4668 case GROUP_LDRS: 4669 inst.reloc.type = entry->ldrs_code; 4670 break; 4671 4672 case GROUP_LDC: 4673 inst.reloc.type = entry->ldc_code; 4674 break; 4675 4676 default: 4677 assert (0); 4678 } 4679 4680 if (inst.reloc.type == 0) 4681 { 4682 inst.error = _("this group relocation is not allowed on this instruction"); 4683 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4684 } 4685 } 4686 else 4687 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 4688 return PARSE_OPERAND_FAIL; 4689 } 4690 } 4691 4692 if (skip_past_char (&p, ']') == FAIL) 4693 { 4694 inst.error = _("']' expected"); 4695 return PARSE_OPERAND_FAIL; 4696 } 4697 4698 if (skip_past_char (&p, '!') == SUCCESS) 4699 inst.operands[i].writeback = 1; 4700 4701 else if (skip_past_comma (&p) == SUCCESS) 4702 { 4703 if (skip_past_char (&p, '{') == SUCCESS) 4704 { 4705 /* [Rn], {expr} - unindexed, with option */ 4706 if (parse_immediate (&p, &inst.operands[i].imm, 4707 0, 255, TRUE) == FAIL) 4708 return PARSE_OPERAND_FAIL; 4709 4710 if (skip_past_char (&p, '}') == FAIL) 4711 { 4712 inst.error = _("'}' expected at end of 'option' field"); 4713 return PARSE_OPERAND_FAIL; 4714 } 4715 if (inst.operands[i].preind) 4716 { 4717 inst.error = _("cannot combine index with option"); 4718 return PARSE_OPERAND_FAIL; 4719 } 4720 *str = p; 4721 return PARSE_OPERAND_SUCCESS; 4722 } 4723 else 4724 { 4725 inst.operands[i].postind = 1; 4726 inst.operands[i].writeback = 1; 4727 4728 if (inst.operands[i].preind) 4729 { 4730 inst.error = _("cannot combine pre- and post-indexing"); 4731 return PARSE_OPERAND_FAIL; 4732 } 4733 4734 if (*p == '+') p++; 4735 else if (*p == '-') p++, inst.operands[i].negative = 1; 4736 4737 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 4738 { 4739 /* We might be using the immediate for alignment already. If we 4740 are, OR the register number into the low-order bits. */ 4741 if (inst.operands[i].immisalign) 4742 inst.operands[i].imm |= reg; 4743 else 4744 inst.operands[i].imm = reg; 4745 inst.operands[i].immisreg = 1; 4746 4747 if (skip_past_comma (&p) == SUCCESS) 4748 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) 4749 return PARSE_OPERAND_FAIL; 4750 } 4751 else 4752 { 4753 if (inst.operands[i].negative) 4754 { 4755 inst.operands[i].negative = 0; 4756 p--; 4757 } 4758 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 4759 return PARSE_OPERAND_FAIL; 4760 } 4761 } 4762 } 4763 4764 /* If at this point neither .preind nor .postind is set, we have a 4765 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ 4766 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) 4767 { 4768 inst.operands[i].preind = 1; 4769 inst.reloc.exp.X_op = O_constant; 4770 inst.reloc.exp.X_add_number = 0; 4771 } 4772 *str = p; 4773 return PARSE_OPERAND_SUCCESS; 4774} 4775 4776static int 4777parse_address (char **str, int i) 4778{ 4779 return parse_address_main (str, i, 0, 0) == PARSE_OPERAND_SUCCESS 4780 ? SUCCESS : FAIL; 4781} 4782 4783static parse_operand_result 4784parse_address_group_reloc (char **str, int i, group_reloc_type type) 4785{ 4786 return parse_address_main (str, i, 1, type); 4787} 4788 4789/* Parse an operand for a MOVW or MOVT instruction. */ 4790static int 4791parse_half (char **str) 4792{ 4793 char * p; 4794 4795 p = *str; 4796 skip_past_char (&p, '#'); 4797 if (strncasecmp (p, ":lower16:", 9) == 0) 4798 inst.reloc.type = BFD_RELOC_ARM_MOVW; 4799 else if (strncasecmp (p, ":upper16:", 9) == 0) 4800 inst.reloc.type = BFD_RELOC_ARM_MOVT; 4801 4802 if (inst.reloc.type != BFD_RELOC_UNUSED) 4803 { 4804 p += 9; 4805 skip_whitespace(p); 4806 } 4807 4808 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 4809 return FAIL; 4810 4811 if (inst.reloc.type == BFD_RELOC_UNUSED) 4812 { 4813 if (inst.reloc.exp.X_op != O_constant) 4814 { 4815 inst.error = _("constant expression expected"); 4816 return FAIL; 4817 } 4818 if (inst.reloc.exp.X_add_number < 0 4819 || inst.reloc.exp.X_add_number > 0xffff) 4820 { 4821 inst.error = _("immediate value out of range"); 4822 return FAIL; 4823 } 4824 } 4825 *str = p; 4826 return SUCCESS; 4827} 4828 4829/* Miscellaneous. */ 4830 4831/* Parse a PSR flag operand. The value returned is FAIL on syntax error, 4832 or a bitmask suitable to be or-ed into the ARM msr instruction. */ 4833static int 4834parse_psr (char **str) 4835{ 4836 char *p; 4837 unsigned long psr_field; 4838 const struct asm_psr *psr; 4839 char *start; 4840 4841 /* CPSR's and SPSR's can now be lowercase. This is just a convenience 4842 feature for ease of use and backwards compatibility. */ 4843 p = *str; 4844 if (strncasecmp (p, "SPSR", 4) == 0) 4845 psr_field = SPSR_BIT; 4846 else if (strncasecmp (p, "CPSR", 4) == 0) 4847 psr_field = 0; 4848 else 4849 { 4850 start = p; 4851 do 4852 p++; 4853 while (ISALNUM (*p) || *p == '_'); 4854 4855 psr = hash_find_n (arm_v7m_psr_hsh, start, p - start); 4856 if (!psr) 4857 return FAIL; 4858 4859 *str = p; 4860 return psr->field; 4861 } 4862 4863 p += 4; 4864 if (*p == '_') 4865 { 4866 /* A suffix follows. */ 4867 p++; 4868 start = p; 4869 4870 do 4871 p++; 4872 while (ISALNUM (*p) || *p == '_'); 4873 4874 psr = hash_find_n (arm_psr_hsh, start, p - start); 4875 if (!psr) 4876 goto error; 4877 4878 psr_field |= psr->field; 4879 } 4880 else 4881 { 4882 if (ISALNUM (*p)) 4883 goto error; /* Garbage after "[CS]PSR". */ 4884 4885 psr_field |= (PSR_c | PSR_f); 4886 } 4887 *str = p; 4888 return psr_field; 4889 4890 error: 4891 inst.error = _("flag for {c}psr instruction expected"); 4892 return FAIL; 4893} 4894 4895/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a 4896 value suitable for splatting into the AIF field of the instruction. */ 4897 4898static int 4899parse_cps_flags (char **str) 4900{ 4901 int val = 0; 4902 int saw_a_flag = 0; 4903 char *s = *str; 4904 4905 for (;;) 4906 switch (*s++) 4907 { 4908 case '\0': case ',': 4909 goto done; 4910 4911 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; 4912 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; 4913 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; 4914 4915 default: 4916 inst.error = _("unrecognized CPS flag"); 4917 return FAIL; 4918 } 4919 4920 done: 4921 if (saw_a_flag == 0) 4922 { 4923 inst.error = _("missing CPS flags"); 4924 return FAIL; 4925 } 4926 4927 *str = s - 1; 4928 return val; 4929} 4930 4931/* Parse an endian specifier ("BE" or "LE", case insensitive); 4932 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ 4933 4934static int 4935parse_endian_specifier (char **str) 4936{ 4937 int little_endian; 4938 char *s = *str; 4939 4940 if (strncasecmp (s, "BE", 2)) 4941 little_endian = 0; 4942 else if (strncasecmp (s, "LE", 2)) 4943 little_endian = 1; 4944 else 4945 { 4946 inst.error = _("valid endian specifiers are be or le"); 4947 return FAIL; 4948 } 4949 4950 if (ISALNUM (s[2]) || s[2] == '_') 4951 { 4952 inst.error = _("valid endian specifiers are be or le"); 4953 return FAIL; 4954 } 4955 4956 *str = s + 2; 4957 return little_endian; 4958} 4959 4960/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a 4961 value suitable for poking into the rotate field of an sxt or sxta 4962 instruction, or FAIL on error. */ 4963 4964static int 4965parse_ror (char **str) 4966{ 4967 int rot; 4968 char *s = *str; 4969 4970 if (strncasecmp (s, "ROR", 3) == 0) 4971 s += 3; 4972 else 4973 { 4974 inst.error = _("missing rotation field after comma"); 4975 return FAIL; 4976 } 4977 4978 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) 4979 return FAIL; 4980 4981 switch (rot) 4982 { 4983 case 0: *str = s; return 0x0; 4984 case 8: *str = s; return 0x1; 4985 case 16: *str = s; return 0x2; 4986 case 24: *str = s; return 0x3; 4987 4988 default: 4989 inst.error = _("rotation can only be 0, 8, 16, or 24"); 4990 return FAIL; 4991 } 4992} 4993 4994/* Parse a conditional code (from conds[] below). The value returned is in the 4995 range 0 .. 14, or FAIL. */ 4996static int 4997parse_cond (char **str) 4998{ 4999 char *p, *q; 5000 const struct asm_cond *c; 5001 5002 p = q = *str; 5003 while (ISALPHA (*q)) 5004 q++; 5005 5006 c = hash_find_n (arm_cond_hsh, p, q - p); 5007 if (!c) 5008 { 5009 inst.error = _("condition required"); 5010 return FAIL; 5011 } 5012 5013 *str = q; 5014 return c->value; 5015} 5016 5017/* Parse an option for a barrier instruction. Returns the encoding for the 5018 option, or FAIL. */ 5019static int 5020parse_barrier (char **str) 5021{ 5022 char *p, *q; 5023 const struct asm_barrier_opt *o; 5024 5025 p = q = *str; 5026 while (ISALPHA (*q)) 5027 q++; 5028 5029 o = hash_find_n (arm_barrier_opt_hsh, p, q - p); 5030 if (!o) 5031 return FAIL; 5032 5033 *str = q; 5034 return o->value; 5035} 5036 5037/* Parse the operands of a table branch instruction. Similar to a memory 5038 operand. */ 5039static int 5040parse_tb (char **str) 5041{ 5042 char * p = *str; 5043 int reg; 5044 5045 if (skip_past_char (&p, '[') == FAIL) 5046 { 5047 inst.error = _("'[' expected"); 5048 return FAIL; 5049 } 5050 5051 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 5052 { 5053 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 5054 return FAIL; 5055 } 5056 inst.operands[0].reg = reg; 5057 5058 if (skip_past_comma (&p) == FAIL) 5059 { 5060 inst.error = _("',' expected"); 5061 return FAIL; 5062 } 5063 5064 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 5065 { 5066 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 5067 return FAIL; 5068 } 5069 inst.operands[0].imm = reg; 5070 5071 if (skip_past_comma (&p) == SUCCESS) 5072 { 5073 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) 5074 return FAIL; 5075 if (inst.reloc.exp.X_add_number != 1) 5076 { 5077 inst.error = _("invalid shift"); 5078 return FAIL; 5079 } 5080 inst.operands[0].shifted = 1; 5081 } 5082 5083 if (skip_past_char (&p, ']') == FAIL) 5084 { 5085 inst.error = _("']' expected"); 5086 return FAIL; 5087 } 5088 *str = p; 5089 return SUCCESS; 5090} 5091 5092/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more 5093 information on the types the operands can take and how they are encoded. 5094 Up to four operands may be read; this function handles setting the 5095 ".present" field for each read operand itself. 5096 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, 5097 else returns FAIL. */ 5098 5099static int 5100parse_neon_mov (char **str, int *which_operand) 5101{ 5102 int i = *which_operand, val; 5103 enum arm_reg_type rtype; 5104 char *ptr = *str; 5105 struct neon_type_el optype; 5106 5107 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) 5108 { 5109 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ 5110 inst.operands[i].reg = val; 5111 inst.operands[i].isscalar = 1; 5112 inst.operands[i].vectype = optype; 5113 inst.operands[i++].present = 1; 5114 5115 if (skip_past_comma (&ptr) == FAIL) 5116 goto wanted_comma; 5117 5118 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5119 goto wanted_arm; 5120 5121 inst.operands[i].reg = val; 5122 inst.operands[i].isreg = 1; 5123 inst.operands[i].present = 1; 5124 } 5125 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) 5126 != FAIL) 5127 { 5128 /* Cases 0, 1, 2, 3, 5 (D only). */ 5129 if (skip_past_comma (&ptr) == FAIL) 5130 goto wanted_comma; 5131 5132 inst.operands[i].reg = val; 5133 inst.operands[i].isreg = 1; 5134 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); 5135 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5136 inst.operands[i].isvec = 1; 5137 inst.operands[i].vectype = optype; 5138 inst.operands[i++].present = 1; 5139 5140 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5141 { 5142 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. 5143 Case 13: VMOV <Sd>, <Rm> */ 5144 inst.operands[i].reg = val; 5145 inst.operands[i].isreg = 1; 5146 inst.operands[i].present = 1; 5147 5148 if (rtype == REG_TYPE_NQ) 5149 { 5150 first_error (_("can't use Neon quad register here")); 5151 return FAIL; 5152 } 5153 else if (rtype != REG_TYPE_VFS) 5154 { 5155 i++; 5156 if (skip_past_comma (&ptr) == FAIL) 5157 goto wanted_comma; 5158 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5159 goto wanted_arm; 5160 inst.operands[i].reg = val; 5161 inst.operands[i].isreg = 1; 5162 inst.operands[i].present = 1; 5163 } 5164 } 5165 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) 5166 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> 5167 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> 5168 Case 10: VMOV.F32 <Sd>, #<imm> 5169 Case 11: VMOV.F64 <Dd>, #<imm> */ 5170 inst.operands[i].immisfloat = 1; 5171 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, 5172 &optype)) != FAIL) 5173 { 5174 /* Case 0: VMOV<c><q> <Qd>, <Qm> 5175 Case 1: VMOV<c><q> <Dd>, <Dm> 5176 Case 8: VMOV.F32 <Sd>, <Sm> 5177 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ 5178 5179 inst.operands[i].reg = val; 5180 inst.operands[i].isreg = 1; 5181 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); 5182 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5183 inst.operands[i].isvec = 1; 5184 inst.operands[i].vectype = optype; 5185 inst.operands[i].present = 1; 5186 5187 if (skip_past_comma (&ptr) == SUCCESS) 5188 { 5189 /* Case 15. */ 5190 i++; 5191 5192 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5193 goto wanted_arm; 5194 5195 inst.operands[i].reg = val; 5196 inst.operands[i].isreg = 1; 5197 inst.operands[i++].present = 1; 5198 5199 if (skip_past_comma (&ptr) == FAIL) 5200 goto wanted_comma; 5201 5202 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5203 goto wanted_arm; 5204 5205 inst.operands[i].reg = val; 5206 inst.operands[i].isreg = 1; 5207 inst.operands[i++].present = 1; 5208 } 5209 } 5210 else if (parse_big_immediate (&ptr, i) == SUCCESS) 5211 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> 5212 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ 5213 ; 5214 else 5215 { 5216 first_error (_("expected <Rm> or <Dm> or <Qm> operand")); 5217 return FAIL; 5218 } 5219 } 5220 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5221 { 5222 /* Cases 6, 7. */ 5223 inst.operands[i].reg = val; 5224 inst.operands[i].isreg = 1; 5225 inst.operands[i++].present = 1; 5226 5227 if (skip_past_comma (&ptr) == FAIL) 5228 goto wanted_comma; 5229 5230 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) 5231 { 5232 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ 5233 inst.operands[i].reg = val; 5234 inst.operands[i].isscalar = 1; 5235 inst.operands[i].present = 1; 5236 inst.operands[i].vectype = optype; 5237 } 5238 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5239 { 5240 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ 5241 inst.operands[i].reg = val; 5242 inst.operands[i].isreg = 1; 5243 inst.operands[i++].present = 1; 5244 5245 if (skip_past_comma (&ptr) == FAIL) 5246 goto wanted_comma; 5247 5248 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) 5249 == FAIL) 5250 { 5251 first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); 5252 return FAIL; 5253 } 5254 5255 inst.operands[i].reg = val; 5256 inst.operands[i].isreg = 1; 5257 inst.operands[i].isvec = 1; 5258 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5259 inst.operands[i].vectype = optype; 5260 inst.operands[i].present = 1; 5261 5262 if (rtype == REG_TYPE_VFS) 5263 { 5264 /* Case 14. */ 5265 i++; 5266 if (skip_past_comma (&ptr) == FAIL) 5267 goto wanted_comma; 5268 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, 5269 &optype)) == FAIL) 5270 { 5271 first_error (_(reg_expected_msgs[REG_TYPE_VFS])); 5272 return FAIL; 5273 } 5274 inst.operands[i].reg = val; 5275 inst.operands[i].isreg = 1; 5276 inst.operands[i].isvec = 1; 5277 inst.operands[i].issingle = 1; 5278 inst.operands[i].vectype = optype; 5279 inst.operands[i].present = 1; 5280 } 5281 } 5282 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) 5283 != FAIL) 5284 { 5285 /* Case 13. */ 5286 inst.operands[i].reg = val; 5287 inst.operands[i].isreg = 1; 5288 inst.operands[i].isvec = 1; 5289 inst.operands[i].issingle = 1; 5290 inst.operands[i].vectype = optype; 5291 inst.operands[i++].present = 1; 5292 } 5293 } 5294 else 5295 { 5296 first_error (_("parse error")); 5297 return FAIL; 5298 } 5299 5300 /* Successfully parsed the operands. Update args. */ 5301 *which_operand = i; 5302 *str = ptr; 5303 return SUCCESS; 5304 5305 wanted_comma: 5306 first_error (_("expected comma")); 5307 return FAIL; 5308 5309 wanted_arm: 5310 first_error (_(reg_expected_msgs[REG_TYPE_RN])); 5311 return FAIL; 5312} 5313 5314/* Matcher codes for parse_operands. */ 5315enum operand_parse_code 5316{ 5317 OP_stop, /* end of line */ 5318 5319 OP_RR, /* ARM register */ 5320 OP_RRnpc, /* ARM register, not r15 */ 5321 OP_RRnpcb, /* ARM register, not r15, in square brackets */ 5322 OP_RRw, /* ARM register, not r15, optional trailing ! */ 5323 OP_RCP, /* Coprocessor number */ 5324 OP_RCN, /* Coprocessor register */ 5325 OP_RF, /* FPA register */ 5326 OP_RVS, /* VFP single precision register */ 5327 OP_RVD, /* VFP double precision register (0..15) */ 5328 OP_RND, /* Neon double precision register (0..31) */ 5329 OP_RNQ, /* Neon quad precision register */ 5330 OP_RVSD, /* VFP single or double precision register */ 5331 OP_RNDQ, /* Neon double or quad precision register */ 5332 OP_RNSDQ, /* Neon single, double or quad precision register */ 5333 OP_RNSC, /* Neon scalar D[X] */ 5334 OP_RVC, /* VFP control register */ 5335 OP_RMF, /* Maverick F register */ 5336 OP_RMD, /* Maverick D register */ 5337 OP_RMFX, /* Maverick FX register */ 5338 OP_RMDX, /* Maverick DX register */ 5339 OP_RMAX, /* Maverick AX register */ 5340 OP_RMDS, /* Maverick DSPSC register */ 5341 OP_RIWR, /* iWMMXt wR register */ 5342 OP_RIWC, /* iWMMXt wC register */ 5343 OP_RIWG, /* iWMMXt wCG register */ 5344 OP_RXA, /* XScale accumulator register */ 5345 5346 OP_REGLST, /* ARM register list */ 5347 OP_VRSLST, /* VFP single-precision register list */ 5348 OP_VRDLST, /* VFP double-precision register list */ 5349 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ 5350 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ 5351 OP_NSTRLST, /* Neon element/structure list */ 5352 5353 OP_NILO, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */ 5354 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ 5355 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ 5356 OP_RR_RNSC, /* ARM reg or Neon scalar. */ 5357 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ 5358 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ 5359 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ 5360 OP_VMOV, /* Neon VMOV operands. */ 5361 OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN. */ 5362 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ 5363 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ 5364 5365 OP_I0, /* immediate zero */ 5366 OP_I7, /* immediate value 0 .. 7 */ 5367 OP_I15, /* 0 .. 15 */ 5368 OP_I16, /* 1 .. 16 */ 5369 OP_I16z, /* 0 .. 16 */ 5370 OP_I31, /* 0 .. 31 */ 5371 OP_I31w, /* 0 .. 31, optional trailing ! */ 5372 OP_I32, /* 1 .. 32 */ 5373 OP_I32z, /* 0 .. 32 */ 5374 OP_I63, /* 0 .. 63 */ 5375 OP_I63s, /* -64 .. 63 */ 5376 OP_I64, /* 1 .. 64 */ 5377 OP_I64z, /* 0 .. 64 */ 5378 OP_I255, /* 0 .. 255 */ 5379 5380 OP_I4b, /* immediate, prefix optional, 1 .. 4 */ 5381 OP_I7b, /* 0 .. 7 */ 5382 OP_I15b, /* 0 .. 15 */ 5383 OP_I31b, /* 0 .. 31 */ 5384 5385 OP_SH, /* shifter operand */ 5386 OP_SHG, /* shifter operand with possible group relocation */ 5387 OP_ADDR, /* Memory address expression (any mode) */ 5388 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ 5389 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ 5390 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ 5391 OP_EXP, /* arbitrary expression */ 5392 OP_EXPi, /* same, with optional immediate prefix */ 5393 OP_EXPr, /* same, with optional relocation suffix */ 5394 OP_HALF, /* 0 .. 65535 or low/high reloc. */ 5395 5396 OP_CPSF, /* CPS flags */ 5397 OP_ENDI, /* Endianness specifier */ 5398 OP_PSR, /* CPSR/SPSR mask for msr */ 5399 OP_COND, /* conditional code */ 5400 OP_TB, /* Table branch. */ 5401 5402 OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */ 5403 OP_APSR_RR, /* ARM register or "APSR_nzcv". */ 5404 5405 OP_RRnpc_I0, /* ARM register or literal 0 */ 5406 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ 5407 OP_RR_EXi, /* ARM register or expression with imm prefix */ 5408 OP_RF_IF, /* FPA register or immediate */ 5409 OP_RIWR_RIWC, /* iWMMXt R or C reg */ 5410 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ 5411 5412 /* Optional operands. */ 5413 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ 5414 OP_oI31b, /* 0 .. 31 */ 5415 OP_oI32b, /* 1 .. 32 */ 5416 OP_oIffffb, /* 0 .. 65535 */ 5417 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ 5418 5419 OP_oRR, /* ARM register */ 5420 OP_oRRnpc, /* ARM register, not the PC */ 5421 OP_oRRw, /* ARM register, not r15, optional trailing ! */ 5422 OP_oRND, /* Optional Neon double precision register */ 5423 OP_oRNQ, /* Optional Neon quad precision register */ 5424 OP_oRNDQ, /* Optional Neon double or quad precision register */ 5425 OP_oRNSDQ, /* Optional single, double or quad precision vector register */ 5426 OP_oSHll, /* LSL immediate */ 5427 OP_oSHar, /* ASR immediate */ 5428 OP_oSHllar, /* LSL or ASR immediate */ 5429 OP_oROR, /* ROR 0/8/16/24 */ 5430 OP_oBARRIER, /* Option argument for a barrier instruction. */ 5431 5432 OP_FIRST_OPTIONAL = OP_oI7b 5433}; 5434 5435/* Generic instruction operand parser. This does no encoding and no 5436 semantic validation; it merely squirrels values away in the inst 5437 structure. Returns SUCCESS or FAIL depending on whether the 5438 specified grammar matched. */ 5439static int 5440parse_operands (char *str, const unsigned char *pattern) 5441{ 5442 unsigned const char *upat = pattern; 5443 char *backtrack_pos = 0; 5444 const char *backtrack_error = 0; 5445 int i, val, backtrack_index = 0; 5446 enum arm_reg_type rtype; 5447 parse_operand_result result; 5448 5449#define po_char_or_fail(chr) do { \ 5450 if (skip_past_char (&str, chr) == FAIL) \ 5451 goto bad_args; \ 5452} while (0) 5453 5454#define po_reg_or_fail(regtype) do { \ 5455 val = arm_typed_reg_parse (&str, regtype, &rtype, \ 5456 &inst.operands[i].vectype); \ 5457 if (val == FAIL) \ 5458 { \ 5459 first_error (_(reg_expected_msgs[regtype])); \ 5460 goto failure; \ 5461 } \ 5462 inst.operands[i].reg = val; \ 5463 inst.operands[i].isreg = 1; \ 5464 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ 5465 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ 5466 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ 5467 || rtype == REG_TYPE_VFD \ 5468 || rtype == REG_TYPE_NQ); \ 5469} while (0) 5470 5471#define po_reg_or_goto(regtype, label) do { \ 5472 val = arm_typed_reg_parse (&str, regtype, &rtype, \ 5473 &inst.operands[i].vectype); \ 5474 if (val == FAIL) \ 5475 goto label; \ 5476 \ 5477 inst.operands[i].reg = val; \ 5478 inst.operands[i].isreg = 1; \ 5479 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ 5480 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ 5481 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ 5482 || rtype == REG_TYPE_VFD \ 5483 || rtype == REG_TYPE_NQ); \ 5484} while (0) 5485 5486#define po_imm_or_fail(min, max, popt) do { \ 5487 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ 5488 goto failure; \ 5489 inst.operands[i].imm = val; \ 5490} while (0) 5491 5492#define po_scalar_or_goto(elsz, label) do { \ 5493 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \ 5494 if (val == FAIL) \ 5495 goto label; \ 5496 inst.operands[i].reg = val; \ 5497 inst.operands[i].isscalar = 1; \ 5498} while (0) 5499 5500#define po_misc_or_fail(expr) do { \ 5501 if (expr) \ 5502 goto failure; \ 5503} while (0) 5504 5505#define po_misc_or_fail_no_backtrack(expr) do { \ 5506 result = expr; \ 5507 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\ 5508 backtrack_pos = 0; \ 5509 if (result != PARSE_OPERAND_SUCCESS) \ 5510 goto failure; \ 5511} while (0) 5512 5513 skip_whitespace (str); 5514 5515 for (i = 0; upat[i] != OP_stop; i++) 5516 { 5517 if (upat[i] >= OP_FIRST_OPTIONAL) 5518 { 5519 /* Remember where we are in case we need to backtrack. */ 5520 assert (!backtrack_pos); 5521 backtrack_pos = str; 5522 backtrack_error = inst.error; 5523 backtrack_index = i; 5524 } 5525 5526 if (i > 0 && (i > 1 || inst.operands[0].present)) 5527 po_char_or_fail (','); 5528 5529 switch (upat[i]) 5530 { 5531 /* Registers */ 5532 case OP_oRRnpc: 5533 case OP_RRnpc: 5534 case OP_oRR: 5535 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; 5536 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; 5537 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; 5538 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; 5539 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; 5540 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; 5541 case OP_oRND: 5542 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; 5543 case OP_RVC: 5544 po_reg_or_goto (REG_TYPE_VFC, coproc_reg); 5545 break; 5546 /* Also accept generic coprocessor regs for unknown registers. */ 5547 coproc_reg: 5548 po_reg_or_fail (REG_TYPE_CN); 5549 break; 5550 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; 5551 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; 5552 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; 5553 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; 5554 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; 5555 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; 5556 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; 5557 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; 5558 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; 5559 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; 5560 case OP_oRNQ: 5561 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; 5562 case OP_oRNDQ: 5563 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; 5564 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; 5565 case OP_oRNSDQ: 5566 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; 5567 5568 /* Neon scalar. Using an element size of 8 means that some invalid 5569 scalars are accepted here, so deal with those in later code. */ 5570 case OP_RNSC: po_scalar_or_goto (8, failure); break; 5571 5572 /* WARNING: We can expand to two operands here. This has the potential 5573 to totally confuse the backtracking mechanism! It will be OK at 5574 least as long as we don't try to use optional args as well, 5575 though. */ 5576 case OP_NILO: 5577 { 5578 po_reg_or_goto (REG_TYPE_NDQ, try_imm); 5579 inst.operands[i].present = 1; 5580 i++; 5581 skip_past_comma (&str); 5582 po_reg_or_goto (REG_TYPE_NDQ, one_reg_only); 5583 break; 5584 one_reg_only: 5585 /* Optional register operand was omitted. Unfortunately, it's in 5586 operands[i-1] and we need it to be in inst.operands[i]. Fix that 5587 here (this is a bit grotty). */ 5588 inst.operands[i] = inst.operands[i-1]; 5589 inst.operands[i-1].present = 0; 5590 break; 5591 try_imm: 5592 /* There's a possibility of getting a 64-bit immediate here, so 5593 we need special handling. */ 5594 if (parse_big_immediate (&str, i) == FAIL) 5595 { 5596 inst.error = _("immediate value is out of range"); 5597 goto failure; 5598 } 5599 } 5600 break; 5601 5602 case OP_RNDQ_I0: 5603 { 5604 po_reg_or_goto (REG_TYPE_NDQ, try_imm0); 5605 break; 5606 try_imm0: 5607 po_imm_or_fail (0, 0, TRUE); 5608 } 5609 break; 5610 5611 case OP_RVSD_I0: 5612 po_reg_or_goto (REG_TYPE_VFSD, try_imm0); 5613 break; 5614 5615 case OP_RR_RNSC: 5616 { 5617 po_scalar_or_goto (8, try_rr); 5618 break; 5619 try_rr: 5620 po_reg_or_fail (REG_TYPE_RN); 5621 } 5622 break; 5623 5624 case OP_RNSDQ_RNSC: 5625 { 5626 po_scalar_or_goto (8, try_nsdq); 5627 break; 5628 try_nsdq: 5629 po_reg_or_fail (REG_TYPE_NSDQ); 5630 } 5631 break; 5632 5633 case OP_RNDQ_RNSC: 5634 { 5635 po_scalar_or_goto (8, try_ndq); 5636 break; 5637 try_ndq: 5638 po_reg_or_fail (REG_TYPE_NDQ); 5639 } 5640 break; 5641 5642 case OP_RND_RNSC: 5643 { 5644 po_scalar_or_goto (8, try_vfd); 5645 break; 5646 try_vfd: 5647 po_reg_or_fail (REG_TYPE_VFD); 5648 } 5649 break; 5650 5651 case OP_VMOV: 5652 /* WARNING: parse_neon_mov can move the operand counter, i. If we're 5653 not careful then bad things might happen. */ 5654 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); 5655 break; 5656 5657 case OP_RNDQ_IMVNb: 5658 { 5659 po_reg_or_goto (REG_TYPE_NDQ, try_mvnimm); 5660 break; 5661 try_mvnimm: 5662 /* There's a possibility of getting a 64-bit immediate here, so 5663 we need special handling. */ 5664 if (parse_big_immediate (&str, i) == FAIL) 5665 { 5666 inst.error = _("immediate value is out of range"); 5667 goto failure; 5668 } 5669 } 5670 break; 5671 5672 case OP_RNDQ_I63b: 5673 { 5674 po_reg_or_goto (REG_TYPE_NDQ, try_shimm); 5675 break; 5676 try_shimm: 5677 po_imm_or_fail (0, 63, TRUE); 5678 } 5679 break; 5680 5681 case OP_RRnpcb: 5682 po_char_or_fail ('['); 5683 po_reg_or_fail (REG_TYPE_RN); 5684 po_char_or_fail (']'); 5685 break; 5686 5687 case OP_RRw: 5688 case OP_oRRw: 5689 po_reg_or_fail (REG_TYPE_RN); 5690 if (skip_past_char (&str, '!') == SUCCESS) 5691 inst.operands[i].writeback = 1; 5692 break; 5693 5694 /* Immediates */ 5695 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; 5696 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; 5697 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; 5698 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; 5699 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; 5700 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; 5701 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; 5702 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; 5703 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; 5704 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; 5705 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; 5706 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; 5707 5708 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; 5709 case OP_oI7b: 5710 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; 5711 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; 5712 case OP_oI31b: 5713 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; 5714 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; 5715 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; 5716 5717 /* Immediate variants */ 5718 case OP_oI255c: 5719 po_char_or_fail ('{'); 5720 po_imm_or_fail (0, 255, TRUE); 5721 po_char_or_fail ('}'); 5722 break; 5723 5724 case OP_I31w: 5725 /* The expression parser chokes on a trailing !, so we have 5726 to find it first and zap it. */ 5727 { 5728 char *s = str; 5729 while (*s && *s != ',') 5730 s++; 5731 if (s[-1] == '!') 5732 { 5733 s[-1] = '\0'; 5734 inst.operands[i].writeback = 1; 5735 } 5736 po_imm_or_fail (0, 31, TRUE); 5737 if (str == s - 1) 5738 str = s; 5739 } 5740 break; 5741 5742 /* Expressions */ 5743 case OP_EXPi: EXPi: 5744 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 5745 GE_OPT_PREFIX)); 5746 break; 5747 5748 case OP_EXP: 5749 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 5750 GE_NO_PREFIX)); 5751 break; 5752 5753 case OP_EXPr: EXPr: 5754 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 5755 GE_NO_PREFIX)); 5756 if (inst.reloc.exp.X_op == O_symbol) 5757 { 5758 val = parse_reloc (&str); 5759 if (val == -1) 5760 { 5761 inst.error = _("unrecognized relocation suffix"); 5762 goto failure; 5763 } 5764 else if (val != BFD_RELOC_UNUSED) 5765 { 5766 inst.operands[i].imm = val; 5767 inst.operands[i].hasreloc = 1; 5768 } 5769 } 5770 break; 5771 5772 /* Operand for MOVW or MOVT. */ 5773 case OP_HALF: 5774 po_misc_or_fail (parse_half (&str)); 5775 break; 5776 5777 /* Register or expression */ 5778 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; 5779 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; 5780 5781 /* Register or immediate */ 5782 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; 5783 I0: po_imm_or_fail (0, 0, FALSE); break; 5784 5785 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; 5786 IF: 5787 if (!is_immediate_prefix (*str)) 5788 goto bad_args; 5789 str++; 5790 val = parse_fpa_immediate (&str); 5791 if (val == FAIL) 5792 goto failure; 5793 /* FPA immediates are encoded as registers 8-15. 5794 parse_fpa_immediate has already applied the offset. */ 5795 inst.operands[i].reg = val; 5796 inst.operands[i].isreg = 1; 5797 break; 5798 5799 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; 5800 I32z: po_imm_or_fail (0, 32, FALSE); break; 5801 5802 /* Two kinds of register */ 5803 case OP_RIWR_RIWC: 5804 { 5805 struct reg_entry *rege = arm_reg_parse_multi (&str); 5806 if (!rege 5807 || (rege->type != REG_TYPE_MMXWR 5808 && rege->type != REG_TYPE_MMXWC 5809 && rege->type != REG_TYPE_MMXWCG)) 5810 { 5811 inst.error = _("iWMMXt data or control register expected"); 5812 goto failure; 5813 } 5814 inst.operands[i].reg = rege->number; 5815 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); 5816 } 5817 break; 5818 5819 case OP_RIWC_RIWG: 5820 { 5821 struct reg_entry *rege = arm_reg_parse_multi (&str); 5822 if (!rege 5823 || (rege->type != REG_TYPE_MMXWC 5824 && rege->type != REG_TYPE_MMXWCG)) 5825 { 5826 inst.error = _("iWMMXt control register expected"); 5827 goto failure; 5828 } 5829 inst.operands[i].reg = rege->number; 5830 inst.operands[i].isreg = 1; 5831 } 5832 break; 5833 5834 /* Misc */ 5835 case OP_CPSF: val = parse_cps_flags (&str); break; 5836 case OP_ENDI: val = parse_endian_specifier (&str); break; 5837 case OP_oROR: val = parse_ror (&str); break; 5838 case OP_PSR: val = parse_psr (&str); break; 5839 case OP_COND: val = parse_cond (&str); break; 5840 case OP_oBARRIER:val = parse_barrier (&str); break; 5841 5842 case OP_RVC_PSR: 5843 po_reg_or_goto (REG_TYPE_VFC, try_psr); 5844 inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */ 5845 break; 5846 try_psr: 5847 val = parse_psr (&str); 5848 break; 5849 5850 case OP_APSR_RR: 5851 po_reg_or_goto (REG_TYPE_RN, try_apsr); 5852 break; 5853 try_apsr: 5854 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS 5855 instruction). */ 5856 if (strncasecmp (str, "APSR_", 5) == 0) 5857 { 5858 unsigned found = 0; 5859 str += 5; 5860 while (found < 15) 5861 switch (*str++) 5862 { 5863 case 'c': found = (found & 1) ? 16 : found | 1; break; 5864 case 'n': found = (found & 2) ? 16 : found | 2; break; 5865 case 'z': found = (found & 4) ? 16 : found | 4; break; 5866 case 'v': found = (found & 8) ? 16 : found | 8; break; 5867 default: found = 16; 5868 } 5869 if (found != 15) 5870 goto failure; 5871 inst.operands[i].isvec = 1; 5872 } 5873 else 5874 goto failure; 5875 break; 5876 5877 case OP_TB: 5878 po_misc_or_fail (parse_tb (&str)); 5879 break; 5880 5881 /* Register lists */ 5882 case OP_REGLST: 5883 val = parse_reg_list (&str); 5884 if (*str == '^') 5885 { 5886 inst.operands[1].writeback = 1; 5887 str++; 5888 } 5889 break; 5890 5891 case OP_VRSLST: 5892 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); 5893 break; 5894 5895 case OP_VRDLST: 5896 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); 5897 break; 5898 5899 case OP_VRSDLST: 5900 /* Allow Q registers too. */ 5901 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 5902 REGLIST_NEON_D); 5903 if (val == FAIL) 5904 { 5905 inst.error = NULL; 5906 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 5907 REGLIST_VFP_S); 5908 inst.operands[i].issingle = 1; 5909 } 5910 break; 5911 5912 case OP_NRDLST: 5913 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 5914 REGLIST_NEON_D); 5915 break; 5916 5917 case OP_NSTRLST: 5918 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, 5919 &inst.operands[i].vectype); 5920 break; 5921 5922 /* Addressing modes */ 5923 case OP_ADDR: 5924 po_misc_or_fail (parse_address (&str, i)); 5925 break; 5926 5927 case OP_ADDRGLDR: 5928 po_misc_or_fail_no_backtrack ( 5929 parse_address_group_reloc (&str, i, GROUP_LDR)); 5930 break; 5931 5932 case OP_ADDRGLDRS: 5933 po_misc_or_fail_no_backtrack ( 5934 parse_address_group_reloc (&str, i, GROUP_LDRS)); 5935 break; 5936 5937 case OP_ADDRGLDC: 5938 po_misc_or_fail_no_backtrack ( 5939 parse_address_group_reloc (&str, i, GROUP_LDC)); 5940 break; 5941 5942 case OP_SH: 5943 po_misc_or_fail (parse_shifter_operand (&str, i)); 5944 break; 5945 5946 case OP_SHG: 5947 po_misc_or_fail_no_backtrack ( 5948 parse_shifter_operand_group_reloc (&str, i)); 5949 break; 5950 5951 case OP_oSHll: 5952 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); 5953 break; 5954 5955 case OP_oSHar: 5956 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); 5957 break; 5958 5959 case OP_oSHllar: 5960 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); 5961 break; 5962 5963 default: 5964 as_fatal ("unhandled operand code %d", upat[i]); 5965 } 5966 5967 /* Various value-based sanity checks and shared operations. We 5968 do not signal immediate failures for the register constraints; 5969 this allows a syntax error to take precedence. */ 5970 switch (upat[i]) 5971 { 5972 case OP_oRRnpc: 5973 case OP_RRnpc: 5974 case OP_RRnpcb: 5975 case OP_RRw: 5976 case OP_oRRw: 5977 case OP_RRnpc_I0: 5978 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) 5979 inst.error = BAD_PC; 5980 break; 5981 5982 case OP_CPSF: 5983 case OP_ENDI: 5984 case OP_oROR: 5985 case OP_PSR: 5986 case OP_RVC_PSR: 5987 case OP_COND: 5988 case OP_oBARRIER: 5989 case OP_REGLST: 5990 case OP_VRSLST: 5991 case OP_VRDLST: 5992 case OP_VRSDLST: 5993 case OP_NRDLST: 5994 case OP_NSTRLST: 5995 if (val == FAIL) 5996 goto failure; 5997 inst.operands[i].imm = val; 5998 break; 5999 6000 default: 6001 break; 6002 } 6003 6004 /* If we get here, this operand was successfully parsed. */ 6005 inst.operands[i].present = 1; 6006 continue; 6007 6008 bad_args: 6009 inst.error = BAD_ARGS; 6010 6011 failure: 6012 if (!backtrack_pos) 6013 { 6014 /* The parse routine should already have set inst.error, but set a 6015 defaut here just in case. */ 6016 if (!inst.error) 6017 inst.error = _("syntax error"); 6018 return FAIL; 6019 } 6020 6021 /* Do not backtrack over a trailing optional argument that 6022 absorbed some text. We will only fail again, with the 6023 'garbage following instruction' error message, which is 6024 probably less helpful than the current one. */ 6025 if (backtrack_index == i && backtrack_pos != str 6026 && upat[i+1] == OP_stop) 6027 { 6028 if (!inst.error) 6029 inst.error = _("syntax error"); 6030 return FAIL; 6031 } 6032 6033 /* Try again, skipping the optional argument at backtrack_pos. */ 6034 str = backtrack_pos; 6035 inst.error = backtrack_error; 6036 inst.operands[backtrack_index].present = 0; 6037 i = backtrack_index; 6038 backtrack_pos = 0; 6039 } 6040 6041 /* Check that we have parsed all the arguments. */ 6042 if (*str != '\0' && !inst.error) 6043 inst.error = _("garbage following instruction"); 6044 6045 return inst.error ? FAIL : SUCCESS; 6046} 6047 6048#undef po_char_or_fail 6049#undef po_reg_or_fail 6050#undef po_reg_or_goto 6051#undef po_imm_or_fail 6052#undef po_scalar_or_fail 6053 6054/* Shorthand macro for instruction encoding functions issuing errors. */ 6055#define constraint(expr, err) do { \ 6056 if (expr) \ 6057 { \ 6058 inst.error = err; \ 6059 return; \ 6060 } \ 6061} while (0) 6062 6063/* Functions for operand encoding. ARM, then Thumb. */ 6064 6065#define rotate_left(v, n) (v << n | v >> (32 - n)) 6066 6067/* If VAL can be encoded in the immediate field of an ARM instruction, 6068 return the encoded form. Otherwise, return FAIL. */ 6069 6070static unsigned int 6071encode_arm_immediate (unsigned int val) 6072{ 6073 unsigned int a, i; 6074 6075 for (i = 0; i < 32; i += 2) 6076 if ((a = rotate_left (val, i)) <= 0xff) 6077 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ 6078 6079 return FAIL; 6080} 6081 6082/* If VAL can be encoded in the immediate field of a Thumb32 instruction, 6083 return the encoded form. Otherwise, return FAIL. */ 6084static unsigned int 6085encode_thumb32_immediate (unsigned int val) 6086{ 6087 unsigned int a, i; 6088 6089 if (val <= 0xff) 6090 return val; 6091 6092 for (i = 1; i <= 24; i++) 6093 { 6094 a = val >> i; 6095 if ((val & ~(0xff << i)) == 0) 6096 return ((val >> i) & 0x7f) | ((32 - i) << 7); 6097 } 6098 6099 a = val & 0xff; 6100 if (val == ((a << 16) | a)) 6101 return 0x100 | a; 6102 if (val == ((a << 24) | (a << 16) | (a << 8) | a)) 6103 return 0x300 | a; 6104 6105 a = val & 0xff00; 6106 if (val == ((a << 16) | a)) 6107 return 0x200 | (a >> 8); 6108 6109 return FAIL; 6110} 6111/* Encode a VFP SP or DP register number into inst.instruction. */ 6112 6113static void 6114encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) 6115{ 6116 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) 6117 && reg > 15) 6118 { 6119 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3)) 6120 { 6121 if (thumb_mode) 6122 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 6123 fpu_vfp_ext_v3); 6124 else 6125 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 6126 fpu_vfp_ext_v3); 6127 } 6128 else 6129 { 6130 first_error (_("D register out of range for selected VFP version")); 6131 return; 6132 } 6133 } 6134 6135 switch (pos) 6136 { 6137 case VFP_REG_Sd: 6138 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); 6139 break; 6140 6141 case VFP_REG_Sn: 6142 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); 6143 break; 6144 6145 case VFP_REG_Sm: 6146 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); 6147 break; 6148 6149 case VFP_REG_Dd: 6150 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); 6151 break; 6152 6153 case VFP_REG_Dn: 6154 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); 6155 break; 6156 6157 case VFP_REG_Dm: 6158 inst.instruction |= (reg & 15) | ((reg >> 4) << 5); 6159 break; 6160 6161 default: 6162 abort (); 6163 } 6164} 6165 6166/* Encode a <shift> in an ARM-format instruction. The immediate, 6167 if any, is handled by md_apply_fix. */ 6168static void 6169encode_arm_shift (int i) 6170{ 6171 if (inst.operands[i].shift_kind == SHIFT_RRX) 6172 inst.instruction |= SHIFT_ROR << 5; 6173 else 6174 { 6175 inst.instruction |= inst.operands[i].shift_kind << 5; 6176 if (inst.operands[i].immisreg) 6177 { 6178 inst.instruction |= SHIFT_BY_REG; 6179 inst.instruction |= inst.operands[i].imm << 8; 6180 } 6181 else 6182 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 6183 } 6184} 6185 6186static void 6187encode_arm_shifter_operand (int i) 6188{ 6189 if (inst.operands[i].isreg) 6190 { 6191 inst.instruction |= inst.operands[i].reg; 6192 encode_arm_shift (i); 6193 } 6194 else 6195 inst.instruction |= INST_IMMEDIATE; 6196} 6197 6198/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ 6199static void 6200encode_arm_addr_mode_common (int i, bfd_boolean is_t) 6201{ 6202 assert (inst.operands[i].isreg); 6203 inst.instruction |= inst.operands[i].reg << 16; 6204 6205 if (inst.operands[i].preind) 6206 { 6207 if (is_t) 6208 { 6209 inst.error = _("instruction does not accept preindexed addressing"); 6210 return; 6211 } 6212 inst.instruction |= PRE_INDEX; 6213 if (inst.operands[i].writeback) 6214 inst.instruction |= WRITE_BACK; 6215 6216 } 6217 else if (inst.operands[i].postind) 6218 { 6219 assert (inst.operands[i].writeback); 6220 if (is_t) 6221 inst.instruction |= WRITE_BACK; 6222 } 6223 else /* unindexed - only for coprocessor */ 6224 { 6225 inst.error = _("instruction does not accept unindexed addressing"); 6226 return; 6227 } 6228 6229 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) 6230 && (((inst.instruction & 0x000f0000) >> 16) 6231 == ((inst.instruction & 0x0000f000) >> 12))) 6232 as_warn ((inst.instruction & LOAD_BIT) 6233 ? _("destination register same as write-back base") 6234 : _("source register same as write-back base")); 6235} 6236 6237/* inst.operands[i] was set up by parse_address. Encode it into an 6238 ARM-format mode 2 load or store instruction. If is_t is true, 6239 reject forms that cannot be used with a T instruction (i.e. not 6240 post-indexed). */ 6241static void 6242encode_arm_addr_mode_2 (int i, bfd_boolean is_t) 6243{ 6244 encode_arm_addr_mode_common (i, is_t); 6245 6246 if (inst.operands[i].immisreg) 6247 { 6248 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ 6249 inst.instruction |= inst.operands[i].imm; 6250 if (!inst.operands[i].negative) 6251 inst.instruction |= INDEX_UP; 6252 if (inst.operands[i].shifted) 6253 { 6254 if (inst.operands[i].shift_kind == SHIFT_RRX) 6255 inst.instruction |= SHIFT_ROR << 5; 6256 else 6257 { 6258 inst.instruction |= inst.operands[i].shift_kind << 5; 6259 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 6260 } 6261 } 6262 } 6263 else /* immediate offset in inst.reloc */ 6264 { 6265 if (inst.reloc.type == BFD_RELOC_UNUSED) 6266 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; 6267 } 6268} 6269 6270/* inst.operands[i] was set up by parse_address. Encode it into an 6271 ARM-format mode 3 load or store instruction. Reject forms that 6272 cannot be used with such instructions. If is_t is true, reject 6273 forms that cannot be used with a T instruction (i.e. not 6274 post-indexed). */ 6275static void 6276encode_arm_addr_mode_3 (int i, bfd_boolean is_t) 6277{ 6278 if (inst.operands[i].immisreg && inst.operands[i].shifted) 6279 { 6280 inst.error = _("instruction does not accept scaled register index"); 6281 return; 6282 } 6283 6284 encode_arm_addr_mode_common (i, is_t); 6285 6286 if (inst.operands[i].immisreg) 6287 { 6288 inst.instruction |= inst.operands[i].imm; 6289 if (!inst.operands[i].negative) 6290 inst.instruction |= INDEX_UP; 6291 } 6292 else /* immediate offset in inst.reloc */ 6293 { 6294 inst.instruction |= HWOFFSET_IMM; 6295 if (inst.reloc.type == BFD_RELOC_UNUSED) 6296 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; 6297 } 6298} 6299 6300/* inst.operands[i] was set up by parse_address. Encode it into an 6301 ARM-format instruction. Reject all forms which cannot be encoded 6302 into a coprocessor load/store instruction. If wb_ok is false, 6303 reject use of writeback; if unind_ok is false, reject use of 6304 unindexed addressing. If reloc_override is not 0, use it instead 6305 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one 6306 (in which case it is preserved). */ 6307 6308static int 6309encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) 6310{ 6311 inst.instruction |= inst.operands[i].reg << 16; 6312 6313 assert (!(inst.operands[i].preind && inst.operands[i].postind)); 6314 6315 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ 6316 { 6317 assert (!inst.operands[i].writeback); 6318 if (!unind_ok) 6319 { 6320 inst.error = _("instruction does not support unindexed addressing"); 6321 return FAIL; 6322 } 6323 inst.instruction |= inst.operands[i].imm; 6324 inst.instruction |= INDEX_UP; 6325 return SUCCESS; 6326 } 6327 6328 if (inst.operands[i].preind) 6329 inst.instruction |= PRE_INDEX; 6330 6331 if (inst.operands[i].writeback) 6332 { 6333 if (inst.operands[i].reg == REG_PC) 6334 { 6335 inst.error = _("pc may not be used with write-back"); 6336 return FAIL; 6337 } 6338 if (!wb_ok) 6339 { 6340 inst.error = _("instruction does not support writeback"); 6341 return FAIL; 6342 } 6343 inst.instruction |= WRITE_BACK; 6344 } 6345 6346 if (reloc_override) 6347 inst.reloc.type = reloc_override; 6348 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC 6349 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) 6350 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) 6351 { 6352 if (thumb_mode) 6353 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; 6354 else 6355 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; 6356 } 6357 6358 return SUCCESS; 6359} 6360 6361/* inst.reloc.exp describes an "=expr" load pseudo-operation. 6362 Determine whether it can be performed with a move instruction; if 6363 it can, convert inst.instruction to that move instruction and 6364 return 1; if it can't, convert inst.instruction to a literal-pool 6365 load and return 0. If this is not a valid thing to do in the 6366 current context, set inst.error and return 1. 6367 6368 inst.operands[i] describes the destination register. */ 6369 6370static int 6371move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) 6372{ 6373 unsigned long tbit; 6374 6375 if (thumb_p) 6376 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; 6377 else 6378 tbit = LOAD_BIT; 6379 6380 if ((inst.instruction & tbit) == 0) 6381 { 6382 inst.error = _("invalid pseudo operation"); 6383 return 1; 6384 } 6385 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) 6386 { 6387 inst.error = _("constant expression expected"); 6388 return 1; 6389 } 6390 if (inst.reloc.exp.X_op == O_constant) 6391 { 6392 if (thumb_p) 6393 { 6394 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) 6395 { 6396 /* This can be done with a mov(1) instruction. */ 6397 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); 6398 inst.instruction |= inst.reloc.exp.X_add_number; 6399 return 1; 6400 } 6401 } 6402 else 6403 { 6404 int value = encode_arm_immediate (inst.reloc.exp.X_add_number); 6405 if (value != FAIL) 6406 { 6407 /* This can be done with a mov instruction. */ 6408 inst.instruction &= LITERAL_MASK; 6409 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); 6410 inst.instruction |= value & 0xfff; 6411 return 1; 6412 } 6413 6414 value = encode_arm_immediate (~inst.reloc.exp.X_add_number); 6415 if (value != FAIL) 6416 { 6417 /* This can be done with a mvn instruction. */ 6418 inst.instruction &= LITERAL_MASK; 6419 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); 6420 inst.instruction |= value & 0xfff; 6421 return 1; 6422 } 6423 } 6424 } 6425 6426 if (add_to_lit_pool () == FAIL) 6427 { 6428 inst.error = _("literal pool insertion failed"); 6429 return 1; 6430 } 6431 inst.operands[1].reg = REG_PC; 6432 inst.operands[1].isreg = 1; 6433 inst.operands[1].preind = 1; 6434 inst.reloc.pc_rel = 1; 6435 inst.reloc.type = (thumb_p 6436 ? BFD_RELOC_ARM_THUMB_OFFSET 6437 : (mode_3 6438 ? BFD_RELOC_ARM_HWLITERAL 6439 : BFD_RELOC_ARM_LITERAL)); 6440 return 0; 6441} 6442 6443/* Functions for instruction encoding, sorted by subarchitecture. 6444 First some generics; their names are taken from the conventional 6445 bit positions for register arguments in ARM format instructions. */ 6446 6447static void 6448do_noargs (void) 6449{ 6450} 6451 6452static void 6453do_rd (void) 6454{ 6455 inst.instruction |= inst.operands[0].reg << 12; 6456} 6457 6458static void 6459do_rd_rm (void) 6460{ 6461 inst.instruction |= inst.operands[0].reg << 12; 6462 inst.instruction |= inst.operands[1].reg; 6463} 6464 6465static void 6466do_rd_rn (void) 6467{ 6468 inst.instruction |= inst.operands[0].reg << 12; 6469 inst.instruction |= inst.operands[1].reg << 16; 6470} 6471 6472static void 6473do_rn_rd (void) 6474{ 6475 inst.instruction |= inst.operands[0].reg << 16; 6476 inst.instruction |= inst.operands[1].reg << 12; 6477} 6478 6479static void 6480do_rd_rm_rn (void) 6481{ 6482 unsigned Rn = inst.operands[2].reg; 6483 /* Enforce restrictions on SWP instruction. */ 6484 if ((inst.instruction & 0x0fbfffff) == 0x01000090) 6485 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, 6486 _("Rn must not overlap other operands")); 6487 inst.instruction |= inst.operands[0].reg << 12; 6488 inst.instruction |= inst.operands[1].reg; 6489 inst.instruction |= Rn << 16; 6490} 6491 6492static void 6493do_rd_rn_rm (void) 6494{ 6495 inst.instruction |= inst.operands[0].reg << 12; 6496 inst.instruction |= inst.operands[1].reg << 16; 6497 inst.instruction |= inst.operands[2].reg; 6498} 6499 6500static void 6501do_rm_rd_rn (void) 6502{ 6503 inst.instruction |= inst.operands[0].reg; 6504 inst.instruction |= inst.operands[1].reg << 12; 6505 inst.instruction |= inst.operands[2].reg << 16; 6506} 6507 6508static void 6509do_imm0 (void) 6510{ 6511 inst.instruction |= inst.operands[0].imm; 6512} 6513 6514static void 6515do_rd_cpaddr (void) 6516{ 6517 inst.instruction |= inst.operands[0].reg << 12; 6518 encode_arm_cp_address (1, TRUE, TRUE, 0); 6519} 6520 6521/* ARM instructions, in alphabetical order by function name (except 6522 that wrapper functions appear immediately after the function they 6523 wrap). */ 6524 6525/* This is a pseudo-op of the form "adr rd, label" to be converted 6526 into a relative address of the form "add rd, pc, #label-.-8". */ 6527 6528static void 6529do_adr (void) 6530{ 6531 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ 6532 6533 /* Frag hacking will turn this into a sub instruction if the offset turns 6534 out to be negative. */ 6535 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 6536 inst.reloc.pc_rel = 1; 6537 inst.reloc.exp.X_add_number -= 8; 6538} 6539 6540/* This is a pseudo-op of the form "adrl rd, label" to be converted 6541 into a relative address of the form: 6542 add rd, pc, #low(label-.-8)" 6543 add rd, rd, #high(label-.-8)" */ 6544 6545static void 6546do_adrl (void) 6547{ 6548 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ 6549 6550 /* Frag hacking will turn this into a sub instruction if the offset turns 6551 out to be negative. */ 6552 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; 6553 inst.reloc.pc_rel = 1; 6554 inst.size = INSN_SIZE * 2; 6555 inst.reloc.exp.X_add_number -= 8; 6556} 6557 6558static void 6559do_arit (void) 6560{ 6561 if (!inst.operands[1].present) 6562 inst.operands[1].reg = inst.operands[0].reg; 6563 inst.instruction |= inst.operands[0].reg << 12; 6564 inst.instruction |= inst.operands[1].reg << 16; 6565 encode_arm_shifter_operand (2); 6566} 6567 6568static void 6569do_barrier (void) 6570{ 6571 if (inst.operands[0].present) 6572 { 6573 constraint ((inst.instruction & 0xf0) != 0x40 6574 && inst.operands[0].imm != 0xf, 6575 "bad barrier type"); 6576 inst.instruction |= inst.operands[0].imm; 6577 } 6578 else 6579 inst.instruction |= 0xf; 6580} 6581 6582static void 6583do_bfc (void) 6584{ 6585 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; 6586 constraint (msb > 32, _("bit-field extends past end of register")); 6587 /* The instruction encoding stores the LSB and MSB, 6588 not the LSB and width. */ 6589 inst.instruction |= inst.operands[0].reg << 12; 6590 inst.instruction |= inst.operands[1].imm << 7; 6591 inst.instruction |= (msb - 1) << 16; 6592} 6593 6594static void 6595do_bfi (void) 6596{ 6597 unsigned int msb; 6598 6599 /* #0 in second position is alternative syntax for bfc, which is 6600 the same instruction but with REG_PC in the Rm field. */ 6601 if (!inst.operands[1].isreg) 6602 inst.operands[1].reg = REG_PC; 6603 6604 msb = inst.operands[2].imm + inst.operands[3].imm; 6605 constraint (msb > 32, _("bit-field extends past end of register")); 6606 /* The instruction encoding stores the LSB and MSB, 6607 not the LSB and width. */ 6608 inst.instruction |= inst.operands[0].reg << 12; 6609 inst.instruction |= inst.operands[1].reg; 6610 inst.instruction |= inst.operands[2].imm << 7; 6611 inst.instruction |= (msb - 1) << 16; 6612} 6613 6614static void 6615do_bfx (void) 6616{ 6617 constraint (inst.operands[2].imm + inst.operands[3].imm > 32, 6618 _("bit-field extends past end of register")); 6619 inst.instruction |= inst.operands[0].reg << 12; 6620 inst.instruction |= inst.operands[1].reg; 6621 inst.instruction |= inst.operands[2].imm << 7; 6622 inst.instruction |= (inst.operands[3].imm - 1) << 16; 6623} 6624 6625/* ARM V5 breakpoint instruction (argument parse) 6626 BKPT <16 bit unsigned immediate> 6627 Instruction is not conditional. 6628 The bit pattern given in insns[] has the COND_ALWAYS condition, 6629 and it is an error if the caller tried to override that. */ 6630 6631static void 6632do_bkpt (void) 6633{ 6634 /* Top 12 of 16 bits to bits 19:8. */ 6635 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; 6636 6637 /* Bottom 4 of 16 bits to bits 3:0. */ 6638 inst.instruction |= inst.operands[0].imm & 0xf; 6639} 6640 6641static void 6642encode_branch (int default_reloc) 6643{ 6644 if (inst.operands[0].hasreloc) 6645 { 6646 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32, 6647 _("the only suffix valid here is '(plt)'")); 6648 inst.reloc.type = BFD_RELOC_ARM_PLT32; 6649 } 6650 else 6651 { 6652 inst.reloc.type = default_reloc; 6653 } 6654 inst.reloc.pc_rel = 1; 6655} 6656 6657static void 6658do_branch (void) 6659{ 6660#ifdef OBJ_ELF 6661 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 6662 encode_branch (BFD_RELOC_ARM_PCREL_JUMP); 6663 else 6664#endif 6665 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); 6666} 6667 6668static void 6669do_bl (void) 6670{ 6671#ifdef OBJ_ELF 6672 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 6673 { 6674 if (inst.cond == COND_ALWAYS) 6675 encode_branch (BFD_RELOC_ARM_PCREL_CALL); 6676 else 6677 encode_branch (BFD_RELOC_ARM_PCREL_JUMP); 6678 } 6679 else 6680#endif 6681 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); 6682} 6683 6684/* ARM V5 branch-link-exchange instruction (argument parse) 6685 BLX <target_addr> ie BLX(1) 6686 BLX{<condition>} <Rm> ie BLX(2) 6687 Unfortunately, there are two different opcodes for this mnemonic. 6688 So, the insns[].value is not used, and the code here zaps values 6689 into inst.instruction. 6690 Also, the <target_addr> can be 25 bits, hence has its own reloc. */ 6691 6692static void 6693do_blx (void) 6694{ 6695 if (inst.operands[0].isreg) 6696 { 6697 /* Arg is a register; the opcode provided by insns[] is correct. 6698 It is not illegal to do "blx pc", just useless. */ 6699 if (inst.operands[0].reg == REG_PC) 6700 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); 6701 6702 inst.instruction |= inst.operands[0].reg; 6703 } 6704 else 6705 { 6706 /* Arg is an address; this instruction cannot be executed 6707 conditionally, and the opcode must be adjusted. */ 6708 constraint (inst.cond != COND_ALWAYS, BAD_COND); 6709 inst.instruction = 0xfa000000; 6710#ifdef OBJ_ELF 6711 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 6712 encode_branch (BFD_RELOC_ARM_PCREL_CALL); 6713 else 6714#endif 6715 encode_branch (BFD_RELOC_ARM_PCREL_BLX); 6716 } 6717} 6718 6719static void 6720do_bx (void) 6721{ 6722 if (inst.operands[0].reg == REG_PC) 6723 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); 6724 6725 inst.instruction |= inst.operands[0].reg; 6726} 6727 6728 6729/* ARM v5TEJ. Jump to Jazelle code. */ 6730 6731static void 6732do_bxj (void) 6733{ 6734 if (inst.operands[0].reg == REG_PC) 6735 as_tsktsk (_("use of r15 in bxj is not really useful")); 6736 6737 inst.instruction |= inst.operands[0].reg; 6738} 6739 6740/* Co-processor data operation: 6741 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} 6742 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ 6743static void 6744do_cdp (void) 6745{ 6746 inst.instruction |= inst.operands[0].reg << 8; 6747 inst.instruction |= inst.operands[1].imm << 20; 6748 inst.instruction |= inst.operands[2].reg << 12; 6749 inst.instruction |= inst.operands[3].reg << 16; 6750 inst.instruction |= inst.operands[4].reg; 6751 inst.instruction |= inst.operands[5].imm << 5; 6752} 6753 6754static void 6755do_cmp (void) 6756{ 6757 inst.instruction |= inst.operands[0].reg << 16; 6758 encode_arm_shifter_operand (1); 6759} 6760 6761/* Transfer between coprocessor and ARM registers. 6762 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} 6763 MRC2 6764 MCR{cond} 6765 MCR2 6766 6767 No special properties. */ 6768 6769static void 6770do_co_reg (void) 6771{ 6772 inst.instruction |= inst.operands[0].reg << 8; 6773 inst.instruction |= inst.operands[1].imm << 21; 6774 inst.instruction |= inst.operands[2].reg << 12; 6775 inst.instruction |= inst.operands[3].reg << 16; 6776 inst.instruction |= inst.operands[4].reg; 6777 inst.instruction |= inst.operands[5].imm << 5; 6778} 6779 6780/* Transfer between coprocessor register and pair of ARM registers. 6781 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. 6782 MCRR2 6783 MRRC{cond} 6784 MRRC2 6785 6786 Two XScale instructions are special cases of these: 6787 6788 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 6789 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 6790 6791 Result unpredicatable if Rd or Rn is R15. */ 6792 6793static void 6794do_co_reg2c (void) 6795{ 6796 inst.instruction |= inst.operands[0].reg << 8; 6797 inst.instruction |= inst.operands[1].imm << 4; 6798 inst.instruction |= inst.operands[2].reg << 12; 6799 inst.instruction |= inst.operands[3].reg << 16; 6800 inst.instruction |= inst.operands[4].reg; 6801} 6802 6803static void 6804do_cpsi (void) 6805{ 6806 inst.instruction |= inst.operands[0].imm << 6; 6807 if (inst.operands[1].present) 6808 { 6809 inst.instruction |= CPSI_MMOD; 6810 inst.instruction |= inst.operands[1].imm; 6811 } 6812} 6813 6814static void 6815do_dbg (void) 6816{ 6817 inst.instruction |= inst.operands[0].imm; 6818} 6819 6820static void 6821do_it (void) 6822{ 6823 /* There is no IT instruction in ARM mode. We 6824 process it but do not generate code for it. */ 6825 inst.size = 0; 6826} 6827 6828static void 6829do_ldmstm (void) 6830{ 6831 int base_reg = inst.operands[0].reg; 6832 int range = inst.operands[1].imm; 6833 6834 inst.instruction |= base_reg << 16; 6835 inst.instruction |= range; 6836 6837 if (inst.operands[1].writeback) 6838 inst.instruction |= LDM_TYPE_2_OR_3; 6839 6840 if (inst.operands[0].writeback) 6841 { 6842 inst.instruction |= WRITE_BACK; 6843 /* Check for unpredictable uses of writeback. */ 6844 if (inst.instruction & LOAD_BIT) 6845 { 6846 /* Not allowed in LDM type 2. */ 6847 if ((inst.instruction & LDM_TYPE_2_OR_3) 6848 && ((range & (1 << REG_PC)) == 0)) 6849 as_warn (_("writeback of base register is UNPREDICTABLE")); 6850 /* Only allowed if base reg not in list for other types. */ 6851 else if (range & (1 << base_reg)) 6852 as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); 6853 } 6854 else /* STM. */ 6855 { 6856 /* Not allowed for type 2. */ 6857 if (inst.instruction & LDM_TYPE_2_OR_3) 6858 as_warn (_("writeback of base register is UNPREDICTABLE")); 6859 /* Only allowed if base reg not in list, or first in list. */ 6860 else if ((range & (1 << base_reg)) 6861 && (range & ((1 << base_reg) - 1))) 6862 as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); 6863 } 6864 } 6865} 6866 6867/* ARMv5TE load-consecutive (argument parse) 6868 Mode is like LDRH. 6869 6870 LDRccD R, mode 6871 STRccD R, mode. */ 6872 6873static void 6874do_ldrd (void) 6875{ 6876 constraint (inst.operands[0].reg % 2 != 0, 6877 _("first destination register must be even")); 6878 constraint (inst.operands[1].present 6879 && inst.operands[1].reg != inst.operands[0].reg + 1, 6880 _("can only load two consecutive registers")); 6881 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); 6882 constraint (!inst.operands[2].isreg, _("'[' expected")); 6883 6884 if (!inst.operands[1].present) 6885 inst.operands[1].reg = inst.operands[0].reg + 1; 6886 6887 if (inst.instruction & LOAD_BIT) 6888 { 6889 /* encode_arm_addr_mode_3 will diagnose overlap between the base 6890 register and the first register written; we have to diagnose 6891 overlap between the base and the second register written here. */ 6892 6893 if (inst.operands[2].reg == inst.operands[1].reg 6894 && (inst.operands[2].writeback || inst.operands[2].postind)) 6895 as_warn (_("base register written back, and overlaps " 6896 "second destination register")); 6897 6898 /* For an index-register load, the index register must not overlap the 6899 destination (even if not write-back). */ 6900 else if (inst.operands[2].immisreg 6901 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg 6902 || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) 6903 as_warn (_("index register overlaps destination register")); 6904 } 6905 6906 inst.instruction |= inst.operands[0].reg << 12; 6907 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); 6908} 6909 6910static void 6911do_ldrex (void) 6912{ 6913 constraint (!inst.operands[1].isreg || !inst.operands[1].preind 6914 || inst.operands[1].postind || inst.operands[1].writeback 6915 || inst.operands[1].immisreg || inst.operands[1].shifted 6916 || inst.operands[1].negative 6917 /* This can arise if the programmer has written 6918 strex rN, rM, foo 6919 or if they have mistakenly used a register name as the last 6920 operand, eg: 6921 strex rN, rM, rX 6922 It is very difficult to distinguish between these two cases 6923 because "rX" might actually be a label. ie the register 6924 name has been occluded by a symbol of the same name. So we 6925 just generate a general 'bad addressing mode' type error 6926 message and leave it up to the programmer to discover the 6927 true cause and fix their mistake. */ 6928 || (inst.operands[1].reg == REG_PC), 6929 BAD_ADDR_MODE); 6930 6931 constraint (inst.reloc.exp.X_op != O_constant 6932 || inst.reloc.exp.X_add_number != 0, 6933 _("offset must be zero in ARM encoding")); 6934 6935 inst.instruction |= inst.operands[0].reg << 12; 6936 inst.instruction |= inst.operands[1].reg << 16; 6937 inst.reloc.type = BFD_RELOC_UNUSED; 6938} 6939 6940static void 6941do_ldrexd (void) 6942{ 6943 constraint (inst.operands[0].reg % 2 != 0, 6944 _("even register required")); 6945 constraint (inst.operands[1].present 6946 && inst.operands[1].reg != inst.operands[0].reg + 1, 6947 _("can only load two consecutive registers")); 6948 /* If op 1 were present and equal to PC, this function wouldn't 6949 have been called in the first place. */ 6950 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); 6951 6952 inst.instruction |= inst.operands[0].reg << 12; 6953 inst.instruction |= inst.operands[2].reg << 16; 6954} 6955 6956static void 6957do_ldst (void) 6958{ 6959 inst.instruction |= inst.operands[0].reg << 12; 6960 if (!inst.operands[1].isreg) 6961 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) 6962 return; 6963 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); 6964} 6965 6966static void 6967do_ldstt (void) 6968{ 6969 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and 6970 reject [Rn,...]. */ 6971 if (inst.operands[1].preind) 6972 { 6973 constraint (inst.reloc.exp.X_op != O_constant || 6974 inst.reloc.exp.X_add_number != 0, 6975 _("this instruction requires a post-indexed address")); 6976 6977 inst.operands[1].preind = 0; 6978 inst.operands[1].postind = 1; 6979 inst.operands[1].writeback = 1; 6980 } 6981 inst.instruction |= inst.operands[0].reg << 12; 6982 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); 6983} 6984 6985/* Halfword and signed-byte load/store operations. */ 6986 6987static void 6988do_ldstv4 (void) 6989{ 6990 inst.instruction |= inst.operands[0].reg << 12; 6991 if (!inst.operands[1].isreg) 6992 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) 6993 return; 6994 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); 6995} 6996 6997static void 6998do_ldsttv4 (void) 6999{ 7000 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and 7001 reject [Rn,...]. */ 7002 if (inst.operands[1].preind) 7003 { 7004 constraint (inst.reloc.exp.X_op != O_constant || 7005 inst.reloc.exp.X_add_number != 0, 7006 _("this instruction requires a post-indexed address")); 7007 7008 inst.operands[1].preind = 0; 7009 inst.operands[1].postind = 1; 7010 inst.operands[1].writeback = 1; 7011 } 7012 inst.instruction |= inst.operands[0].reg << 12; 7013 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); 7014} 7015 7016/* Co-processor register load/store. 7017 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ 7018static void 7019do_lstc (void) 7020{ 7021 inst.instruction |= inst.operands[0].reg << 8; 7022 inst.instruction |= inst.operands[1].reg << 12; 7023 encode_arm_cp_address (2, TRUE, TRUE, 0); 7024} 7025 7026static void 7027do_mlas (void) 7028{ 7029 /* This restriction does not apply to mls (nor to mla in v6 or later). */ 7030 if (inst.operands[0].reg == inst.operands[1].reg 7031 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) 7032 && !(inst.instruction & 0x00400000)) 7033 as_tsktsk (_("Rd and Rm should be different in mla")); 7034 7035 inst.instruction |= inst.operands[0].reg << 16; 7036 inst.instruction |= inst.operands[1].reg; 7037 inst.instruction |= inst.operands[2].reg << 8; 7038 inst.instruction |= inst.operands[3].reg << 12; 7039} 7040 7041static void 7042do_mov (void) 7043{ 7044 inst.instruction |= inst.operands[0].reg << 12; 7045 encode_arm_shifter_operand (1); 7046} 7047 7048/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ 7049static void 7050do_mov16 (void) 7051{ 7052 bfd_vma imm; 7053 bfd_boolean top; 7054 7055 top = (inst.instruction & 0x00400000) != 0; 7056 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, 7057 _(":lower16: not allowed this instruction")); 7058 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, 7059 _(":upper16: not allowed instruction")); 7060 inst.instruction |= inst.operands[0].reg << 12; 7061 if (inst.reloc.type == BFD_RELOC_UNUSED) 7062 { 7063 imm = inst.reloc.exp.X_add_number; 7064 /* The value is in two pieces: 0:11, 16:19. */ 7065 inst.instruction |= (imm & 0x00000fff); 7066 inst.instruction |= (imm & 0x0000f000) << 4; 7067 } 7068} 7069 7070static void do_vfp_nsyn_opcode (const char *); 7071 7072static int 7073do_vfp_nsyn_mrs (void) 7074{ 7075 if (inst.operands[0].isvec) 7076 { 7077 if (inst.operands[1].reg != 1) 7078 first_error (_("operand 1 must be FPSCR")); 7079 memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); 7080 memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); 7081 do_vfp_nsyn_opcode ("fmstat"); 7082 } 7083 else if (inst.operands[1].isvec) 7084 do_vfp_nsyn_opcode ("fmrx"); 7085 else 7086 return FAIL; 7087 7088 return SUCCESS; 7089} 7090 7091static int 7092do_vfp_nsyn_msr (void) 7093{ 7094 if (inst.operands[0].isvec) 7095 do_vfp_nsyn_opcode ("fmxr"); 7096 else 7097 return FAIL; 7098 7099 return SUCCESS; 7100} 7101 7102static void 7103do_vfp_vmrs (void) 7104{ 7105 int rt; 7106 7107 /* The destination register can be r0-r14 or APSR_nzcv */ 7108 if (inst.operands[0].reg > 14) 7109 { 7110 inst.error = BAD_PC; 7111 return; 7112 } 7113 7114 /* If the destination is r13 and not in ARM mode then unprefictable */ 7115 if (thumb_mode && inst.operands[0].reg == REG_SP) 7116 { 7117 inst.error = BAD_SP; 7118 return; 7119 } 7120 7121 /* If the destination is APSR_nzcv */ 7122 if (inst.operands[0].isvec && inst.operands[1].reg != 1) 7123 { 7124 inst.error = BAD_VMRS; 7125 return; 7126 } 7127 7128 if (inst.operands[0].isvec) 7129 rt = 15; 7130 else 7131 rt = inst.operands[0].reg; 7132 7133 /* Or in the registers to use */ 7134 inst.instruction |= rt << 12; 7135 inst.instruction |= inst.operands[1].reg << 16; 7136} 7137 7138static void 7139do_vfp_vmsr (void) 7140{ 7141 /* The destination register can be r0-r14 or APSR_nzcv */ 7142 if (inst.operands[1].reg > 14) 7143 { 7144 inst.error = BAD_PC; 7145 return; 7146 } 7147 7148 /* If the destination is r13 and not in ARM mode then unprefictable */ 7149 if (thumb_mode && inst.operands[0].reg == REG_SP) 7150 { 7151 inst.error = BAD_SP; 7152 return; 7153 } 7154 7155 /* Or in the registers to use */ 7156 inst.instruction |= inst.operands[1].reg << 12; 7157 inst.instruction |= inst.operands[0].reg << 16; 7158} 7159 7160static void 7161do_mrs (void) 7162{ 7163 if (do_vfp_nsyn_mrs () == SUCCESS) 7164 return; 7165 7166 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ 7167 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) 7168 != (PSR_c|PSR_f), 7169 _("'CPSR' or 'SPSR' expected")); 7170 inst.instruction |= inst.operands[0].reg << 12; 7171 inst.instruction |= (inst.operands[1].imm & SPSR_BIT); 7172} 7173 7174/* Two possible forms: 7175 "{C|S}PSR_<field>, Rm", 7176 "{C|S}PSR_f, #expression". */ 7177 7178static void 7179do_msr (void) 7180{ 7181 if (do_vfp_nsyn_msr () == SUCCESS) 7182 return; 7183 7184 inst.instruction |= inst.operands[0].imm; 7185 if (inst.operands[1].isreg) 7186 inst.instruction |= inst.operands[1].reg; 7187 else 7188 { 7189 inst.instruction |= INST_IMMEDIATE; 7190 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 7191 inst.reloc.pc_rel = 0; 7192 } 7193} 7194 7195static void 7196do_mul (void) 7197{ 7198 if (!inst.operands[2].present) 7199 inst.operands[2].reg = inst.operands[0].reg; 7200 inst.instruction |= inst.operands[0].reg << 16; 7201 inst.instruction |= inst.operands[1].reg; 7202 inst.instruction |= inst.operands[2].reg << 8; 7203 7204 if (inst.operands[0].reg == inst.operands[1].reg 7205 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) 7206 as_tsktsk (_("Rd and Rm should be different in mul")); 7207} 7208 7209/* Long Multiply Parser 7210 UMULL RdLo, RdHi, Rm, Rs 7211 SMULL RdLo, RdHi, Rm, Rs 7212 UMLAL RdLo, RdHi, Rm, Rs 7213 SMLAL RdLo, RdHi, Rm, Rs. */ 7214 7215static void 7216do_mull (void) 7217{ 7218 inst.instruction |= inst.operands[0].reg << 12; 7219 inst.instruction |= inst.operands[1].reg << 16; 7220 inst.instruction |= inst.operands[2].reg; 7221 inst.instruction |= inst.operands[3].reg << 8; 7222 7223 /* rdhi, rdlo and rm must all be different prior to ARMv6. */ 7224 if (inst.operands[0].reg == inst.operands[1].reg 7225 || ((inst.operands[0].reg == inst.operands[2].reg 7226 || inst.operands[1].reg == inst.operands[2].reg) 7227 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))) 7228 as_tsktsk (_("rdhi, rdlo and rm must all be different")); 7229} 7230 7231static void 7232do_nop (void) 7233{ 7234 if (inst.operands[0].present) 7235 { 7236 /* Architectural NOP hints are CPSR sets with no bits selected. */ 7237 inst.instruction &= 0xf0000000; 7238 inst.instruction |= 0x0320f000 + inst.operands[0].imm; 7239 } 7240} 7241 7242/* ARM V6 Pack Halfword Bottom Top instruction (argument parse). 7243 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} 7244 Condition defaults to COND_ALWAYS. 7245 Error if Rd, Rn or Rm are R15. */ 7246 7247static void 7248do_pkhbt (void) 7249{ 7250 inst.instruction |= inst.operands[0].reg << 12; 7251 inst.instruction |= inst.operands[1].reg << 16; 7252 inst.instruction |= inst.operands[2].reg; 7253 if (inst.operands[3].present) 7254 encode_arm_shift (3); 7255} 7256 7257/* ARM V6 PKHTB (Argument Parse). */ 7258 7259static void 7260do_pkhtb (void) 7261{ 7262 if (!inst.operands[3].present) 7263 { 7264 /* If the shift specifier is omitted, turn the instruction 7265 into pkhbt rd, rm, rn. */ 7266 inst.instruction &= 0xfff00010; 7267 inst.instruction |= inst.operands[0].reg << 12; 7268 inst.instruction |= inst.operands[1].reg; 7269 inst.instruction |= inst.operands[2].reg << 16; 7270 } 7271 else 7272 { 7273 inst.instruction |= inst.operands[0].reg << 12; 7274 inst.instruction |= inst.operands[1].reg << 16; 7275 inst.instruction |= inst.operands[2].reg; 7276 encode_arm_shift (3); 7277 } 7278} 7279 7280/* ARMv5TE: Preload-Cache 7281 7282 PLD <addr_mode> 7283 7284 Syntactically, like LDR with B=1, W=0, L=1. */ 7285 7286static void 7287do_pld (void) 7288{ 7289 constraint (!inst.operands[0].isreg, 7290 _("'[' expected after PLD mnemonic")); 7291 constraint (inst.operands[0].postind, 7292 _("post-indexed expression used in preload instruction")); 7293 constraint (inst.operands[0].writeback, 7294 _("writeback used in preload instruction")); 7295 constraint (!inst.operands[0].preind, 7296 _("unindexed addressing used in preload instruction")); 7297 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); 7298} 7299 7300/* ARMv7: PLI <addr_mode> */ 7301static void 7302do_pli (void) 7303{ 7304 constraint (!inst.operands[0].isreg, 7305 _("'[' expected after PLI mnemonic")); 7306 constraint (inst.operands[0].postind, 7307 _("post-indexed expression used in preload instruction")); 7308 constraint (inst.operands[0].writeback, 7309 _("writeback used in preload instruction")); 7310 constraint (!inst.operands[0].preind, 7311 _("unindexed addressing used in preload instruction")); 7312 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); 7313 inst.instruction &= ~PRE_INDEX; 7314} 7315 7316static void 7317do_push_pop (void) 7318{ 7319 inst.operands[1] = inst.operands[0]; 7320 memset (&inst.operands[0], 0, sizeof inst.operands[0]); 7321 inst.operands[0].isreg = 1; 7322 inst.operands[0].writeback = 1; 7323 inst.operands[0].reg = REG_SP; 7324 do_ldmstm (); 7325} 7326 7327/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the 7328 word at the specified address and the following word 7329 respectively. 7330 Unconditionally executed. 7331 Error if Rn is R15. */ 7332 7333static void 7334do_rfe (void) 7335{ 7336 inst.instruction |= inst.operands[0].reg << 16; 7337 if (inst.operands[0].writeback) 7338 inst.instruction |= WRITE_BACK; 7339} 7340 7341/* ARM V6 ssat (argument parse). */ 7342 7343static void 7344do_ssat (void) 7345{ 7346 inst.instruction |= inst.operands[0].reg << 12; 7347 inst.instruction |= (inst.operands[1].imm - 1) << 16; 7348 inst.instruction |= inst.operands[2].reg; 7349 7350 if (inst.operands[3].present) 7351 encode_arm_shift (3); 7352} 7353 7354/* ARM V6 usat (argument parse). */ 7355 7356static void 7357do_usat (void) 7358{ 7359 inst.instruction |= inst.operands[0].reg << 12; 7360 inst.instruction |= inst.operands[1].imm << 16; 7361 inst.instruction |= inst.operands[2].reg; 7362 7363 if (inst.operands[3].present) 7364 encode_arm_shift (3); 7365} 7366 7367/* ARM V6 ssat16 (argument parse). */ 7368 7369static void 7370do_ssat16 (void) 7371{ 7372 inst.instruction |= inst.operands[0].reg << 12; 7373 inst.instruction |= ((inst.operands[1].imm - 1) << 16); 7374 inst.instruction |= inst.operands[2].reg; 7375} 7376 7377static void 7378do_usat16 (void) 7379{ 7380 inst.instruction |= inst.operands[0].reg << 12; 7381 inst.instruction |= inst.operands[1].imm << 16; 7382 inst.instruction |= inst.operands[2].reg; 7383} 7384 7385/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while 7386 preserving the other bits. 7387 7388 setend <endian_specifier>, where <endian_specifier> is either 7389 BE or LE. */ 7390 7391static void 7392do_setend (void) 7393{ 7394 if (inst.operands[0].imm) 7395 inst.instruction |= 0x200; 7396} 7397 7398static void 7399do_shift (void) 7400{ 7401 unsigned int Rm = (inst.operands[1].present 7402 ? inst.operands[1].reg 7403 : inst.operands[0].reg); 7404 7405 inst.instruction |= inst.operands[0].reg << 12; 7406 inst.instruction |= Rm; 7407 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ 7408 { 7409 inst.instruction |= inst.operands[2].reg << 8; 7410 inst.instruction |= SHIFT_BY_REG; 7411 } 7412 else 7413 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 7414} 7415 7416static void 7417do_smc (void) 7418{ 7419 inst.reloc.type = BFD_RELOC_ARM_SMC; 7420 inst.reloc.pc_rel = 0; 7421} 7422 7423static void 7424do_swi (void) 7425{ 7426 inst.reloc.type = BFD_RELOC_ARM_SWI; 7427 inst.reloc.pc_rel = 0; 7428} 7429 7430/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) 7431 SMLAxy{cond} Rd,Rm,Rs,Rn 7432 SMLAWy{cond} Rd,Rm,Rs,Rn 7433 Error if any register is R15. */ 7434 7435static void 7436do_smla (void) 7437{ 7438 inst.instruction |= inst.operands[0].reg << 16; 7439 inst.instruction |= inst.operands[1].reg; 7440 inst.instruction |= inst.operands[2].reg << 8; 7441 inst.instruction |= inst.operands[3].reg << 12; 7442} 7443 7444/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) 7445 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs 7446 Error if any register is R15. 7447 Warning if Rdlo == Rdhi. */ 7448 7449static void 7450do_smlal (void) 7451{ 7452 inst.instruction |= inst.operands[0].reg << 12; 7453 inst.instruction |= inst.operands[1].reg << 16; 7454 inst.instruction |= inst.operands[2].reg; 7455 inst.instruction |= inst.operands[3].reg << 8; 7456 7457 if (inst.operands[0].reg == inst.operands[1].reg) 7458 as_tsktsk (_("rdhi and rdlo must be different")); 7459} 7460 7461/* ARM V5E (El Segundo) signed-multiply (argument parse) 7462 SMULxy{cond} Rd,Rm,Rs 7463 Error if any register is R15. */ 7464 7465static void 7466do_smul (void) 7467{ 7468 inst.instruction |= inst.operands[0].reg << 16; 7469 inst.instruction |= inst.operands[1].reg; 7470 inst.instruction |= inst.operands[2].reg << 8; 7471} 7472 7473/* ARM V6 srs (argument parse). The variable fields in the encoding are 7474 the same for both ARM and Thumb-2. */ 7475 7476static void 7477do_srs (void) 7478{ 7479 int reg; 7480 7481 if (inst.operands[0].present) 7482 { 7483 reg = inst.operands[0].reg; 7484 constraint (reg != 13, _("SRS base register must be r13")); 7485 } 7486 else 7487 reg = 13; 7488 7489 inst.instruction |= reg << 16; 7490 inst.instruction |= inst.operands[1].imm; 7491 if (inst.operands[0].writeback || inst.operands[1].writeback) 7492 inst.instruction |= WRITE_BACK; 7493} 7494 7495/* ARM V6 strex (argument parse). */ 7496 7497static void 7498do_strex (void) 7499{ 7500 constraint (!inst.operands[2].isreg || !inst.operands[2].preind 7501 || inst.operands[2].postind || inst.operands[2].writeback 7502 || inst.operands[2].immisreg || inst.operands[2].shifted 7503 || inst.operands[2].negative 7504 /* See comment in do_ldrex(). */ 7505 || (inst.operands[2].reg == REG_PC), 7506 BAD_ADDR_MODE); 7507 7508 constraint (inst.operands[0].reg == inst.operands[1].reg 7509 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); 7510 7511 constraint (inst.reloc.exp.X_op != O_constant 7512 || inst.reloc.exp.X_add_number != 0, 7513 _("offset must be zero in ARM encoding")); 7514 7515 inst.instruction |= inst.operands[0].reg << 12; 7516 inst.instruction |= inst.operands[1].reg; 7517 inst.instruction |= inst.operands[2].reg << 16; 7518 inst.reloc.type = BFD_RELOC_UNUSED; 7519} 7520 7521static void 7522do_strexd (void) 7523{ 7524 constraint (inst.operands[1].reg % 2 != 0, 7525 _("even register required")); 7526 constraint (inst.operands[2].present 7527 && inst.operands[2].reg != inst.operands[1].reg + 1, 7528 _("can only store two consecutive registers")); 7529 /* If op 2 were present and equal to PC, this function wouldn't 7530 have been called in the first place. */ 7531 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); 7532 7533 constraint (inst.operands[0].reg == inst.operands[1].reg 7534 || inst.operands[0].reg == inst.operands[1].reg + 1 7535 || inst.operands[0].reg == inst.operands[3].reg, 7536 BAD_OVERLAP); 7537 7538 inst.instruction |= inst.operands[0].reg << 12; 7539 inst.instruction |= inst.operands[1].reg; 7540 inst.instruction |= inst.operands[3].reg << 16; 7541} 7542 7543/* ARM V6 SXTAH extracts a 16-bit value from a register, sign 7544 extends it to 32-bits, and adds the result to a value in another 7545 register. You can specify a rotation by 0, 8, 16, or 24 bits 7546 before extracting the 16-bit value. 7547 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} 7548 Condition defaults to COND_ALWAYS. 7549 Error if any register uses R15. */ 7550 7551static void 7552do_sxtah (void) 7553{ 7554 inst.instruction |= inst.operands[0].reg << 12; 7555 inst.instruction |= inst.operands[1].reg << 16; 7556 inst.instruction |= inst.operands[2].reg; 7557 inst.instruction |= inst.operands[3].imm << 10; 7558} 7559 7560/* ARM V6 SXTH. 7561 7562 SXTH {<cond>} <Rd>, <Rm>{, <rotation>} 7563 Condition defaults to COND_ALWAYS. 7564 Error if any register uses R15. */ 7565 7566static void 7567do_sxth (void) 7568{ 7569 inst.instruction |= inst.operands[0].reg << 12; 7570 inst.instruction |= inst.operands[1].reg; 7571 inst.instruction |= inst.operands[2].imm << 10; 7572} 7573 7574/* VFP instructions. In a logical order: SP variant first, monad 7575 before dyad, arithmetic then move then load/store. */ 7576 7577static void 7578do_vfp_sp_monadic (void) 7579{ 7580 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7581 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); 7582} 7583 7584static void 7585do_vfp_sp_dyadic (void) 7586{ 7587 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7588 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); 7589 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); 7590} 7591 7592static void 7593do_vfp_sp_compare_z (void) 7594{ 7595 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7596} 7597 7598static void 7599do_vfp_dp_sp_cvt (void) 7600{ 7601 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7602 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); 7603} 7604 7605static void 7606do_vfp_sp_dp_cvt (void) 7607{ 7608 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7609 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); 7610} 7611 7612static void 7613do_vfp_reg_from_sp (void) 7614{ 7615 inst.instruction |= inst.operands[0].reg << 12; 7616 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); 7617} 7618 7619static void 7620do_vfp_reg2_from_sp2 (void) 7621{ 7622 constraint (inst.operands[2].imm != 2, 7623 _("only two consecutive VFP SP registers allowed here")); 7624 inst.instruction |= inst.operands[0].reg << 12; 7625 inst.instruction |= inst.operands[1].reg << 16; 7626 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); 7627} 7628 7629static void 7630do_vfp_sp_from_reg (void) 7631{ 7632 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); 7633 inst.instruction |= inst.operands[1].reg << 12; 7634} 7635 7636static void 7637do_vfp_sp2_from_reg2 (void) 7638{ 7639 constraint (inst.operands[0].imm != 2, 7640 _("only two consecutive VFP SP registers allowed here")); 7641 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); 7642 inst.instruction |= inst.operands[1].reg << 12; 7643 inst.instruction |= inst.operands[2].reg << 16; 7644} 7645 7646static void 7647do_vfp_sp_ldst (void) 7648{ 7649 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7650 encode_arm_cp_address (1, FALSE, TRUE, 0); 7651} 7652 7653static void 7654do_vfp_dp_ldst (void) 7655{ 7656 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7657 encode_arm_cp_address (1, FALSE, TRUE, 0); 7658} 7659 7660 7661static void 7662vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) 7663{ 7664 if (inst.operands[0].writeback) 7665 inst.instruction |= WRITE_BACK; 7666 else 7667 constraint (ldstm_type != VFP_LDSTMIA, 7668 _("this addressing mode requires base-register writeback")); 7669 inst.instruction |= inst.operands[0].reg << 16; 7670 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); 7671 inst.instruction |= inst.operands[1].imm; 7672} 7673 7674static void 7675vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) 7676{ 7677 int count; 7678 7679 if (inst.operands[0].writeback) 7680 inst.instruction |= WRITE_BACK; 7681 else 7682 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, 7683 _("this addressing mode requires base-register writeback")); 7684 7685 inst.instruction |= inst.operands[0].reg << 16; 7686 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 7687 7688 count = inst.operands[1].imm << 1; 7689 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) 7690 count += 1; 7691 7692 inst.instruction |= count; 7693} 7694 7695static void 7696do_vfp_sp_ldstmia (void) 7697{ 7698 vfp_sp_ldstm (VFP_LDSTMIA); 7699} 7700 7701static void 7702do_vfp_sp_ldstmdb (void) 7703{ 7704 vfp_sp_ldstm (VFP_LDSTMDB); 7705} 7706 7707static void 7708do_vfp_dp_ldstmia (void) 7709{ 7710 vfp_dp_ldstm (VFP_LDSTMIA); 7711} 7712 7713static void 7714do_vfp_dp_ldstmdb (void) 7715{ 7716 vfp_dp_ldstm (VFP_LDSTMDB); 7717} 7718 7719static void 7720do_vfp_xp_ldstmia (void) 7721{ 7722 vfp_dp_ldstm (VFP_LDSTMIAX); 7723} 7724 7725static void 7726do_vfp_xp_ldstmdb (void) 7727{ 7728 vfp_dp_ldstm (VFP_LDSTMDBX); 7729} 7730 7731static void 7732do_vfp_dp_rd_rm (void) 7733{ 7734 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7735 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); 7736} 7737 7738static void 7739do_vfp_dp_rn_rd (void) 7740{ 7741 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); 7742 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 7743} 7744 7745static void 7746do_vfp_dp_rd_rn (void) 7747{ 7748 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7749 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); 7750} 7751 7752static void 7753do_vfp_dp_rd_rn_rm (void) 7754{ 7755 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7756 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); 7757 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); 7758} 7759 7760static void 7761do_vfp_dp_rd (void) 7762{ 7763 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7764} 7765 7766static void 7767do_vfp_dp_rm_rd_rn (void) 7768{ 7769 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); 7770 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 7771 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); 7772} 7773 7774/* VFPv3 instructions. */ 7775static void 7776do_vfp_sp_const (void) 7777{ 7778 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7779 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; 7780 inst.instruction |= (inst.operands[1].imm & 0x0f); 7781} 7782 7783static void 7784do_vfp_dp_const (void) 7785{ 7786 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7787 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; 7788 inst.instruction |= (inst.operands[1].imm & 0x0f); 7789} 7790 7791static void 7792vfp_conv (int srcsize) 7793{ 7794 unsigned immbits = srcsize - inst.operands[1].imm; 7795 inst.instruction |= (immbits & 1) << 5; 7796 inst.instruction |= (immbits >> 1); 7797} 7798 7799static void 7800do_vfp_sp_conv_16 (void) 7801{ 7802 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7803 vfp_conv (16); 7804} 7805 7806static void 7807do_vfp_dp_conv_16 (void) 7808{ 7809 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7810 vfp_conv (16); 7811} 7812 7813static void 7814do_vfp_sp_conv_32 (void) 7815{ 7816 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7817 vfp_conv (32); 7818} 7819 7820static void 7821do_vfp_dp_conv_32 (void) 7822{ 7823 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7824 vfp_conv (32); 7825} 7826 7827 7828/* FPA instructions. Also in a logical order. */ 7829 7830static void 7831do_fpa_cmp (void) 7832{ 7833 inst.instruction |= inst.operands[0].reg << 16; 7834 inst.instruction |= inst.operands[1].reg; 7835} 7836 7837static void 7838do_fpa_ldmstm (void) 7839{ 7840 inst.instruction |= inst.operands[0].reg << 12; 7841 switch (inst.operands[1].imm) 7842 { 7843 case 1: inst.instruction |= CP_T_X; break; 7844 case 2: inst.instruction |= CP_T_Y; break; 7845 case 3: inst.instruction |= CP_T_Y | CP_T_X; break; 7846 case 4: break; 7847 default: abort (); 7848 } 7849 7850 if (inst.instruction & (PRE_INDEX | INDEX_UP)) 7851 { 7852 /* The instruction specified "ea" or "fd", so we can only accept 7853 [Rn]{!}. The instruction does not really support stacking or 7854 unstacking, so we have to emulate these by setting appropriate 7855 bits and offsets. */ 7856 constraint (inst.reloc.exp.X_op != O_constant 7857 || inst.reloc.exp.X_add_number != 0, 7858 _("this instruction does not support indexing")); 7859 7860 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) 7861 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; 7862 7863 if (!(inst.instruction & INDEX_UP)) 7864 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; 7865 7866 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) 7867 { 7868 inst.operands[2].preind = 0; 7869 inst.operands[2].postind = 1; 7870 } 7871 } 7872 7873 encode_arm_cp_address (2, TRUE, TRUE, 0); 7874} 7875 7876 7877/* iWMMXt instructions: strictly in alphabetical order. */ 7878 7879static void 7880do_iwmmxt_tandorc (void) 7881{ 7882 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); 7883} 7884 7885static void 7886do_iwmmxt_textrc (void) 7887{ 7888 inst.instruction |= inst.operands[0].reg << 12; 7889 inst.instruction |= inst.operands[1].imm; 7890} 7891 7892static void 7893do_iwmmxt_textrm (void) 7894{ 7895 inst.instruction |= inst.operands[0].reg << 12; 7896 inst.instruction |= inst.operands[1].reg << 16; 7897 inst.instruction |= inst.operands[2].imm; 7898} 7899 7900static void 7901do_iwmmxt_tinsr (void) 7902{ 7903 inst.instruction |= inst.operands[0].reg << 16; 7904 inst.instruction |= inst.operands[1].reg << 12; 7905 inst.instruction |= inst.operands[2].imm; 7906} 7907 7908static void 7909do_iwmmxt_tmia (void) 7910{ 7911 inst.instruction |= inst.operands[0].reg << 5; 7912 inst.instruction |= inst.operands[1].reg; 7913 inst.instruction |= inst.operands[2].reg << 12; 7914} 7915 7916static void 7917do_iwmmxt_waligni (void) 7918{ 7919 inst.instruction |= inst.operands[0].reg << 12; 7920 inst.instruction |= inst.operands[1].reg << 16; 7921 inst.instruction |= inst.operands[2].reg; 7922 inst.instruction |= inst.operands[3].imm << 20; 7923} 7924 7925static void 7926do_iwmmxt_wmerge (void) 7927{ 7928 inst.instruction |= inst.operands[0].reg << 12; 7929 inst.instruction |= inst.operands[1].reg << 16; 7930 inst.instruction |= inst.operands[2].reg; 7931 inst.instruction |= inst.operands[3].imm << 21; 7932} 7933 7934static void 7935do_iwmmxt_wmov (void) 7936{ 7937 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ 7938 inst.instruction |= inst.operands[0].reg << 12; 7939 inst.instruction |= inst.operands[1].reg << 16; 7940 inst.instruction |= inst.operands[1].reg; 7941} 7942 7943static void 7944do_iwmmxt_wldstbh (void) 7945{ 7946 int reloc; 7947 inst.instruction |= inst.operands[0].reg << 12; 7948 if (thumb_mode) 7949 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; 7950 else 7951 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; 7952 encode_arm_cp_address (1, TRUE, FALSE, reloc); 7953} 7954 7955static void 7956do_iwmmxt_wldstw (void) 7957{ 7958 /* RIWR_RIWC clears .isreg for a control register. */ 7959 if (!inst.operands[0].isreg) 7960 { 7961 constraint (inst.cond != COND_ALWAYS, BAD_COND); 7962 inst.instruction |= 0xf0000000; 7963 } 7964 7965 inst.instruction |= inst.operands[0].reg << 12; 7966 encode_arm_cp_address (1, TRUE, TRUE, 0); 7967} 7968 7969static void 7970do_iwmmxt_wldstd (void) 7971{ 7972 inst.instruction |= inst.operands[0].reg << 12; 7973 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) 7974 && inst.operands[1].immisreg) 7975 { 7976 inst.instruction &= ~0x1a000ff; 7977 inst.instruction |= (0xf << 28); 7978 if (inst.operands[1].preind) 7979 inst.instruction |= PRE_INDEX; 7980 if (!inst.operands[1].negative) 7981 inst.instruction |= INDEX_UP; 7982 if (inst.operands[1].writeback) 7983 inst.instruction |= WRITE_BACK; 7984 inst.instruction |= inst.operands[1].reg << 16; 7985 inst.instruction |= inst.reloc.exp.X_add_number << 4; 7986 inst.instruction |= inst.operands[1].imm; 7987 } 7988 else 7989 encode_arm_cp_address (1, TRUE, FALSE, 0); 7990} 7991 7992static void 7993do_iwmmxt_wshufh (void) 7994{ 7995 inst.instruction |= inst.operands[0].reg << 12; 7996 inst.instruction |= inst.operands[1].reg << 16; 7997 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); 7998 inst.instruction |= (inst.operands[2].imm & 0x0f); 7999} 8000 8001static void 8002do_iwmmxt_wzero (void) 8003{ 8004 /* WZERO reg is an alias for WANDN reg, reg, reg. */ 8005 inst.instruction |= inst.operands[0].reg; 8006 inst.instruction |= inst.operands[0].reg << 12; 8007 inst.instruction |= inst.operands[0].reg << 16; 8008} 8009 8010static void 8011do_iwmmxt_wrwrwr_or_imm5 (void) 8012{ 8013 if (inst.operands[2].isreg) 8014 do_rd_rn_rm (); 8015 else { 8016 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), 8017 _("immediate operand requires iWMMXt2")); 8018 do_rd_rn (); 8019 if (inst.operands[2].imm == 0) 8020 { 8021 switch ((inst.instruction >> 20) & 0xf) 8022 { 8023 case 4: 8024 case 5: 8025 case 6: 8026 case 7: 8027 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ 8028 inst.operands[2].imm = 16; 8029 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); 8030 break; 8031 case 8: 8032 case 9: 8033 case 10: 8034 case 11: 8035 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ 8036 inst.operands[2].imm = 32; 8037 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); 8038 break; 8039 case 12: 8040 case 13: 8041 case 14: 8042 case 15: 8043 { 8044 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ 8045 unsigned long wrn; 8046 wrn = (inst.instruction >> 16) & 0xf; 8047 inst.instruction &= 0xff0fff0f; 8048 inst.instruction |= wrn; 8049 /* Bail out here; the instruction is now assembled. */ 8050 return; 8051 } 8052 } 8053 } 8054 /* Map 32 -> 0, etc. */ 8055 inst.operands[2].imm &= 0x1f; 8056 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); 8057 } 8058} 8059 8060/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register 8061 operations first, then control, shift, and load/store. */ 8062 8063/* Insns like "foo X,Y,Z". */ 8064 8065static void 8066do_mav_triple (void) 8067{ 8068 inst.instruction |= inst.operands[0].reg << 16; 8069 inst.instruction |= inst.operands[1].reg; 8070 inst.instruction |= inst.operands[2].reg << 12; 8071} 8072 8073/* Insns like "foo W,X,Y,Z". 8074 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ 8075 8076static void 8077do_mav_quad (void) 8078{ 8079 inst.instruction |= inst.operands[0].reg << 5; 8080 inst.instruction |= inst.operands[1].reg << 12; 8081 inst.instruction |= inst.operands[2].reg << 16; 8082 inst.instruction |= inst.operands[3].reg; 8083} 8084 8085/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ 8086static void 8087do_mav_dspsc (void) 8088{ 8089 inst.instruction |= inst.operands[1].reg << 12; 8090} 8091 8092/* Maverick shift immediate instructions. 8093 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. 8094 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ 8095 8096static void 8097do_mav_shift (void) 8098{ 8099 int imm = inst.operands[2].imm; 8100 8101 inst.instruction |= inst.operands[0].reg << 12; 8102 inst.instruction |= inst.operands[1].reg << 16; 8103 8104 /* Bits 0-3 of the insn should have bits 0-3 of the immediate. 8105 Bits 5-7 of the insn should have bits 4-6 of the immediate. 8106 Bit 4 should be 0. */ 8107 imm = (imm & 0xf) | ((imm & 0x70) << 1); 8108 8109 inst.instruction |= imm; 8110} 8111 8112/* XScale instructions. Also sorted arithmetic before move. */ 8113 8114/* Xscale multiply-accumulate (argument parse) 8115 MIAcc acc0,Rm,Rs 8116 MIAPHcc acc0,Rm,Rs 8117 MIAxycc acc0,Rm,Rs. */ 8118 8119static void 8120do_xsc_mia (void) 8121{ 8122 inst.instruction |= inst.operands[1].reg; 8123 inst.instruction |= inst.operands[2].reg << 12; 8124} 8125 8126/* Xscale move-accumulator-register (argument parse) 8127 8128 MARcc acc0,RdLo,RdHi. */ 8129 8130static void 8131do_xsc_mar (void) 8132{ 8133 inst.instruction |= inst.operands[1].reg << 12; 8134 inst.instruction |= inst.operands[2].reg << 16; 8135} 8136 8137/* Xscale move-register-accumulator (argument parse) 8138 8139 MRAcc RdLo,RdHi,acc0. */ 8140 8141static void 8142do_xsc_mra (void) 8143{ 8144 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); 8145 inst.instruction |= inst.operands[0].reg << 12; 8146 inst.instruction |= inst.operands[1].reg << 16; 8147} 8148 8149/* Encoding functions relevant only to Thumb. */ 8150 8151/* inst.operands[i] is a shifted-register operand; encode 8152 it into inst.instruction in the format used by Thumb32. */ 8153 8154static void 8155encode_thumb32_shifted_operand (int i) 8156{ 8157 unsigned int value = inst.reloc.exp.X_add_number; 8158 unsigned int shift = inst.operands[i].shift_kind; 8159 8160 constraint (inst.operands[i].immisreg, 8161 _("shift by register not allowed in thumb mode")); 8162 inst.instruction |= inst.operands[i].reg; 8163 if (shift == SHIFT_RRX) 8164 inst.instruction |= SHIFT_ROR << 4; 8165 else 8166 { 8167 constraint (inst.reloc.exp.X_op != O_constant, 8168 _("expression too complex")); 8169 8170 constraint (value > 32 8171 || (value == 32 && (shift == SHIFT_LSL 8172 || shift == SHIFT_ROR)), 8173 _("shift expression is too large")); 8174 8175 if (value == 0) 8176 shift = SHIFT_LSL; 8177 else if (value == 32) 8178 value = 0; 8179 8180 inst.instruction |= shift << 4; 8181 inst.instruction |= (value & 0x1c) << 10; 8182 inst.instruction |= (value & 0x03) << 6; 8183 } 8184} 8185 8186 8187/* inst.operands[i] was set up by parse_address. Encode it into a 8188 Thumb32 format load or store instruction. Reject forms that cannot 8189 be used with such instructions. If is_t is true, reject forms that 8190 cannot be used with a T instruction; if is_d is true, reject forms 8191 that cannot be used with a D instruction. */ 8192 8193static void 8194encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) 8195{ 8196 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); 8197 8198 constraint (!inst.operands[i].isreg, 8199 _("Instruction does not support =N addresses")); 8200 8201 inst.instruction |= inst.operands[i].reg << 16; 8202 if (inst.operands[i].immisreg) 8203 { 8204 constraint (is_pc, _("cannot use register index with PC-relative addressing")); 8205 constraint (is_t || is_d, _("cannot use register index with this instruction")); 8206 constraint (inst.operands[i].negative, 8207 _("Thumb does not support negative register indexing")); 8208 constraint (inst.operands[i].postind, 8209 _("Thumb does not support register post-indexing")); 8210 constraint (inst.operands[i].writeback, 8211 _("Thumb does not support register indexing with writeback")); 8212 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, 8213 _("Thumb supports only LSL in shifted register indexing")); 8214 8215 inst.instruction |= inst.operands[i].imm; 8216 if (inst.operands[i].shifted) 8217 { 8218 constraint (inst.reloc.exp.X_op != O_constant, 8219 _("expression too complex")); 8220 constraint (inst.reloc.exp.X_add_number < 0 8221 || inst.reloc.exp.X_add_number > 3, 8222 _("shift out of range")); 8223 inst.instruction |= inst.reloc.exp.X_add_number << 4; 8224 } 8225 inst.reloc.type = BFD_RELOC_UNUSED; 8226 } 8227 else if (inst.operands[i].preind) 8228 { 8229 constraint (is_pc && inst.operands[i].writeback, 8230 _("cannot use writeback with PC-relative addressing")); 8231 constraint (is_t && inst.operands[i].writeback, 8232 _("cannot use writeback with this instruction")); 8233 8234 if (is_d) 8235 { 8236 inst.instruction |= 0x01000000; 8237 if (inst.operands[i].writeback) 8238 inst.instruction |= 0x00200000; 8239 } 8240 else 8241 { 8242 inst.instruction |= 0x00000c00; 8243 if (inst.operands[i].writeback) 8244 inst.instruction |= 0x00000100; 8245 } 8246 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; 8247 } 8248 else if (inst.operands[i].postind) 8249 { 8250 assert (inst.operands[i].writeback); 8251 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); 8252 constraint (is_t, _("cannot use post-indexing with this instruction")); 8253 8254 if (is_d) 8255 inst.instruction |= 0x00200000; 8256 else 8257 inst.instruction |= 0x00000900; 8258 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; 8259 } 8260 else /* unindexed - only for coprocessor */ 8261 inst.error = _("instruction does not accept unindexed addressing"); 8262} 8263 8264/* Table of Thumb instructions which exist in both 16- and 32-bit 8265 encodings (the latter only in post-V6T2 cores). The index is the 8266 value used in the insns table below. When there is more than one 8267 possible 16-bit encoding for the instruction, this table always 8268 holds variant (1). 8269 Also contains several pseudo-instructions used during relaxation. */ 8270#define T16_32_TAB \ 8271 X(adc, 4140, eb400000), \ 8272 X(adcs, 4140, eb500000), \ 8273 X(add, 1c00, eb000000), \ 8274 X(adds, 1c00, eb100000), \ 8275 X(addi, 0000, f1000000), \ 8276 X(addis, 0000, f1100000), \ 8277 X(add_pc,000f, f20f0000), \ 8278 X(add_sp,000d, f10d0000), \ 8279 X(adr, 000f, f20f0000), \ 8280 X(and, 4000, ea000000), \ 8281 X(ands, 4000, ea100000), \ 8282 X(asr, 1000, fa40f000), \ 8283 X(asrs, 1000, fa50f000), \ 8284 X(b, e000, f000b000), \ 8285 X(bcond, d000, f0008000), \ 8286 X(bic, 4380, ea200000), \ 8287 X(bics, 4380, ea300000), \ 8288 X(cmn, 42c0, eb100f00), \ 8289 X(cmp, 2800, ebb00f00), \ 8290 X(cpsie, b660, f3af8400), \ 8291 X(cpsid, b670, f3af8600), \ 8292 X(cpy, 4600, ea4f0000), \ 8293 X(dec_sp,80dd, f1ad0d00), \ 8294 X(eor, 4040, ea800000), \ 8295 X(eors, 4040, ea900000), \ 8296 X(inc_sp,00dd, f10d0d00), \ 8297 X(ldmia, c800, e8900000), \ 8298 X(ldr, 6800, f8500000), \ 8299 X(ldrb, 7800, f8100000), \ 8300 X(ldrh, 8800, f8300000), \ 8301 X(ldrsb, 5600, f9100000), \ 8302 X(ldrsh, 5e00, f9300000), \ 8303 X(ldr_pc,4800, f85f0000), \ 8304 X(ldr_pc2,4800, f85f0000), \ 8305 X(ldr_sp,9800, f85d0000), \ 8306 X(lsl, 0000, fa00f000), \ 8307 X(lsls, 0000, fa10f000), \ 8308 X(lsr, 0800, fa20f000), \ 8309 X(lsrs, 0800, fa30f000), \ 8310 X(mov, 2000, ea4f0000), \ 8311 X(movs, 2000, ea5f0000), \ 8312 X(mul, 4340, fb00f000), \ 8313 X(muls, 4340, ffffffff), /* no 32b muls */ \ 8314 X(mvn, 43c0, ea6f0000), \ 8315 X(mvns, 43c0, ea7f0000), \ 8316 X(neg, 4240, f1c00000), /* rsb #0 */ \ 8317 X(negs, 4240, f1d00000), /* rsbs #0 */ \ 8318 X(orr, 4300, ea400000), \ 8319 X(orrs, 4300, ea500000), \ 8320 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \ 8321 X(push, b400, e92d0000), /* stmdb sp!,... */ \ 8322 X(rev, ba00, fa90f080), \ 8323 X(rev16, ba40, fa90f090), \ 8324 X(revsh, bac0, fa90f0b0), \ 8325 X(ror, 41c0, fa60f000), \ 8326 X(rors, 41c0, fa70f000), \ 8327 X(sbc, 4180, eb600000), \ 8328 X(sbcs, 4180, eb700000), \ 8329 X(stmia, c000, e8800000), \ 8330 X(str, 6000, f8400000), \ 8331 X(strb, 7000, f8000000), \ 8332 X(strh, 8000, f8200000), \ 8333 X(str_sp,9000, f84d0000), \ 8334 X(sub, 1e00, eba00000), \ 8335 X(subs, 1e00, ebb00000), \ 8336 X(subi, 8000, f1a00000), \ 8337 X(subis, 8000, f1b00000), \ 8338 X(sxtb, b240, fa4ff080), \ 8339 X(sxth, b200, fa0ff080), \ 8340 X(tst, 4200, ea100f00), \ 8341 X(uxtb, b2c0, fa5ff080), \ 8342 X(uxth, b280, fa1ff080), \ 8343 X(nop, bf00, f3af8000), \ 8344 X(yield, bf10, f3af8001), \ 8345 X(wfe, bf20, f3af8002), \ 8346 X(wfi, bf30, f3af8003), \ 8347 X(sev, bf40, f3af9004), /* typo, 8004? */ 8348 8349/* To catch errors in encoding functions, the codes are all offset by 8350 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined 8351 as 16-bit instructions. */ 8352#define X(a,b,c) T_MNEM_##a 8353enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; 8354#undef X 8355 8356#define X(a,b,c) 0x##b 8357static const unsigned short thumb_op16[] = { T16_32_TAB }; 8358#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) 8359#undef X 8360 8361#define X(a,b,c) 0x##c 8362static const unsigned int thumb_op32[] = { T16_32_TAB }; 8363#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) 8364#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) 8365#undef X 8366#undef T16_32_TAB 8367 8368/* Thumb instruction encoders, in alphabetical order. */ 8369 8370/* ADDW or SUBW. */ 8371static void 8372do_t_add_sub_w (void) 8373{ 8374 int Rd, Rn; 8375 8376 Rd = inst.operands[0].reg; 8377 Rn = inst.operands[1].reg; 8378 8379 constraint (Rd == 15, _("PC not allowed as destination")); 8380 inst.instruction |= (Rn << 16) | (Rd << 8); 8381 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; 8382} 8383 8384/* Parse an add or subtract instruction. We get here with inst.instruction 8385 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ 8386 8387static void 8388do_t_add_sub (void) 8389{ 8390 int Rd, Rs, Rn; 8391 8392 Rd = inst.operands[0].reg; 8393 Rs = (inst.operands[1].present 8394 ? inst.operands[1].reg /* Rd, Rs, foo */ 8395 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 8396 8397 if (unified_syntax) 8398 { 8399 bfd_boolean flags; 8400 bfd_boolean narrow; 8401 int opcode; 8402 8403 flags = (inst.instruction == T_MNEM_adds 8404 || inst.instruction == T_MNEM_subs); 8405 if (flags) 8406 narrow = (current_it_mask == 0); 8407 else 8408 narrow = (current_it_mask != 0); 8409 if (!inst.operands[2].isreg) 8410 { 8411 int add; 8412 8413 add = (inst.instruction == T_MNEM_add 8414 || inst.instruction == T_MNEM_adds); 8415 opcode = 0; 8416 if (inst.size_req != 4) 8417 { 8418 /* Attempt to use a narrow opcode, with relaxation if 8419 appropriate. */ 8420 if (Rd == REG_SP && Rs == REG_SP && !flags) 8421 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; 8422 else if (Rd <= 7 && Rs == REG_SP && add && !flags) 8423 opcode = T_MNEM_add_sp; 8424 else if (Rd <= 7 && Rs == REG_PC && add && !flags) 8425 opcode = T_MNEM_add_pc; 8426 else if (Rd <= 7 && Rs <= 7 && narrow) 8427 { 8428 if (flags) 8429 opcode = add ? T_MNEM_addis : T_MNEM_subis; 8430 else 8431 opcode = add ? T_MNEM_addi : T_MNEM_subi; 8432 } 8433 if (opcode) 8434 { 8435 inst.instruction = THUMB_OP16(opcode); 8436 inst.instruction |= (Rd << 4) | Rs; 8437 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 8438 if (inst.size_req != 2) 8439 inst.relax = opcode; 8440 } 8441 else 8442 constraint (inst.size_req == 2, BAD_HIREG); 8443 } 8444 if (inst.size_req == 4 8445 || (inst.size_req != 2 && !opcode)) 8446 { 8447 if (Rd == REG_PC) 8448 { 8449 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, 8450 _("only SUBS PC, LR, #const allowed")); 8451 constraint (inst.reloc.exp.X_op != O_constant, 8452 _("expression too complex")); 8453 constraint (inst.reloc.exp.X_add_number < 0 8454 || inst.reloc.exp.X_add_number > 0xff, 8455 _("immediate value out of range")); 8456 inst.instruction = T2_SUBS_PC_LR 8457 | inst.reloc.exp.X_add_number; 8458 inst.reloc.type = BFD_RELOC_UNUSED; 8459 return; 8460 } 8461 else if (Rs == REG_PC) 8462 { 8463 /* Always use addw/subw. */ 8464 inst.instruction = add ? 0xf20f0000 : 0xf2af0000; 8465 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; 8466 } 8467 else 8468 { 8469 inst.instruction = THUMB_OP32 (inst.instruction); 8470 inst.instruction = (inst.instruction & 0xe1ffffff) 8471 | 0x10000000; 8472 if (flags) 8473 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 8474 else 8475 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; 8476 } 8477 inst.instruction |= Rd << 8; 8478 inst.instruction |= Rs << 16; 8479 } 8480 } 8481 else 8482 { 8483 Rn = inst.operands[2].reg; 8484 /* See if we can do this with a 16-bit instruction. */ 8485 if (!inst.operands[2].shifted && inst.size_req != 4) 8486 { 8487 if (Rd > 7 || Rs > 7 || Rn > 7) 8488 narrow = FALSE; 8489 8490 if (narrow) 8491 { 8492 inst.instruction = ((inst.instruction == T_MNEM_adds 8493 || inst.instruction == T_MNEM_add) 8494 ? T_OPCODE_ADD_R3 8495 : T_OPCODE_SUB_R3); 8496 inst.instruction |= Rd | (Rs << 3) | (Rn << 6); 8497 return; 8498 } 8499 8500 if (inst.instruction == T_MNEM_add) 8501 { 8502 if (Rd == Rs) 8503 { 8504 inst.instruction = T_OPCODE_ADD_HI; 8505 inst.instruction |= (Rd & 8) << 4; 8506 inst.instruction |= (Rd & 7); 8507 inst.instruction |= Rn << 3; 8508 return; 8509 } 8510 /* ... because addition is commutative! */ 8511 else if (Rd == Rn) 8512 { 8513 inst.instruction = T_OPCODE_ADD_HI; 8514 inst.instruction |= (Rd & 8) << 4; 8515 inst.instruction |= (Rd & 7); 8516 inst.instruction |= Rs << 3; 8517 return; 8518 } 8519 } 8520 } 8521 /* If we get here, it can't be done in 16 bits. */ 8522 constraint (inst.operands[2].shifted && inst.operands[2].immisreg, 8523 _("shift must be constant")); 8524 inst.instruction = THUMB_OP32 (inst.instruction); 8525 inst.instruction |= Rd << 8; 8526 inst.instruction |= Rs << 16; 8527 encode_thumb32_shifted_operand (2); 8528 } 8529 } 8530 else 8531 { 8532 constraint (inst.instruction == T_MNEM_adds 8533 || inst.instruction == T_MNEM_subs, 8534 BAD_THUMB32); 8535 8536 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ 8537 { 8538 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) 8539 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), 8540 BAD_HIREG); 8541 8542 inst.instruction = (inst.instruction == T_MNEM_add 8543 ? 0x0000 : 0x8000); 8544 inst.instruction |= (Rd << 4) | Rs; 8545 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 8546 return; 8547 } 8548 8549 Rn = inst.operands[2].reg; 8550 constraint (inst.operands[2].shifted, _("unshifted register required")); 8551 8552 /* We now have Rd, Rs, and Rn set to registers. */ 8553 if (Rd > 7 || Rs > 7 || Rn > 7) 8554 { 8555 /* Can't do this for SUB. */ 8556 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); 8557 inst.instruction = T_OPCODE_ADD_HI; 8558 inst.instruction |= (Rd & 8) << 4; 8559 inst.instruction |= (Rd & 7); 8560 if (Rs == Rd) 8561 inst.instruction |= Rn << 3; 8562 else if (Rn == Rd) 8563 inst.instruction |= Rs << 3; 8564 else 8565 constraint (1, _("dest must overlap one source register")); 8566 } 8567 else 8568 { 8569 inst.instruction = (inst.instruction == T_MNEM_add 8570 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); 8571 inst.instruction |= Rd | (Rs << 3) | (Rn << 6); 8572 } 8573 } 8574} 8575 8576static void 8577do_t_adr (void) 8578{ 8579 if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7) 8580 { 8581 /* Defer to section relaxation. */ 8582 inst.relax = inst.instruction; 8583 inst.instruction = THUMB_OP16 (inst.instruction); 8584 inst.instruction |= inst.operands[0].reg << 4; 8585 } 8586 else if (unified_syntax && inst.size_req != 2) 8587 { 8588 /* Generate a 32-bit opcode. */ 8589 inst.instruction = THUMB_OP32 (inst.instruction); 8590 inst.instruction |= inst.operands[0].reg << 8; 8591 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; 8592 inst.reloc.pc_rel = 1; 8593 } 8594 else 8595 { 8596 /* Generate a 16-bit opcode. */ 8597 inst.instruction = THUMB_OP16 (inst.instruction); 8598 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 8599 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ 8600 inst.reloc.pc_rel = 1; 8601 8602 inst.instruction |= inst.operands[0].reg << 4; 8603 } 8604} 8605 8606/* Arithmetic instructions for which there is just one 16-bit 8607 instruction encoding, and it allows only two low registers. 8608 For maximal compatibility with ARM syntax, we allow three register 8609 operands even when Thumb-32 instructions are not available, as long 8610 as the first two are identical. For instance, both "sbc r0,r1" and 8611 "sbc r0,r0,r1" are allowed. */ 8612static void 8613do_t_arit3 (void) 8614{ 8615 int Rd, Rs, Rn; 8616 8617 Rd = inst.operands[0].reg; 8618 Rs = (inst.operands[1].present 8619 ? inst.operands[1].reg /* Rd, Rs, foo */ 8620 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 8621 Rn = inst.operands[2].reg; 8622 8623 if (unified_syntax) 8624 { 8625 if (!inst.operands[2].isreg) 8626 { 8627 /* For an immediate, we always generate a 32-bit opcode; 8628 section relaxation will shrink it later if possible. */ 8629 inst.instruction = THUMB_OP32 (inst.instruction); 8630 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 8631 inst.instruction |= Rd << 8; 8632 inst.instruction |= Rs << 16; 8633 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 8634 } 8635 else 8636 { 8637 bfd_boolean narrow; 8638 8639 /* See if we can do this with a 16-bit instruction. */ 8640 if (THUMB_SETS_FLAGS (inst.instruction)) 8641 narrow = current_it_mask == 0; 8642 else 8643 narrow = current_it_mask != 0; 8644 8645 if (Rd > 7 || Rn > 7 || Rs > 7) 8646 narrow = FALSE; 8647 if (inst.operands[2].shifted) 8648 narrow = FALSE; 8649 if (inst.size_req == 4) 8650 narrow = FALSE; 8651 8652 if (narrow 8653 && Rd == Rs) 8654 { 8655 inst.instruction = THUMB_OP16 (inst.instruction); 8656 inst.instruction |= Rd; 8657 inst.instruction |= Rn << 3; 8658 return; 8659 } 8660 8661 /* If we get here, it can't be done in 16 bits. */ 8662 constraint (inst.operands[2].shifted 8663 && inst.operands[2].immisreg, 8664 _("shift must be constant")); 8665 inst.instruction = THUMB_OP32 (inst.instruction); 8666 inst.instruction |= Rd << 8; 8667 inst.instruction |= Rs << 16; 8668 encode_thumb32_shifted_operand (2); 8669 } 8670 } 8671 else 8672 { 8673 /* On its face this is a lie - the instruction does set the 8674 flags. However, the only supported mnemonic in this mode 8675 says it doesn't. */ 8676 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 8677 8678 constraint (!inst.operands[2].isreg || inst.operands[2].shifted, 8679 _("unshifted register required")); 8680 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); 8681 constraint (Rd != Rs, 8682 _("dest and source1 must be the same register")); 8683 8684 inst.instruction = THUMB_OP16 (inst.instruction); 8685 inst.instruction |= Rd; 8686 inst.instruction |= Rn << 3; 8687 } 8688} 8689 8690/* Similarly, but for instructions where the arithmetic operation is 8691 commutative, so we can allow either of them to be different from 8692 the destination operand in a 16-bit instruction. For instance, all 8693 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are 8694 accepted. */ 8695static void 8696do_t_arit3c (void) 8697{ 8698 int Rd, Rs, Rn; 8699 8700 Rd = inst.operands[0].reg; 8701 Rs = (inst.operands[1].present 8702 ? inst.operands[1].reg /* Rd, Rs, foo */ 8703 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 8704 Rn = inst.operands[2].reg; 8705 8706 if (unified_syntax) 8707 { 8708 if (!inst.operands[2].isreg) 8709 { 8710 /* For an immediate, we always generate a 32-bit opcode; 8711 section relaxation will shrink it later if possible. */ 8712 inst.instruction = THUMB_OP32 (inst.instruction); 8713 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 8714 inst.instruction |= Rd << 8; 8715 inst.instruction |= Rs << 16; 8716 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 8717 } 8718 else 8719 { 8720 bfd_boolean narrow; 8721 8722 /* See if we can do this with a 16-bit instruction. */ 8723 if (THUMB_SETS_FLAGS (inst.instruction)) 8724 narrow = current_it_mask == 0; 8725 else 8726 narrow = current_it_mask != 0; 8727 8728 if (Rd > 7 || Rn > 7 || Rs > 7) 8729 narrow = FALSE; 8730 if (inst.operands[2].shifted) 8731 narrow = FALSE; 8732 if (inst.size_req == 4) 8733 narrow = FALSE; 8734 8735 if (narrow) 8736 { 8737 if (Rd == Rs) 8738 { 8739 inst.instruction = THUMB_OP16 (inst.instruction); 8740 inst.instruction |= Rd; 8741 inst.instruction |= Rn << 3; 8742 return; 8743 } 8744 if (Rd == Rn) 8745 { 8746 inst.instruction = THUMB_OP16 (inst.instruction); 8747 inst.instruction |= Rd; 8748 inst.instruction |= Rs << 3; 8749 return; 8750 } 8751 } 8752 8753 /* If we get here, it can't be done in 16 bits. */ 8754 constraint (inst.operands[2].shifted 8755 && inst.operands[2].immisreg, 8756 _("shift must be constant")); 8757 inst.instruction = THUMB_OP32 (inst.instruction); 8758 inst.instruction |= Rd << 8; 8759 inst.instruction |= Rs << 16; 8760 encode_thumb32_shifted_operand (2); 8761 } 8762 } 8763 else 8764 { 8765 /* On its face this is a lie - the instruction does set the 8766 flags. However, the only supported mnemonic in this mode 8767 says it doesn't. */ 8768 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 8769 8770 constraint (!inst.operands[2].isreg || inst.operands[2].shifted, 8771 _("unshifted register required")); 8772 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); 8773 8774 inst.instruction = THUMB_OP16 (inst.instruction); 8775 inst.instruction |= Rd; 8776 8777 if (Rd == Rs) 8778 inst.instruction |= Rn << 3; 8779 else if (Rd == Rn) 8780 inst.instruction |= Rs << 3; 8781 else 8782 constraint (1, _("dest must overlap one source register")); 8783 } 8784} 8785 8786static void 8787do_t_barrier (void) 8788{ 8789 if (inst.operands[0].present) 8790 { 8791 constraint ((inst.instruction & 0xf0) != 0x40 8792 && inst.operands[0].imm != 0xf, 8793 "bad barrier type"); 8794 inst.instruction |= inst.operands[0].imm; 8795 } 8796 else 8797 inst.instruction |= 0xf; 8798} 8799 8800static void 8801do_t_bfc (void) 8802{ 8803 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; 8804 constraint (msb > 32, _("bit-field extends past end of register")); 8805 /* The instruction encoding stores the LSB and MSB, 8806 not the LSB and width. */ 8807 inst.instruction |= inst.operands[0].reg << 8; 8808 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; 8809 inst.instruction |= (inst.operands[1].imm & 0x03) << 6; 8810 inst.instruction |= msb - 1; 8811} 8812 8813static void 8814do_t_bfi (void) 8815{ 8816 unsigned int msb; 8817 8818 /* #0 in second position is alternative syntax for bfc, which is 8819 the same instruction but with REG_PC in the Rm field. */ 8820 if (!inst.operands[1].isreg) 8821 inst.operands[1].reg = REG_PC; 8822 8823 msb = inst.operands[2].imm + inst.operands[3].imm; 8824 constraint (msb > 32, _("bit-field extends past end of register")); 8825 /* The instruction encoding stores the LSB and MSB, 8826 not the LSB and width. */ 8827 inst.instruction |= inst.operands[0].reg << 8; 8828 inst.instruction |= inst.operands[1].reg << 16; 8829 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; 8830 inst.instruction |= (inst.operands[2].imm & 0x03) << 6; 8831 inst.instruction |= msb - 1; 8832} 8833 8834static void 8835do_t_bfx (void) 8836{ 8837 constraint (inst.operands[2].imm + inst.operands[3].imm > 32, 8838 _("bit-field extends past end of register")); 8839 inst.instruction |= inst.operands[0].reg << 8; 8840 inst.instruction |= inst.operands[1].reg << 16; 8841 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; 8842 inst.instruction |= (inst.operands[2].imm & 0x03) << 6; 8843 inst.instruction |= inst.operands[3].imm - 1; 8844} 8845 8846/* ARM V5 Thumb BLX (argument parse) 8847 BLX <target_addr> which is BLX(1) 8848 BLX <Rm> which is BLX(2) 8849 Unfortunately, there are two different opcodes for this mnemonic. 8850 So, the insns[].value is not used, and the code here zaps values 8851 into inst.instruction. 8852 8853 ??? How to take advantage of the additional two bits of displacement 8854 available in Thumb32 mode? Need new relocation? */ 8855 8856static void 8857do_t_blx (void) 8858{ 8859 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 8860 if (inst.operands[0].isreg) 8861 /* We have a register, so this is BLX(2). */ 8862 inst.instruction |= inst.operands[0].reg << 3; 8863 else 8864 { 8865 /* No register. This must be BLX(1). */ 8866 inst.instruction = 0xf000e800; 8867#ifdef OBJ_ELF 8868 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 8869 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; 8870 else 8871#endif 8872 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX; 8873 inst.reloc.pc_rel = 1; 8874 } 8875} 8876 8877static void 8878do_t_branch (void) 8879{ 8880 int opcode; 8881 int cond; 8882 8883 if (current_it_mask) 8884 { 8885 /* Conditional branches inside IT blocks are encoded as unconditional 8886 branches. */ 8887 cond = COND_ALWAYS; 8888 /* A branch must be the last instruction in an IT block. */ 8889 constraint (current_it_mask != 0x10, BAD_BRANCH); 8890 } 8891 else 8892 cond = inst.cond; 8893 8894 if (cond != COND_ALWAYS) 8895 opcode = T_MNEM_bcond; 8896 else 8897 opcode = inst.instruction; 8898 8899 if (unified_syntax && inst.size_req == 4) 8900 { 8901 inst.instruction = THUMB_OP32(opcode); 8902 if (cond == COND_ALWAYS) 8903 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25; 8904 else 8905 { 8906 assert (cond != 0xF); 8907 inst.instruction |= cond << 22; 8908 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20; 8909 } 8910 } 8911 else 8912 { 8913 inst.instruction = THUMB_OP16(opcode); 8914 if (cond == COND_ALWAYS) 8915 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12; 8916 else 8917 { 8918 inst.instruction |= cond << 8; 8919 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9; 8920 } 8921 /* Allow section relaxation. */ 8922 if (unified_syntax && inst.size_req != 2) 8923 inst.relax = opcode; 8924 } 8925 8926 inst.reloc.pc_rel = 1; 8927} 8928 8929static void 8930do_t_bkpt (void) 8931{ 8932 constraint (inst.cond != COND_ALWAYS, 8933 _("instruction is always unconditional")); 8934 if (inst.operands[0].present) 8935 { 8936 constraint (inst.operands[0].imm > 255, 8937 _("immediate value out of range")); 8938 inst.instruction |= inst.operands[0].imm; 8939 } 8940} 8941 8942static void 8943do_t_branch23 (void) 8944{ 8945 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 8946 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; 8947 inst.reloc.pc_rel = 1; 8948 8949 /* If the destination of the branch is a defined symbol which does not have 8950 the THUMB_FUNC attribute, then we must be calling a function which has 8951 the (interfacearm) attribute. We look for the Thumb entry point to that 8952 function and change the branch to refer to that function instead. */ 8953 if ( inst.reloc.exp.X_op == O_symbol 8954 && inst.reloc.exp.X_add_symbol != NULL 8955 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) 8956 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) 8957 inst.reloc.exp.X_add_symbol = 8958 find_real_start (inst.reloc.exp.X_add_symbol); 8959} 8960 8961static void 8962do_t_bx (void) 8963{ 8964 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 8965 inst.instruction |= inst.operands[0].reg << 3; 8966 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc 8967 should cause the alignment to be checked once it is known. This is 8968 because BX PC only works if the instruction is word aligned. */ 8969} 8970 8971static void 8972do_t_bxj (void) 8973{ 8974 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 8975 if (inst.operands[0].reg == REG_PC) 8976 as_tsktsk (_("use of r15 in bxj is not really useful")); 8977 8978 inst.instruction |= inst.operands[0].reg << 16; 8979} 8980 8981static void 8982do_t_clz (void) 8983{ 8984 inst.instruction |= inst.operands[0].reg << 8; 8985 inst.instruction |= inst.operands[1].reg << 16; 8986 inst.instruction |= inst.operands[1].reg; 8987} 8988 8989static void 8990do_t_cps (void) 8991{ 8992 constraint (current_it_mask, BAD_NOT_IT); 8993 inst.instruction |= inst.operands[0].imm; 8994} 8995 8996static void 8997do_t_cpsi (void) 8998{ 8999 constraint (current_it_mask, BAD_NOT_IT); 9000 if (unified_syntax 9001 && (inst.operands[1].present || inst.size_req == 4) 9002 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) 9003 { 9004 unsigned int imod = (inst.instruction & 0x0030) >> 4; 9005 inst.instruction = 0xf3af8000; 9006 inst.instruction |= imod << 9; 9007 inst.instruction |= inst.operands[0].imm << 5; 9008 if (inst.operands[1].present) 9009 inst.instruction |= 0x100 | inst.operands[1].imm; 9010 } 9011 else 9012 { 9013 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) 9014 && (inst.operands[0].imm & 4), 9015 _("selected processor does not support 'A' form " 9016 "of this instruction")); 9017 constraint (inst.operands[1].present || inst.size_req == 4, 9018 _("Thumb does not support the 2-argument " 9019 "form of this instruction")); 9020 inst.instruction |= inst.operands[0].imm; 9021 } 9022} 9023 9024/* THUMB CPY instruction (argument parse). */ 9025 9026static void 9027do_t_cpy (void) 9028{ 9029 if (inst.size_req == 4) 9030 { 9031 inst.instruction = THUMB_OP32 (T_MNEM_mov); 9032 inst.instruction |= inst.operands[0].reg << 8; 9033 inst.instruction |= inst.operands[1].reg; 9034 } 9035 else 9036 { 9037 inst.instruction |= (inst.operands[0].reg & 0x8) << 4; 9038 inst.instruction |= (inst.operands[0].reg & 0x7); 9039 inst.instruction |= inst.operands[1].reg << 3; 9040 } 9041} 9042 9043static void 9044do_t_cbz (void) 9045{ 9046 constraint (current_it_mask, BAD_NOT_IT); 9047 constraint (inst.operands[0].reg > 7, BAD_HIREG); 9048 inst.instruction |= inst.operands[0].reg; 9049 inst.reloc.pc_rel = 1; 9050 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; 9051} 9052 9053static void 9054do_t_dbg (void) 9055{ 9056 inst.instruction |= inst.operands[0].imm; 9057} 9058 9059static void 9060do_t_div (void) 9061{ 9062 if (!inst.operands[1].present) 9063 inst.operands[1].reg = inst.operands[0].reg; 9064 inst.instruction |= inst.operands[0].reg << 8; 9065 inst.instruction |= inst.operands[1].reg << 16; 9066 inst.instruction |= inst.operands[2].reg; 9067} 9068 9069static void 9070do_t_hint (void) 9071{ 9072 if (unified_syntax && inst.size_req == 4) 9073 inst.instruction = THUMB_OP32 (inst.instruction); 9074 else 9075 inst.instruction = THUMB_OP16 (inst.instruction); 9076} 9077 9078static void 9079do_t_it (void) 9080{ 9081 unsigned int cond = inst.operands[0].imm; 9082 9083 constraint (current_it_mask, BAD_NOT_IT); 9084 current_it_mask = (inst.instruction & 0xf) | 0x10; 9085 current_cc = cond; 9086 9087 /* If the condition is a negative condition, invert the mask. */ 9088 if ((cond & 0x1) == 0x0) 9089 { 9090 unsigned int mask = inst.instruction & 0x000f; 9091 9092 if ((mask & 0x7) == 0) 9093 /* no conversion needed */; 9094 else if ((mask & 0x3) == 0) 9095 mask ^= 0x8; 9096 else if ((mask & 0x1) == 0) 9097 mask ^= 0xC; 9098 else 9099 mask ^= 0xE; 9100 9101 inst.instruction &= 0xfff0; 9102 inst.instruction |= mask; 9103 } 9104 9105 inst.instruction |= cond << 4; 9106} 9107 9108/* Helper function used for both push/pop and ldm/stm. */ 9109static void 9110encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) 9111{ 9112 bfd_boolean load; 9113 9114 load = (inst.instruction & (1 << 20)) != 0; 9115 9116 if (mask & (1 << 13)) 9117 inst.error = _("SP not allowed in register list"); 9118 if (load) 9119 { 9120 if (mask & (1 << 14) 9121 && mask & (1 << 15)) 9122 inst.error = _("LR and PC should not both be in register list"); 9123 9124 if ((mask & (1 << base)) != 0 9125 && writeback) 9126 as_warn (_("base register should not be in register list " 9127 "when written back")); 9128 } 9129 else 9130 { 9131 if (mask & (1 << 15)) 9132 inst.error = _("PC not allowed in register list"); 9133 9134 if (mask & (1 << base)) 9135 as_warn (_("value stored for r%d is UNPREDICTABLE"), base); 9136 } 9137 9138 if ((mask & (mask - 1)) == 0) 9139 { 9140 /* Single register transfers implemented as str/ldr. */ 9141 if (writeback) 9142 { 9143 if (inst.instruction & (1 << 23)) 9144 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ 9145 else 9146 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ 9147 } 9148 else 9149 { 9150 if (inst.instruction & (1 << 23)) 9151 inst.instruction = 0x00800000; /* ia -> [base] */ 9152 else 9153 inst.instruction = 0x00000c04; /* db -> [base, #-4] */ 9154 } 9155 9156 inst.instruction |= 0xf8400000; 9157 if (load) 9158 inst.instruction |= 0x00100000; 9159 9160 mask = ffs(mask) - 1; 9161 mask <<= 12; 9162 } 9163 else if (writeback) 9164 inst.instruction |= WRITE_BACK; 9165 9166 inst.instruction |= mask; 9167 inst.instruction |= base << 16; 9168} 9169 9170static void 9171do_t_ldmstm (void) 9172{ 9173 /* This really doesn't seem worth it. */ 9174 constraint (inst.reloc.type != BFD_RELOC_UNUSED, 9175 _("expression too complex")); 9176 constraint (inst.operands[1].writeback, 9177 _("Thumb load/store multiple does not support {reglist}^")); 9178 9179 if (unified_syntax) 9180 { 9181 bfd_boolean narrow; 9182 unsigned mask; 9183 9184 narrow = FALSE; 9185 /* See if we can use a 16-bit instruction. */ 9186 if (inst.instruction < 0xffff /* not ldmdb/stmdb */ 9187 && inst.size_req != 4 9188 && !(inst.operands[1].imm & ~0xff)) 9189 { 9190 mask = 1 << inst.operands[0].reg; 9191 9192 if (inst.operands[0].reg <= 7 9193 && (inst.instruction == T_MNEM_stmia 9194 ? inst.operands[0].writeback 9195 : (inst.operands[0].writeback 9196 == !(inst.operands[1].imm & mask)))) 9197 { 9198 if (inst.instruction == T_MNEM_stmia 9199 && (inst.operands[1].imm & mask) 9200 && (inst.operands[1].imm & (mask - 1))) 9201 as_warn (_("value stored for r%d is UNPREDICTABLE"), 9202 inst.operands[0].reg); 9203 9204 inst.instruction = THUMB_OP16 (inst.instruction); 9205 inst.instruction |= inst.operands[0].reg << 8; 9206 inst.instruction |= inst.operands[1].imm; 9207 narrow = TRUE; 9208 } 9209 else if (inst.operands[0] .reg == REG_SP 9210 && inst.operands[0].writeback) 9211 { 9212 inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia 9213 ? T_MNEM_push : T_MNEM_pop); 9214 inst.instruction |= inst.operands[1].imm; 9215 narrow = TRUE; 9216 } 9217 } 9218 9219 if (!narrow) 9220 { 9221 if (inst.instruction < 0xffff) 9222 inst.instruction = THUMB_OP32 (inst.instruction); 9223 9224 encode_thumb2_ldmstm(inst.operands[0].reg, inst.operands[1].imm, 9225 inst.operands[0].writeback); 9226 } 9227 } 9228 else 9229 { 9230 constraint (inst.operands[0].reg > 7 9231 || (inst.operands[1].imm & ~0xff), BAD_HIREG); 9232 constraint (inst.instruction != T_MNEM_ldmia 9233 && inst.instruction != T_MNEM_stmia, 9234 _("Thumb-2 instruction only valid in unified syntax")); 9235 if (inst.instruction == T_MNEM_stmia) 9236 { 9237 if (!inst.operands[0].writeback) 9238 as_warn (_("this instruction will write back the base register")); 9239 if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) 9240 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) 9241 as_warn (_("value stored for r%d is UNPREDICTABLE"), 9242 inst.operands[0].reg); 9243 } 9244 else 9245 { 9246 if (!inst.operands[0].writeback 9247 && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) 9248 as_warn (_("this instruction will write back the base register")); 9249 else if (inst.operands[0].writeback 9250 && (inst.operands[1].imm & (1 << inst.operands[0].reg))) 9251 as_warn (_("this instruction will not write back the base register")); 9252 } 9253 9254 inst.instruction = THUMB_OP16 (inst.instruction); 9255 inst.instruction |= inst.operands[0].reg << 8; 9256 inst.instruction |= inst.operands[1].imm; 9257 } 9258} 9259 9260static void 9261do_t_ldrex (void) 9262{ 9263 constraint (!inst.operands[1].isreg || !inst.operands[1].preind 9264 || inst.operands[1].postind || inst.operands[1].writeback 9265 || inst.operands[1].immisreg || inst.operands[1].shifted 9266 || inst.operands[1].negative, 9267 BAD_ADDR_MODE); 9268 9269 inst.instruction |= inst.operands[0].reg << 12; 9270 inst.instruction |= inst.operands[1].reg << 16; 9271 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; 9272} 9273 9274static void 9275do_t_ldrexd (void) 9276{ 9277 if (!inst.operands[1].present) 9278 { 9279 constraint (inst.operands[0].reg == REG_LR, 9280 _("r14 not allowed as first register " 9281 "when second register is omitted")); 9282 inst.operands[1].reg = inst.operands[0].reg + 1; 9283 } 9284 constraint (inst.operands[0].reg == inst.operands[1].reg, 9285 BAD_OVERLAP); 9286 9287 inst.instruction |= inst.operands[0].reg << 12; 9288 inst.instruction |= inst.operands[1].reg << 8; 9289 inst.instruction |= inst.operands[2].reg << 16; 9290} 9291 9292static void 9293do_t_ldst (void) 9294{ 9295 unsigned long opcode; 9296 int Rn; 9297 9298 opcode = inst.instruction; 9299 if (unified_syntax) 9300 { 9301 if (!inst.operands[1].isreg) 9302 { 9303 if (opcode <= 0xffff) 9304 inst.instruction = THUMB_OP32 (opcode); 9305 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) 9306 return; 9307 } 9308 if (inst.operands[1].isreg 9309 && !inst.operands[1].writeback 9310 && !inst.operands[1].shifted && !inst.operands[1].postind 9311 && !inst.operands[1].negative && inst.operands[0].reg <= 7 9312 && opcode <= 0xffff 9313 && inst.size_req != 4) 9314 { 9315 /* Insn may have a 16-bit form. */ 9316 Rn = inst.operands[1].reg; 9317 if (inst.operands[1].immisreg) 9318 { 9319 inst.instruction = THUMB_OP16 (opcode); 9320 /* [Rn, Ri] */ 9321 if (Rn <= 7 && inst.operands[1].imm <= 7) 9322 goto op16; 9323 } 9324 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh 9325 && opcode != T_MNEM_ldrsb) 9326 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) 9327 || (Rn == REG_SP && opcode == T_MNEM_str)) 9328 { 9329 /* [Rn, #const] */ 9330 if (Rn > 7) 9331 { 9332 if (Rn == REG_PC) 9333 { 9334 if (inst.reloc.pc_rel) 9335 opcode = T_MNEM_ldr_pc2; 9336 else 9337 opcode = T_MNEM_ldr_pc; 9338 } 9339 else 9340 { 9341 if (opcode == T_MNEM_ldr) 9342 opcode = T_MNEM_ldr_sp; 9343 else 9344 opcode = T_MNEM_str_sp; 9345 } 9346 inst.instruction = inst.operands[0].reg << 8; 9347 } 9348 else 9349 { 9350 inst.instruction = inst.operands[0].reg; 9351 inst.instruction |= inst.operands[1].reg << 3; 9352 } 9353 inst.instruction |= THUMB_OP16 (opcode); 9354 if (inst.size_req == 2) 9355 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 9356 else 9357 inst.relax = opcode; 9358 return; 9359 } 9360 } 9361 /* Definitely a 32-bit variant. */ 9362 inst.instruction = THUMB_OP32 (opcode); 9363 inst.instruction |= inst.operands[0].reg << 12; 9364 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); 9365 return; 9366 } 9367 9368 constraint (inst.operands[0].reg > 7, BAD_HIREG); 9369 9370 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) 9371 { 9372 /* Only [Rn,Rm] is acceptable. */ 9373 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); 9374 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg 9375 || inst.operands[1].postind || inst.operands[1].shifted 9376 || inst.operands[1].negative, 9377 _("Thumb does not support this addressing mode")); 9378 inst.instruction = THUMB_OP16 (inst.instruction); 9379 goto op16; 9380 } 9381 9382 inst.instruction = THUMB_OP16 (inst.instruction); 9383 if (!inst.operands[1].isreg) 9384 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) 9385 return; 9386 9387 constraint (!inst.operands[1].preind 9388 || inst.operands[1].shifted 9389 || inst.operands[1].writeback, 9390 _("Thumb does not support this addressing mode")); 9391 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) 9392 { 9393 constraint (inst.instruction & 0x0600, 9394 _("byte or halfword not valid for base register")); 9395 constraint (inst.operands[1].reg == REG_PC 9396 && !(inst.instruction & THUMB_LOAD_BIT), 9397 _("r15 based store not allowed")); 9398 constraint (inst.operands[1].immisreg, 9399 _("invalid base register for register offset")); 9400 9401 if (inst.operands[1].reg == REG_PC) 9402 inst.instruction = T_OPCODE_LDR_PC; 9403 else if (inst.instruction & THUMB_LOAD_BIT) 9404 inst.instruction = T_OPCODE_LDR_SP; 9405 else 9406 inst.instruction = T_OPCODE_STR_SP; 9407 9408 inst.instruction |= inst.operands[0].reg << 8; 9409 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 9410 return; 9411 } 9412 9413 constraint (inst.operands[1].reg > 7, BAD_HIREG); 9414 if (!inst.operands[1].immisreg) 9415 { 9416 /* Immediate offset. */ 9417 inst.instruction |= inst.operands[0].reg; 9418 inst.instruction |= inst.operands[1].reg << 3; 9419 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 9420 return; 9421 } 9422 9423 /* Register offset. */ 9424 constraint (inst.operands[1].imm > 7, BAD_HIREG); 9425 constraint (inst.operands[1].negative, 9426 _("Thumb does not support this addressing mode")); 9427 9428 op16: 9429 switch (inst.instruction) 9430 { 9431 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; 9432 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; 9433 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; 9434 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; 9435 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; 9436 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; 9437 case 0x5600 /* ldrsb */: 9438 case 0x5e00 /* ldrsh */: break; 9439 default: abort (); 9440 } 9441 9442 inst.instruction |= inst.operands[0].reg; 9443 inst.instruction |= inst.operands[1].reg << 3; 9444 inst.instruction |= inst.operands[1].imm << 6; 9445} 9446 9447static void 9448do_t_ldstd (void) 9449{ 9450 if (!inst.operands[1].present) 9451 { 9452 inst.operands[1].reg = inst.operands[0].reg + 1; 9453 constraint (inst.operands[0].reg == REG_LR, 9454 _("r14 not allowed here")); 9455 } 9456 inst.instruction |= inst.operands[0].reg << 12; 9457 inst.instruction |= inst.operands[1].reg << 8; 9458 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); 9459 9460} 9461 9462static void 9463do_t_ldstt (void) 9464{ 9465 inst.instruction |= inst.operands[0].reg << 12; 9466 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); 9467} 9468 9469static void 9470do_t_mla (void) 9471{ 9472 inst.instruction |= inst.operands[0].reg << 8; 9473 inst.instruction |= inst.operands[1].reg << 16; 9474 inst.instruction |= inst.operands[2].reg; 9475 inst.instruction |= inst.operands[3].reg << 12; 9476} 9477 9478static void 9479do_t_mlal (void) 9480{ 9481 inst.instruction |= inst.operands[0].reg << 12; 9482 inst.instruction |= inst.operands[1].reg << 8; 9483 inst.instruction |= inst.operands[2].reg << 16; 9484 inst.instruction |= inst.operands[3].reg; 9485} 9486 9487static void 9488do_t_mov_cmp (void) 9489{ 9490 if (unified_syntax) 9491 { 9492 int r0off = (inst.instruction == T_MNEM_mov 9493 || inst.instruction == T_MNEM_movs) ? 8 : 16; 9494 unsigned long opcode; 9495 bfd_boolean narrow; 9496 bfd_boolean low_regs; 9497 9498 low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7); 9499 opcode = inst.instruction; 9500 if (current_it_mask) 9501 narrow = opcode != T_MNEM_movs; 9502 else 9503 narrow = opcode != T_MNEM_movs || low_regs; 9504 if (inst.size_req == 4 9505 || inst.operands[1].shifted) 9506 narrow = FALSE; 9507 9508 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ 9509 if (opcode == T_MNEM_movs && inst.operands[1].isreg 9510 && !inst.operands[1].shifted 9511 && inst.operands[0].reg == REG_PC 9512 && inst.operands[1].reg == REG_LR) 9513 { 9514 inst.instruction = T2_SUBS_PC_LR; 9515 return; 9516 } 9517 9518 if (!inst.operands[1].isreg) 9519 { 9520 /* Immediate operand. */ 9521 if (current_it_mask == 0 && opcode == T_MNEM_mov) 9522 narrow = 0; 9523 if (low_regs && narrow) 9524 { 9525 inst.instruction = THUMB_OP16 (opcode); 9526 inst.instruction |= inst.operands[0].reg << 8; 9527 if (inst.size_req == 2) 9528 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; 9529 else 9530 inst.relax = opcode; 9531 } 9532 else 9533 { 9534 inst.instruction = THUMB_OP32 (inst.instruction); 9535 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 9536 inst.instruction |= inst.operands[0].reg << r0off; 9537 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 9538 } 9539 } 9540 else if (inst.operands[1].shifted && inst.operands[1].immisreg 9541 && (inst.instruction == T_MNEM_mov 9542 || inst.instruction == T_MNEM_movs)) 9543 { 9544 /* Register shifts are encoded as separate shift instructions. */ 9545 bfd_boolean flags = (inst.instruction == T_MNEM_movs); 9546 9547 if (current_it_mask) 9548 narrow = !flags; 9549 else 9550 narrow = flags; 9551 9552 if (inst.size_req == 4) 9553 narrow = FALSE; 9554 9555 if (!low_regs || inst.operands[1].imm > 7) 9556 narrow = FALSE; 9557 9558 if (inst.operands[0].reg != inst.operands[1].reg) 9559 narrow = FALSE; 9560 9561 switch (inst.operands[1].shift_kind) 9562 { 9563 case SHIFT_LSL: 9564 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); 9565 break; 9566 case SHIFT_ASR: 9567 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); 9568 break; 9569 case SHIFT_LSR: 9570 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); 9571 break; 9572 case SHIFT_ROR: 9573 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); 9574 break; 9575 default: 9576 abort(); 9577 } 9578 9579 inst.instruction = opcode; 9580 if (narrow) 9581 { 9582 inst.instruction |= inst.operands[0].reg; 9583 inst.instruction |= inst.operands[1].imm << 3; 9584 } 9585 else 9586 { 9587 if (flags) 9588 inst.instruction |= CONDS_BIT; 9589 9590 inst.instruction |= inst.operands[0].reg << 8; 9591 inst.instruction |= inst.operands[1].reg << 16; 9592 inst.instruction |= inst.operands[1].imm; 9593 } 9594 } 9595 else if (!narrow) 9596 { 9597 /* Some mov with immediate shift have narrow variants. 9598 Register shifts are handled above. */ 9599 if (low_regs && inst.operands[1].shifted 9600 && (inst.instruction == T_MNEM_mov 9601 || inst.instruction == T_MNEM_movs)) 9602 { 9603 if (current_it_mask) 9604 narrow = (inst.instruction == T_MNEM_mov); 9605 else 9606 narrow = (inst.instruction == T_MNEM_movs); 9607 } 9608 9609 if (narrow) 9610 { 9611 switch (inst.operands[1].shift_kind) 9612 { 9613 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; 9614 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; 9615 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; 9616 default: narrow = FALSE; break; 9617 } 9618 } 9619 9620 if (narrow) 9621 { 9622 inst.instruction |= inst.operands[0].reg; 9623 inst.instruction |= inst.operands[1].reg << 3; 9624 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 9625 } 9626 else 9627 { 9628 inst.instruction = THUMB_OP32 (inst.instruction); 9629 inst.instruction |= inst.operands[0].reg << r0off; 9630 encode_thumb32_shifted_operand (1); 9631 } 9632 } 9633 else 9634 switch (inst.instruction) 9635 { 9636 case T_MNEM_mov: 9637 inst.instruction = T_OPCODE_MOV_HR; 9638 inst.instruction |= (inst.operands[0].reg & 0x8) << 4; 9639 inst.instruction |= (inst.operands[0].reg & 0x7); 9640 inst.instruction |= inst.operands[1].reg << 3; 9641 break; 9642 9643 case T_MNEM_movs: 9644 /* We know we have low registers at this point. 9645 Generate ADD Rd, Rs, #0. */ 9646 inst.instruction = T_OPCODE_ADD_I3; 9647 inst.instruction |= inst.operands[0].reg; 9648 inst.instruction |= inst.operands[1].reg << 3; 9649 break; 9650 9651 case T_MNEM_cmp: 9652 if (low_regs) 9653 { 9654 inst.instruction = T_OPCODE_CMP_LR; 9655 inst.instruction |= inst.operands[0].reg; 9656 inst.instruction |= inst.operands[1].reg << 3; 9657 } 9658 else 9659 { 9660 inst.instruction = T_OPCODE_CMP_HR; 9661 inst.instruction |= (inst.operands[0].reg & 0x8) << 4; 9662 inst.instruction |= (inst.operands[0].reg & 0x7); 9663 inst.instruction |= inst.operands[1].reg << 3; 9664 } 9665 break; 9666 } 9667 return; 9668 } 9669 9670 inst.instruction = THUMB_OP16 (inst.instruction); 9671 if (inst.operands[1].isreg) 9672 { 9673 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8) 9674 { 9675 /* A move of two lowregs is encoded as ADD Rd, Rs, #0 9676 since a MOV instruction produces unpredictable results. */ 9677 if (inst.instruction == T_OPCODE_MOV_I8) 9678 inst.instruction = T_OPCODE_ADD_I3; 9679 else 9680 inst.instruction = T_OPCODE_CMP_LR; 9681 9682 inst.instruction |= inst.operands[0].reg; 9683 inst.instruction |= inst.operands[1].reg << 3; 9684 } 9685 else 9686 { 9687 if (inst.instruction == T_OPCODE_MOV_I8) 9688 inst.instruction = T_OPCODE_MOV_HR; 9689 else 9690 inst.instruction = T_OPCODE_CMP_HR; 9691 do_t_cpy (); 9692 } 9693 } 9694 else 9695 { 9696 constraint (inst.operands[0].reg > 7, 9697 _("only lo regs allowed with immediate")); 9698 inst.instruction |= inst.operands[0].reg << 8; 9699 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; 9700 } 9701} 9702 9703static void 9704do_t_mov16 (void) 9705{ 9706 bfd_vma imm; 9707 bfd_boolean top; 9708 9709 top = (inst.instruction & 0x00800000) != 0; 9710 if (inst.reloc.type == BFD_RELOC_ARM_MOVW) 9711 { 9712 constraint (top, _(":lower16: not allowed this instruction")); 9713 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; 9714 } 9715 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) 9716 { 9717 constraint (!top, _(":upper16: not allowed this instruction")); 9718 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; 9719 } 9720 9721 inst.instruction |= inst.operands[0].reg << 8; 9722 if (inst.reloc.type == BFD_RELOC_UNUSED) 9723 { 9724 imm = inst.reloc.exp.X_add_number; 9725 inst.instruction |= (imm & 0xf000) << 4; 9726 inst.instruction |= (imm & 0x0800) << 15; 9727 inst.instruction |= (imm & 0x0700) << 4; 9728 inst.instruction |= (imm & 0x00ff); 9729 } 9730} 9731 9732static void 9733do_t_mvn_tst (void) 9734{ 9735 if (unified_syntax) 9736 { 9737 int r0off = (inst.instruction == T_MNEM_mvn 9738 || inst.instruction == T_MNEM_mvns) ? 8 : 16; 9739 bfd_boolean narrow; 9740 9741 if (inst.size_req == 4 9742 || inst.instruction > 0xffff 9743 || inst.operands[1].shifted 9744 || inst.operands[0].reg > 7 || inst.operands[1].reg > 7) 9745 narrow = FALSE; 9746 else if (inst.instruction == T_MNEM_cmn) 9747 narrow = TRUE; 9748 else if (THUMB_SETS_FLAGS (inst.instruction)) 9749 narrow = (current_it_mask == 0); 9750 else 9751 narrow = (current_it_mask != 0); 9752 9753 if (!inst.operands[1].isreg) 9754 { 9755 /* For an immediate, we always generate a 32-bit opcode; 9756 section relaxation will shrink it later if possible. */ 9757 if (inst.instruction < 0xffff) 9758 inst.instruction = THUMB_OP32 (inst.instruction); 9759 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 9760 inst.instruction |= inst.operands[0].reg << r0off; 9761 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 9762 } 9763 else 9764 { 9765 /* See if we can do this with a 16-bit instruction. */ 9766 if (narrow) 9767 { 9768 inst.instruction = THUMB_OP16 (inst.instruction); 9769 inst.instruction |= inst.operands[0].reg; 9770 inst.instruction |= inst.operands[1].reg << 3; 9771 } 9772 else 9773 { 9774 constraint (inst.operands[1].shifted 9775 && inst.operands[1].immisreg, 9776 _("shift must be constant")); 9777 if (inst.instruction < 0xffff) 9778 inst.instruction = THUMB_OP32 (inst.instruction); 9779 inst.instruction |= inst.operands[0].reg << r0off; 9780 encode_thumb32_shifted_operand (1); 9781 } 9782 } 9783 } 9784 else 9785 { 9786 constraint (inst.instruction > 0xffff 9787 || inst.instruction == T_MNEM_mvns, BAD_THUMB32); 9788 constraint (!inst.operands[1].isreg || inst.operands[1].shifted, 9789 _("unshifted register required")); 9790 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, 9791 BAD_HIREG); 9792 9793 inst.instruction = THUMB_OP16 (inst.instruction); 9794 inst.instruction |= inst.operands[0].reg; 9795 inst.instruction |= inst.operands[1].reg << 3; 9796 } 9797} 9798 9799static void 9800do_t_mrs (void) 9801{ 9802 int flags; 9803 9804 if (do_vfp_nsyn_mrs () == SUCCESS) 9805 return; 9806 9807 flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); 9808 if (flags == 0) 9809 { 9810 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m), 9811 _("selected processor does not support " 9812 "requested special purpose register")); 9813 } 9814 else 9815 { 9816 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), 9817 _("selected processor does not support " 9818 "requested special purpose register %x")); 9819 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ 9820 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), 9821 _("'CPSR' or 'SPSR' expected")); 9822 } 9823 9824 inst.instruction |= inst.operands[0].reg << 8; 9825 inst.instruction |= (flags & SPSR_BIT) >> 2; 9826 inst.instruction |= inst.operands[1].imm & 0xff; 9827} 9828 9829static void 9830do_t_msr (void) 9831{ 9832 int flags; 9833 9834 if (do_vfp_nsyn_msr () == SUCCESS) 9835 return; 9836 9837 constraint (!inst.operands[1].isreg, 9838 _("Thumb encoding does not support an immediate here")); 9839 flags = inst.operands[0].imm; 9840 if (flags & ~0xff) 9841 { 9842 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), 9843 _("selected processor does not support " 9844 "requested special purpose register")); 9845 } 9846 else 9847 { 9848 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m), 9849 _("selected processor does not support " 9850 "requested special purpose register")); 9851 flags |= PSR_f; 9852 } 9853 inst.instruction |= (flags & SPSR_BIT) >> 2; 9854 inst.instruction |= (flags & ~SPSR_BIT) >> 8; 9855 inst.instruction |= (flags & 0xff); 9856 inst.instruction |= inst.operands[1].reg << 16; 9857} 9858 9859static void 9860do_t_mul (void) 9861{ 9862 if (!inst.operands[2].present) 9863 inst.operands[2].reg = inst.operands[0].reg; 9864 9865 /* There is no 32-bit MULS and no 16-bit MUL. */ 9866 if (unified_syntax && inst.instruction == T_MNEM_mul) 9867 { 9868 inst.instruction = THUMB_OP32 (inst.instruction); 9869 inst.instruction |= inst.operands[0].reg << 8; 9870 inst.instruction |= inst.operands[1].reg << 16; 9871 inst.instruction |= inst.operands[2].reg << 0; 9872 } 9873 else 9874 { 9875 constraint (!unified_syntax 9876 && inst.instruction == T_MNEM_muls, BAD_THUMB32); 9877 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, 9878 BAD_HIREG); 9879 9880 inst.instruction = THUMB_OP16 (inst.instruction); 9881 inst.instruction |= inst.operands[0].reg; 9882 9883 if (inst.operands[0].reg == inst.operands[1].reg) 9884 inst.instruction |= inst.operands[2].reg << 3; 9885 else if (inst.operands[0].reg == inst.operands[2].reg) 9886 inst.instruction |= inst.operands[1].reg << 3; 9887 else 9888 constraint (1, _("dest must overlap one source register")); 9889 } 9890} 9891 9892static void 9893do_t_mull (void) 9894{ 9895 inst.instruction |= inst.operands[0].reg << 12; 9896 inst.instruction |= inst.operands[1].reg << 8; 9897 inst.instruction |= inst.operands[2].reg << 16; 9898 inst.instruction |= inst.operands[3].reg; 9899 9900 if (inst.operands[0].reg == inst.operands[1].reg) 9901 as_tsktsk (_("rdhi and rdlo must be different")); 9902} 9903 9904static void 9905do_t_nop (void) 9906{ 9907 if (unified_syntax) 9908 { 9909 if (inst.size_req == 4 || inst.operands[0].imm > 15) 9910 { 9911 inst.instruction = THUMB_OP32 (inst.instruction); 9912 inst.instruction |= inst.operands[0].imm; 9913 } 9914 else 9915 { 9916 inst.instruction = THUMB_OP16 (inst.instruction); 9917 inst.instruction |= inst.operands[0].imm << 4; 9918 } 9919 } 9920 else 9921 { 9922 constraint (inst.operands[0].present, 9923 _("Thumb does not support NOP with hints")); 9924 inst.instruction = 0x46c0; 9925 } 9926} 9927 9928static void 9929do_t_neg (void) 9930{ 9931 if (unified_syntax) 9932 { 9933 bfd_boolean narrow; 9934 9935 if (THUMB_SETS_FLAGS (inst.instruction)) 9936 narrow = (current_it_mask == 0); 9937 else 9938 narrow = (current_it_mask != 0); 9939 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) 9940 narrow = FALSE; 9941 if (inst.size_req == 4) 9942 narrow = FALSE; 9943 9944 if (!narrow) 9945 { 9946 inst.instruction = THUMB_OP32 (inst.instruction); 9947 inst.instruction |= inst.operands[0].reg << 8; 9948 inst.instruction |= inst.operands[1].reg << 16; 9949 } 9950 else 9951 { 9952 inst.instruction = THUMB_OP16 (inst.instruction); 9953 inst.instruction |= inst.operands[0].reg; 9954 inst.instruction |= inst.operands[1].reg << 3; 9955 } 9956 } 9957 else 9958 { 9959 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, 9960 BAD_HIREG); 9961 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 9962 9963 inst.instruction = THUMB_OP16 (inst.instruction); 9964 inst.instruction |= inst.operands[0].reg; 9965 inst.instruction |= inst.operands[1].reg << 3; 9966 } 9967} 9968 9969static void 9970do_t_pkhbt (void) 9971{ 9972 inst.instruction |= inst.operands[0].reg << 8; 9973 inst.instruction |= inst.operands[1].reg << 16; 9974 inst.instruction |= inst.operands[2].reg; 9975 if (inst.operands[3].present) 9976 { 9977 unsigned int val = inst.reloc.exp.X_add_number; 9978 constraint (inst.reloc.exp.X_op != O_constant, 9979 _("expression too complex")); 9980 inst.instruction |= (val & 0x1c) << 10; 9981 inst.instruction |= (val & 0x03) << 6; 9982 } 9983} 9984 9985static void 9986do_t_pkhtb (void) 9987{ 9988 if (!inst.operands[3].present) 9989 inst.instruction &= ~0x00000020; 9990 do_t_pkhbt (); 9991} 9992 9993static void 9994do_t_pld (void) 9995{ 9996 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); 9997} 9998 9999static void 10000do_t_push_pop (void) 10001{ 10002 unsigned mask; 10003 10004 constraint (inst.operands[0].writeback, 10005 _("push/pop do not support {reglist}^")); 10006 constraint (inst.reloc.type != BFD_RELOC_UNUSED, 10007 _("expression too complex")); 10008 10009 mask = inst.operands[0].imm; 10010 if ((mask & ~0xff) == 0) 10011 inst.instruction = THUMB_OP16 (inst.instruction) | mask; 10012 else if ((inst.instruction == T_MNEM_push 10013 && (mask & ~0xff) == 1 << REG_LR) 10014 || (inst.instruction == T_MNEM_pop 10015 && (mask & ~0xff) == 1 << REG_PC)) 10016 { 10017 inst.instruction = THUMB_OP16 (inst.instruction); 10018 inst.instruction |= THUMB_PP_PC_LR; 10019 inst.instruction |= mask & 0xff; 10020 } 10021 else if (unified_syntax) 10022 { 10023 inst.instruction = THUMB_OP32 (inst.instruction); 10024 encode_thumb2_ldmstm(13, mask, TRUE); 10025 } 10026 else 10027 { 10028 inst.error = _("invalid register list to push/pop instruction"); 10029 return; 10030 } 10031} 10032 10033static void 10034do_t_rbit (void) 10035{ 10036 inst.instruction |= inst.operands[0].reg << 8; 10037 inst.instruction |= inst.operands[1].reg << 16; 10038} 10039 10040static void 10041do_t_rd_rm (void) 10042{ 10043 inst.instruction |= inst.operands[0].reg << 8; 10044 inst.instruction |= inst.operands[1].reg; 10045} 10046 10047static void 10048do_t_rev (void) 10049{ 10050 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 10051 && inst.size_req != 4) 10052 { 10053 inst.instruction = THUMB_OP16 (inst.instruction); 10054 inst.instruction |= inst.operands[0].reg; 10055 inst.instruction |= inst.operands[1].reg << 3; 10056 } 10057 else if (unified_syntax) 10058 { 10059 inst.instruction = THUMB_OP32 (inst.instruction); 10060 inst.instruction |= inst.operands[0].reg << 8; 10061 inst.instruction |= inst.operands[1].reg << 16; 10062 inst.instruction |= inst.operands[1].reg; 10063 } 10064 else 10065 inst.error = BAD_HIREG; 10066} 10067 10068static void 10069do_t_rsb (void) 10070{ 10071 int Rd, Rs; 10072 10073 Rd = inst.operands[0].reg; 10074 Rs = (inst.operands[1].present 10075 ? inst.operands[1].reg /* Rd, Rs, foo */ 10076 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 10077 10078 inst.instruction |= Rd << 8; 10079 inst.instruction |= Rs << 16; 10080 if (!inst.operands[2].isreg) 10081 { 10082 bfd_boolean narrow; 10083 10084 if ((inst.instruction & 0x00100000) != 0) 10085 narrow = (current_it_mask == 0); 10086 else 10087 narrow = (current_it_mask != 0); 10088 10089 if (Rd > 7 || Rs > 7) 10090 narrow = FALSE; 10091 10092 if (inst.size_req == 4 || !unified_syntax) 10093 narrow = FALSE; 10094 10095 if (inst.reloc.exp.X_op != O_constant 10096 || inst.reloc.exp.X_add_number != 0) 10097 narrow = FALSE; 10098 10099 /* Turn rsb #0 into 16-bit neg. We should probably do this via 10100 relaxation, but it doesn't seem worth the hassle. */ 10101 if (narrow) 10102 { 10103 inst.reloc.type = BFD_RELOC_UNUSED; 10104 inst.instruction = THUMB_OP16 (T_MNEM_negs); 10105 inst.instruction |= Rs << 3; 10106 inst.instruction |= Rd; 10107 } 10108 else 10109 { 10110 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 10111 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 10112 } 10113 } 10114 else 10115 encode_thumb32_shifted_operand (2); 10116} 10117 10118static void 10119do_t_setend (void) 10120{ 10121 constraint (current_it_mask, BAD_NOT_IT); 10122 if (inst.operands[0].imm) 10123 inst.instruction |= 0x8; 10124} 10125 10126static void 10127do_t_shift (void) 10128{ 10129 if (!inst.operands[1].present) 10130 inst.operands[1].reg = inst.operands[0].reg; 10131 10132 if (unified_syntax) 10133 { 10134 bfd_boolean narrow; 10135 int shift_kind; 10136 10137 switch (inst.instruction) 10138 { 10139 case T_MNEM_asr: 10140 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; 10141 case T_MNEM_lsl: 10142 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; 10143 case T_MNEM_lsr: 10144 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; 10145 case T_MNEM_ror: 10146 case T_MNEM_rors: shift_kind = SHIFT_ROR; break; 10147 default: abort (); 10148 } 10149 10150 if (THUMB_SETS_FLAGS (inst.instruction)) 10151 narrow = (current_it_mask == 0); 10152 else 10153 narrow = (current_it_mask != 0); 10154 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) 10155 narrow = FALSE; 10156 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) 10157 narrow = FALSE; 10158 if (inst.operands[2].isreg 10159 && (inst.operands[1].reg != inst.operands[0].reg 10160 || inst.operands[2].reg > 7)) 10161 narrow = FALSE; 10162 if (inst.size_req == 4) 10163 narrow = FALSE; 10164 10165 if (!narrow) 10166 { 10167 if (inst.operands[2].isreg) 10168 { 10169 inst.instruction = THUMB_OP32 (inst.instruction); 10170 inst.instruction |= inst.operands[0].reg << 8; 10171 inst.instruction |= inst.operands[1].reg << 16; 10172 inst.instruction |= inst.operands[2].reg; 10173 } 10174 else 10175 { 10176 inst.operands[1].shifted = 1; 10177 inst.operands[1].shift_kind = shift_kind; 10178 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) 10179 ? T_MNEM_movs : T_MNEM_mov); 10180 inst.instruction |= inst.operands[0].reg << 8; 10181 encode_thumb32_shifted_operand (1); 10182 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ 10183 inst.reloc.type = BFD_RELOC_UNUSED; 10184 } 10185 } 10186 else 10187 { 10188 if (inst.operands[2].isreg) 10189 { 10190 switch (shift_kind) 10191 { 10192 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; 10193 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; 10194 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; 10195 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; 10196 default: abort (); 10197 } 10198 10199 inst.instruction |= inst.operands[0].reg; 10200 inst.instruction |= inst.operands[2].reg << 3; 10201 } 10202 else 10203 { 10204 switch (shift_kind) 10205 { 10206 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; 10207 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; 10208 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; 10209 default: abort (); 10210 } 10211 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 10212 inst.instruction |= inst.operands[0].reg; 10213 inst.instruction |= inst.operands[1].reg << 3; 10214 } 10215 } 10216 } 10217 else 10218 { 10219 constraint (inst.operands[0].reg > 7 10220 || inst.operands[1].reg > 7, BAD_HIREG); 10221 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 10222 10223 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ 10224 { 10225 constraint (inst.operands[2].reg > 7, BAD_HIREG); 10226 constraint (inst.operands[0].reg != inst.operands[1].reg, 10227 _("source1 and dest must be same register")); 10228 10229 switch (inst.instruction) 10230 { 10231 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; 10232 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; 10233 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; 10234 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; 10235 default: abort (); 10236 } 10237 10238 inst.instruction |= inst.operands[0].reg; 10239 inst.instruction |= inst.operands[2].reg << 3; 10240 } 10241 else 10242 { 10243 switch (inst.instruction) 10244 { 10245 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; 10246 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; 10247 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; 10248 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; 10249 default: abort (); 10250 } 10251 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 10252 inst.instruction |= inst.operands[0].reg; 10253 inst.instruction |= inst.operands[1].reg << 3; 10254 } 10255 } 10256} 10257 10258static void 10259do_t_simd (void) 10260{ 10261 inst.instruction |= inst.operands[0].reg << 8; 10262 inst.instruction |= inst.operands[1].reg << 16; 10263 inst.instruction |= inst.operands[2].reg; 10264} 10265 10266static void 10267do_t_smc (void) 10268{ 10269 unsigned int value = inst.reloc.exp.X_add_number; 10270 constraint (inst.reloc.exp.X_op != O_constant, 10271 _("expression too complex")); 10272 inst.reloc.type = BFD_RELOC_UNUSED; 10273 inst.instruction |= (value & 0xf000) >> 12; 10274 inst.instruction |= (value & 0x0ff0); 10275 inst.instruction |= (value & 0x000f) << 16; 10276} 10277 10278static void 10279do_t_ssat (void) 10280{ 10281 inst.instruction |= inst.operands[0].reg << 8; 10282 inst.instruction |= inst.operands[1].imm - 1; 10283 inst.instruction |= inst.operands[2].reg << 16; 10284 10285 if (inst.operands[3].present) 10286 { 10287 constraint (inst.reloc.exp.X_op != O_constant, 10288 _("expression too complex")); 10289 10290 if (inst.reloc.exp.X_add_number != 0) 10291 { 10292 if (inst.operands[3].shift_kind == SHIFT_ASR) 10293 inst.instruction |= 0x00200000; /* sh bit */ 10294 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; 10295 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; 10296 } 10297 inst.reloc.type = BFD_RELOC_UNUSED; 10298 } 10299} 10300 10301static void 10302do_t_ssat16 (void) 10303{ 10304 inst.instruction |= inst.operands[0].reg << 8; 10305 inst.instruction |= inst.operands[1].imm - 1; 10306 inst.instruction |= inst.operands[2].reg << 16; 10307} 10308 10309static void 10310do_t_strex (void) 10311{ 10312 constraint (!inst.operands[2].isreg || !inst.operands[2].preind 10313 || inst.operands[2].postind || inst.operands[2].writeback 10314 || inst.operands[2].immisreg || inst.operands[2].shifted 10315 || inst.operands[2].negative, 10316 BAD_ADDR_MODE); 10317 10318 inst.instruction |= inst.operands[0].reg << 8; 10319 inst.instruction |= inst.operands[1].reg << 12; 10320 inst.instruction |= inst.operands[2].reg << 16; 10321 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; 10322} 10323 10324static void 10325do_t_strexd (void) 10326{ 10327 if (!inst.operands[2].present) 10328 inst.operands[2].reg = inst.operands[1].reg + 1; 10329 10330 constraint (inst.operands[0].reg == inst.operands[1].reg 10331 || inst.operands[0].reg == inst.operands[2].reg 10332 || inst.operands[0].reg == inst.operands[3].reg 10333 || inst.operands[1].reg == inst.operands[2].reg, 10334 BAD_OVERLAP); 10335 10336 inst.instruction |= inst.operands[0].reg; 10337 inst.instruction |= inst.operands[1].reg << 12; 10338 inst.instruction |= inst.operands[2].reg << 8; 10339 inst.instruction |= inst.operands[3].reg << 16; 10340} 10341 10342static void 10343do_t_sxtah (void) 10344{ 10345 inst.instruction |= inst.operands[0].reg << 8; 10346 inst.instruction |= inst.operands[1].reg << 16; 10347 inst.instruction |= inst.operands[2].reg; 10348 inst.instruction |= inst.operands[3].imm << 4; 10349} 10350 10351static void 10352do_t_sxth (void) 10353{ 10354 if (inst.instruction <= 0xffff && inst.size_req != 4 10355 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 10356 && (!inst.operands[2].present || inst.operands[2].imm == 0)) 10357 { 10358 inst.instruction = THUMB_OP16 (inst.instruction); 10359 inst.instruction |= inst.operands[0].reg; 10360 inst.instruction |= inst.operands[1].reg << 3; 10361 } 10362 else if (unified_syntax) 10363 { 10364 if (inst.instruction <= 0xffff) 10365 inst.instruction = THUMB_OP32 (inst.instruction); 10366 inst.instruction |= inst.operands[0].reg << 8; 10367 inst.instruction |= inst.operands[1].reg; 10368 inst.instruction |= inst.operands[2].imm << 4; 10369 } 10370 else 10371 { 10372 constraint (inst.operands[2].present && inst.operands[2].imm != 0, 10373 _("Thumb encoding does not support rotation")); 10374 constraint (1, BAD_HIREG); 10375 } 10376} 10377 10378static void 10379do_t_swi (void) 10380{ 10381 inst.reloc.type = BFD_RELOC_ARM_SWI; 10382} 10383 10384static void 10385do_t_tb (void) 10386{ 10387 int half; 10388 10389 half = (inst.instruction & 0x10) != 0; 10390 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 10391 constraint (inst.operands[0].immisreg, 10392 _("instruction requires register index")); 10393 constraint (inst.operands[0].imm == 15, 10394 _("PC is not a valid index register")); 10395 constraint (!half && inst.operands[0].shifted, 10396 _("instruction does not allow shifted index")); 10397 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm; 10398} 10399 10400static void 10401do_t_usat (void) 10402{ 10403 inst.instruction |= inst.operands[0].reg << 8; 10404 inst.instruction |= inst.operands[1].imm; 10405 inst.instruction |= inst.operands[2].reg << 16; 10406 10407 if (inst.operands[3].present) 10408 { 10409 constraint (inst.reloc.exp.X_op != O_constant, 10410 _("expression too complex")); 10411 if (inst.reloc.exp.X_add_number != 0) 10412 { 10413 if (inst.operands[3].shift_kind == SHIFT_ASR) 10414 inst.instruction |= 0x00200000; /* sh bit */ 10415 10416 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; 10417 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; 10418 } 10419 inst.reloc.type = BFD_RELOC_UNUSED; 10420 } 10421} 10422 10423static void 10424do_t_usat16 (void) 10425{ 10426 inst.instruction |= inst.operands[0].reg << 8; 10427 inst.instruction |= inst.operands[1].imm; 10428 inst.instruction |= inst.operands[2].reg << 16; 10429} 10430 10431/* Neon instruction encoder helpers. */ 10432 10433/* Encodings for the different types for various Neon opcodes. */ 10434 10435/* An "invalid" code for the following tables. */ 10436#define N_INV -1u 10437 10438struct neon_tab_entry 10439{ 10440 unsigned integer; 10441 unsigned float_or_poly; 10442 unsigned scalar_or_imm; 10443}; 10444 10445/* Map overloaded Neon opcodes to their respective encodings. */ 10446#define NEON_ENC_TAB \ 10447 X(vabd, 0x0000700, 0x1200d00, N_INV), \ 10448 X(vmax, 0x0000600, 0x0000f00, N_INV), \ 10449 X(vmin, 0x0000610, 0x0200f00, N_INV), \ 10450 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ 10451 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ 10452 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ 10453 X(vadd, 0x0000800, 0x0000d00, N_INV), \ 10454 X(vsub, 0x1000800, 0x0200d00, N_INV), \ 10455 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ 10456 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ 10457 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ 10458 /* Register variants of the following two instructions are encoded as 10459 vcge / vcgt with the operands reversed. */ \ 10460 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ 10461 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ 10462 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ 10463 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ 10464 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ 10465 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ 10466 X(vmlal, 0x0800800, N_INV, 0x0800240), \ 10467 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ 10468 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ 10469 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ 10470 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ 10471 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ 10472 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ 10473 X(vshl, 0x0000400, N_INV, 0x0800510), \ 10474 X(vqshl, 0x0000410, N_INV, 0x0800710), \ 10475 X(vand, 0x0000110, N_INV, 0x0800030), \ 10476 X(vbic, 0x0100110, N_INV, 0x0800030), \ 10477 X(veor, 0x1000110, N_INV, N_INV), \ 10478 X(vorn, 0x0300110, N_INV, 0x0800010), \ 10479 X(vorr, 0x0200110, N_INV, 0x0800010), \ 10480 X(vmvn, 0x1b00580, N_INV, 0x0800030), \ 10481 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ 10482 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ 10483 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ 10484 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ 10485 X(vst1, 0x0000000, 0x0800000, N_INV), \ 10486 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ 10487 X(vst2, 0x0000100, 0x0800100, N_INV), \ 10488 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ 10489 X(vst3, 0x0000200, 0x0800200, N_INV), \ 10490 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ 10491 X(vst4, 0x0000300, 0x0800300, N_INV), \ 10492 X(vmovn, 0x1b20200, N_INV, N_INV), \ 10493 X(vtrn, 0x1b20080, N_INV, N_INV), \ 10494 X(vqmovn, 0x1b20200, N_INV, N_INV), \ 10495 X(vqmovun, 0x1b20240, N_INV, N_INV), \ 10496 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ 10497 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \ 10498 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \ 10499 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ 10500 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ 10501 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ 10502 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV) 10503 10504enum neon_opc 10505{ 10506#define X(OPC,I,F,S) N_MNEM_##OPC 10507NEON_ENC_TAB 10508#undef X 10509}; 10510 10511static const struct neon_tab_entry neon_enc_tab[] = 10512{ 10513#define X(OPC,I,F,S) { (I), (F), (S) } 10514NEON_ENC_TAB 10515#undef X 10516}; 10517 10518#define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 10519#define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 10520#define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 10521#define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 10522#define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 10523#define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 10524#define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 10525#define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 10526#define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 10527#define NEON_ENC_SINGLE(X) \ 10528 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) 10529#define NEON_ENC_DOUBLE(X) \ 10530 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) 10531 10532/* Define shapes for instruction operands. The following mnemonic characters 10533 are used in this table: 10534 10535 F - VFP S<n> register 10536 D - Neon D<n> register 10537 Q - Neon Q<n> register 10538 I - Immediate 10539 S - Scalar 10540 R - ARM register 10541 L - D<n> register list 10542 10543 This table is used to generate various data: 10544 - enumerations of the form NS_DDR to be used as arguments to 10545 neon_select_shape. 10546 - a table classifying shapes into single, double, quad, mixed. 10547 - a table used to drive neon_select_shape. 10548*/ 10549 10550#define NEON_SHAPE_DEF \ 10551 X(3, (D, D, D), DOUBLE), \ 10552 X(3, (Q, Q, Q), QUAD), \ 10553 X(3, (D, D, I), DOUBLE), \ 10554 X(3, (Q, Q, I), QUAD), \ 10555 X(3, (D, D, S), DOUBLE), \ 10556 X(3, (Q, Q, S), QUAD), \ 10557 X(2, (D, D), DOUBLE), \ 10558 X(2, (Q, Q), QUAD), \ 10559 X(2, (D, S), DOUBLE), \ 10560 X(2, (Q, S), QUAD), \ 10561 X(2, (D, R), DOUBLE), \ 10562 X(2, (Q, R), QUAD), \ 10563 X(2, (D, I), DOUBLE), \ 10564 X(2, (Q, I), QUAD), \ 10565 X(3, (D, L, D), DOUBLE), \ 10566 X(2, (D, Q), MIXED), \ 10567 X(2, (Q, D), MIXED), \ 10568 X(3, (D, Q, I), MIXED), \ 10569 X(3, (Q, D, I), MIXED), \ 10570 X(3, (Q, D, D), MIXED), \ 10571 X(3, (D, Q, Q), MIXED), \ 10572 X(3, (Q, Q, D), MIXED), \ 10573 X(3, (Q, D, S), MIXED), \ 10574 X(3, (D, Q, S), MIXED), \ 10575 X(4, (D, D, D, I), DOUBLE), \ 10576 X(4, (Q, Q, Q, I), QUAD), \ 10577 X(2, (F, F), SINGLE), \ 10578 X(3, (F, F, F), SINGLE), \ 10579 X(2, (F, I), SINGLE), \ 10580 X(2, (F, D), MIXED), \ 10581 X(2, (D, F), MIXED), \ 10582 X(3, (F, F, I), MIXED), \ 10583 X(4, (R, R, F, F), SINGLE), \ 10584 X(4, (F, F, R, R), SINGLE), \ 10585 X(3, (D, R, R), DOUBLE), \ 10586 X(3, (R, R, D), DOUBLE), \ 10587 X(2, (S, R), SINGLE), \ 10588 X(2, (R, S), SINGLE), \ 10589 X(2, (F, R), SINGLE), \ 10590 X(2, (R, F), SINGLE) 10591 10592#define S2(A,B) NS_##A##B 10593#define S3(A,B,C) NS_##A##B##C 10594#define S4(A,B,C,D) NS_##A##B##C##D 10595 10596#define X(N, L, C) S##N L 10597 10598enum neon_shape 10599{ 10600 NEON_SHAPE_DEF, 10601 NS_NULL 10602}; 10603 10604#undef X 10605#undef S2 10606#undef S3 10607#undef S4 10608 10609enum neon_shape_class 10610{ 10611 SC_SINGLE, 10612 SC_DOUBLE, 10613 SC_QUAD, 10614 SC_MIXED 10615}; 10616 10617#define X(N, L, C) SC_##C 10618 10619static enum neon_shape_class neon_shape_class[] = 10620{ 10621 NEON_SHAPE_DEF 10622}; 10623 10624#undef X 10625 10626enum neon_shape_el 10627{ 10628 SE_F, 10629 SE_D, 10630 SE_Q, 10631 SE_I, 10632 SE_S, 10633 SE_R, 10634 SE_L 10635}; 10636 10637/* Register widths of above. */ 10638static unsigned neon_shape_el_size[] = 10639{ 10640 32, 10641 64, 10642 128, 10643 0, 10644 32, 10645 32, 10646 0 10647}; 10648 10649struct neon_shape_info 10650{ 10651 unsigned els; 10652 enum neon_shape_el el[NEON_MAX_TYPE_ELS]; 10653}; 10654 10655#define S2(A,B) { SE_##A, SE_##B } 10656#define S3(A,B,C) { SE_##A, SE_##B, SE_##C } 10657#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } 10658 10659#define X(N, L, C) { N, S##N L } 10660 10661static struct neon_shape_info neon_shape_tab[] = 10662{ 10663 NEON_SHAPE_DEF 10664}; 10665 10666#undef X 10667#undef S2 10668#undef S3 10669#undef S4 10670 10671/* Bit masks used in type checking given instructions. 10672 'N_EQK' means the type must be the same as (or based on in some way) the key 10673 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is 10674 set, various other bits can be set as well in order to modify the meaning of 10675 the type constraint. */ 10676 10677enum neon_type_mask 10678{ 10679 N_S8 = 0x000001, 10680 N_S16 = 0x000002, 10681 N_S32 = 0x000004, 10682 N_S64 = 0x000008, 10683 N_U8 = 0x000010, 10684 N_U16 = 0x000020, 10685 N_U32 = 0x000040, 10686 N_U64 = 0x000080, 10687 N_I8 = 0x000100, 10688 N_I16 = 0x000200, 10689 N_I32 = 0x000400, 10690 N_I64 = 0x000800, 10691 N_8 = 0x001000, 10692 N_16 = 0x002000, 10693 N_32 = 0x004000, 10694 N_64 = 0x008000, 10695 N_P8 = 0x010000, 10696 N_P16 = 0x020000, 10697 N_F32 = 0x040000, 10698 N_F64 = 0x080000, 10699 N_KEY = 0x100000, /* key element (main type specifier). */ 10700 N_EQK = 0x200000, /* given operand has the same type & size as the key. */ 10701 N_VFP = 0x400000, /* VFP mode: operand size must match register width. */ 10702 N_DBL = 0x000001, /* if N_EQK, this operand is twice the size. */ 10703 N_HLF = 0x000002, /* if N_EQK, this operand is half the size. */ 10704 N_SGN = 0x000004, /* if N_EQK, this operand is forced to be signed. */ 10705 N_UNS = 0x000008, /* if N_EQK, this operand is forced to be unsigned. */ 10706 N_INT = 0x000010, /* if N_EQK, this operand is forced to be integer. */ 10707 N_FLT = 0x000020, /* if N_EQK, this operand is forced to be float. */ 10708 N_SIZ = 0x000040, /* if N_EQK, this operand is forced to be size-only. */ 10709 N_UTYP = 0, 10710 N_MAX_NONSPECIAL = N_F64 10711}; 10712 10713#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) 10714 10715#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) 10716#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) 10717#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) 10718#define N_SUF_32 (N_SU_32 | N_F32) 10719#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) 10720#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) 10721 10722/* Pass this as the first type argument to neon_check_type to ignore types 10723 altogether. */ 10724#define N_IGNORE_TYPE (N_KEY | N_EQK) 10725 10726/* Select a "shape" for the current instruction (describing register types or 10727 sizes) from a list of alternatives. Return NS_NULL if the current instruction 10728 doesn't fit. For non-polymorphic shapes, checking is usually done as a 10729 function of operand parsing, so this function doesn't need to be called. 10730 Shapes should be listed in order of decreasing length. */ 10731 10732static enum neon_shape 10733neon_select_shape (enum neon_shape shape, ...) 10734{ 10735 va_list ap; 10736 enum neon_shape first_shape = shape; 10737 10738 /* Fix missing optional operands. FIXME: we don't know at this point how 10739 many arguments we should have, so this makes the assumption that we have 10740 > 1. This is true of all current Neon opcodes, I think, but may not be 10741 true in the future. */ 10742 if (!inst.operands[1].present) 10743 inst.operands[1] = inst.operands[0]; 10744 10745 va_start (ap, shape); 10746 10747 for (; shape != NS_NULL; shape = va_arg (ap, int)) 10748 { 10749 unsigned j; 10750 int matches = 1; 10751 10752 for (j = 0; j < neon_shape_tab[shape].els; j++) 10753 { 10754 if (!inst.operands[j].present) 10755 { 10756 matches = 0; 10757 break; 10758 } 10759 10760 switch (neon_shape_tab[shape].el[j]) 10761 { 10762 case SE_F: 10763 if (!(inst.operands[j].isreg 10764 && inst.operands[j].isvec 10765 && inst.operands[j].issingle 10766 && !inst.operands[j].isquad)) 10767 matches = 0; 10768 break; 10769 10770 case SE_D: 10771 if (!(inst.operands[j].isreg 10772 && inst.operands[j].isvec 10773 && !inst.operands[j].isquad 10774 && !inst.operands[j].issingle)) 10775 matches = 0; 10776 break; 10777 10778 case SE_R: 10779 if (!(inst.operands[j].isreg 10780 && !inst.operands[j].isvec)) 10781 matches = 0; 10782 break; 10783 10784 case SE_Q: 10785 if (!(inst.operands[j].isreg 10786 && inst.operands[j].isvec 10787 && inst.operands[j].isquad 10788 && !inst.operands[j].issingle)) 10789 matches = 0; 10790 break; 10791 10792 case SE_I: 10793 if (!(!inst.operands[j].isreg 10794 && !inst.operands[j].isscalar)) 10795 matches = 0; 10796 break; 10797 10798 case SE_S: 10799 if (!(!inst.operands[j].isreg 10800 && inst.operands[j].isscalar)) 10801 matches = 0; 10802 break; 10803 10804 case SE_L: 10805 break; 10806 } 10807 } 10808 if (matches) 10809 break; 10810 } 10811 10812 va_end (ap); 10813 10814 if (shape == NS_NULL && first_shape != NS_NULL) 10815 first_error (_("invalid instruction shape")); 10816 10817 return shape; 10818} 10819 10820/* True if SHAPE is predominantly a quadword operation (most of the time, this 10821 means the Q bit should be set). */ 10822 10823static int 10824neon_quad (enum neon_shape shape) 10825{ 10826 return neon_shape_class[shape] == SC_QUAD; 10827} 10828 10829static void 10830neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, 10831 unsigned *g_size) 10832{ 10833 /* Allow modification to be made to types which are constrained to be 10834 based on the key element, based on bits set alongside N_EQK. */ 10835 if ((typebits & N_EQK) != 0) 10836 { 10837 if ((typebits & N_HLF) != 0) 10838 *g_size /= 2; 10839 else if ((typebits & N_DBL) != 0) 10840 *g_size *= 2; 10841 if ((typebits & N_SGN) != 0) 10842 *g_type = NT_signed; 10843 else if ((typebits & N_UNS) != 0) 10844 *g_type = NT_unsigned; 10845 else if ((typebits & N_INT) != 0) 10846 *g_type = NT_integer; 10847 else if ((typebits & N_FLT) != 0) 10848 *g_type = NT_float; 10849 else if ((typebits & N_SIZ) != 0) 10850 *g_type = NT_untyped; 10851 } 10852} 10853 10854/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" 10855 operand type, i.e. the single type specified in a Neon instruction when it 10856 is the only one given. */ 10857 10858static struct neon_type_el 10859neon_type_promote (struct neon_type_el *key, unsigned thisarg) 10860{ 10861 struct neon_type_el dest = *key; 10862 10863 assert ((thisarg & N_EQK) != 0); 10864 10865 neon_modify_type_size (thisarg, &dest.type, &dest.size); 10866 10867 return dest; 10868} 10869 10870/* Convert Neon type and size into compact bitmask representation. */ 10871 10872static enum neon_type_mask 10873type_chk_of_el_type (enum neon_el_type type, unsigned size) 10874{ 10875 switch (type) 10876 { 10877 case NT_untyped: 10878 switch (size) 10879 { 10880 case 8: return N_8; 10881 case 16: return N_16; 10882 case 32: return N_32; 10883 case 64: return N_64; 10884 default: ; 10885 } 10886 break; 10887 10888 case NT_integer: 10889 switch (size) 10890 { 10891 case 8: return N_I8; 10892 case 16: return N_I16; 10893 case 32: return N_I32; 10894 case 64: return N_I64; 10895 default: ; 10896 } 10897 break; 10898 10899 case NT_float: 10900 switch (size) 10901 { 10902 case 32: return N_F32; 10903 case 64: return N_F64; 10904 default: ; 10905 } 10906 break; 10907 10908 case NT_poly: 10909 switch (size) 10910 { 10911 case 8: return N_P8; 10912 case 16: return N_P16; 10913 default: ; 10914 } 10915 break; 10916 10917 case NT_signed: 10918 switch (size) 10919 { 10920 case 8: return N_S8; 10921 case 16: return N_S16; 10922 case 32: return N_S32; 10923 case 64: return N_S64; 10924 default: ; 10925 } 10926 break; 10927 10928 case NT_unsigned: 10929 switch (size) 10930 { 10931 case 8: return N_U8; 10932 case 16: return N_U16; 10933 case 32: return N_U32; 10934 case 64: return N_U64; 10935 default: ; 10936 } 10937 break; 10938 10939 default: ; 10940 } 10941 10942 return N_UTYP; 10943} 10944 10945/* Convert compact Neon bitmask type representation to a type and size. Only 10946 handles the case where a single bit is set in the mask. */ 10947 10948static int 10949el_type_of_type_chk (enum neon_el_type *type, unsigned *size, 10950 enum neon_type_mask mask) 10951{ 10952 if ((mask & N_EQK) != 0) 10953 return FAIL; 10954 10955 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) 10956 *size = 8; 10957 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0) 10958 *size = 16; 10959 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) 10960 *size = 32; 10961 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0) 10962 *size = 64; 10963 else 10964 return FAIL; 10965 10966 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) 10967 *type = NT_signed; 10968 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) 10969 *type = NT_unsigned; 10970 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) 10971 *type = NT_integer; 10972 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) 10973 *type = NT_untyped; 10974 else if ((mask & (N_P8 | N_P16)) != 0) 10975 *type = NT_poly; 10976 else if ((mask & (N_F32 | N_F64)) != 0) 10977 *type = NT_float; 10978 else 10979 return FAIL; 10980 10981 return SUCCESS; 10982} 10983 10984/* Modify a bitmask of allowed types. This is only needed for type 10985 relaxation. */ 10986 10987static unsigned 10988modify_types_allowed (unsigned allowed, unsigned mods) 10989{ 10990 unsigned size; 10991 enum neon_el_type type; 10992 unsigned destmask; 10993 int i; 10994 10995 destmask = 0; 10996 10997 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) 10998 { 10999 if (el_type_of_type_chk (&type, &size, allowed & i) == SUCCESS) 11000 { 11001 neon_modify_type_size (mods, &type, &size); 11002 destmask |= type_chk_of_el_type (type, size); 11003 } 11004 } 11005 11006 return destmask; 11007} 11008 11009/* Check type and return type classification. 11010 The manual states (paraphrase): If one datatype is given, it indicates the 11011 type given in: 11012 - the second operand, if there is one 11013 - the operand, if there is no second operand 11014 - the result, if there are no operands. 11015 This isn't quite good enough though, so we use a concept of a "key" datatype 11016 which is set on a per-instruction basis, which is the one which matters when 11017 only one data type is written. 11018 Note: this function has side-effects (e.g. filling in missing operands). All 11019 Neon instructions should call it before performing bit encoding. */ 11020 11021static struct neon_type_el 11022neon_check_type (unsigned els, enum neon_shape ns, ...) 11023{ 11024 va_list ap; 11025 unsigned i, pass, key_el = 0; 11026 unsigned types[NEON_MAX_TYPE_ELS]; 11027 enum neon_el_type k_type = NT_invtype; 11028 unsigned k_size = -1u; 11029 struct neon_type_el badtype = {NT_invtype, -1}; 11030 unsigned key_allowed = 0; 11031 11032 /* Optional registers in Neon instructions are always (not) in operand 1. 11033 Fill in the missing operand here, if it was omitted. */ 11034 if (els > 1 && !inst.operands[1].present) 11035 inst.operands[1] = inst.operands[0]; 11036 11037 /* Suck up all the varargs. */ 11038 va_start (ap, ns); 11039 for (i = 0; i < els; i++) 11040 { 11041 unsigned thisarg = va_arg (ap, unsigned); 11042 if (thisarg == N_IGNORE_TYPE) 11043 { 11044 va_end (ap); 11045 return badtype; 11046 } 11047 types[i] = thisarg; 11048 if ((thisarg & N_KEY) != 0) 11049 key_el = i; 11050 } 11051 va_end (ap); 11052 11053 if (inst.vectype.elems > 0) 11054 for (i = 0; i < els; i++) 11055 if (inst.operands[i].vectype.type != NT_invtype) 11056 { 11057 first_error (_("types specified in both the mnemonic and operands")); 11058 return badtype; 11059 } 11060 11061 /* Duplicate inst.vectype elements here as necessary. 11062 FIXME: No idea if this is exactly the same as the ARM assembler, 11063 particularly when an insn takes one register and one non-register 11064 operand. */ 11065 if (inst.vectype.elems == 1 && els > 1) 11066 { 11067 unsigned j; 11068 inst.vectype.elems = els; 11069 inst.vectype.el[key_el] = inst.vectype.el[0]; 11070 for (j = 0; j < els; j++) 11071 if (j != key_el) 11072 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], 11073 types[j]); 11074 } 11075 else if (inst.vectype.elems == 0 && els > 0) 11076 { 11077 unsigned j; 11078 /* No types were given after the mnemonic, so look for types specified 11079 after each operand. We allow some flexibility here; as long as the 11080 "key" operand has a type, we can infer the others. */ 11081 for (j = 0; j < els; j++) 11082 if (inst.operands[j].vectype.type != NT_invtype) 11083 inst.vectype.el[j] = inst.operands[j].vectype; 11084 11085 if (inst.operands[key_el].vectype.type != NT_invtype) 11086 { 11087 for (j = 0; j < els; j++) 11088 if (inst.operands[j].vectype.type == NT_invtype) 11089 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], 11090 types[j]); 11091 } 11092 else 11093 { 11094 first_error (_("operand types can't be inferred")); 11095 return badtype; 11096 } 11097 } 11098 else if (inst.vectype.elems != els) 11099 { 11100 first_error (_("type specifier has the wrong number of parts")); 11101 return badtype; 11102 } 11103 11104 for (pass = 0; pass < 2; pass++) 11105 { 11106 for (i = 0; i < els; i++) 11107 { 11108 unsigned thisarg = types[i]; 11109 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) 11110 ? modify_types_allowed (key_allowed, thisarg) : thisarg; 11111 enum neon_el_type g_type = inst.vectype.el[i].type; 11112 unsigned g_size = inst.vectype.el[i].size; 11113 11114 /* Decay more-specific signed & unsigned types to sign-insensitive 11115 integer types if sign-specific variants are unavailable. */ 11116 if ((g_type == NT_signed || g_type == NT_unsigned) 11117 && (types_allowed & N_SU_ALL) == 0) 11118 g_type = NT_integer; 11119 11120 /* If only untyped args are allowed, decay any more specific types to 11121 them. Some instructions only care about signs for some element 11122 sizes, so handle that properly. */ 11123 if ((g_size == 8 && (types_allowed & N_8) != 0) 11124 || (g_size == 16 && (types_allowed & N_16) != 0) 11125 || (g_size == 32 && (types_allowed & N_32) != 0) 11126 || (g_size == 64 && (types_allowed & N_64) != 0)) 11127 g_type = NT_untyped; 11128 11129 if (pass == 0) 11130 { 11131 if ((thisarg & N_KEY) != 0) 11132 { 11133 k_type = g_type; 11134 k_size = g_size; 11135 key_allowed = thisarg & ~N_KEY; 11136 } 11137 } 11138 else 11139 { 11140 if ((thisarg & N_VFP) != 0) 11141 { 11142 enum neon_shape_el regshape = neon_shape_tab[ns].el[i]; 11143 unsigned regwidth = neon_shape_el_size[regshape], match; 11144 11145 /* In VFP mode, operands must match register widths. If we 11146 have a key operand, use its width, else use the width of 11147 the current operand. */ 11148 if (k_size != -1u) 11149 match = k_size; 11150 else 11151 match = g_size; 11152 11153 if (regwidth != match) 11154 { 11155 first_error (_("operand size must match register width")); 11156 return badtype; 11157 } 11158 } 11159 11160 if ((thisarg & N_EQK) == 0) 11161 { 11162 unsigned given_type = type_chk_of_el_type (g_type, g_size); 11163 11164 if ((given_type & types_allowed) == 0) 11165 { 11166 first_error (_("bad type in Neon instruction")); 11167 return badtype; 11168 } 11169 } 11170 else 11171 { 11172 enum neon_el_type mod_k_type = k_type; 11173 unsigned mod_k_size = k_size; 11174 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); 11175 if (g_type != mod_k_type || g_size != mod_k_size) 11176 { 11177 first_error (_("inconsistent types in Neon instruction")); 11178 return badtype; 11179 } 11180 } 11181 } 11182 } 11183 } 11184 11185 return inst.vectype.el[key_el]; 11186} 11187 11188/* Neon-style VFP instruction forwarding. */ 11189 11190/* Thumb VFP instructions have 0xE in the condition field. */ 11191 11192static void 11193do_vfp_cond_or_thumb (void) 11194{ 11195 if (thumb_mode) 11196 inst.instruction |= 0xe0000000; 11197 else 11198 inst.instruction |= inst.cond << 28; 11199} 11200 11201/* Look up and encode a simple mnemonic, for use as a helper function for the 11202 Neon-style VFP syntax. This avoids duplication of bits of the insns table, 11203 etc. It is assumed that operand parsing has already been done, and that the 11204 operands are in the form expected by the given opcode (this isn't necessarily 11205 the same as the form in which they were parsed, hence some massaging must 11206 take place before this function is called). 11207 Checks current arch version against that in the looked-up opcode. */ 11208 11209static void 11210do_vfp_nsyn_opcode (const char *opname) 11211{ 11212 const struct asm_opcode *opcode; 11213 11214 opcode = hash_find (arm_ops_hsh, opname); 11215 11216 if (!opcode) 11217 abort (); 11218 11219 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, 11220 thumb_mode ? *opcode->tvariant : *opcode->avariant), 11221 _(BAD_FPU)); 11222 11223 if (thumb_mode) 11224 { 11225 inst.instruction = opcode->tvalue; 11226 opcode->tencode (); 11227 } 11228 else 11229 { 11230 inst.instruction = (inst.cond << 28) | opcode->avalue; 11231 opcode->aencode (); 11232 } 11233} 11234 11235static void 11236do_vfp_nsyn_add_sub (enum neon_shape rs) 11237{ 11238 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; 11239 11240 if (rs == NS_FFF) 11241 { 11242 if (is_add) 11243 do_vfp_nsyn_opcode ("fadds"); 11244 else 11245 do_vfp_nsyn_opcode ("fsubs"); 11246 } 11247 else 11248 { 11249 if (is_add) 11250 do_vfp_nsyn_opcode ("faddd"); 11251 else 11252 do_vfp_nsyn_opcode ("fsubd"); 11253 } 11254} 11255 11256/* Check operand types to see if this is a VFP instruction, and if so call 11257 PFN (). */ 11258 11259static int 11260try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) 11261{ 11262 enum neon_shape rs; 11263 struct neon_type_el et; 11264 11265 switch (args) 11266 { 11267 case 2: 11268 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 11269 et = neon_check_type (2, rs, 11270 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11271 break; 11272 11273 case 3: 11274 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 11275 et = neon_check_type (3, rs, 11276 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11277 break; 11278 11279 default: 11280 abort (); 11281 } 11282 11283 if (et.type != NT_invtype) 11284 { 11285 pfn (rs); 11286 return SUCCESS; 11287 } 11288 else 11289 inst.error = NULL; 11290 11291 return FAIL; 11292} 11293 11294static void 11295do_vfp_nsyn_mla_mls (enum neon_shape rs) 11296{ 11297 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; 11298 11299 if (rs == NS_FFF) 11300 { 11301 if (is_mla) 11302 do_vfp_nsyn_opcode ("fmacs"); 11303 else 11304 do_vfp_nsyn_opcode ("fmscs"); 11305 } 11306 else 11307 { 11308 if (is_mla) 11309 do_vfp_nsyn_opcode ("fmacd"); 11310 else 11311 do_vfp_nsyn_opcode ("fmscd"); 11312 } 11313} 11314 11315static void 11316do_vfp_nsyn_mul (enum neon_shape rs) 11317{ 11318 if (rs == NS_FFF) 11319 do_vfp_nsyn_opcode ("fmuls"); 11320 else 11321 do_vfp_nsyn_opcode ("fmuld"); 11322} 11323 11324static void 11325do_vfp_nsyn_abs_neg (enum neon_shape rs) 11326{ 11327 int is_neg = (inst.instruction & 0x80) != 0; 11328 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); 11329 11330 if (rs == NS_FF) 11331 { 11332 if (is_neg) 11333 do_vfp_nsyn_opcode ("fnegs"); 11334 else 11335 do_vfp_nsyn_opcode ("fabss"); 11336 } 11337 else 11338 { 11339 if (is_neg) 11340 do_vfp_nsyn_opcode ("fnegd"); 11341 else 11342 do_vfp_nsyn_opcode ("fabsd"); 11343 } 11344} 11345 11346/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision 11347 insns belong to Neon, and are handled elsewhere. */ 11348 11349static void 11350do_vfp_nsyn_ldm_stm (int is_dbmode) 11351{ 11352 int is_ldm = (inst.instruction & (1 << 20)) != 0; 11353 if (is_ldm) 11354 { 11355 if (is_dbmode) 11356 do_vfp_nsyn_opcode ("fldmdbs"); 11357 else 11358 do_vfp_nsyn_opcode ("fldmias"); 11359 } 11360 else 11361 { 11362 if (is_dbmode) 11363 do_vfp_nsyn_opcode ("fstmdbs"); 11364 else 11365 do_vfp_nsyn_opcode ("fstmias"); 11366 } 11367} 11368 11369static void 11370do_vfp_nsyn_sqrt (void) 11371{ 11372 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 11373 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11374 11375 if (rs == NS_FF) 11376 do_vfp_nsyn_opcode ("fsqrts"); 11377 else 11378 do_vfp_nsyn_opcode ("fsqrtd"); 11379} 11380 11381static void 11382do_vfp_nsyn_div (void) 11383{ 11384 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 11385 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, 11386 N_F32 | N_F64 | N_KEY | N_VFP); 11387 11388 if (rs == NS_FFF) 11389 do_vfp_nsyn_opcode ("fdivs"); 11390 else 11391 do_vfp_nsyn_opcode ("fdivd"); 11392} 11393 11394static void 11395do_vfp_nsyn_nmul (void) 11396{ 11397 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 11398 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, 11399 N_F32 | N_F64 | N_KEY | N_VFP); 11400 11401 if (rs == NS_FFF) 11402 { 11403 inst.instruction = NEON_ENC_SINGLE (inst.instruction); 11404 do_vfp_sp_dyadic (); 11405 } 11406 else 11407 { 11408 inst.instruction = NEON_ENC_DOUBLE (inst.instruction); 11409 do_vfp_dp_rd_rn_rm (); 11410 } 11411 do_vfp_cond_or_thumb (); 11412} 11413 11414static void 11415do_vfp_nsyn_cmp (void) 11416{ 11417 if (inst.operands[1].isreg) 11418 { 11419 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 11420 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11421 11422 if (rs == NS_FF) 11423 { 11424 inst.instruction = NEON_ENC_SINGLE (inst.instruction); 11425 do_vfp_sp_monadic (); 11426 } 11427 else 11428 { 11429 inst.instruction = NEON_ENC_DOUBLE (inst.instruction); 11430 do_vfp_dp_rd_rm (); 11431 } 11432 } 11433 else 11434 { 11435 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); 11436 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); 11437 11438 switch (inst.instruction & 0x0fffffff) 11439 { 11440 case N_MNEM_vcmp: 11441 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; 11442 break; 11443 case N_MNEM_vcmpe: 11444 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; 11445 break; 11446 default: 11447 abort (); 11448 } 11449 11450 if (rs == NS_FI) 11451 { 11452 inst.instruction = NEON_ENC_SINGLE (inst.instruction); 11453 do_vfp_sp_compare_z (); 11454 } 11455 else 11456 { 11457 inst.instruction = NEON_ENC_DOUBLE (inst.instruction); 11458 do_vfp_dp_rd (); 11459 } 11460 } 11461 do_vfp_cond_or_thumb (); 11462} 11463 11464static void 11465nsyn_insert_sp (void) 11466{ 11467 inst.operands[1] = inst.operands[0]; 11468 memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); 11469 inst.operands[0].reg = 13; 11470 inst.operands[0].isreg = 1; 11471 inst.operands[0].writeback = 1; 11472 inst.operands[0].present = 1; 11473} 11474 11475static void 11476do_vfp_nsyn_push (void) 11477{ 11478 nsyn_insert_sp (); 11479 if (inst.operands[1].issingle) 11480 do_vfp_nsyn_opcode ("fstmdbs"); 11481 else 11482 do_vfp_nsyn_opcode ("fstmdbd"); 11483} 11484 11485static void 11486do_vfp_nsyn_pop (void) 11487{ 11488 nsyn_insert_sp (); 11489 if (inst.operands[1].issingle) 11490 do_vfp_nsyn_opcode ("fldmias"); 11491 else 11492 do_vfp_nsyn_opcode ("fldmiad"); 11493} 11494 11495/* Fix up Neon data-processing instructions, ORing in the correct bits for 11496 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ 11497 11498static unsigned 11499neon_dp_fixup (unsigned i) 11500{ 11501 if (thumb_mode) 11502 { 11503 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ 11504 if (i & (1 << 24)) 11505 i |= 1 << 28; 11506 11507 i &= ~(1 << 24); 11508 11509 i |= 0xef000000; 11510 } 11511 else 11512 i |= 0xf2000000; 11513 11514 return i; 11515} 11516 11517/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 11518 (0, 1, 2, 3). */ 11519 11520static unsigned 11521neon_logbits (unsigned x) 11522{ 11523 return ffs (x) - 4; 11524} 11525 11526#define LOW4(R) ((R) & 0xf) 11527#define HI1(R) (((R) >> 4) & 1) 11528 11529/* Encode insns with bit pattern: 11530 11531 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| 11532 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | 11533 11534 SIZE is passed in bits. -1 means size field isn't changed, in case it has a 11535 different meaning for some instruction. */ 11536 11537static void 11538neon_three_same (int isquad, int ubit, int size) 11539{ 11540 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 11541 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 11542 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 11543 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 11544 inst.instruction |= LOW4 (inst.operands[2].reg); 11545 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 11546 inst.instruction |= (isquad != 0) << 6; 11547 inst.instruction |= (ubit != 0) << 24; 11548 if (size != -1) 11549 inst.instruction |= neon_logbits (size) << 20; 11550 11551 inst.instruction = neon_dp_fixup (inst.instruction); 11552} 11553 11554/* Encode instructions of the form: 11555 11556 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| 11557 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | 11558 11559 Don't write size if SIZE == -1. */ 11560 11561static void 11562neon_two_same (int qbit, int ubit, int size) 11563{ 11564 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 11565 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 11566 inst.instruction |= LOW4 (inst.operands[1].reg); 11567 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 11568 inst.instruction |= (qbit != 0) << 6; 11569 inst.instruction |= (ubit != 0) << 24; 11570 11571 if (size != -1) 11572 inst.instruction |= neon_logbits (size) << 18; 11573 11574 inst.instruction = neon_dp_fixup (inst.instruction); 11575} 11576 11577/* Neon instruction encoders, in approximate order of appearance. */ 11578 11579static void 11580do_neon_dyadic_i_su (void) 11581{ 11582 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11583 struct neon_type_el et = neon_check_type (3, rs, 11584 N_EQK, N_EQK, N_SU_32 | N_KEY); 11585 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11586} 11587 11588static void 11589do_neon_dyadic_i64_su (void) 11590{ 11591 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11592 struct neon_type_el et = neon_check_type (3, rs, 11593 N_EQK, N_EQK, N_SU_ALL | N_KEY); 11594 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11595} 11596 11597static void 11598neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, 11599 unsigned immbits) 11600{ 11601 unsigned size = et.size >> 3; 11602 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 11603 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 11604 inst.instruction |= LOW4 (inst.operands[1].reg); 11605 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 11606 inst.instruction |= (isquad != 0) << 6; 11607 inst.instruction |= immbits << 16; 11608 inst.instruction |= (size >> 3) << 7; 11609 inst.instruction |= (size & 0x7) << 19; 11610 if (write_ubit) 11611 inst.instruction |= (uval != 0) << 24; 11612 11613 inst.instruction = neon_dp_fixup (inst.instruction); 11614} 11615 11616static void 11617do_neon_shl_imm (void) 11618{ 11619 if (!inst.operands[2].isreg) 11620 { 11621 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 11622 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); 11623 inst.instruction = NEON_ENC_IMMED (inst.instruction); 11624 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm); 11625 } 11626 else 11627 { 11628 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11629 struct neon_type_el et = neon_check_type (3, rs, 11630 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); 11631 unsigned int tmp; 11632 11633 /* VSHL/VQSHL 3-register variants have syntax such as: 11634 vshl.xx Dd, Dm, Dn 11635 whereas other 3-register operations encoded by neon_three_same have 11636 syntax like: 11637 vadd.xx Dd, Dn, Dm 11638 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg 11639 here. */ 11640 tmp = inst.operands[2].reg; 11641 inst.operands[2].reg = inst.operands[1].reg; 11642 inst.operands[1].reg = tmp; 11643 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 11644 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11645 } 11646} 11647 11648static void 11649do_neon_qshl_imm (void) 11650{ 11651 if (!inst.operands[2].isreg) 11652 { 11653 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 11654 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); 11655 11656 inst.instruction = NEON_ENC_IMMED (inst.instruction); 11657 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, 11658 inst.operands[2].imm); 11659 } 11660 else 11661 { 11662 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11663 struct neon_type_el et = neon_check_type (3, rs, 11664 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); 11665 unsigned int tmp; 11666 11667 /* See note in do_neon_shl_imm. */ 11668 tmp = inst.operands[2].reg; 11669 inst.operands[2].reg = inst.operands[1].reg; 11670 inst.operands[1].reg = tmp; 11671 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 11672 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11673 } 11674} 11675 11676static void 11677do_neon_rshl (void) 11678{ 11679 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11680 struct neon_type_el et = neon_check_type (3, rs, 11681 N_EQK, N_EQK, N_SU_ALL | N_KEY); 11682 unsigned int tmp; 11683 11684 tmp = inst.operands[2].reg; 11685 inst.operands[2].reg = inst.operands[1].reg; 11686 inst.operands[1].reg = tmp; 11687 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11688} 11689 11690static int 11691neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) 11692{ 11693 /* Handle .I8 pseudo-instructions. */ 11694 if (size == 8) 11695 { 11696 /* Unfortunately, this will make everything apart from zero out-of-range. 11697 FIXME is this the intended semantics? There doesn't seem much point in 11698 accepting .I8 if so. */ 11699 immediate |= immediate << 8; 11700 size = 16; 11701 } 11702 11703 if (size >= 32) 11704 { 11705 if (immediate == (immediate & 0x000000ff)) 11706 { 11707 *immbits = immediate; 11708 return 0x1; 11709 } 11710 else if (immediate == (immediate & 0x0000ff00)) 11711 { 11712 *immbits = immediate >> 8; 11713 return 0x3; 11714 } 11715 else if (immediate == (immediate & 0x00ff0000)) 11716 { 11717 *immbits = immediate >> 16; 11718 return 0x5; 11719 } 11720 else if (immediate == (immediate & 0xff000000)) 11721 { 11722 *immbits = immediate >> 24; 11723 return 0x7; 11724 } 11725 if ((immediate & 0xffff) != (immediate >> 16)) 11726 goto bad_immediate; 11727 immediate &= 0xffff; 11728 } 11729 11730 if (immediate == (immediate & 0x000000ff)) 11731 { 11732 *immbits = immediate; 11733 return 0x9; 11734 } 11735 else if (immediate == (immediate & 0x0000ff00)) 11736 { 11737 *immbits = immediate >> 8; 11738 return 0xb; 11739 } 11740 11741 bad_immediate: 11742 first_error (_("immediate value out of range")); 11743 return FAIL; 11744} 11745 11746/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits 11747 A, B, C, D. */ 11748 11749static int 11750neon_bits_same_in_bytes (unsigned imm) 11751{ 11752 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) 11753 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) 11754 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) 11755 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); 11756} 11757 11758/* For immediate of above form, return 0bABCD. */ 11759 11760static unsigned 11761neon_squash_bits (unsigned imm) 11762{ 11763 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) 11764 | ((imm & 0x01000000) >> 21); 11765} 11766 11767/* Compress quarter-float representation to 0b...000 abcdefgh. */ 11768 11769static unsigned 11770neon_qfloat_bits (unsigned imm) 11771{ 11772 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); 11773} 11774 11775/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into 11776 the instruction. *OP is passed as the initial value of the op field, and 11777 may be set to a different value depending on the constant (i.e. 11778 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not 11779 MVN). If the immediate looks like a repeated parttern then also 11780 try smaller element sizes. */ 11781 11782static int 11783neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, 11784 unsigned *immbits, int *op, int size, 11785 enum neon_el_type type) 11786{ 11787 /* Only permit float immediates (including 0.0/-0.0) if the operand type is 11788 float. */ 11789 if (type == NT_float && !float_p) 11790 return FAIL; 11791 11792 if (type == NT_float && is_quarter_float (immlo) && immhi == 0) 11793 { 11794 if (size != 32 || *op == 1) 11795 return FAIL; 11796 *immbits = neon_qfloat_bits (immlo); 11797 return 0xf; 11798 } 11799 11800 if (size == 64) 11801 { 11802 if (neon_bits_same_in_bytes (immhi) 11803 && neon_bits_same_in_bytes (immlo)) 11804 { 11805 if (*op == 1) 11806 return FAIL; 11807 *immbits = (neon_squash_bits (immhi) << 4) 11808 | neon_squash_bits (immlo); 11809 *op = 1; 11810 return 0xe; 11811 } 11812 11813 if (immhi != immlo) 11814 return FAIL; 11815 } 11816 11817 if (size >= 32) 11818 { 11819 if (immlo == (immlo & 0x000000ff)) 11820 { 11821 *immbits = immlo; 11822 return 0x0; 11823 } 11824 else if (immlo == (immlo & 0x0000ff00)) 11825 { 11826 *immbits = immlo >> 8; 11827 return 0x2; 11828 } 11829 else if (immlo == (immlo & 0x00ff0000)) 11830 { 11831 *immbits = immlo >> 16; 11832 return 0x4; 11833 } 11834 else if (immlo == (immlo & 0xff000000)) 11835 { 11836 *immbits = immlo >> 24; 11837 return 0x6; 11838 } 11839 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) 11840 { 11841 *immbits = (immlo >> 8) & 0xff; 11842 return 0xc; 11843 } 11844 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) 11845 { 11846 *immbits = (immlo >> 16) & 0xff; 11847 return 0xd; 11848 } 11849 11850 if ((immlo & 0xffff) != (immlo >> 16)) 11851 return FAIL; 11852 immlo &= 0xffff; 11853 } 11854 11855 if (size >= 16) 11856 { 11857 if (immlo == (immlo & 0x000000ff)) 11858 { 11859 *immbits = immlo; 11860 return 0x8; 11861 } 11862 else if (immlo == (immlo & 0x0000ff00)) 11863 { 11864 *immbits = immlo >> 8; 11865 return 0xa; 11866 } 11867 11868 if ((immlo & 0xff) != (immlo >> 8)) 11869 return FAIL; 11870 immlo &= 0xff; 11871 } 11872 11873 if (immlo == (immlo & 0x000000ff)) 11874 { 11875 /* Don't allow MVN with 8-bit immediate. */ 11876 if (*op == 1) 11877 return FAIL; 11878 *immbits = immlo; 11879 return 0xe; 11880 } 11881 11882 return FAIL; 11883} 11884 11885/* Write immediate bits [7:0] to the following locations: 11886 11887 |28/24|23 19|18 16|15 4|3 0| 11888 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| 11889 11890 This function is used by VMOV/VMVN/VORR/VBIC. */ 11891 11892static void 11893neon_write_immbits (unsigned immbits) 11894{ 11895 inst.instruction |= immbits & 0xf; 11896 inst.instruction |= ((immbits >> 4) & 0x7) << 16; 11897 inst.instruction |= ((immbits >> 7) & 0x1) << 24; 11898} 11899 11900/* Invert low-order SIZE bits of XHI:XLO. */ 11901 11902static void 11903neon_invert_size (unsigned *xlo, unsigned *xhi, int size) 11904{ 11905 unsigned immlo = xlo ? *xlo : 0; 11906 unsigned immhi = xhi ? *xhi : 0; 11907 11908 switch (size) 11909 { 11910 case 8: 11911 immlo = (~immlo) & 0xff; 11912 break; 11913 11914 case 16: 11915 immlo = (~immlo) & 0xffff; 11916 break; 11917 11918 case 64: 11919 immhi = (~immhi) & 0xffffffff; 11920 /* fall through. */ 11921 11922 case 32: 11923 immlo = (~immlo) & 0xffffffff; 11924 break; 11925 11926 default: 11927 abort (); 11928 } 11929 11930 if (xlo) 11931 *xlo = immlo; 11932 11933 if (xhi) 11934 *xhi = immhi; 11935} 11936 11937static void 11938do_neon_logic (void) 11939{ 11940 if (inst.operands[2].present && inst.operands[2].isreg) 11941 { 11942 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11943 neon_check_type (3, rs, N_IGNORE_TYPE); 11944 /* U bit and size field were set as part of the bitmask. */ 11945 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 11946 neon_three_same (neon_quad (rs), 0, -1); 11947 } 11948 else 11949 { 11950 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); 11951 struct neon_type_el et = neon_check_type (2, rs, 11952 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); 11953 enum neon_opc opcode = inst.instruction & 0x0fffffff; 11954 unsigned immbits; 11955 int cmode; 11956 11957 if (et.type == NT_invtype) 11958 return; 11959 11960 inst.instruction = NEON_ENC_IMMED (inst.instruction); 11961 11962 immbits = inst.operands[1].imm; 11963 if (et.size == 64) 11964 { 11965 /* .i64 is a pseudo-op, so the immediate must be a repeating 11966 pattern. */ 11967 if (immbits != (inst.operands[1].regisimm ? 11968 inst.operands[1].reg : 0)) 11969 { 11970 /* Set immbits to an invalid constant. */ 11971 immbits = 0xdeadbeef; 11972 } 11973 } 11974 11975 switch (opcode) 11976 { 11977 case N_MNEM_vbic: 11978 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 11979 break; 11980 11981 case N_MNEM_vorr: 11982 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 11983 break; 11984 11985 case N_MNEM_vand: 11986 /* Pseudo-instruction for VBIC. */ 11987 neon_invert_size (&immbits, 0, et.size); 11988 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 11989 break; 11990 11991 case N_MNEM_vorn: 11992 /* Pseudo-instruction for VORR. */ 11993 neon_invert_size (&immbits, 0, et.size); 11994 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 11995 break; 11996 11997 default: 11998 abort (); 11999 } 12000 12001 if (cmode == FAIL) 12002 return; 12003 12004 inst.instruction |= neon_quad (rs) << 6; 12005 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12006 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12007 inst.instruction |= cmode << 8; 12008 neon_write_immbits (immbits); 12009 12010 inst.instruction = neon_dp_fixup (inst.instruction); 12011 } 12012} 12013 12014static void 12015do_neon_bitfield (void) 12016{ 12017 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12018 neon_check_type (3, rs, N_IGNORE_TYPE); 12019 neon_three_same (neon_quad (rs), 0, -1); 12020} 12021 12022static void 12023neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, 12024 unsigned destbits) 12025{ 12026 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12027 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, 12028 types | N_KEY); 12029 if (et.type == NT_float) 12030 { 12031 inst.instruction = NEON_ENC_FLOAT (inst.instruction); 12032 neon_three_same (neon_quad (rs), 0, -1); 12033 } 12034 else 12035 { 12036 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12037 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); 12038 } 12039} 12040 12041static void 12042do_neon_dyadic_if_su (void) 12043{ 12044 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); 12045} 12046 12047static void 12048do_neon_dyadic_if_su_d (void) 12049{ 12050 /* This version only allow D registers, but that constraint is enforced during 12051 operand parsing so we don't need to do anything extra here. */ 12052 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); 12053} 12054 12055static void 12056do_neon_dyadic_if_i_d (void) 12057{ 12058 /* The "untyped" case can't happen. Do this to stop the "U" bit being 12059 affected if we specify unsigned args. */ 12060 neon_dyadic_misc (NT_untyped, N_IF_32, 0); 12061} 12062 12063enum vfp_or_neon_is_neon_bits 12064{ 12065 NEON_CHECK_CC = 1, 12066 NEON_CHECK_ARCH = 2 12067}; 12068 12069/* Call this function if an instruction which may have belonged to the VFP or 12070 Neon instruction sets, but turned out to be a Neon instruction (due to the 12071 operand types involved, etc.). We have to check and/or fix-up a couple of 12072 things: 12073 12074 - Make sure the user hasn't attempted to make a Neon instruction 12075 conditional. 12076 - Alter the value in the condition code field if necessary. 12077 - Make sure that the arch supports Neon instructions. 12078 12079 Which of these operations take place depends on bits from enum 12080 vfp_or_neon_is_neon_bits. 12081 12082 WARNING: This function has side effects! If NEON_CHECK_CC is used and the 12083 current instruction's condition is COND_ALWAYS, the condition field is 12084 changed to inst.uncond_value. This is necessary because instructions shared 12085 between VFP and Neon may be conditional for the VFP variants only, and the 12086 unconditional Neon version must have, e.g., 0xF in the condition field. */ 12087 12088static int 12089vfp_or_neon_is_neon (unsigned check) 12090{ 12091 /* Conditions are always legal in Thumb mode (IT blocks). */ 12092 if (!thumb_mode && (check & NEON_CHECK_CC)) 12093 { 12094 if (inst.cond != COND_ALWAYS) 12095 { 12096 first_error (_(BAD_COND)); 12097 return FAIL; 12098 } 12099 if (inst.uncond_value != -1) 12100 inst.instruction |= inst.uncond_value << 28; 12101 } 12102 12103 if ((check & NEON_CHECK_ARCH) 12104 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) 12105 { 12106 first_error (_(BAD_FPU)); 12107 return FAIL; 12108 } 12109 12110 return SUCCESS; 12111} 12112 12113static void 12114do_neon_addsub_if_i (void) 12115{ 12116 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) 12117 return; 12118 12119 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12120 return; 12121 12122 /* The "untyped" case can't happen. Do this to stop the "U" bit being 12123 affected if we specify unsigned args. */ 12124 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); 12125} 12126 12127/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the 12128 result to be: 12129 V<op> A,B (A is operand 0, B is operand 2) 12130 to mean: 12131 V<op> A,B,A 12132 not: 12133 V<op> A,B,B 12134 so handle that case specially. */ 12135 12136static void 12137neon_exchange_operands (void) 12138{ 12139 void *scratch = alloca (sizeof (inst.operands[0])); 12140 if (inst.operands[1].present) 12141 { 12142 /* Swap operands[1] and operands[2]. */ 12143 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); 12144 inst.operands[1] = inst.operands[2]; 12145 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); 12146 } 12147 else 12148 { 12149 inst.operands[1] = inst.operands[2]; 12150 inst.operands[2] = inst.operands[0]; 12151 } 12152} 12153 12154static void 12155neon_compare (unsigned regtypes, unsigned immtypes, int invert) 12156{ 12157 if (inst.operands[2].isreg) 12158 { 12159 if (invert) 12160 neon_exchange_operands (); 12161 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); 12162 } 12163 else 12164 { 12165 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12166 struct neon_type_el et = neon_check_type (2, rs, 12167 N_EQK | N_SIZ, immtypes | N_KEY); 12168 12169 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12170 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12171 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12172 inst.instruction |= LOW4 (inst.operands[1].reg); 12173 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12174 inst.instruction |= neon_quad (rs) << 6; 12175 inst.instruction |= (et.type == NT_float) << 10; 12176 inst.instruction |= neon_logbits (et.size) << 18; 12177 12178 inst.instruction = neon_dp_fixup (inst.instruction); 12179 } 12180} 12181 12182static void 12183do_neon_cmp (void) 12184{ 12185 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); 12186} 12187 12188static void 12189do_neon_cmp_inv (void) 12190{ 12191 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); 12192} 12193 12194static void 12195do_neon_ceq (void) 12196{ 12197 neon_compare (N_IF_32, N_IF_32, FALSE); 12198} 12199 12200/* For multiply instructions, we have the possibility of 16-bit or 32-bit 12201 scalars, which are encoded in 5 bits, M : Rm. 12202 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in 12203 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the 12204 index in M. */ 12205 12206static unsigned 12207neon_scalar_for_mul (unsigned scalar, unsigned elsize) 12208{ 12209 unsigned regno = NEON_SCALAR_REG (scalar); 12210 unsigned elno = NEON_SCALAR_INDEX (scalar); 12211 12212 switch (elsize) 12213 { 12214 case 16: 12215 if (regno > 7 || elno > 3) 12216 goto bad_scalar; 12217 return regno | (elno << 3); 12218 12219 case 32: 12220 if (regno > 15 || elno > 1) 12221 goto bad_scalar; 12222 return regno | (elno << 4); 12223 12224 default: 12225 bad_scalar: 12226 first_error (_("scalar out of range for multiply instruction")); 12227 } 12228 12229 return 0; 12230} 12231 12232/* Encode multiply / multiply-accumulate scalar instructions. */ 12233 12234static void 12235neon_mul_mac (struct neon_type_el et, int ubit) 12236{ 12237 unsigned scalar; 12238 12239 /* Give a more helpful error message if we have an invalid type. */ 12240 if (et.type == NT_invtype) 12241 return; 12242 12243 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); 12244 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12245 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12246 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 12247 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 12248 inst.instruction |= LOW4 (scalar); 12249 inst.instruction |= HI1 (scalar) << 5; 12250 inst.instruction |= (et.type == NT_float) << 8; 12251 inst.instruction |= neon_logbits (et.size) << 20; 12252 inst.instruction |= (ubit != 0) << 24; 12253 12254 inst.instruction = neon_dp_fixup (inst.instruction); 12255} 12256 12257static void 12258do_neon_mac_maybe_scalar (void) 12259{ 12260 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) 12261 return; 12262 12263 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12264 return; 12265 12266 if (inst.operands[2].isscalar) 12267 { 12268 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); 12269 struct neon_type_el et = neon_check_type (3, rs, 12270 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); 12271 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 12272 neon_mul_mac (et, neon_quad (rs)); 12273 } 12274 else 12275 { 12276 /* The "untyped" case can't happen. Do this to stop the "U" bit being 12277 affected if we specify unsigned args. */ 12278 neon_dyadic_misc (NT_untyped, N_IF_32, 0); 12279 } 12280} 12281 12282static void 12283do_neon_tst (void) 12284{ 12285 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12286 struct neon_type_el et = neon_check_type (3, rs, 12287 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); 12288 neon_three_same (neon_quad (rs), 0, et.size); 12289} 12290 12291/* VMUL with 3 registers allows the P8 type. The scalar version supports the 12292 same types as the MAC equivalents. The polynomial type for this instruction 12293 is encoded the same as the integer type. */ 12294 12295static void 12296do_neon_mul (void) 12297{ 12298 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) 12299 return; 12300 12301 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12302 return; 12303 12304 if (inst.operands[2].isscalar) 12305 do_neon_mac_maybe_scalar (); 12306 else 12307 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); 12308} 12309 12310static void 12311do_neon_qdmulh (void) 12312{ 12313 if (inst.operands[2].isscalar) 12314 { 12315 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); 12316 struct neon_type_el et = neon_check_type (3, rs, 12317 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); 12318 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 12319 neon_mul_mac (et, neon_quad (rs)); 12320 } 12321 else 12322 { 12323 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12324 struct neon_type_el et = neon_check_type (3, rs, 12325 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); 12326 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12327 /* The U bit (rounding) comes from bit mask. */ 12328 neon_three_same (neon_quad (rs), 0, et.size); 12329 } 12330} 12331 12332static void 12333do_neon_fcmp_absolute (void) 12334{ 12335 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12336 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); 12337 /* Size field comes from bit mask. */ 12338 neon_three_same (neon_quad (rs), 1, -1); 12339} 12340 12341static void 12342do_neon_fcmp_absolute_inv (void) 12343{ 12344 neon_exchange_operands (); 12345 do_neon_fcmp_absolute (); 12346} 12347 12348static void 12349do_neon_step (void) 12350{ 12351 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12352 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); 12353 neon_three_same (neon_quad (rs), 0, -1); 12354} 12355 12356static void 12357do_neon_abs_neg (void) 12358{ 12359 enum neon_shape rs; 12360 struct neon_type_el et; 12361 12362 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) 12363 return; 12364 12365 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12366 return; 12367 12368 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 12369 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); 12370 12371 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12372 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12373 inst.instruction |= LOW4 (inst.operands[1].reg); 12374 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12375 inst.instruction |= neon_quad (rs) << 6; 12376 inst.instruction |= (et.type == NT_float) << 10; 12377 inst.instruction |= neon_logbits (et.size) << 18; 12378 12379 inst.instruction = neon_dp_fixup (inst.instruction); 12380} 12381 12382static void 12383do_neon_sli (void) 12384{ 12385 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12386 struct neon_type_el et = neon_check_type (2, rs, 12387 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 12388 int imm = inst.operands[2].imm; 12389 constraint (imm < 0 || (unsigned)imm >= et.size, 12390 _("immediate out of range for insert")); 12391 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); 12392} 12393 12394static void 12395do_neon_sri (void) 12396{ 12397 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12398 struct neon_type_el et = neon_check_type (2, rs, 12399 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 12400 int imm = inst.operands[2].imm; 12401 constraint (imm < 1 || (unsigned)imm > et.size, 12402 _("immediate out of range for insert")); 12403 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); 12404} 12405 12406static void 12407do_neon_qshlu_imm (void) 12408{ 12409 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12410 struct neon_type_el et = neon_check_type (2, rs, 12411 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); 12412 int imm = inst.operands[2].imm; 12413 constraint (imm < 0 || (unsigned)imm >= et.size, 12414 _("immediate out of range for shift")); 12415 /* Only encodes the 'U present' variant of the instruction. 12416 In this case, signed types have OP (bit 8) set to 0. 12417 Unsigned types have OP set to 1. */ 12418 inst.instruction |= (et.type == NT_unsigned) << 8; 12419 /* The rest of the bits are the same as other immediate shifts. */ 12420 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); 12421} 12422 12423static void 12424do_neon_qmovn (void) 12425{ 12426 struct neon_type_el et = neon_check_type (2, NS_DQ, 12427 N_EQK | N_HLF, N_SU_16_64 | N_KEY); 12428 /* Saturating move where operands can be signed or unsigned, and the 12429 destination has the same signedness. */ 12430 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12431 if (et.type == NT_unsigned) 12432 inst.instruction |= 0xc0; 12433 else 12434 inst.instruction |= 0x80; 12435 neon_two_same (0, 1, et.size / 2); 12436} 12437 12438static void 12439do_neon_qmovun (void) 12440{ 12441 struct neon_type_el et = neon_check_type (2, NS_DQ, 12442 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); 12443 /* Saturating move with unsigned results. Operands must be signed. */ 12444 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12445 neon_two_same (0, 1, et.size / 2); 12446} 12447 12448static void 12449do_neon_rshift_sat_narrow (void) 12450{ 12451 /* FIXME: Types for narrowing. If operands are signed, results can be signed 12452 or unsigned. If operands are unsigned, results must also be unsigned. */ 12453 struct neon_type_el et = neon_check_type (2, NS_DQI, 12454 N_EQK | N_HLF, N_SU_16_64 | N_KEY); 12455 int imm = inst.operands[2].imm; 12456 /* This gets the bounds check, size encoding and immediate bits calculation 12457 right. */ 12458 et.size /= 2; 12459 12460 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for 12461 VQMOVN.I<size> <Dd>, <Qm>. */ 12462 if (imm == 0) 12463 { 12464 inst.operands[2].present = 0; 12465 inst.instruction = N_MNEM_vqmovn; 12466 do_neon_qmovn (); 12467 return; 12468 } 12469 12470 constraint (imm < 1 || (unsigned)imm > et.size, 12471 _("immediate out of range")); 12472 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); 12473} 12474 12475static void 12476do_neon_rshift_sat_narrow_u (void) 12477{ 12478 /* FIXME: Types for narrowing. If operands are signed, results can be signed 12479 or unsigned. If operands are unsigned, results must also be unsigned. */ 12480 struct neon_type_el et = neon_check_type (2, NS_DQI, 12481 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); 12482 int imm = inst.operands[2].imm; 12483 /* This gets the bounds check, size encoding and immediate bits calculation 12484 right. */ 12485 et.size /= 2; 12486 12487 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for 12488 VQMOVUN.I<size> <Dd>, <Qm>. */ 12489 if (imm == 0) 12490 { 12491 inst.operands[2].present = 0; 12492 inst.instruction = N_MNEM_vqmovun; 12493 do_neon_qmovun (); 12494 return; 12495 } 12496 12497 constraint (imm < 1 || (unsigned)imm > et.size, 12498 _("immediate out of range")); 12499 /* FIXME: The manual is kind of unclear about what value U should have in 12500 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it 12501 must be 1. */ 12502 neon_imm_shift (TRUE, 1, 0, et, et.size - imm); 12503} 12504 12505static void 12506do_neon_movn (void) 12507{ 12508 struct neon_type_el et = neon_check_type (2, NS_DQ, 12509 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); 12510 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12511 neon_two_same (0, 1, et.size / 2); 12512} 12513 12514static void 12515do_neon_rshift_narrow (void) 12516{ 12517 struct neon_type_el et = neon_check_type (2, NS_DQI, 12518 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); 12519 int imm = inst.operands[2].imm; 12520 /* This gets the bounds check, size encoding and immediate bits calculation 12521 right. */ 12522 et.size /= 2; 12523 12524 /* If immediate is zero then we are a pseudo-instruction for 12525 VMOVN.I<size> <Dd>, <Qm> */ 12526 if (imm == 0) 12527 { 12528 inst.operands[2].present = 0; 12529 inst.instruction = N_MNEM_vmovn; 12530 do_neon_movn (); 12531 return; 12532 } 12533 12534 constraint (imm < 1 || (unsigned)imm > et.size, 12535 _("immediate out of range for narrowing operation")); 12536 neon_imm_shift (FALSE, 0, 0, et, et.size - imm); 12537} 12538 12539static void 12540do_neon_shll (void) 12541{ 12542 /* FIXME: Type checking when lengthening. */ 12543 struct neon_type_el et = neon_check_type (2, NS_QDI, 12544 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); 12545 unsigned imm = inst.operands[2].imm; 12546 12547 if (imm == et.size) 12548 { 12549 /* Maximum shift variant. */ 12550 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12551 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12552 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12553 inst.instruction |= LOW4 (inst.operands[1].reg); 12554 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12555 inst.instruction |= neon_logbits (et.size) << 18; 12556 12557 inst.instruction = neon_dp_fixup (inst.instruction); 12558 } 12559 else 12560 { 12561 /* A more-specific type check for non-max versions. */ 12562 et = neon_check_type (2, NS_QDI, 12563 N_EQK | N_DBL, N_SU_32 | N_KEY); 12564 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12565 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); 12566 } 12567} 12568 12569/* Check the various types for the VCVT instruction, and return which version 12570 the current instruction is. */ 12571 12572static int 12573neon_cvt_flavour (enum neon_shape rs) 12574{ 12575#define CVT_VAR(C,X,Y) \ 12576 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \ 12577 if (et.type != NT_invtype) \ 12578 { \ 12579 inst.error = NULL; \ 12580 return (C); \ 12581 } 12582 struct neon_type_el et; 12583 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF 12584 || rs == NS_FF) ? N_VFP : 0; 12585 /* The instruction versions which take an immediate take one register 12586 argument, which is extended to the width of the full register. Thus the 12587 "source" and "destination" registers must have the same width. Hack that 12588 here by making the size equal to the key (wider, in this case) operand. */ 12589 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; 12590 12591 CVT_VAR (0, N_S32, N_F32); 12592 CVT_VAR (1, N_U32, N_F32); 12593 CVT_VAR (2, N_F32, N_S32); 12594 CVT_VAR (3, N_F32, N_U32); 12595 12596 whole_reg = N_VFP; 12597 12598 /* VFP instructions. */ 12599 CVT_VAR (4, N_F32, N_F64); 12600 CVT_VAR (5, N_F64, N_F32); 12601 CVT_VAR (6, N_S32, N_F64 | key); 12602 CVT_VAR (7, N_U32, N_F64 | key); 12603 CVT_VAR (8, N_F64 | key, N_S32); 12604 CVT_VAR (9, N_F64 | key, N_U32); 12605 /* VFP instructions with bitshift. */ 12606 CVT_VAR (10, N_F32 | key, N_S16); 12607 CVT_VAR (11, N_F32 | key, N_U16); 12608 CVT_VAR (12, N_F64 | key, N_S16); 12609 CVT_VAR (13, N_F64 | key, N_U16); 12610 CVT_VAR (14, N_S16, N_F32 | key); 12611 CVT_VAR (15, N_U16, N_F32 | key); 12612 CVT_VAR (16, N_S16, N_F64 | key); 12613 CVT_VAR (17, N_U16, N_F64 | key); 12614 12615 return -1; 12616#undef CVT_VAR 12617} 12618 12619/* Neon-syntax VFP conversions. */ 12620 12621static void 12622do_vfp_nsyn_cvt (enum neon_shape rs, int flavour) 12623{ 12624 const char *opname = 0; 12625 12626 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) 12627 { 12628 /* Conversions with immediate bitshift. */ 12629 const char *enc[] = 12630 { 12631 "ftosls", 12632 "ftouls", 12633 "fsltos", 12634 "fultos", 12635 NULL, 12636 NULL, 12637 "ftosld", 12638 "ftould", 12639 "fsltod", 12640 "fultod", 12641 "fshtos", 12642 "fuhtos", 12643 "fshtod", 12644 "fuhtod", 12645 "ftoshs", 12646 "ftouhs", 12647 "ftoshd", 12648 "ftouhd" 12649 }; 12650 12651 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) 12652 { 12653 opname = enc[flavour]; 12654 constraint (inst.operands[0].reg != inst.operands[1].reg, 12655 _("operands 0 and 1 must be the same register")); 12656 inst.operands[1] = inst.operands[2]; 12657 memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); 12658 } 12659 } 12660 else 12661 { 12662 /* Conversions without bitshift. */ 12663 const char *enc[] = 12664 { 12665 "ftosizs", 12666 "ftouizs", 12667 "fsitos", 12668 "fuitos", 12669 "fcvtsd", 12670 "fcvtds", 12671 "ftosizd", 12672 "ftouizd", 12673 "fsitod", 12674 "fuitod" 12675 }; 12676 12677 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) 12678 opname = enc[flavour]; 12679 } 12680 12681 if (opname) 12682 do_vfp_nsyn_opcode (opname); 12683} 12684 12685static void 12686do_vfp_nsyn_cvtz (void) 12687{ 12688 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); 12689 int flavour = neon_cvt_flavour (rs); 12690 const char *enc[] = 12691 { 12692 "ftosizs", 12693 "ftouizs", 12694 NULL, 12695 NULL, 12696 NULL, 12697 NULL, 12698 "ftosizd", 12699 "ftouizd" 12700 }; 12701 12702 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) 12703 do_vfp_nsyn_opcode (enc[flavour]); 12704} 12705 12706static void 12707do_neon_cvt (void) 12708{ 12709 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, 12710 NS_FD, NS_DF, NS_FF, NS_NULL); 12711 int flavour = neon_cvt_flavour (rs); 12712 12713 /* VFP rather than Neon conversions. */ 12714 if (flavour >= 4) 12715 { 12716 do_vfp_nsyn_cvt (rs, flavour); 12717 return; 12718 } 12719 12720 switch (rs) 12721 { 12722 case NS_DDI: 12723 case NS_QQI: 12724 { 12725 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12726 return; 12727 12728 /* Fixed-point conversion with #0 immediate is encoded as an 12729 integer conversion. */ 12730 if (inst.operands[2].present && inst.operands[2].imm == 0) 12731 goto int_encode; 12732 unsigned immbits = 32 - inst.operands[2].imm; 12733 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; 12734 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12735 if (flavour != -1) 12736 inst.instruction |= enctab[flavour]; 12737 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12738 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12739 inst.instruction |= LOW4 (inst.operands[1].reg); 12740 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12741 inst.instruction |= neon_quad (rs) << 6; 12742 inst.instruction |= 1 << 21; 12743 inst.instruction |= immbits << 16; 12744 12745 inst.instruction = neon_dp_fixup (inst.instruction); 12746 } 12747 break; 12748 12749 case NS_DD: 12750 case NS_QQ: 12751 int_encode: 12752 { 12753 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; 12754 12755 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12756 12757 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12758 return; 12759 12760 if (flavour != -1) 12761 inst.instruction |= enctab[flavour]; 12762 12763 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12764 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12765 inst.instruction |= LOW4 (inst.operands[1].reg); 12766 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12767 inst.instruction |= neon_quad (rs) << 6; 12768 inst.instruction |= 2 << 18; 12769 12770 inst.instruction = neon_dp_fixup (inst.instruction); 12771 } 12772 break; 12773 12774 default: 12775 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ 12776 do_vfp_nsyn_cvt (rs, flavour); 12777 } 12778} 12779 12780static void 12781neon_move_immediate (void) 12782{ 12783 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); 12784 struct neon_type_el et = neon_check_type (2, rs, 12785 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); 12786 unsigned immlo, immhi = 0, immbits; 12787 int op, cmode, float_p; 12788 12789 constraint (et.type == NT_invtype, 12790 _("operand size must be specified for immediate VMOV")); 12791 12792 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ 12793 op = (inst.instruction & (1 << 5)) != 0; 12794 12795 immlo = inst.operands[1].imm; 12796 if (inst.operands[1].regisimm) 12797 immhi = inst.operands[1].reg; 12798 12799 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, 12800 _("immediate has bits set outside the operand size")); 12801 12802 float_p = inst.operands[1].immisfloat; 12803 12804 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, 12805 et.size, et.type)) == FAIL) 12806 { 12807 /* Invert relevant bits only. */ 12808 neon_invert_size (&immlo, &immhi, et.size); 12809 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable 12810 with one or the other; those cases are caught by 12811 neon_cmode_for_move_imm. */ 12812 op = !op; 12813 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, 12814 &op, et.size, et.type)) == FAIL) 12815 { 12816 first_error (_("immediate out of range")); 12817 return; 12818 } 12819 } 12820 12821 inst.instruction &= ~(1 << 5); 12822 inst.instruction |= op << 5; 12823 12824 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12825 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12826 inst.instruction |= neon_quad (rs) << 6; 12827 inst.instruction |= cmode << 8; 12828 12829 neon_write_immbits (immbits); 12830} 12831 12832static void 12833do_neon_mvn (void) 12834{ 12835 if (inst.operands[1].isreg) 12836 { 12837 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 12838 12839 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12840 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12841 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12842 inst.instruction |= LOW4 (inst.operands[1].reg); 12843 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12844 inst.instruction |= neon_quad (rs) << 6; 12845 } 12846 else 12847 { 12848 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12849 neon_move_immediate (); 12850 } 12851 12852 inst.instruction = neon_dp_fixup (inst.instruction); 12853} 12854 12855/* Encode instructions of form: 12856 12857 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| 12858 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | 12859 12860*/ 12861 12862static void 12863neon_mixed_length (struct neon_type_el et, unsigned size) 12864{ 12865 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12866 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12867 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 12868 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 12869 inst.instruction |= LOW4 (inst.operands[2].reg); 12870 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 12871 inst.instruction |= (et.type == NT_unsigned) << 24; 12872 inst.instruction |= neon_logbits (size) << 20; 12873 12874 inst.instruction = neon_dp_fixup (inst.instruction); 12875} 12876 12877static void 12878do_neon_dyadic_long (void) 12879{ 12880 /* FIXME: Type checking for lengthening op. */ 12881 struct neon_type_el et = neon_check_type (3, NS_QDD, 12882 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); 12883 neon_mixed_length (et, et.size); 12884} 12885 12886static void 12887do_neon_abal (void) 12888{ 12889 struct neon_type_el et = neon_check_type (3, NS_QDD, 12890 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); 12891 neon_mixed_length (et, et.size); 12892} 12893 12894static void 12895neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) 12896{ 12897 if (inst.operands[2].isscalar) 12898 { 12899 struct neon_type_el et = neon_check_type (3, NS_QDS, 12900 N_EQK | N_DBL, N_EQK, regtypes | N_KEY); 12901 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 12902 neon_mul_mac (et, et.type == NT_unsigned); 12903 } 12904 else 12905 { 12906 struct neon_type_el et = neon_check_type (3, NS_QDD, 12907 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); 12908 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12909 neon_mixed_length (et, et.size); 12910 } 12911} 12912 12913static void 12914do_neon_mac_maybe_scalar_long (void) 12915{ 12916 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); 12917} 12918 12919static void 12920do_neon_dyadic_wide (void) 12921{ 12922 struct neon_type_el et = neon_check_type (3, NS_QQD, 12923 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); 12924 neon_mixed_length (et, et.size); 12925} 12926 12927static void 12928do_neon_dyadic_narrow (void) 12929{ 12930 struct neon_type_el et = neon_check_type (3, NS_QDD, 12931 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); 12932 /* Operand sign is unimportant, and the U bit is part of the opcode, 12933 so force the operand type to integer. */ 12934 et.type = NT_integer; 12935 neon_mixed_length (et, et.size / 2); 12936} 12937 12938static void 12939do_neon_mul_sat_scalar_long (void) 12940{ 12941 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); 12942} 12943 12944static void 12945do_neon_vmull (void) 12946{ 12947 if (inst.operands[2].isscalar) 12948 do_neon_mac_maybe_scalar_long (); 12949 else 12950 { 12951 struct neon_type_el et = neon_check_type (3, NS_QDD, 12952 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY); 12953 if (et.type == NT_poly) 12954 inst.instruction = NEON_ENC_POLY (inst.instruction); 12955 else 12956 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12957 /* For polynomial encoding, size field must be 0b00 and the U bit must be 12958 zero. Should be OK as-is. */ 12959 neon_mixed_length (et, et.size); 12960 } 12961} 12962 12963static void 12964do_neon_ext (void) 12965{ 12966 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); 12967 struct neon_type_el et = neon_check_type (3, rs, 12968 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 12969 unsigned imm = (inst.operands[3].imm * et.size) / 8; 12970 constraint (imm >= (neon_quad (rs) ? 16 : 8), _("shift out of range")); 12971 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12972 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12973 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 12974 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 12975 inst.instruction |= LOW4 (inst.operands[2].reg); 12976 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 12977 inst.instruction |= neon_quad (rs) << 6; 12978 inst.instruction |= imm << 8; 12979 12980 inst.instruction = neon_dp_fixup (inst.instruction); 12981} 12982 12983static void 12984do_neon_rev (void) 12985{ 12986 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 12987 struct neon_type_el et = neon_check_type (2, rs, 12988 N_EQK, N_8 | N_16 | N_32 | N_KEY); 12989 unsigned op = (inst.instruction >> 7) & 3; 12990 /* N (width of reversed regions) is encoded as part of the bitmask. We 12991 extract it here to check the elements to be reversed are smaller. 12992 Otherwise we'd get a reserved instruction. */ 12993 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; 12994 assert (elsize != 0); 12995 constraint (et.size >= elsize, 12996 _("elements must be smaller than reversal region")); 12997 neon_two_same (neon_quad (rs), 1, et.size); 12998} 12999 13000static void 13001do_neon_dup (void) 13002{ 13003 if (inst.operands[1].isscalar) 13004 { 13005 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); 13006 struct neon_type_el et = neon_check_type (2, rs, 13007 N_EQK, N_8 | N_16 | N_32 | N_KEY); 13008 unsigned sizebits = et.size >> 3; 13009 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); 13010 int logsize = neon_logbits (et.size); 13011 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; 13012 13013 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) 13014 return; 13015 13016 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 13017 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13018 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13019 inst.instruction |= LOW4 (dm); 13020 inst.instruction |= HI1 (dm) << 5; 13021 inst.instruction |= neon_quad (rs) << 6; 13022 inst.instruction |= x << 17; 13023 inst.instruction |= sizebits << 16; 13024 13025 inst.instruction = neon_dp_fixup (inst.instruction); 13026 } 13027 else 13028 { 13029 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); 13030 struct neon_type_el et = neon_check_type (2, rs, 13031 N_8 | N_16 | N_32 | N_KEY, N_EQK); 13032 /* Duplicate ARM register to lanes of vector. */ 13033 inst.instruction = NEON_ENC_ARMREG (inst.instruction); 13034 switch (et.size) 13035 { 13036 case 8: inst.instruction |= 0x400000; break; 13037 case 16: inst.instruction |= 0x000020; break; 13038 case 32: inst.instruction |= 0x000000; break; 13039 default: break; 13040 } 13041 inst.instruction |= LOW4 (inst.operands[1].reg) << 12; 13042 inst.instruction |= LOW4 (inst.operands[0].reg) << 16; 13043 inst.instruction |= HI1 (inst.operands[0].reg) << 7; 13044 inst.instruction |= neon_quad (rs) << 21; 13045 /* The encoding for this instruction is identical for the ARM and Thumb 13046 variants, except for the condition field. */ 13047 do_vfp_cond_or_thumb (); 13048 } 13049} 13050 13051/* VMOV has particularly many variations. It can be one of: 13052 0. VMOV<c><q> <Qd>, <Qm> 13053 1. VMOV<c><q> <Dd>, <Dm> 13054 (Register operations, which are VORR with Rm = Rn.) 13055 2. VMOV<c><q>.<dt> <Qd>, #<imm> 13056 3. VMOV<c><q>.<dt> <Dd>, #<imm> 13057 (Immediate loads.) 13058 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> 13059 (ARM register to scalar.) 13060 5. VMOV<c><q> <Dm>, <Rd>, <Rn> 13061 (Two ARM registers to vector.) 13062 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> 13063 (Scalar to ARM register.) 13064 7. VMOV<c><q> <Rd>, <Rn>, <Dm> 13065 (Vector to two ARM registers.) 13066 8. VMOV.F32 <Sd>, <Sm> 13067 9. VMOV.F64 <Dd>, <Dm> 13068 (VFP register moves.) 13069 10. VMOV.F32 <Sd>, #imm 13070 11. VMOV.F64 <Dd>, #imm 13071 (VFP float immediate load.) 13072 12. VMOV <Rd>, <Sm> 13073 (VFP single to ARM reg.) 13074 13. VMOV <Sd>, <Rm> 13075 (ARM reg to VFP single.) 13076 14. VMOV <Rd>, <Re>, <Sn>, <Sm> 13077 (Two ARM regs to two VFP singles.) 13078 15. VMOV <Sd>, <Se>, <Rn>, <Rm> 13079 (Two VFP singles to two ARM regs.) 13080 13081 These cases can be disambiguated using neon_select_shape, except cases 1/9 13082 and 3/11 which depend on the operand type too. 13083 13084 All the encoded bits are hardcoded by this function. 13085 13086 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). 13087 Cases 5, 7 may be used with VFPv2 and above. 13088 13089 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you 13090 can specify a type where it doesn't make sense to, and is ignored). 13091*/ 13092 13093static void 13094do_neon_mov (void) 13095{ 13096 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, 13097 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, 13098 NS_NULL); 13099 struct neon_type_el et; 13100 const char *ldconst = 0; 13101 13102 switch (rs) 13103 { 13104 case NS_DD: /* case 1/9. */ 13105 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); 13106 /* It is not an error here if no type is given. */ 13107 inst.error = NULL; 13108 if (et.type == NT_float && et.size == 64) 13109 { 13110 do_vfp_nsyn_opcode ("fcpyd"); 13111 break; 13112 } 13113 /* fall through. */ 13114 13115 case NS_QQ: /* case 0/1. */ 13116 { 13117 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 13118 return; 13119 /* The architecture manual I have doesn't explicitly state which 13120 value the U bit should have for register->register moves, but 13121 the equivalent VORR instruction has U = 0, so do that. */ 13122 inst.instruction = 0x0200110; 13123 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13124 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13125 inst.instruction |= LOW4 (inst.operands[1].reg); 13126 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 13127 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 13128 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 13129 inst.instruction |= neon_quad (rs) << 6; 13130 13131 inst.instruction = neon_dp_fixup (inst.instruction); 13132 } 13133 break; 13134 13135 case NS_DI: /* case 3/11. */ 13136 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); 13137 inst.error = NULL; 13138 if (et.type == NT_float && et.size == 64) 13139 { 13140 /* case 11 (fconstd). */ 13141 ldconst = "fconstd"; 13142 goto encode_fconstd; 13143 } 13144 /* fall through. */ 13145 13146 case NS_QI: /* case 2/3. */ 13147 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 13148 return; 13149 inst.instruction = 0x0800010; 13150 neon_move_immediate (); 13151 inst.instruction = neon_dp_fixup (inst.instruction); 13152 break; 13153 13154 case NS_SR: /* case 4. */ 13155 { 13156 unsigned bcdebits = 0; 13157 struct neon_type_el et = neon_check_type (2, NS_NULL, 13158 N_8 | N_16 | N_32 | N_KEY, N_EQK); 13159 int logsize = neon_logbits (et.size); 13160 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); 13161 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); 13162 13163 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), 13164 _(BAD_FPU)); 13165 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) 13166 && et.size != 32, _(BAD_FPU)); 13167 constraint (et.type == NT_invtype, _("bad type for scalar")); 13168 constraint (x >= 64 / et.size, _("scalar index out of range")); 13169 13170 switch (et.size) 13171 { 13172 case 8: bcdebits = 0x8; break; 13173 case 16: bcdebits = 0x1; break; 13174 case 32: bcdebits = 0x0; break; 13175 default: ; 13176 } 13177 13178 bcdebits |= x << logsize; 13179 13180 inst.instruction = 0xe000b10; 13181 do_vfp_cond_or_thumb (); 13182 inst.instruction |= LOW4 (dn) << 16; 13183 inst.instruction |= HI1 (dn) << 7; 13184 inst.instruction |= inst.operands[1].reg << 12; 13185 inst.instruction |= (bcdebits & 3) << 5; 13186 inst.instruction |= (bcdebits >> 2) << 21; 13187 } 13188 break; 13189 13190 case NS_DRR: /* case 5 (fmdrr). */ 13191 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), 13192 _(BAD_FPU)); 13193 13194 inst.instruction = 0xc400b10; 13195 do_vfp_cond_or_thumb (); 13196 inst.instruction |= LOW4 (inst.operands[0].reg); 13197 inst.instruction |= HI1 (inst.operands[0].reg) << 5; 13198 inst.instruction |= inst.operands[1].reg << 12; 13199 inst.instruction |= inst.operands[2].reg << 16; 13200 break; 13201 13202 case NS_RS: /* case 6. */ 13203 { 13204 struct neon_type_el et = neon_check_type (2, NS_NULL, 13205 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); 13206 unsigned logsize = neon_logbits (et.size); 13207 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); 13208 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); 13209 unsigned abcdebits = 0; 13210 13211 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), 13212 _(BAD_FPU)); 13213 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) 13214 && et.size != 32, _(BAD_FPU)); 13215 constraint (et.type == NT_invtype, _("bad type for scalar")); 13216 constraint (x >= 64 / et.size, _("scalar index out of range")); 13217 13218 switch (et.size) 13219 { 13220 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; 13221 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; 13222 case 32: abcdebits = 0x00; break; 13223 default: ; 13224 } 13225 13226 abcdebits |= x << logsize; 13227 inst.instruction = 0xe100b10; 13228 do_vfp_cond_or_thumb (); 13229 inst.instruction |= LOW4 (dn) << 16; 13230 inst.instruction |= HI1 (dn) << 7; 13231 inst.instruction |= inst.operands[0].reg << 12; 13232 inst.instruction |= (abcdebits & 3) << 5; 13233 inst.instruction |= (abcdebits >> 2) << 21; 13234 } 13235 break; 13236 13237 case NS_RRD: /* case 7 (fmrrd). */ 13238 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), 13239 _(BAD_FPU)); 13240 13241 inst.instruction = 0xc500b10; 13242 do_vfp_cond_or_thumb (); 13243 inst.instruction |= inst.operands[0].reg << 12; 13244 inst.instruction |= inst.operands[1].reg << 16; 13245 inst.instruction |= LOW4 (inst.operands[2].reg); 13246 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 13247 break; 13248 13249 case NS_FF: /* case 8 (fcpys). */ 13250 do_vfp_nsyn_opcode ("fcpys"); 13251 break; 13252 13253 case NS_FI: /* case 10 (fconsts). */ 13254 ldconst = "fconsts"; 13255 encode_fconstd: 13256 if (is_quarter_float (inst.operands[1].imm)) 13257 { 13258 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); 13259 do_vfp_nsyn_opcode (ldconst); 13260 } 13261 else 13262 first_error (_("immediate out of range")); 13263 break; 13264 13265 case NS_RF: /* case 12 (fmrs). */ 13266 do_vfp_nsyn_opcode ("fmrs"); 13267 break; 13268 13269 case NS_FR: /* case 13 (fmsr). */ 13270 do_vfp_nsyn_opcode ("fmsr"); 13271 break; 13272 13273 /* The encoders for the fmrrs and fmsrr instructions expect three operands 13274 (one of which is a list), but we have parsed four. Do some fiddling to 13275 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 13276 expect. */ 13277 case NS_RRFF: /* case 14 (fmrrs). */ 13278 constraint (inst.operands[3].reg != inst.operands[2].reg + 1, 13279 _("VFP registers must be adjacent")); 13280 inst.operands[2].imm = 2; 13281 memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); 13282 do_vfp_nsyn_opcode ("fmrrs"); 13283 break; 13284 13285 case NS_FFRR: /* case 15 (fmsrr). */ 13286 constraint (inst.operands[1].reg != inst.operands[0].reg + 1, 13287 _("VFP registers must be adjacent")); 13288 inst.operands[1] = inst.operands[2]; 13289 inst.operands[2] = inst.operands[3]; 13290 inst.operands[0].imm = 2; 13291 memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); 13292 do_vfp_nsyn_opcode ("fmsrr"); 13293 break; 13294 13295 default: 13296 abort (); 13297 } 13298} 13299 13300static void 13301do_neon_rshift_round_imm (void) 13302{ 13303 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 13304 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); 13305 int imm = inst.operands[2].imm; 13306 13307 /* imm == 0 case is encoded as VMOV for V{R}SHR. */ 13308 if (imm == 0) 13309 { 13310 inst.operands[2].present = 0; 13311 do_neon_mov (); 13312 return; 13313 } 13314 13315 constraint (imm < 1 || (unsigned)imm > et.size, 13316 _("immediate out of range for shift")); 13317 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, 13318 et.size - imm); 13319} 13320 13321static void 13322do_neon_movl (void) 13323{ 13324 struct neon_type_el et = neon_check_type (2, NS_QD, 13325 N_EQK | N_DBL, N_SU_32 | N_KEY); 13326 unsigned sizebits = et.size >> 3; 13327 inst.instruction |= sizebits << 19; 13328 neon_two_same (0, et.type == NT_unsigned, -1); 13329} 13330 13331static void 13332do_neon_trn (void) 13333{ 13334 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13335 struct neon_type_el et = neon_check_type (2, rs, 13336 N_EQK, N_8 | N_16 | N_32 | N_KEY); 13337 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 13338 neon_two_same (neon_quad (rs), 1, et.size); 13339} 13340 13341static void 13342do_neon_zip_uzp (void) 13343{ 13344 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13345 struct neon_type_el et = neon_check_type (2, rs, 13346 N_EQK, N_8 | N_16 | N_32 | N_KEY); 13347 if (rs == NS_DD && et.size == 32) 13348 { 13349 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ 13350 inst.instruction = N_MNEM_vtrn; 13351 do_neon_trn (); 13352 return; 13353 } 13354 neon_two_same (neon_quad (rs), 1, et.size); 13355} 13356 13357static void 13358do_neon_sat_abs_neg (void) 13359{ 13360 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13361 struct neon_type_el et = neon_check_type (2, rs, 13362 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); 13363 neon_two_same (neon_quad (rs), 1, et.size); 13364} 13365 13366static void 13367do_neon_pair_long (void) 13368{ 13369 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13370 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); 13371 /* Unsigned is encoded in OP field (bit 7) for these instruction. */ 13372 inst.instruction |= (et.type == NT_unsigned) << 7; 13373 neon_two_same (neon_quad (rs), 1, et.size); 13374} 13375 13376static void 13377do_neon_recip_est (void) 13378{ 13379 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13380 struct neon_type_el et = neon_check_type (2, rs, 13381 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); 13382 inst.instruction |= (et.type == NT_float) << 8; 13383 neon_two_same (neon_quad (rs), 1, et.size); 13384} 13385 13386static void 13387do_neon_cls (void) 13388{ 13389 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13390 struct neon_type_el et = neon_check_type (2, rs, 13391 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); 13392 neon_two_same (neon_quad (rs), 1, et.size); 13393} 13394 13395static void 13396do_neon_clz (void) 13397{ 13398 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13399 struct neon_type_el et = neon_check_type (2, rs, 13400 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); 13401 neon_two_same (neon_quad (rs), 1, et.size); 13402} 13403 13404static void 13405do_neon_cnt (void) 13406{ 13407 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13408 struct neon_type_el et = neon_check_type (2, rs, 13409 N_EQK | N_INT, N_8 | N_KEY); 13410 neon_two_same (neon_quad (rs), 1, et.size); 13411} 13412 13413static void 13414do_neon_swp (void) 13415{ 13416 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13417 neon_two_same (neon_quad (rs), 1, -1); 13418} 13419 13420static void 13421do_neon_tbl_tbx (void) 13422{ 13423 unsigned listlenbits; 13424 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); 13425 13426 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) 13427 { 13428 first_error (_("bad list length for table lookup")); 13429 return; 13430 } 13431 13432 listlenbits = inst.operands[1].imm - 1; 13433 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13434 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13435 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 13436 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 13437 inst.instruction |= LOW4 (inst.operands[2].reg); 13438 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 13439 inst.instruction |= listlenbits << 8; 13440 13441 inst.instruction = neon_dp_fixup (inst.instruction); 13442} 13443 13444static void 13445do_neon_ldm_stm (void) 13446{ 13447 /* P, U and L bits are part of bitmask. */ 13448 int is_dbmode = (inst.instruction & (1 << 24)) != 0; 13449 unsigned offsetbits = inst.operands[1].imm * 2; 13450 13451 if (inst.operands[1].issingle) 13452 { 13453 do_vfp_nsyn_ldm_stm (is_dbmode); 13454 return; 13455 } 13456 13457 constraint (is_dbmode && !inst.operands[0].writeback, 13458 _("writeback (!) must be used for VLDMDB and VSTMDB")); 13459 13460 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, 13461 _("register list must contain at least 1 and at most 16 " 13462 "registers")); 13463 13464 inst.instruction |= inst.operands[0].reg << 16; 13465 inst.instruction |= inst.operands[0].writeback << 21; 13466 inst.instruction |= LOW4 (inst.operands[1].reg) << 12; 13467 inst.instruction |= HI1 (inst.operands[1].reg) << 22; 13468 13469 inst.instruction |= offsetbits; 13470 13471 do_vfp_cond_or_thumb (); 13472} 13473 13474static void 13475do_neon_ldr_str (void) 13476{ 13477 int is_ldr = (inst.instruction & (1 << 20)) != 0; 13478 13479 if (inst.operands[0].issingle) 13480 { 13481 if (is_ldr) 13482 do_vfp_nsyn_opcode ("flds"); 13483 else 13484 do_vfp_nsyn_opcode ("fsts"); 13485 } 13486 else 13487 { 13488 if (is_ldr) 13489 do_vfp_nsyn_opcode ("fldd"); 13490 else 13491 do_vfp_nsyn_opcode ("fstd"); 13492 } 13493} 13494 13495/* "interleave" version also handles non-interleaving register VLD1/VST1 13496 instructions. */ 13497 13498static void 13499do_neon_ld_st_interleave (void) 13500{ 13501 struct neon_type_el et = neon_check_type (1, NS_NULL, 13502 N_8 | N_16 | N_32 | N_64); 13503 unsigned alignbits = 0; 13504 unsigned idx; 13505 /* The bits in this table go: 13506 0: register stride of one (0) or two (1) 13507 1,2: register list length, minus one (1, 2, 3, 4). 13508 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). 13509 We use -1 for invalid entries. */ 13510 const int typetable[] = 13511 { 13512 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ 13513 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ 13514 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ 13515 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ 13516 }; 13517 int typebits; 13518 13519 if (et.type == NT_invtype) 13520 return; 13521 13522 if (inst.operands[1].immisalign) 13523 switch (inst.operands[1].imm >> 8) 13524 { 13525 case 64: alignbits = 1; break; 13526 case 128: 13527 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3) 13528 goto bad_alignment; 13529 alignbits = 2; 13530 break; 13531 case 256: 13532 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3) 13533 goto bad_alignment; 13534 alignbits = 3; 13535 break; 13536 default: 13537 bad_alignment: 13538 first_error (_("bad alignment")); 13539 return; 13540 } 13541 13542 inst.instruction |= alignbits << 4; 13543 inst.instruction |= neon_logbits (et.size) << 6; 13544 13545 /* Bits [4:6] of the immediate in a list specifier encode register stride 13546 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of 13547 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look 13548 up the right value for "type" in a table based on this value and the given 13549 list style, then stick it back. */ 13550 idx = ((inst.operands[0].imm >> 4) & 7) 13551 | (((inst.instruction >> 8) & 3) << 3); 13552 13553 typebits = typetable[idx]; 13554 13555 constraint (typebits == -1, _("bad list type for instruction")); 13556 13557 inst.instruction &= ~0xf00; 13558 inst.instruction |= typebits << 8; 13559} 13560 13561/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. 13562 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 13563 otherwise. The variable arguments are a list of pairs of legal (size, align) 13564 values, terminated with -1. */ 13565 13566static int 13567neon_alignment_bit (int size, int align, int *do_align, ...) 13568{ 13569 va_list ap; 13570 int result = FAIL, thissize, thisalign; 13571 13572 if (!inst.operands[1].immisalign) 13573 { 13574 *do_align = 0; 13575 return SUCCESS; 13576 } 13577 13578 va_start (ap, do_align); 13579 13580 do 13581 { 13582 thissize = va_arg (ap, int); 13583 if (thissize == -1) 13584 break; 13585 thisalign = va_arg (ap, int); 13586 13587 if (size == thissize && align == thisalign) 13588 result = SUCCESS; 13589 } 13590 while (result != SUCCESS); 13591 13592 va_end (ap); 13593 13594 if (result == SUCCESS) 13595 *do_align = 1; 13596 else 13597 first_error (_("unsupported alignment for instruction")); 13598 13599 return result; 13600} 13601 13602static void 13603do_neon_ld_st_lane (void) 13604{ 13605 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); 13606 int align_good, do_align = 0; 13607 int logsize = neon_logbits (et.size); 13608 int align = inst.operands[1].imm >> 8; 13609 int n = (inst.instruction >> 8) & 3; 13610 int max_el = 64 / et.size; 13611 13612 if (et.type == NT_invtype) 13613 return; 13614 13615 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, 13616 _("bad list length")); 13617 constraint (NEON_LANE (inst.operands[0].imm) >= max_el, 13618 _("scalar index out of range")); 13619 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 13620 && et.size == 8, 13621 _("stride of 2 unavailable when element size is 8")); 13622 13623 switch (n) 13624 { 13625 case 0: /* VLD1 / VST1. */ 13626 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, 13627 32, 32, -1); 13628 if (align_good == FAIL) 13629 return; 13630 if (do_align) 13631 { 13632 unsigned alignbits = 0; 13633 switch (et.size) 13634 { 13635 case 16: alignbits = 0x1; break; 13636 case 32: alignbits = 0x3; break; 13637 default: ; 13638 } 13639 inst.instruction |= alignbits << 4; 13640 } 13641 break; 13642 13643 case 1: /* VLD2 / VST2. */ 13644 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, 13645 32, 64, -1); 13646 if (align_good == FAIL) 13647 return; 13648 if (do_align) 13649 inst.instruction |= 1 << 4; 13650 break; 13651 13652 case 2: /* VLD3 / VST3. */ 13653 constraint (inst.operands[1].immisalign, 13654 _("can't use alignment with this instruction")); 13655 break; 13656 13657 case 3: /* VLD4 / VST4. */ 13658 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, 13659 16, 64, 32, 64, 32, 128, -1); 13660 if (align_good == FAIL) 13661 return; 13662 if (do_align) 13663 { 13664 unsigned alignbits = 0; 13665 switch (et.size) 13666 { 13667 case 8: alignbits = 0x1; break; 13668 case 16: alignbits = 0x1; break; 13669 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; 13670 default: ; 13671 } 13672 inst.instruction |= alignbits << 4; 13673 } 13674 break; 13675 13676 default: ; 13677 } 13678 13679 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ 13680 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13681 inst.instruction |= 1 << (4 + logsize); 13682 13683 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); 13684 inst.instruction |= logsize << 10; 13685} 13686 13687/* Encode single n-element structure to all lanes VLD<n> instructions. */ 13688 13689static void 13690do_neon_ld_dup (void) 13691{ 13692 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); 13693 int align_good, do_align = 0; 13694 13695 if (et.type == NT_invtype) 13696 return; 13697 13698 switch ((inst.instruction >> 8) & 3) 13699 { 13700 case 0: /* VLD1. */ 13701 assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); 13702 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, 13703 &do_align, 16, 16, 32, 32, -1); 13704 if (align_good == FAIL) 13705 return; 13706 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) 13707 { 13708 case 1: break; 13709 case 2: inst.instruction |= 1 << 5; break; 13710 default: first_error (_("bad list length")); return; 13711 } 13712 inst.instruction |= neon_logbits (et.size) << 6; 13713 break; 13714 13715 case 1: /* VLD2. */ 13716 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, 13717 &do_align, 8, 16, 16, 32, 32, 64, -1); 13718 if (align_good == FAIL) 13719 return; 13720 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, 13721 _("bad list length")); 13722 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13723 inst.instruction |= 1 << 5; 13724 inst.instruction |= neon_logbits (et.size) << 6; 13725 break; 13726 13727 case 2: /* VLD3. */ 13728 constraint (inst.operands[1].immisalign, 13729 _("can't use alignment with this instruction")); 13730 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, 13731 _("bad list length")); 13732 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13733 inst.instruction |= 1 << 5; 13734 inst.instruction |= neon_logbits (et.size) << 6; 13735 break; 13736 13737 case 3: /* VLD4. */ 13738 { 13739 int align = inst.operands[1].imm >> 8; 13740 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, 13741 16, 64, 32, 64, 32, 128, -1); 13742 if (align_good == FAIL) 13743 return; 13744 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, 13745 _("bad list length")); 13746 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13747 inst.instruction |= 1 << 5; 13748 if (et.size == 32 && align == 128) 13749 inst.instruction |= 0x3 << 6; 13750 else 13751 inst.instruction |= neon_logbits (et.size) << 6; 13752 } 13753 break; 13754 13755 default: ; 13756 } 13757 13758 inst.instruction |= do_align << 4; 13759} 13760 13761/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those 13762 apart from bits [11:4]. */ 13763 13764static void 13765do_neon_ldx_stx (void) 13766{ 13767 switch (NEON_LANE (inst.operands[0].imm)) 13768 { 13769 case NEON_INTERLEAVE_LANES: 13770 inst.instruction = NEON_ENC_INTERLV (inst.instruction); 13771 do_neon_ld_st_interleave (); 13772 break; 13773 13774 case NEON_ALL_LANES: 13775 inst.instruction = NEON_ENC_DUP (inst.instruction); 13776 do_neon_ld_dup (); 13777 break; 13778 13779 default: 13780 inst.instruction = NEON_ENC_LANE (inst.instruction); 13781 do_neon_ld_st_lane (); 13782 } 13783 13784 /* L bit comes from bit mask. */ 13785 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13786 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13787 inst.instruction |= inst.operands[1].reg << 16; 13788 13789 if (inst.operands[1].postind) 13790 { 13791 int postreg = inst.operands[1].imm & 0xf; 13792 constraint (!inst.operands[1].immisreg, 13793 _("post-index must be a register")); 13794 constraint (postreg == 0xd || postreg == 0xf, 13795 _("bad register for post-index")); 13796 inst.instruction |= postreg; 13797 } 13798 else if (inst.operands[1].writeback) 13799 { 13800 inst.instruction |= 0xd; 13801 } 13802 else 13803 inst.instruction |= 0xf; 13804 13805 if (thumb_mode) 13806 inst.instruction |= 0xf9000000; 13807 else 13808 inst.instruction |= 0xf4000000; 13809} 13810 13811 13812/* Overall per-instruction processing. */ 13813 13814/* We need to be able to fix up arbitrary expressions in some statements. 13815 This is so that we can handle symbols that are an arbitrary distance from 13816 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), 13817 which returns part of an address in a form which will be valid for 13818 a data instruction. We do this by pushing the expression into a symbol 13819 in the expr_section, and creating a fix for that. */ 13820 13821static void 13822fix_new_arm (fragS * frag, 13823 int where, 13824 short int size, 13825 expressionS * exp, 13826 int pc_rel, 13827 int reloc) 13828{ 13829 fixS * new_fix; 13830 13831 switch (exp->X_op) 13832 { 13833 case O_constant: 13834 case O_symbol: 13835 case O_add: 13836 case O_subtract: 13837 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc); 13838 break; 13839 13840 default: 13841 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0, 13842 pc_rel, reloc); 13843 break; 13844 } 13845 13846 /* Mark whether the fix is to a THUMB instruction, or an ARM 13847 instruction. */ 13848 new_fix->tc_fix_data = thumb_mode; 13849} 13850 13851/* Create a frg for an instruction requiring relaxation. */ 13852static void 13853output_relax_insn (void) 13854{ 13855 char * to; 13856 symbolS *sym; 13857 int offset; 13858 13859 /* The size of the instruction is unknown, so tie the debug info to the 13860 start of the instruction. */ 13861 dwarf2_emit_insn (0); 13862 13863 switch (inst.reloc.exp.X_op) 13864 { 13865 case O_symbol: 13866 sym = inst.reloc.exp.X_add_symbol; 13867 offset = inst.reloc.exp.X_add_number; 13868 break; 13869 case O_constant: 13870 sym = NULL; 13871 offset = inst.reloc.exp.X_add_number; 13872 break; 13873 default: 13874 sym = make_expr_symbol (&inst.reloc.exp); 13875 offset = 0; 13876 break; 13877 } 13878 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, 13879 inst.relax, sym, offset, NULL/*offset, opcode*/); 13880 md_number_to_chars (to, inst.instruction, THUMB_SIZE); 13881} 13882 13883/* Write a 32-bit thumb instruction to buf. */ 13884static void 13885put_thumb32_insn (char * buf, unsigned long insn) 13886{ 13887 md_number_to_chars (buf, insn >> 16, THUMB_SIZE); 13888 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); 13889} 13890 13891static void 13892output_inst (const char * str) 13893{ 13894 char * to = NULL; 13895 13896 if (inst.error) 13897 { 13898 as_bad ("%s -- `%s'", inst.error, str); 13899 return; 13900 } 13901 if (inst.relax) { 13902 output_relax_insn(); 13903 return; 13904 } 13905 if (inst.size == 0) 13906 return; 13907 13908 to = frag_more (inst.size); 13909 13910 if (thumb_mode && (inst.size > THUMB_SIZE)) 13911 { 13912 assert (inst.size == (2 * THUMB_SIZE)); 13913 put_thumb32_insn (to, inst.instruction); 13914 } 13915 else if (inst.size > INSN_SIZE) 13916 { 13917 assert (inst.size == (2 * INSN_SIZE)); 13918 md_number_to_chars (to, inst.instruction, INSN_SIZE); 13919 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); 13920 } 13921 else 13922 md_number_to_chars (to, inst.instruction, inst.size); 13923 13924 if (inst.reloc.type != BFD_RELOC_UNUSED) 13925 fix_new_arm (frag_now, to - frag_now->fr_literal, 13926 inst.size, & inst.reloc.exp, inst.reloc.pc_rel, 13927 inst.reloc.type); 13928 13929 dwarf2_emit_insn (inst.size); 13930} 13931 13932/* Tag values used in struct asm_opcode's tag field. */ 13933enum opcode_tag 13934{ 13935 OT_unconditional, /* Instruction cannot be conditionalized. 13936 The ARM condition field is still 0xE. */ 13937 OT_unconditionalF, /* Instruction cannot be conditionalized 13938 and carries 0xF in its ARM condition field. */ 13939 OT_csuffix, /* Instruction takes a conditional suffix. */ 13940 OT_csuffixF, /* Some forms of the instruction take a conditional 13941 suffix, others place 0xF where the condition field 13942 would be. */ 13943 OT_cinfix3, /* Instruction takes a conditional infix, 13944 beginning at character index 3. (In 13945 unified mode, it becomes a suffix.) */ 13946 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for 13947 tsts, cmps, cmns, and teqs. */ 13948 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at 13949 character index 3, even in unified mode. Used for 13950 legacy instructions where suffix and infix forms 13951 may be ambiguous. */ 13952 OT_csuf_or_in3, /* Instruction takes either a conditional 13953 suffix or an infix at character index 3. */ 13954 OT_odd_infix_unc, /* This is the unconditional variant of an 13955 instruction that takes a conditional infix 13956 at an unusual position. In unified mode, 13957 this variant will accept a suffix. */ 13958 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 13959 are the conditional variants of instructions that 13960 take conditional infixes in unusual positions. 13961 The infix appears at character index 13962 (tag - OT_odd_infix_0). These are not accepted 13963 in unified mode. */ 13964}; 13965 13966/* Subroutine of md_assemble, responsible for looking up the primary 13967 opcode from the mnemonic the user wrote. STR points to the 13968 beginning of the mnemonic. 13969 13970 This is not simply a hash table lookup, because of conditional 13971 variants. Most instructions have conditional variants, which are 13972 expressed with a _conditional affix_ to the mnemonic. If we were 13973 to encode each conditional variant as a literal string in the opcode 13974 table, it would have approximately 20,000 entries. 13975 13976 Most mnemonics take this affix as a suffix, and in unified syntax, 13977 'most' is upgraded to 'all'. However, in the divided syntax, some 13978 instructions take the affix as an infix, notably the s-variants of 13979 the arithmetic instructions. Of those instructions, all but six 13980 have the infix appear after the third character of the mnemonic. 13981 13982 Accordingly, the algorithm for looking up primary opcodes given 13983 an identifier is: 13984 13985 1. Look up the identifier in the opcode table. 13986 If we find a match, go to step U. 13987 13988 2. Look up the last two characters of the identifier in the 13989 conditions table. If we find a match, look up the first N-2 13990 characters of the identifier in the opcode table. If we 13991 find a match, go to step CE. 13992 13993 3. Look up the fourth and fifth characters of the identifier in 13994 the conditions table. If we find a match, extract those 13995 characters from the identifier, and look up the remaining 13996 characters in the opcode table. If we find a match, go 13997 to step CM. 13998 13999 4. Fail. 14000 14001 U. Examine the tag field of the opcode structure, in case this is 14002 one of the six instructions with its conditional infix in an 14003 unusual place. If it is, the tag tells us where to find the 14004 infix; look it up in the conditions table and set inst.cond 14005 accordingly. Otherwise, this is an unconditional instruction. 14006 Again set inst.cond accordingly. Return the opcode structure. 14007 14008 CE. Examine the tag field to make sure this is an instruction that 14009 should receive a conditional suffix. If it is not, fail. 14010 Otherwise, set inst.cond from the suffix we already looked up, 14011 and return the opcode structure. 14012 14013 CM. Examine the tag field to make sure this is an instruction that 14014 should receive a conditional infix after the third character. 14015 If it is not, fail. Otherwise, undo the edits to the current 14016 line of input and proceed as for case CE. */ 14017 14018static const struct asm_opcode * 14019opcode_lookup (char **str) 14020{ 14021 char *end, *base; 14022 char *affix; 14023 const struct asm_opcode *opcode; 14024 const struct asm_cond *cond; 14025 char save[2]; 14026 bfd_boolean neon_supported; 14027 14028 neon_supported = ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1); 14029 14030 /* Scan up to the end of the mnemonic, which must end in white space, 14031 '.' (in unified mode, or for Neon instructions), or end of string. */ 14032 for (base = end = *str; *end != '\0'; end++) 14033 if (*end == ' ' || ((unified_syntax || neon_supported) && *end == '.')) 14034 break; 14035 14036 if (end == base) 14037 return 0; 14038 14039 /* Handle a possible width suffix and/or Neon type suffix. */ 14040 if (end[0] == '.') 14041 { 14042 int offset = 2; 14043 14044 /* The .w and .n suffixes are only valid if the unified syntax is in 14045 use. */ 14046 if (unified_syntax && end[1] == 'w') 14047 inst.size_req = 4; 14048 else if (unified_syntax && end[1] == 'n') 14049 inst.size_req = 2; 14050 else 14051 offset = 0; 14052 14053 inst.vectype.elems = 0; 14054 14055 *str = end + offset; 14056 14057 if (end[offset] == '.') 14058 { 14059 /* See if we have a Neon type suffix (possible in either unified or 14060 non-unified ARM syntax mode). */ 14061 if (parse_neon_type (&inst.vectype, str) == FAIL) 14062 return 0; 14063 } 14064 else if (end[offset] != '\0' && end[offset] != ' ') 14065 return 0; 14066 } 14067 else 14068 *str = end; 14069 14070 /* Look for unaffixed or special-case affixed mnemonic. */ 14071 opcode = hash_find_n (arm_ops_hsh, base, end - base); 14072 if (opcode) 14073 { 14074 /* step U */ 14075 if (opcode->tag < OT_odd_infix_0) 14076 { 14077 inst.cond = COND_ALWAYS; 14078 return opcode; 14079 } 14080 14081 if (unified_syntax) 14082 as_warn (_("conditional infixes are deprecated in unified syntax")); 14083 affix = base + (opcode->tag - OT_odd_infix_0); 14084 cond = hash_find_n (arm_cond_hsh, affix, 2); 14085 assert (cond); 14086 14087 inst.cond = cond->value; 14088 return opcode; 14089 } 14090 14091 /* Cannot have a conditional suffix on a mnemonic of less than two 14092 characters. */ 14093 if (end - base < 3) 14094 return 0; 14095 14096 /* Look for suffixed mnemonic. */ 14097 affix = end - 2; 14098 cond = hash_find_n (arm_cond_hsh, affix, 2); 14099 opcode = hash_find_n (arm_ops_hsh, base, affix - base); 14100 if (opcode && cond) 14101 { 14102 /* step CE */ 14103 switch (opcode->tag) 14104 { 14105 case OT_cinfix3_legacy: 14106 /* Ignore conditional suffixes matched on infix only mnemonics. */ 14107 break; 14108 14109 case OT_cinfix3: 14110 case OT_cinfix3_deprecated: 14111 case OT_odd_infix_unc: 14112 if (!unified_syntax) 14113 return 0; 14114 /* else fall through */ 14115 14116 case OT_csuffix: 14117 case OT_csuffixF: 14118 case OT_csuf_or_in3: 14119 inst.cond = cond->value; 14120 return opcode; 14121 14122 case OT_unconditional: 14123 case OT_unconditionalF: 14124 if (thumb_mode) 14125 { 14126 inst.cond = cond->value; 14127 } 14128 else 14129 { 14130 /* delayed diagnostic */ 14131 inst.error = BAD_COND; 14132 inst.cond = COND_ALWAYS; 14133 } 14134 return opcode; 14135 14136 default: 14137 return 0; 14138 } 14139 } 14140 14141 /* Cannot have a usual-position infix on a mnemonic of less than 14142 six characters (five would be a suffix). */ 14143 if (end - base < 6) 14144 return 0; 14145 14146 /* Look for infixed mnemonic in the usual position. */ 14147 affix = base + 3; 14148 cond = hash_find_n (arm_cond_hsh, affix, 2); 14149 if (!cond) 14150 return 0; 14151 14152 memcpy (save, affix, 2); 14153 memmove (affix, affix + 2, (end - affix) - 2); 14154 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2); 14155 memmove (affix + 2, affix, (end - affix) - 2); 14156 memcpy (affix, save, 2); 14157 14158 if (opcode 14159 && (opcode->tag == OT_cinfix3 14160 || opcode->tag == OT_cinfix3_deprecated 14161 || opcode->tag == OT_csuf_or_in3 14162 || opcode->tag == OT_cinfix3_legacy)) 14163 { 14164 /* step CM */ 14165 if (unified_syntax 14166 && (opcode->tag == OT_cinfix3 14167 || opcode->tag == OT_cinfix3_deprecated)) 14168 as_warn (_("conditional infixes are deprecated in unified syntax")); 14169 14170 inst.cond = cond->value; 14171 return opcode; 14172 } 14173 14174 return 0; 14175} 14176 14177void 14178md_assemble (char *str) 14179{ 14180 char *p = str; 14181 const struct asm_opcode * opcode; 14182 14183 /* Align the previous label if needed. */ 14184 if (last_label_seen != NULL) 14185 { 14186 symbol_set_frag (last_label_seen, frag_now); 14187 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); 14188 S_SET_SEGMENT (last_label_seen, now_seg); 14189 } 14190 14191 memset (&inst, '\0', sizeof (inst)); 14192 inst.reloc.type = BFD_RELOC_UNUSED; 14193 14194 opcode = opcode_lookup (&p); 14195 if (!opcode) 14196 { 14197 /* It wasn't an instruction, but it might be a register alias of 14198 the form alias .req reg, or a Neon .dn/.qn directive. */ 14199 if (!create_register_alias (str, p) 14200 && !create_neon_reg_alias (str, p)) 14201 as_bad (_("bad instruction `%s'"), str); 14202 14203 return; 14204 } 14205 14206 if (opcode->tag == OT_cinfix3_deprecated) 14207 as_warn (_("s suffix on comparison instruction is deprecated")); 14208 14209 /* The value which unconditional instructions should have in place of the 14210 condition field. */ 14211 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; 14212 14213 if (thumb_mode) 14214 { 14215 arm_feature_set variant; 14216 14217 variant = cpu_variant; 14218 /* Only allow coprocessor instructions on Thumb-2 capable devices. */ 14219 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) 14220 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); 14221 /* Check that this instruction is supported for this CPU. */ 14222 if (!opcode->tvariant 14223 || (thumb_mode == 1 14224 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) 14225 { 14226 as_bad (_("selected processor does not support `%s'"), str); 14227 return; 14228 } 14229 if (inst.cond != COND_ALWAYS && !unified_syntax 14230 && opcode->tencode != do_t_branch) 14231 { 14232 as_bad (_("Thumb does not support conditional execution")); 14233 return; 14234 } 14235 14236 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) && !inst.size_req) 14237 { 14238 /* Implicit require narrow instructions on Thumb-1. This avoids 14239 relaxation accidentally introducing Thumb-2 instructions. */ 14240 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23) 14241 inst.size_req = 2; 14242 } 14243 14244 /* Check conditional suffixes. */ 14245 if (current_it_mask) 14246 { 14247 int cond; 14248 cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1; 14249 current_it_mask <<= 1; 14250 current_it_mask &= 0x1f; 14251 /* The BKPT instruction is unconditional even in an IT block. */ 14252 if (!inst.error 14253 && cond != inst.cond && opcode->tencode != do_t_bkpt) 14254 { 14255 as_bad (_("incorrect condition in IT block")); 14256 return; 14257 } 14258 } 14259 else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch) 14260 { 14261 as_bad (_("thumb conditional instrunction not in IT block")); 14262 return; 14263 } 14264 14265 mapping_state (MAP_THUMB); 14266 inst.instruction = opcode->tvalue; 14267 14268 if (!parse_operands (p, opcode->operands)) 14269 opcode->tencode (); 14270 14271 /* Clear current_it_mask at the end of an IT block. */ 14272 if (current_it_mask == 0x10) 14273 current_it_mask = 0; 14274 14275 if (!(inst.error || inst.relax)) 14276 { 14277 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); 14278 inst.size = (inst.instruction > 0xffff ? 4 : 2); 14279 if (inst.size_req && inst.size_req != inst.size) 14280 { 14281 as_bad (_("cannot honor width suffix -- `%s'"), str); 14282 return; 14283 } 14284 } 14285 14286 /* Something has gone badly wrong if we try to relax a fixed size 14287 instruction. */ 14288 assert (inst.size_req == 0 || !inst.relax); 14289 14290 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 14291 *opcode->tvariant); 14292 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly 14293 set those bits when Thumb-2 32-bit instructions are seen. ie. 14294 anything other than bl/blx. 14295 This is overly pessimistic for relaxable instructions. */ 14296 if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) 14297 || inst.relax) 14298 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 14299 arm_ext_v6t2); 14300 } 14301 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 14302 { 14303 /* Check that this instruction is supported for this CPU. */ 14304 if (!opcode->avariant || 14305 !ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)) 14306 { 14307 as_bad (_("selected processor does not support `%s'"), str); 14308 return; 14309 } 14310 if (inst.size_req) 14311 { 14312 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); 14313 return; 14314 } 14315 14316 mapping_state (MAP_ARM); 14317 inst.instruction = opcode->avalue; 14318 if (opcode->tag == OT_unconditionalF) 14319 inst.instruction |= 0xF << 28; 14320 else 14321 inst.instruction |= inst.cond << 28; 14322 inst.size = INSN_SIZE; 14323 if (!parse_operands (p, opcode->operands)) 14324 opcode->aencode (); 14325 /* Arm mode bx is marked as both v4T and v5 because it's still required 14326 on a hypothetical non-thumb v5 core. */ 14327 if (ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v4t) 14328 || ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v5)) 14329 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); 14330 else 14331 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 14332 *opcode->avariant); 14333 } 14334 else 14335 { 14336 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " 14337 "-- `%s'"), str); 14338 return; 14339 } 14340 output_inst (str); 14341} 14342 14343/* Various frobbings of labels and their addresses. */ 14344 14345void 14346arm_start_line_hook (void) 14347{ 14348 last_label_seen = NULL; 14349} 14350 14351void 14352arm_frob_label (symbolS * sym) 14353{ 14354 last_label_seen = sym; 14355 14356 ARM_SET_THUMB (sym, thumb_mode); 14357 14358#if defined OBJ_COFF || defined OBJ_ELF 14359 ARM_SET_INTERWORK (sym, support_interwork); 14360#endif 14361 14362 /* Note - do not allow local symbols (.Lxxx) to be labeled 14363 as Thumb functions. This is because these labels, whilst 14364 they exist inside Thumb code, are not the entry points for 14365 possible ARM->Thumb calls. Also, these labels can be used 14366 as part of a computed goto or switch statement. eg gcc 14367 can generate code that looks like this: 14368 14369 ldr r2, [pc, .Laaa] 14370 lsl r3, r3, #2 14371 ldr r2, [r3, r2] 14372 mov pc, r2 14373 14374 .Lbbb: .word .Lxxx 14375 .Lccc: .word .Lyyy 14376 ..etc... 14377 .Laaa: .word Lbbb 14378 14379 The first instruction loads the address of the jump table. 14380 The second instruction converts a table index into a byte offset. 14381 The third instruction gets the jump address out of the table. 14382 The fourth instruction performs the jump. 14383 14384 If the address stored at .Laaa is that of a symbol which has the 14385 Thumb_Func bit set, then the linker will arrange for this address 14386 to have the bottom bit set, which in turn would mean that the 14387 address computation performed by the third instruction would end 14388 up with the bottom bit set. Since the ARM is capable of unaligned 14389 word loads, the instruction would then load the incorrect address 14390 out of the jump table, and chaos would ensue. */ 14391 if (label_is_thumb_function_name 14392 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') 14393 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) 14394 { 14395 /* When the address of a Thumb function is taken the bottom 14396 bit of that address should be set. This will allow 14397 interworking between Arm and Thumb functions to work 14398 correctly. */ 14399 14400 THUMB_SET_FUNC (sym, 1); 14401 14402 label_is_thumb_function_name = FALSE; 14403 } 14404 14405 dwarf2_emit_label (sym); 14406} 14407 14408int 14409arm_data_in_code (void) 14410{ 14411 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) 14412 { 14413 *input_line_pointer = '/'; 14414 input_line_pointer += 5; 14415 *input_line_pointer = 0; 14416 return 1; 14417 } 14418 14419 return 0; 14420} 14421 14422char * 14423arm_canonicalize_symbol_name (char * name) 14424{ 14425 int len; 14426 14427 if (thumb_mode && (len = strlen (name)) > 5 14428 && streq (name + len - 5, "/data")) 14429 *(name + len - 5) = 0; 14430 14431 return name; 14432} 14433 14434/* Table of all register names defined by default. The user can 14435 define additional names with .req. Note that all register names 14436 should appear in both upper and lowercase variants. Some registers 14437 also have mixed-case names. */ 14438 14439#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } 14440#define REGNUM(p,n,t) REGDEF(p##n, n, t) 14441#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) 14442#define REGSET(p,t) \ 14443 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ 14444 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ 14445 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ 14446 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) 14447#define REGSETH(p,t) \ 14448 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ 14449 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ 14450 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ 14451 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) 14452#define REGSET2(p,t) \ 14453 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ 14454 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ 14455 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ 14456 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) 14457 14458static const struct reg_entry reg_names[] = 14459{ 14460 /* ARM integer registers. */ 14461 REGSET(r, RN), REGSET(R, RN), 14462 14463 /* ATPCS synonyms. */ 14464 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), 14465 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), 14466 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), 14467 14468 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), 14469 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), 14470 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), 14471 14472 /* Well-known aliases. */ 14473 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), 14474 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), 14475 14476 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), 14477 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), 14478 14479 /* Coprocessor numbers. */ 14480 REGSET(p, CP), REGSET(P, CP), 14481 14482 /* Coprocessor register numbers. The "cr" variants are for backward 14483 compatibility. */ 14484 REGSET(c, CN), REGSET(C, CN), 14485 REGSET(cr, CN), REGSET(CR, CN), 14486 14487 /* FPA registers. */ 14488 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), 14489 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), 14490 14491 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), 14492 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), 14493 14494 /* VFP SP registers. */ 14495 REGSET(s,VFS), REGSET(S,VFS), 14496 REGSETH(s,VFS), REGSETH(S,VFS), 14497 14498 /* VFP DP Registers. */ 14499 REGSET(d,VFD), REGSET(D,VFD), 14500 /* Extra Neon DP registers. */ 14501 REGSETH(d,VFD), REGSETH(D,VFD), 14502 14503 /* Neon QP registers. */ 14504 REGSET2(q,NQ), REGSET2(Q,NQ), 14505 14506 /* VFP control registers. */ 14507 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), 14508 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), 14509 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), 14510 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), 14511 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), 14512 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), 14513 14514 /* Maverick DSP coprocessor registers. */ 14515 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), 14516 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), 14517 14518 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), 14519 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), 14520 REGDEF(dspsc,0,DSPSC), 14521 14522 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), 14523 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), 14524 REGDEF(DSPSC,0,DSPSC), 14525 14526 /* iWMMXt data registers - p0, c0-15. */ 14527 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), 14528 14529 /* iWMMXt control registers - p1, c0-3. */ 14530 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), 14531 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), 14532 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), 14533 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), 14534 14535 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ 14536 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), 14537 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), 14538 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), 14539 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), 14540 14541 /* XScale accumulator registers. */ 14542 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), 14543}; 14544#undef REGDEF 14545#undef REGNUM 14546#undef REGSET 14547 14548/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled 14549 within psr_required_here. */ 14550static const struct asm_psr psrs[] = 14551{ 14552 /* Backward compatibility notation. Note that "all" is no longer 14553 truly all possible PSR bits. */ 14554 {"all", PSR_c | PSR_f}, 14555 {"flg", PSR_f}, 14556 {"ctl", PSR_c}, 14557 14558 /* Individual flags. */ 14559 {"f", PSR_f}, 14560 {"c", PSR_c}, 14561 {"x", PSR_x}, 14562 {"s", PSR_s}, 14563 /* Combinations of flags. */ 14564 {"fs", PSR_f | PSR_s}, 14565 {"fx", PSR_f | PSR_x}, 14566 {"fc", PSR_f | PSR_c}, 14567 {"sf", PSR_s | PSR_f}, 14568 {"sx", PSR_s | PSR_x}, 14569 {"sc", PSR_s | PSR_c}, 14570 {"xf", PSR_x | PSR_f}, 14571 {"xs", PSR_x | PSR_s}, 14572 {"xc", PSR_x | PSR_c}, 14573 {"cf", PSR_c | PSR_f}, 14574 {"cs", PSR_c | PSR_s}, 14575 {"cx", PSR_c | PSR_x}, 14576 {"fsx", PSR_f | PSR_s | PSR_x}, 14577 {"fsc", PSR_f | PSR_s | PSR_c}, 14578 {"fxs", PSR_f | PSR_x | PSR_s}, 14579 {"fxc", PSR_f | PSR_x | PSR_c}, 14580 {"fcs", PSR_f | PSR_c | PSR_s}, 14581 {"fcx", PSR_f | PSR_c | PSR_x}, 14582 {"sfx", PSR_s | PSR_f | PSR_x}, 14583 {"sfc", PSR_s | PSR_f | PSR_c}, 14584 {"sxf", PSR_s | PSR_x | PSR_f}, 14585 {"sxc", PSR_s | PSR_x | PSR_c}, 14586 {"scf", PSR_s | PSR_c | PSR_f}, 14587 {"scx", PSR_s | PSR_c | PSR_x}, 14588 {"xfs", PSR_x | PSR_f | PSR_s}, 14589 {"xfc", PSR_x | PSR_f | PSR_c}, 14590 {"xsf", PSR_x | PSR_s | PSR_f}, 14591 {"xsc", PSR_x | PSR_s | PSR_c}, 14592 {"xcf", PSR_x | PSR_c | PSR_f}, 14593 {"xcs", PSR_x | PSR_c | PSR_s}, 14594 {"cfs", PSR_c | PSR_f | PSR_s}, 14595 {"cfx", PSR_c | PSR_f | PSR_x}, 14596 {"csf", PSR_c | PSR_s | PSR_f}, 14597 {"csx", PSR_c | PSR_s | PSR_x}, 14598 {"cxf", PSR_c | PSR_x | PSR_f}, 14599 {"cxs", PSR_c | PSR_x | PSR_s}, 14600 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, 14601 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, 14602 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, 14603 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, 14604 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, 14605 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, 14606 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, 14607 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, 14608 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, 14609 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, 14610 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, 14611 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, 14612 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, 14613 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, 14614 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, 14615 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, 14616 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, 14617 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, 14618 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, 14619 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, 14620 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, 14621 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, 14622 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, 14623 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, 14624}; 14625 14626/* Table of V7M psr names. */ 14627static const struct asm_psr v7m_psrs[] = 14628{ 14629 {"apsr", 0 }, {"APSR", 0 }, 14630 {"iapsr", 1 }, {"IAPSR", 1 }, 14631 {"eapsr", 2 }, {"EAPSR", 2 }, 14632 {"psr", 3 }, {"PSR", 3 }, 14633 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, 14634 {"ipsr", 5 }, {"IPSR", 5 }, 14635 {"epsr", 6 }, {"EPSR", 6 }, 14636 {"iepsr", 7 }, {"IEPSR", 7 }, 14637 {"msp", 8 }, {"MSP", 8 }, 14638 {"psp", 9 }, {"PSP", 9 }, 14639 {"primask", 16}, {"PRIMASK", 16}, 14640 {"basepri", 17}, {"BASEPRI", 17}, 14641 {"basepri_max", 18}, {"BASEPRI_MAX", 18}, 14642 {"faultmask", 19}, {"FAULTMASK", 19}, 14643 {"control", 20}, {"CONTROL", 20} 14644}; 14645 14646/* Table of all shift-in-operand names. */ 14647static const struct asm_shift_name shift_names [] = 14648{ 14649 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, 14650 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, 14651 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, 14652 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, 14653 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, 14654 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } 14655}; 14656 14657/* Table of all explicit relocation names. */ 14658#ifdef OBJ_ELF 14659static struct reloc_entry reloc_names[] = 14660{ 14661 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, 14662 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, 14663 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, 14664 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, 14665 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, 14666 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, 14667 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, 14668 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, 14669 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, 14670 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, 14671 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32} 14672}; 14673#endif 14674 14675/* Table of all conditional affixes. 0xF is not defined as a condition code. */ 14676static const struct asm_cond conds[] = 14677{ 14678 {"eq", 0x0}, 14679 {"ne", 0x1}, 14680 {"cs", 0x2}, {"hs", 0x2}, 14681 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, 14682 {"mi", 0x4}, 14683 {"pl", 0x5}, 14684 {"vs", 0x6}, 14685 {"vc", 0x7}, 14686 {"hi", 0x8}, 14687 {"ls", 0x9}, 14688 {"ge", 0xa}, 14689 {"lt", 0xb}, 14690 {"gt", 0xc}, 14691 {"le", 0xd}, 14692 {"al", 0xe} 14693}; 14694 14695static struct asm_barrier_opt barrier_opt_names[] = 14696{ 14697 { "sy", 0xf }, 14698 { "un", 0x7 }, 14699 { "st", 0xe }, 14700 { "unst", 0x6 } 14701}; 14702 14703/* Table of ARM-format instructions. */ 14704 14705/* Macros for gluing together operand strings. N.B. In all cases 14706 other than OPS0, the trailing OP_stop comes from default 14707 zero-initialization of the unspecified elements of the array. */ 14708#define OPS0() { OP_stop, } 14709#define OPS1(a) { OP_##a, } 14710#define OPS2(a,b) { OP_##a,OP_##b, } 14711#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } 14712#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } 14713#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } 14714#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } 14715 14716/* These macros abstract out the exact format of the mnemonic table and 14717 save some repeated characters. */ 14718 14719/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ 14720#define TxCE(mnem, op, top, nops, ops, ae, te) \ 14721 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ 14722 THUMB_VARIANT, do_##ae, do_##te } 14723 14724/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for 14725 a T_MNEM_xyz enumerator. */ 14726#define TCE(mnem, aop, top, nops, ops, ae, te) \ 14727 TxCE(mnem, aop, 0x##top, nops, ops, ae, te) 14728#define tCE(mnem, aop, top, nops, ops, ae, te) \ 14729 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te) 14730 14731/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional 14732 infix after the third character. */ 14733#define TxC3(mnem, op, top, nops, ops, ae, te) \ 14734 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ 14735 THUMB_VARIANT, do_##ae, do_##te } 14736#define TxC3w(mnem, op, top, nops, ops, ae, te) \ 14737 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ 14738 THUMB_VARIANT, do_##ae, do_##te } 14739#define TC3(mnem, aop, top, nops, ops, ae, te) \ 14740 TxC3(mnem, aop, 0x##top, nops, ops, ae, te) 14741#define TC3w(mnem, aop, top, nops, ops, ae, te) \ 14742 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te) 14743#define tC3(mnem, aop, top, nops, ops, ae, te) \ 14744 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te) 14745#define tC3w(mnem, aop, top, nops, ops, ae, te) \ 14746 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te) 14747 14748/* Mnemonic with a conditional infix in an unusual place. Each and every variant has to 14749 appear in the condition table. */ 14750#define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ 14751 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ 14752 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } 14753 14754#define TxCM(m1, m2, op, top, nops, ops, ae, te) \ 14755 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \ 14756 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \ 14757 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \ 14758 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \ 14759 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \ 14760 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \ 14761 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \ 14762 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \ 14763 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \ 14764 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \ 14765 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \ 14766 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \ 14767 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \ 14768 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \ 14769 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \ 14770 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \ 14771 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \ 14772 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \ 14773 TxCM_(m1, al, m2, op, top, nops, ops, ae, te) 14774 14775#define TCM(m1,m2, aop, top, nops, ops, ae, te) \ 14776 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te) 14777#define tCM(m1,m2, aop, top, nops, ops, ae, te) \ 14778 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te) 14779 14780/* Mnemonic that cannot be conditionalized. The ARM condition-code 14781 field is still 0xE. Many of the Thumb variants can be executed 14782 conditionally, so this is checked separately. */ 14783#define TUE(mnem, op, top, nops, ops, ae, te) \ 14784 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ 14785 THUMB_VARIANT, do_##ae, do_##te } 14786 14787/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM 14788 condition code field. */ 14789#define TUF(mnem, op, top, nops, ops, ae, te) \ 14790 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ 14791 THUMB_VARIANT, do_##ae, do_##te } 14792 14793/* ARM-only variants of all the above. */ 14794#define CE(mnem, op, nops, ops, ae) \ 14795 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14796 14797#define C3(mnem, op, nops, ops, ae) \ 14798 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14799 14800/* Legacy mnemonics that always have conditional infix after the third 14801 character. */ 14802#define CL(mnem, op, nops, ops, ae) \ 14803 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ 14804 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14805 14806/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ 14807#define cCE(mnem, op, nops, ops, ae) \ 14808 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 14809 14810/* Legacy coprocessor instructions where conditional infix and conditional 14811 suffix are ambiguous. For consistency this includes all FPA instructions, 14812 not just the potentially ambiguous ones. */ 14813#define cCL(mnem, op, nops, ops, ae) \ 14814 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ 14815 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 14816 14817/* Coprocessor, takes either a suffix or a position-3 infix 14818 (for an FPA corner case). */ 14819#define C3E(mnem, op, nops, ops, ae) \ 14820 { #mnem, OPS##nops ops, OT_csuf_or_in3, \ 14821 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 14822 14823#define xCM_(m1, m2, m3, op, nops, ops, ae) \ 14824 { #m1 #m2 #m3, OPS##nops ops, \ 14825 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ 14826 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14827 14828#define CM(m1, m2, op, nops, ops, ae) \ 14829 xCM_(m1, , m2, op, nops, ops, ae), \ 14830 xCM_(m1, eq, m2, op, nops, ops, ae), \ 14831 xCM_(m1, ne, m2, op, nops, ops, ae), \ 14832 xCM_(m1, cs, m2, op, nops, ops, ae), \ 14833 xCM_(m1, hs, m2, op, nops, ops, ae), \ 14834 xCM_(m1, cc, m2, op, nops, ops, ae), \ 14835 xCM_(m1, ul, m2, op, nops, ops, ae), \ 14836 xCM_(m1, lo, m2, op, nops, ops, ae), \ 14837 xCM_(m1, mi, m2, op, nops, ops, ae), \ 14838 xCM_(m1, pl, m2, op, nops, ops, ae), \ 14839 xCM_(m1, vs, m2, op, nops, ops, ae), \ 14840 xCM_(m1, vc, m2, op, nops, ops, ae), \ 14841 xCM_(m1, hi, m2, op, nops, ops, ae), \ 14842 xCM_(m1, ls, m2, op, nops, ops, ae), \ 14843 xCM_(m1, ge, m2, op, nops, ops, ae), \ 14844 xCM_(m1, lt, m2, op, nops, ops, ae), \ 14845 xCM_(m1, gt, m2, op, nops, ops, ae), \ 14846 xCM_(m1, le, m2, op, nops, ops, ae), \ 14847 xCM_(m1, al, m2, op, nops, ops, ae) 14848 14849#define UE(mnem, op, nops, ops, ae) \ 14850 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } 14851 14852#define UF(mnem, op, nops, ops, ae) \ 14853 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } 14854 14855/* Neon data-processing. ARM versions are unconditional with cond=0xf. 14856 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we 14857 use the same encoding function for each. */ 14858#define NUF(mnem, op, nops, ops, enc) \ 14859 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ 14860 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 14861 14862/* Neon data processing, version which indirects through neon_enc_tab for 14863 the various overloaded versions of opcodes. */ 14864#define nUF(mnem, op, nops, ops, enc) \ 14865 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \ 14866 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 14867 14868/* Neon insn with conditional suffix for the ARM version, non-overloaded 14869 version. */ 14870#define NCE_tag(mnem, op, nops, ops, enc, tag) \ 14871 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ 14872 THUMB_VARIANT, do_##enc, do_##enc } 14873 14874#define NCE(mnem, op, nops, ops, enc) \ 14875 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix) 14876 14877#define NCEF(mnem, op, nops, ops, enc) \ 14878 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF) 14879 14880/* Neon insn with conditional suffix for the ARM version, overloaded types. */ 14881#define nCE_tag(mnem, op, nops, ops, enc, tag) \ 14882 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \ 14883 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 14884 14885#define nCE(mnem, op, nops, ops, enc) \ 14886 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix) 14887 14888#define nCEF(mnem, op, nops, ops, enc) \ 14889 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF) 14890 14891#define do_0 0 14892 14893/* Thumb-only, unconditional. */ 14894#define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te) 14895 14896static const struct asm_opcode insns[] = 14897{ 14898#define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */ 14899#define THUMB_VARIANT &arm_ext_v4t 14900 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c), 14901 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c), 14902 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c), 14903 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c), 14904 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub), 14905 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub), 14906 tCE(add, 0800000, add, 3, (RR, oRR, SHG), arit, t_add_sub), 14907 tC3(adds, 0900000, adds, 3, (RR, oRR, SHG), arit, t_add_sub), 14908 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c), 14909 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c), 14910 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3), 14911 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3), 14912 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c), 14913 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c), 14914 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3), 14915 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3), 14916 14917 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism 14918 for setting PSR flag bits. They are obsolete in V6 and do not 14919 have Thumb equivalents. */ 14920 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), 14921 tC3w(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), 14922 CL(tstp, 110f000, 2, (RR, SH), cmp), 14923 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), 14924 tC3w(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), 14925 CL(cmpp, 150f000, 2, (RR, SH), cmp), 14926 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), 14927 tC3w(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), 14928 CL(cmnp, 170f000, 2, (RR, SH), cmp), 14929 14930 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp), 14931 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp), 14932 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst), 14933 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst), 14934 14935 tCE(ldr, 4100000, ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), 14936 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDRGLDR),ldst, t_ldst), 14937 tCE(str, 4000000, str, 2, (RR, ADDRGLDR),ldst, t_ldst), 14938 tC3(strb, 4400000, strb, 2, (RR, ADDRGLDR),ldst, t_ldst), 14939 14940 tCE(stm, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14941 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14942 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14943 tCE(ldm, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14944 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14945 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14946 14947 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi), 14948 TCE(svc, f000000, df00, 1, (EXPi), swi, t_swi), 14949 tCE(b, a000000, b, 1, (EXPr), branch, t_branch), 14950 TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23), 14951 14952 /* Pseudo ops. */ 14953 tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr), 14954 C3(adrl, 28f0000, 2, (RR, EXP), adrl), 14955 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop), 14956 14957 /* Thumb-compatibility pseudo ops. */ 14958 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift), 14959 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift), 14960 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift), 14961 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift), 14962 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift), 14963 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift), 14964 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift), 14965 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift), 14966 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg), 14967 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg), 14968 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop), 14969 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop), 14970 14971 /* These may simplify to neg. */ 14972 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), 14973 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), 14974 14975 TCE(rrx, 1a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rd_rm), 14976 TCE(rrxs, 1b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rd_rm), 14977 14978#undef THUMB_VARIANT 14979#define THUMB_VARIANT &arm_ext_v6 14980 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), 14981 14982 /* V1 instructions with no Thumb analogue prior to V6T2. */ 14983#undef THUMB_VARIANT 14984#define THUMB_VARIANT &arm_ext_v6t2 14985 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), 14986 TC3w(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), 14987 CL(teqp, 130f000, 2, (RR, SH), cmp), 14988 14989 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt), 14990 TC3(ldrbt, 4700000, f8100e00, 2, (RR, ADDR), ldstt, t_ldstt), 14991 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt), 14992 TC3(strbt, 4600000, f8000e00, 2, (RR, ADDR), ldstt, t_ldstt), 14993 14994 TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14995 TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14996 14997 TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14998 TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14999 15000 /* V1 instructions with no Thumb analogue at all. */ 15001 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit), 15002 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), 15003 15004 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), 15005 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), 15006 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), 15007 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), 15008 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), 15009 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), 15010 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), 15011 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), 15012 15013#undef ARM_VARIANT 15014#define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */ 15015#undef THUMB_VARIANT 15016#define THUMB_VARIANT &arm_ext_v4t 15017 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), 15018 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), 15019 15020#undef THUMB_VARIANT 15021#define THUMB_VARIANT &arm_ext_v6t2 15022 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), 15023 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), 15024 15025 /* Generic coprocessor instructions. */ 15026 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), 15027 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15028 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15029 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15030 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15031 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 15032 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 15033 15034#undef ARM_VARIANT 15035#define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */ 15036 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), 15037 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), 15038 15039#undef ARM_VARIANT 15040#define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */ 15041 TCE(mrs, 10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs), 15042 TCE(msr, 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr), 15043 15044#undef ARM_VARIANT 15045#define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */ 15046 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 15047 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 15048 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 15049 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 15050 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 15051 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 15052 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 15053 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 15054 15055#undef ARM_VARIANT 15056#define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */ 15057#undef THUMB_VARIANT 15058#define THUMB_VARIANT &arm_ext_v4t 15059 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15060 tC3(strh, 00000b0, strh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15061 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15062 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15063 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15064 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15065 15066#undef ARM_VARIANT 15067#define ARM_VARIANT &arm_ext_v4t_5 15068 /* ARM Architecture 4T. */ 15069 /* Note: bx (and blx) are required on V5, even if the processor does 15070 not support Thumb. */ 15071 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx), 15072 15073#undef ARM_VARIANT 15074#define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */ 15075#undef THUMB_VARIANT 15076#define THUMB_VARIANT &arm_ext_v5t 15077 /* Note: blx has 2 variants; the .value coded here is for 15078 BLX(2). Only this variant has conditional execution. */ 15079 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx), 15080 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), 15081 15082#undef THUMB_VARIANT 15083#define THUMB_VARIANT &arm_ext_v6t2 15084 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), 15085 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15086 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15087 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15088 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15089 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), 15090 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 15091 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 15092 15093#undef ARM_VARIANT 15094#define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */ 15095 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15096 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15097 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15098 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15099 15100 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15101 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15102 15103 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15104 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15105 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15106 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15107 15108 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15109 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15110 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15111 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15112 15113 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15114 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15115 15116 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15117 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15118 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15119 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15120 15121#undef ARM_VARIANT 15122#define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */ 15123 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld), 15124 TC3(ldrd, 00000d0, e8500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), 15125 TC3(strd, 00000f0, e8400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), 15126 15127 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15128 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15129 15130#undef ARM_VARIANT 15131#define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */ 15132 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), 15133 15134#undef ARM_VARIANT 15135#define ARM_VARIANT &arm_ext_v6 /* ARM V6. */ 15136#undef THUMB_VARIANT 15137#define THUMB_VARIANT &arm_ext_v6 15138 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), 15139 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), 15140 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), 15141 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), 15142 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), 15143 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15144 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15145 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15146 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15147 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend), 15148 15149#undef THUMB_VARIANT 15150#define THUMB_VARIANT &arm_ext_v6t2 15151 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex), 15152 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex), 15153 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15154 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15155 15156 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), 15157 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), 15158 15159/* ARM V6 not included in V7M (eg. integer SIMD). */ 15160#undef THUMB_VARIANT 15161#define THUMB_VARIANT &arm_ext_v6_notm 15162 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, t_cps), 15163 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), 15164 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), 15165 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15166 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15167 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15168 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15169 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15170 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15171 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15172 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15173 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15174 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15175 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15176 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15177 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15178 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15179 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15180 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15181 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15182 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15183 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15184 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15185 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15186 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15187 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15188 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15189 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15190 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15191 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15192 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15193 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15194 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15195 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15196 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15197 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15198 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15199 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15200 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15201 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe), 15202 UF(rfeib, 9900a00, 1, (RRw), rfe), 15203 UF(rfeda, 8100a00, 1, (RRw), rfe), 15204 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe), 15205 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe), 15206 UF(rfefa, 9900a00, 1, (RRw), rfe), 15207 UF(rfeea, 8100a00, 1, (RRw), rfe), 15208 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe), 15209 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15210 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15211 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15212 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15213 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15214 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15215 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15216 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15217 TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15218 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15219 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15220 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15221 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15222 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15223 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15224 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15225 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15226 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15227 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15228 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15229 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15230 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15231 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15232 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15233 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15234 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15235 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15236 TUF(srsia, 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), 15237 UF(srsib, 9c00500, 2, (oRRw, I31w), srs), 15238 UF(srsda, 8400500, 2, (oRRw, I31w), srs), 15239 TUF(srsdb, 9400500, e800c000, 2, (oRRw, I31w), srs, srs), 15240 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), 15241 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), 15242 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15243 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15244 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), 15245 15246#undef ARM_VARIANT 15247#define ARM_VARIANT &arm_ext_v6k 15248#undef THUMB_VARIANT 15249#define THUMB_VARIANT &arm_ext_v6k 15250 tCE(yield, 320f001, yield, 0, (), noargs, t_hint), 15251 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint), 15252 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint), 15253 tCE(sev, 320f004, sev, 0, (), noargs, t_hint), 15254 15255#undef THUMB_VARIANT 15256#define THUMB_VARIANT &arm_ext_v6_notm 15257 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd), 15258 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd), 15259 15260#undef THUMB_VARIANT 15261#define THUMB_VARIANT &arm_ext_v6t2 15262 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), 15263 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), 15264 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), 15265 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), 15266 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs), 15267 15268#undef ARM_VARIANT 15269#define ARM_VARIANT &arm_ext_v6z 15270 TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc), 15271 15272#undef ARM_VARIANT 15273#define ARM_VARIANT &arm_ext_v6t2 15274 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), 15275 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), 15276 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), 15277 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), 15278 15279 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), 15280 TCE(movw, 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), 15281 TCE(movt, 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), 15282 TCE(rbit, 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), 15283 15284 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15285 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15286 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15287 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15288 15289 UT(cbnz, b900, 2, (RR, EXP), t_cbz), 15290 UT(cbz, b100, 2, (RR, EXP), t_cbz), 15291 /* ARM does not really have an IT instruction, so always allow it. */ 15292#undef ARM_VARIANT 15293#define ARM_VARIANT &arm_ext_v1 15294 TUE(it, 0, bf08, 1, (COND), it, t_it), 15295 TUE(itt, 0, bf0c, 1, (COND), it, t_it), 15296 TUE(ite, 0, bf04, 1, (COND), it, t_it), 15297 TUE(ittt, 0, bf0e, 1, (COND), it, t_it), 15298 TUE(itet, 0, bf06, 1, (COND), it, t_it), 15299 TUE(itte, 0, bf0a, 1, (COND), it, t_it), 15300 TUE(itee, 0, bf02, 1, (COND), it, t_it), 15301 TUE(itttt, 0, bf0f, 1, (COND), it, t_it), 15302 TUE(itett, 0, bf07, 1, (COND), it, t_it), 15303 TUE(ittet, 0, bf0b, 1, (COND), it, t_it), 15304 TUE(iteet, 0, bf03, 1, (COND), it, t_it), 15305 TUE(ittte, 0, bf0d, 1, (COND), it, t_it), 15306 TUE(itete, 0, bf05, 1, (COND), it, t_it), 15307 TUE(ittee, 0, bf09, 1, (COND), it, t_it), 15308 TUE(iteee, 0, bf01, 1, (COND), it, t_it), 15309 15310 /* Thumb2 only instructions. */ 15311#undef ARM_VARIANT 15312#define ARM_VARIANT NULL 15313 15314 TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), 15315 TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), 15316 TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb), 15317 TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb), 15318 15319 /* Thumb-2 hardware division instructions (R and M profiles only). */ 15320#undef THUMB_VARIANT 15321#define THUMB_VARIANT &arm_ext_div 15322 TCE(sdiv, 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div), 15323 TCE(udiv, 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div), 15324 15325 /* ARM V7 instructions. */ 15326#undef ARM_VARIANT 15327#define ARM_VARIANT &arm_ext_v7 15328#undef THUMB_VARIANT 15329#define THUMB_VARIANT &arm_ext_v7 15330 TUF(pli, 450f000, f910f000, 1, (ADDR), pli, t_pld), 15331 TCE(dbg, 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), 15332 TUF(dmb, 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier), 15333 TUF(dsb, 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier), 15334 TUF(isb, 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier), 15335 15336#undef ARM_VARIANT 15337#define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ 15338 cCE(wfs, e200110, 1, (RR), rd), 15339 cCE(rfs, e300110, 1, (RR), rd), 15340 cCE(wfc, e400110, 1, (RR), rd), 15341 cCE(rfc, e500110, 1, (RR), rd), 15342 15343 cCL(ldfs, c100100, 2, (RF, ADDRGLDC), rd_cpaddr), 15344 cCL(ldfd, c108100, 2, (RF, ADDRGLDC), rd_cpaddr), 15345 cCL(ldfe, c500100, 2, (RF, ADDRGLDC), rd_cpaddr), 15346 cCL(ldfp, c508100, 2, (RF, ADDRGLDC), rd_cpaddr), 15347 15348 cCL(stfs, c000100, 2, (RF, ADDRGLDC), rd_cpaddr), 15349 cCL(stfd, c008100, 2, (RF, ADDRGLDC), rd_cpaddr), 15350 cCL(stfe, c400100, 2, (RF, ADDRGLDC), rd_cpaddr), 15351 cCL(stfp, c408100, 2, (RF, ADDRGLDC), rd_cpaddr), 15352 15353 cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm), 15354 cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm), 15355 cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm), 15356 cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm), 15357 cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm), 15358 cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm), 15359 cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm), 15360 cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm), 15361 cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm), 15362 cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm), 15363 cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm), 15364 cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm), 15365 15366 cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm), 15367 cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm), 15368 cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm), 15369 cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm), 15370 cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm), 15371 cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm), 15372 cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm), 15373 cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm), 15374 cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm), 15375 cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm), 15376 cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm), 15377 cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm), 15378 15379 cCL(abss, e208100, 2, (RF, RF_IF), rd_rm), 15380 cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm), 15381 cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm), 15382 cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm), 15383 cCL(absd, e208180, 2, (RF, RF_IF), rd_rm), 15384 cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm), 15385 cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm), 15386 cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm), 15387 cCL(abse, e288100, 2, (RF, RF_IF), rd_rm), 15388 cCL(absep, e288120, 2, (RF, RF_IF), rd_rm), 15389 cCL(absem, e288140, 2, (RF, RF_IF), rd_rm), 15390 cCL(absez, e288160, 2, (RF, RF_IF), rd_rm), 15391 15392 cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm), 15393 cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm), 15394 cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm), 15395 cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm), 15396 cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm), 15397 cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm), 15398 cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm), 15399 cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm), 15400 cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm), 15401 cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm), 15402 cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm), 15403 cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm), 15404 15405 cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm), 15406 cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm), 15407 cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm), 15408 cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm), 15409 cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm), 15410 cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm), 15411 cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm), 15412 cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm), 15413 cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm), 15414 cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm), 15415 cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm), 15416 cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm), 15417 15418 cCL(logs, e508100, 2, (RF, RF_IF), rd_rm), 15419 cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm), 15420 cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm), 15421 cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm), 15422 cCL(logd, e508180, 2, (RF, RF_IF), rd_rm), 15423 cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm), 15424 cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm), 15425 cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm), 15426 cCL(loge, e588100, 2, (RF, RF_IF), rd_rm), 15427 cCL(logep, e588120, 2, (RF, RF_IF), rd_rm), 15428 cCL(logem, e588140, 2, (RF, RF_IF), rd_rm), 15429 cCL(logez, e588160, 2, (RF, RF_IF), rd_rm), 15430 15431 cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm), 15432 cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm), 15433 cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm), 15434 cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm), 15435 cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm), 15436 cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm), 15437 cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm), 15438 cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm), 15439 cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm), 15440 cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm), 15441 cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm), 15442 cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm), 15443 15444 cCL(exps, e708100, 2, (RF, RF_IF), rd_rm), 15445 cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm), 15446 cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm), 15447 cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm), 15448 cCL(expd, e708180, 2, (RF, RF_IF), rd_rm), 15449 cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm), 15450 cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm), 15451 cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm), 15452 cCL(expe, e788100, 2, (RF, RF_IF), rd_rm), 15453 cCL(expep, e788120, 2, (RF, RF_IF), rd_rm), 15454 cCL(expem, e788140, 2, (RF, RF_IF), rd_rm), 15455 cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm), 15456 15457 cCL(sins, e808100, 2, (RF, RF_IF), rd_rm), 15458 cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm), 15459 cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm), 15460 cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm), 15461 cCL(sind, e808180, 2, (RF, RF_IF), rd_rm), 15462 cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm), 15463 cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm), 15464 cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm), 15465 cCL(sine, e888100, 2, (RF, RF_IF), rd_rm), 15466 cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm), 15467 cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm), 15468 cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm), 15469 15470 cCL(coss, e908100, 2, (RF, RF_IF), rd_rm), 15471 cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm), 15472 cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm), 15473 cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm), 15474 cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm), 15475 cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm), 15476 cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm), 15477 cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm), 15478 cCL(cose, e988100, 2, (RF, RF_IF), rd_rm), 15479 cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm), 15480 cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm), 15481 cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm), 15482 15483 cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm), 15484 cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm), 15485 cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm), 15486 cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm), 15487 cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm), 15488 cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm), 15489 cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm), 15490 cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm), 15491 cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm), 15492 cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm), 15493 cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm), 15494 cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm), 15495 15496 cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm), 15497 cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm), 15498 cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm), 15499 cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm), 15500 cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm), 15501 cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm), 15502 cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm), 15503 cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm), 15504 cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm), 15505 cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm), 15506 cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm), 15507 cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm), 15508 15509 cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm), 15510 cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm), 15511 cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm), 15512 cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm), 15513 cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm), 15514 cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm), 15515 cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm), 15516 cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm), 15517 cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm), 15518 cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm), 15519 cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm), 15520 cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm), 15521 15522 cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm), 15523 cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm), 15524 cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm), 15525 cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm), 15526 cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm), 15527 cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm), 15528 cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm), 15529 cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm), 15530 cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm), 15531 cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm), 15532 cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm), 15533 cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm), 15534 15535 cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm), 15536 cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm), 15537 cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm), 15538 cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm), 15539 cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm), 15540 cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm), 15541 cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm), 15542 cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm), 15543 cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm), 15544 cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm), 15545 cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm), 15546 cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm), 15547 15548 cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm), 15549 cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm), 15550 cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm), 15551 cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm), 15552 cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm), 15553 cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm), 15554 cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm), 15555 cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm), 15556 cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm), 15557 cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm), 15558 cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm), 15559 cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm), 15560 15561 cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm), 15562 cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm), 15563 cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm), 15564 cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm), 15565 cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm), 15566 cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15567 cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15568 cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15569 cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm), 15570 cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm), 15571 cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm), 15572 cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm), 15573 15574 cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm), 15575 cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm), 15576 cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm), 15577 cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm), 15578 cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm), 15579 cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15580 cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15581 cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15582 cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm), 15583 cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm), 15584 cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm), 15585 cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm), 15586 15587 cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm), 15588 cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm), 15589 cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm), 15590 cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm), 15591 cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm), 15592 cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15593 cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15594 cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15595 cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm), 15596 cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm), 15597 cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm), 15598 cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm), 15599 15600 cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm), 15601 cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm), 15602 cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm), 15603 cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm), 15604 cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm), 15605 cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15606 cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15607 cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15608 cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm), 15609 cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm), 15610 cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm), 15611 cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm), 15612 15613 cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm), 15614 cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm), 15615 cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm), 15616 cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm), 15617 cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm), 15618 cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15619 cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15620 cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15621 cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm), 15622 cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm), 15623 cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm), 15624 cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm), 15625 15626 cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm), 15627 cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm), 15628 cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm), 15629 cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm), 15630 cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm), 15631 cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15632 cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15633 cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15634 cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm), 15635 cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm), 15636 cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm), 15637 cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm), 15638 15639 cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm), 15640 cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm), 15641 cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm), 15642 cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm), 15643 cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm), 15644 cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15645 cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15646 cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15647 cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm), 15648 cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm), 15649 cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm), 15650 cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm), 15651 15652 cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm), 15653 cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm), 15654 cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm), 15655 cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm), 15656 cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm), 15657 cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15658 cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15659 cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15660 cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm), 15661 cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm), 15662 cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm), 15663 cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm), 15664 15665 cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm), 15666 cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm), 15667 cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm), 15668 cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm), 15669 cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm), 15670 cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15671 cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15672 cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15673 cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm), 15674 cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm), 15675 cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm), 15676 cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm), 15677 15678 cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm), 15679 cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm), 15680 cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm), 15681 cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm), 15682 cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm), 15683 cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15684 cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15685 cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15686 cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm), 15687 cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm), 15688 cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm), 15689 cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm), 15690 15691 cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), 15692 cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), 15693 cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), 15694 cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), 15695 cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), 15696 cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15697 cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15698 cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15699 cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), 15700 cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), 15701 cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), 15702 cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), 15703 15704 cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), 15705 cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), 15706 cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), 15707 cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), 15708 cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), 15709 cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15710 cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15711 cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15712 cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), 15713 cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), 15714 cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), 15715 cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), 15716 15717 cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), 15718 cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), 15719 cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), 15720 cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), 15721 cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), 15722 cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15723 cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15724 cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15725 cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), 15726 cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), 15727 cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), 15728 cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), 15729 15730 cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp), 15731 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp), 15732 cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp), 15733 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp), 15734 15735 cCL(flts, e000110, 2, (RF, RR), rn_rd), 15736 cCL(fltsp, e000130, 2, (RF, RR), rn_rd), 15737 cCL(fltsm, e000150, 2, (RF, RR), rn_rd), 15738 cCL(fltsz, e000170, 2, (RF, RR), rn_rd), 15739 cCL(fltd, e000190, 2, (RF, RR), rn_rd), 15740 cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd), 15741 cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd), 15742 cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd), 15743 cCL(flte, e080110, 2, (RF, RR), rn_rd), 15744 cCL(fltep, e080130, 2, (RF, RR), rn_rd), 15745 cCL(fltem, e080150, 2, (RF, RR), rn_rd), 15746 cCL(fltez, e080170, 2, (RF, RR), rn_rd), 15747 15748 /* The implementation of the FIX instruction is broken on some 15749 assemblers, in that it accepts a precision specifier as well as a 15750 rounding specifier, despite the fact that this is meaningless. 15751 To be more compatible, we accept it as well, though of course it 15752 does not set any bits. */ 15753 cCE(fix, e100110, 2, (RR, RF), rd_rm), 15754 cCL(fixp, e100130, 2, (RR, RF), rd_rm), 15755 cCL(fixm, e100150, 2, (RR, RF), rd_rm), 15756 cCL(fixz, e100170, 2, (RR, RF), rd_rm), 15757 cCL(fixsp, e100130, 2, (RR, RF), rd_rm), 15758 cCL(fixsm, e100150, 2, (RR, RF), rd_rm), 15759 cCL(fixsz, e100170, 2, (RR, RF), rd_rm), 15760 cCL(fixdp, e100130, 2, (RR, RF), rd_rm), 15761 cCL(fixdm, e100150, 2, (RR, RF), rd_rm), 15762 cCL(fixdz, e100170, 2, (RR, RF), rd_rm), 15763 cCL(fixep, e100130, 2, (RR, RF), rd_rm), 15764 cCL(fixem, e100150, 2, (RR, RF), rd_rm), 15765 cCL(fixez, e100170, 2, (RR, RF), rd_rm), 15766 15767 /* Instructions that were new with the real FPA, call them V2. */ 15768#undef ARM_VARIANT 15769#define ARM_VARIANT &fpu_fpa_ext_v2 15770 cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15771 cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15772 cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15773 cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15774 cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15775 cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15776 15777#undef ARM_VARIANT 15778#define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ 15779 /* Moves and type conversions. */ 15780 cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic), 15781 cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp), 15782 cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg), 15783 cCE(fmstat, ef1fa10, 0, (), noargs), 15784 cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), 15785 cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic), 15786 cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), 15787 cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), 15788 cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), 15789 cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), 15790 cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn), 15791 cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd), 15792 cCE(vmrs, ef00a10, 2, (APSR_RR, RVC), vfp_vmrs), 15793 cCE(vmsr, ee00a10, 2, (RVC, RR), vfp_vmsr), 15794 15795 /* Memory operations. */ 15796 cCE(flds, d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), 15797 cCE(fsts, d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), 15798 cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15799 cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15800 cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15801 cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15802 cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15803 cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15804 cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15805 cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15806 cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15807 cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15808 cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15809 cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15810 cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15811 cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15812 cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15813 cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15814 15815 /* Monadic operations. */ 15816 cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), 15817 cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic), 15818 cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), 15819 15820 /* Dyadic operations. */ 15821 cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15822 cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15823 cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15824 cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15825 cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15826 cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15827 cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15828 cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15829 cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15830 15831 /* Comparisons. */ 15832 cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic), 15833 cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z), 15834 cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), 15835 cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z), 15836 15837#undef ARM_VARIANT 15838#define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ 15839 /* Moves and type conversions. */ 15840 cCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), 15841 cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), 15842 cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 15843 cCE(fmdhr, e200b10, 2, (RVD, RR), vfp_dp_rn_rd), 15844 cCE(fmdlr, e000b10, 2, (RVD, RR), vfp_dp_rn_rd), 15845 cCE(fmrdh, e300b10, 2, (RR, RVD), vfp_dp_rd_rn), 15846 cCE(fmrdl, e100b10, 2, (RR, RVD), vfp_dp_rd_rn), 15847 cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), 15848 cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), 15849 cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), 15850 cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 15851 cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), 15852 cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 15853 15854 /* Memory operations. */ 15855 cCE(fldd, d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), 15856 cCE(fstd, d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), 15857 cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15858 cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15859 cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15860 cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15861 cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15862 cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15863 cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15864 cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15865 15866 /* Monadic operations. */ 15867 cCE(fabsd, eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 15868 cCE(fnegd, eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), 15869 cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 15870 15871 /* Dyadic operations. */ 15872 cCE(faddd, e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15873 cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15874 cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15875 cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15876 cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15877 cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15878 cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15879 cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15880 cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15881 15882 /* Comparisons. */ 15883 cCE(fcmpd, eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), 15884 cCE(fcmpzd, eb50b40, 1, (RVD), vfp_dp_rd), 15885 cCE(fcmped, eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 15886 cCE(fcmpezd, eb50bc0, 1, (RVD), vfp_dp_rd), 15887 15888#undef ARM_VARIANT 15889#define ARM_VARIANT &fpu_vfp_ext_v2 15890 cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), 15891 cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), 15892 cCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), 15893 cCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), 15894 15895/* Instructions which may belong to either the Neon or VFP instruction sets. 15896 Individual encoder functions perform additional architecture checks. */ 15897#undef ARM_VARIANT 15898#define ARM_VARIANT &fpu_vfp_ext_v1xd 15899#undef THUMB_VARIANT 15900#define THUMB_VARIANT &fpu_vfp_ext_v1xd 15901 /* These mnemonics are unique to VFP. */ 15902 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), 15903 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), 15904 nCE(vnmul, vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 15905 nCE(vnmla, vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 15906 nCE(vnmls, vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 15907 nCE(vcmp, vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), 15908 nCE(vcmpe, vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), 15909 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), 15910 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), 15911 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), 15912 15913 /* Mnemonics shared by Neon and VFP. */ 15914 nCEF(vmul, vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), 15915 nCEF(vmla, vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), 15916 nCEF(vmls, vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), 15917 15918 nCEF(vadd, vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), 15919 nCEF(vsub, vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), 15920 15921 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), 15922 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), 15923 15924 NCE(vldm, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15925 NCE(vldmia, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15926 NCE(vldmdb, d100b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15927 NCE(vstm, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15928 NCE(vstmia, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15929 NCE(vstmdb, d000b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15930 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), 15931 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), 15932 15933 nCEF(vcvt, vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt), 15934 15935 /* NOTE: All VMOV encoding is special-cased! */ 15936 NCE(vmov, 0, 1, (VMOV), neon_mov), 15937 NCE(vmovq, 0, 1, (VMOV), neon_mov), 15938 15939#undef THUMB_VARIANT 15940#define THUMB_VARIANT &fpu_neon_ext_v1 15941#undef ARM_VARIANT 15942#define ARM_VARIANT &fpu_neon_ext_v1 15943 /* Data processing with three registers of the same length. */ 15944 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ 15945 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), 15946 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), 15947 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 15948 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 15949 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 15950 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 15951 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 15952 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 15953 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ 15954 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), 15955 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), 15956 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), 15957 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), 15958 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), 15959 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), 15960 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), 15961 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), 15962 /* If not immediate, fall back to neon_dyadic_i64_su. 15963 shl_imm should accept I8 I16 I32 I64, 15964 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ 15965 nUF(vshl, vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), 15966 nUF(vshlq, vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), 15967 nUF(vqshl, vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), 15968 nUF(vqshlq, vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), 15969 /* Logic ops, types optional & ignored. */ 15970 nUF(vand, vand, 2, (RNDQ, NILO), neon_logic), 15971 nUF(vandq, vand, 2, (RNQ, NILO), neon_logic), 15972 nUF(vbic, vbic, 2, (RNDQ, NILO), neon_logic), 15973 nUF(vbicq, vbic, 2, (RNQ, NILO), neon_logic), 15974 nUF(vorr, vorr, 2, (RNDQ, NILO), neon_logic), 15975 nUF(vorrq, vorr, 2, (RNQ, NILO), neon_logic), 15976 nUF(vorn, vorn, 2, (RNDQ, NILO), neon_logic), 15977 nUF(vornq, vorn, 2, (RNQ, NILO), neon_logic), 15978 nUF(veor, veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), 15979 nUF(veorq, veor, 3, (RNQ, oRNQ, RNQ), neon_logic), 15980 /* Bitfield ops, untyped. */ 15981 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 15982 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 15983 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 15984 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 15985 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 15986 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 15987 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ 15988 nUF(vabd, vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 15989 nUF(vabdq, vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 15990 nUF(vmax, vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 15991 nUF(vmaxq, vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 15992 nUF(vmin, vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 15993 nUF(vminq, vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 15994 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall 15995 back to neon_dyadic_if_su. */ 15996 nUF(vcge, vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), 15997 nUF(vcgeq, vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), 15998 nUF(vcgt, vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), 15999 nUF(vcgtq, vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), 16000 nUF(vclt, vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), 16001 nUF(vcltq, vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), 16002 nUF(vcle, vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), 16003 nUF(vcleq, vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), 16004 /* Comparison. Type I8 I16 I32 F32. */ 16005 nUF(vceq, vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), 16006 nUF(vceqq, vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), 16007 /* As above, D registers only. */ 16008 nUF(vpmax, vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), 16009 nUF(vpmin, vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), 16010 /* Int and float variants, signedness unimportant. */ 16011 nUF(vmlaq, vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), 16012 nUF(vmlsq, vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), 16013 nUF(vpadd, vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), 16014 /* Add/sub take types I8 I16 I32 I64 F32. */ 16015 nUF(vaddq, vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), 16016 nUF(vsubq, vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), 16017 /* vtst takes sizes 8, 16, 32. */ 16018 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), 16019 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), 16020 /* VMUL takes I8 I16 I32 F32 P8. */ 16021 nUF(vmulq, vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), 16022 /* VQD{R}MULH takes S16 S32. */ 16023 nUF(vqdmulh, vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), 16024 nUF(vqdmulhq, vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), 16025 nUF(vqrdmulh, vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), 16026 nUF(vqrdmulhq, vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), 16027 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), 16028 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), 16029 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), 16030 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), 16031 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), 16032 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), 16033 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), 16034 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), 16035 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), 16036 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), 16037 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), 16038 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), 16039 16040 /* Two address, int/float. Types S8 S16 S32 F32. */ 16041 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), 16042 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), 16043 16044 /* Data processing with two registers and a shift amount. */ 16045 /* Right shifts, and variants with rounding. 16046 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ 16047 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), 16048 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), 16049 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), 16050 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), 16051 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), 16052 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), 16053 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), 16054 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), 16055 /* Shift and insert. Sizes accepted 8 16 32 64. */ 16056 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), 16057 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), 16058 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), 16059 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), 16060 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ 16061 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), 16062 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), 16063 /* Right shift immediate, saturating & narrowing, with rounding variants. 16064 Types accepted S16 S32 S64 U16 U32 U64. */ 16065 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), 16066 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), 16067 /* As above, unsigned. Types accepted S16 S32 S64. */ 16068 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), 16069 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), 16070 /* Right shift narrowing. Types accepted I16 I32 I64. */ 16071 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), 16072 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), 16073 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ 16074 nUF(vshll, vshll, 3, (RNQ, RND, I32), neon_shll), 16075 /* CVT with optional immediate for fixed-point variant. */ 16076 nUF(vcvtq, vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), 16077 16078 nUF(vmvn, vmvn, 2, (RNDQ, RNDQ_IMVNb), neon_mvn), 16079 nUF(vmvnq, vmvn, 2, (RNQ, RNDQ_IMVNb), neon_mvn), 16080 16081 /* Data processing, three registers of different lengths. */ 16082 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ 16083 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), 16084 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), 16085 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), 16086 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), 16087 /* If not scalar, fall back to neon_dyadic_long. 16088 Vector types as above, scalar types S16 S32 U16 U32. */ 16089 nUF(vmlal, vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), 16090 nUF(vmlsl, vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), 16091 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ 16092 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), 16093 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), 16094 /* Dyadic, narrowing insns. Types I16 I32 I64. */ 16095 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16096 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16097 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16098 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16099 /* Saturating doubling multiplies. Types S16 S32. */ 16100 nUF(vqdmlal, vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 16101 nUF(vqdmlsl, vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 16102 nUF(vqdmull, vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 16103 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types 16104 S16 S32 U16 U32. */ 16105 nUF(vmull, vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), 16106 16107 /* Extract. Size 8. */ 16108 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), 16109 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), 16110 16111 /* Two registers, miscellaneous. */ 16112 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ 16113 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), 16114 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), 16115 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), 16116 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), 16117 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), 16118 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), 16119 /* Vector replicate. Sizes 8 16 32. */ 16120 nCE(vdup, vdup, 2, (RNDQ, RR_RNSC), neon_dup), 16121 nCE(vdupq, vdup, 2, (RNQ, RR_RNSC), neon_dup), 16122 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ 16123 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), 16124 /* VMOVN. Types I16 I32 I64. */ 16125 nUF(vmovn, vmovn, 2, (RND, RNQ), neon_movn), 16126 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ 16127 nUF(vqmovn, vqmovn, 2, (RND, RNQ), neon_qmovn), 16128 /* VQMOVUN. Types S16 S32 S64. */ 16129 nUF(vqmovun, vqmovun, 2, (RND, RNQ), neon_qmovun), 16130 /* VZIP / VUZP. Sizes 8 16 32. */ 16131 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), 16132 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), 16133 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), 16134 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), 16135 /* VQABS / VQNEG. Types S8 S16 S32. */ 16136 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), 16137 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), 16138 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), 16139 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), 16140 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ 16141 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), 16142 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), 16143 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), 16144 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), 16145 /* Reciprocal estimates. Types U32 F32. */ 16146 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), 16147 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), 16148 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), 16149 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), 16150 /* VCLS. Types S8 S16 S32. */ 16151 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), 16152 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), 16153 /* VCLZ. Types I8 I16 I32. */ 16154 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), 16155 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), 16156 /* VCNT. Size 8. */ 16157 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), 16158 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), 16159 /* Two address, untyped. */ 16160 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), 16161 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), 16162 /* VTRN. Sizes 8 16 32. */ 16163 nUF(vtrn, vtrn, 2, (RNDQ, RNDQ), neon_trn), 16164 nUF(vtrnq, vtrn, 2, (RNQ, RNQ), neon_trn), 16165 16166 /* Table lookup. Size 8. */ 16167 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), 16168 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), 16169 16170#undef THUMB_VARIANT 16171#define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext 16172#undef ARM_VARIANT 16173#define ARM_VARIANT &fpu_vfp_v3_or_neon_ext 16174 /* Neon element/structure load/store. */ 16175 nUF(vld1, vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), 16176 nUF(vst1, vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), 16177 nUF(vld2, vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), 16178 nUF(vst2, vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), 16179 nUF(vld3, vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), 16180 nUF(vst3, vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), 16181 nUF(vld4, vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), 16182 nUF(vst4, vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), 16183 16184#undef THUMB_VARIANT 16185#define THUMB_VARIANT &fpu_vfp_ext_v3 16186#undef ARM_VARIANT 16187#define ARM_VARIANT &fpu_vfp_ext_v3 16188 cCE(fconsts, eb00a00, 2, (RVS, I255), vfp_sp_const), 16189 cCE(fconstd, eb00b00, 2, (RVD, I255), vfp_dp_const), 16190 cCE(fshtos, eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16191 cCE(fshtod, eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16192 cCE(fsltos, eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16193 cCE(fsltod, eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16194 cCE(fuhtos, ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16195 cCE(fuhtod, ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16196 cCE(fultos, ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16197 cCE(fultod, ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16198 cCE(ftoshs, ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16199 cCE(ftoshd, ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16200 cCE(ftosls, ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16201 cCE(ftosld, ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16202 cCE(ftouhs, ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16203 cCE(ftouhd, ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16204 cCE(ftouls, ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16205 cCE(ftould, ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16206 16207#undef THUMB_VARIANT 16208#undef ARM_VARIANT 16209#define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */ 16210 cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16211 cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16212 cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16213 cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16214 cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16215 cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16216 cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), 16217 cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), 16218 16219#undef ARM_VARIANT 16220#define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */ 16221 cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc), 16222 cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc), 16223 cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc), 16224 cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd), 16225 cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd), 16226 cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd), 16227 cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc), 16228 cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc), 16229 cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc), 16230 cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), 16231 cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), 16232 cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), 16233 cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), 16234 cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), 16235 cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), 16236 cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), 16237 cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), 16238 cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), 16239 cCE(tmcr, e000110, 2, (RIWC_RIWG, RR), rn_rd), 16240 cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn), 16241 cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16242 cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16243 cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16244 cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16245 cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16246 cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16247 cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn), 16248 cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn), 16249 cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn), 16250 cCE(tmrc, e100110, 2, (RR, RIWC_RIWG), rd_rn), 16251 cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm), 16252 cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc), 16253 cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc), 16254 cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc), 16255 cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn), 16256 cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn), 16257 cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn), 16258 cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16259 cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16260 cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16261 cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16262 cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16263 cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16264 cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16265 cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16266 cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16267 cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), 16268 cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16269 cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16270 cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16271 cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16272 cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16273 cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16274 cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16275 cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16276 cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16277 cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16278 cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16279 cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16280 cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16281 cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16282 cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16283 cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16284 cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16285 cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16286 cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16287 cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16288 cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16289 cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), 16290 cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), 16291 cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16292 cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16293 cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16294 cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16295 cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16296 cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16297 cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16298 cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16299 cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16300 cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16301 cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16302 cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16303 cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16304 cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16305 cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16306 cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16307 cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16308 cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16309 cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov), 16310 cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16311 cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16312 cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16313 cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16314 cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16315 cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16316 cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16317 cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16318 cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16319 cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16320 cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16321 cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16322 cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16323 cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16324 cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16325 cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16326 cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16327 cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16328 cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16329 cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16330 cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16331 cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), 16332 cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16333 cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16334 cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16335 cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16336 cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16337 cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16338 cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16339 cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16340 cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16341 cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16342 cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16343 cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16344 cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16345 cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16346 cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16347 cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16348 cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16349 cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16350 cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16351 cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16352 cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), 16353 cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), 16354 cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16355 cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16356 cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16357 cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16358 cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16359 cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16360 cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16361 cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16362 cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16363 cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn), 16364 cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn), 16365 cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn), 16366 cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn), 16367 cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn), 16368 cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn), 16369 cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16370 cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16371 cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16372 cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn), 16373 cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn), 16374 cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn), 16375 cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn), 16376 cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn), 16377 cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn), 16378 cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16379 cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16380 cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16381 cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16382 cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero), 16383 16384#undef ARM_VARIANT 16385#define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ 16386 cCE(torvscb, e13f190, 1, (RR), iwmmxt_tandorc), 16387 cCE(torvsch, e53f190, 1, (RR), iwmmxt_tandorc), 16388 cCE(torvscw, e93f190, 1, (RR), iwmmxt_tandorc), 16389 cCE(wabsb, e2001c0, 2, (RIWR, RIWR), rd_rn), 16390 cCE(wabsh, e6001c0, 2, (RIWR, RIWR), rd_rn), 16391 cCE(wabsw, ea001c0, 2, (RIWR, RIWR), rd_rn), 16392 cCE(wabsdiffb, e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16393 cCE(wabsdiffh, e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16394 cCE(wabsdiffw, e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16395 cCE(waddbhusl, e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16396 cCE(waddbhusm, e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16397 cCE(waddhc, e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16398 cCE(waddwc, ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16399 cCE(waddsubhx, ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16400 cCE(wavg4, e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16401 cCE(wavg4r, e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16402 cCE(wmaddsn, ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16403 cCE(wmaddsx, eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16404 cCE(wmaddun, ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16405 cCE(wmaddux, e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16406 cCE(wmerge, e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), 16407 cCE(wmiabb, e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16408 cCE(wmiabt, e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16409 cCE(wmiatb, e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16410 cCE(wmiatt, e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16411 cCE(wmiabbn, e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16412 cCE(wmiabtn, e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16413 cCE(wmiatbn, e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16414 cCE(wmiattn, e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16415 cCE(wmiawbb, e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16416 cCE(wmiawbt, e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16417 cCE(wmiawtb, ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16418 cCE(wmiawtt, eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16419 cCE(wmiawbbn, ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16420 cCE(wmiawbtn, ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16421 cCE(wmiawtbn, ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16422 cCE(wmiawttn, ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16423 cCE(wmulsmr, ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16424 cCE(wmulumr, ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16425 cCE(wmulwumr, ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16426 cCE(wmulwsmr, ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16427 cCE(wmulwum, ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16428 cCE(wmulwsm, ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16429 cCE(wmulwl, eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16430 cCE(wqmiabb, e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16431 cCE(wqmiabt, e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16432 cCE(wqmiatb, ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16433 cCE(wqmiatt, eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16434 cCE(wqmiabbn, ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16435 cCE(wqmiabtn, ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16436 cCE(wqmiatbn, ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16437 cCE(wqmiattn, ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16438 cCE(wqmulm, e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16439 cCE(wqmulmr, e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16440 cCE(wqmulwm, ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16441 cCE(wqmulwmr, ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16442 cCE(wsubaddhx, ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16443 16444#undef ARM_VARIANT 16445#define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */ 16446 cCE(cfldrs, c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), 16447 cCE(cfldrd, c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), 16448 cCE(cfldr32, c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), 16449 cCE(cfldr64, c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), 16450 cCE(cfstrs, c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), 16451 cCE(cfstrd, c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), 16452 cCE(cfstr32, c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), 16453 cCE(cfstr64, c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), 16454 cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd), 16455 cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn), 16456 cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd), 16457 cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn), 16458 cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd), 16459 cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn), 16460 cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd), 16461 cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn), 16462 cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd), 16463 cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn), 16464 cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn), 16465 cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn), 16466 cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn), 16467 cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn), 16468 cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn), 16469 cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn), 16470 cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn), 16471 cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn), 16472 cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn), 16473 cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn), 16474 cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc), 16475 cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd), 16476 cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn), 16477 cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn), 16478 cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn), 16479 cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn), 16480 cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn), 16481 cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn), 16482 cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn), 16483 cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn), 16484 cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn), 16485 cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn), 16486 cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn), 16487 cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn), 16488 cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple), 16489 cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple), 16490 cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift), 16491 cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift), 16492 cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm), 16493 cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), 16494 cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), 16495 cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), 16496 cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn), 16497 cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn), 16498 cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn), 16499 cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn), 16500 cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm), 16501 cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), 16502 cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), 16503 cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), 16504 cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm), 16505 cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm), 16506 cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn), 16507 cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn), 16508 cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn), 16509 cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn), 16510 cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16511 cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 16512 cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16513 cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 16514 cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16515 cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 16516 cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16517 cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16518 cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), 16519 cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), 16520 cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), 16521 cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), 16522}; 16523#undef ARM_VARIANT 16524#undef THUMB_VARIANT 16525#undef TCE 16526#undef TCM 16527#undef TUE 16528#undef TUF 16529#undef TCC 16530#undef cCE 16531#undef cCL 16532#undef C3E 16533#undef CE 16534#undef CM 16535#undef UE 16536#undef UF 16537#undef UT 16538#undef NUF 16539#undef nUF 16540#undef NCE 16541#undef nCE 16542#undef OPS0 16543#undef OPS1 16544#undef OPS2 16545#undef OPS3 16546#undef OPS4 16547#undef OPS5 16548#undef OPS6 16549#undef do_0 16550 16551/* MD interface: bits in the object file. */ 16552 16553/* Turn an integer of n bytes (in val) into a stream of bytes appropriate 16554 for use in the a.out file, and stores them in the array pointed to by buf. 16555 This knows about the endian-ness of the target machine and does 16556 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) 16557 2 (short) and 4 (long) Floating numbers are put out as a series of 16558 LITTLENUMS (shorts, here at least). */ 16559 16560void 16561md_number_to_chars (char * buf, valueT val, int n) 16562{ 16563 if (target_big_endian) 16564 number_to_chars_bigendian (buf, val, n); 16565 else 16566 number_to_chars_littleendian (buf, val, n); 16567} 16568 16569static valueT 16570md_chars_to_number (char * buf, int n) 16571{ 16572 valueT result = 0; 16573 unsigned char * where = (unsigned char *) buf; 16574 16575 if (target_big_endian) 16576 { 16577 while (n--) 16578 { 16579 result <<= 8; 16580 result |= (*where++ & 255); 16581 } 16582 } 16583 else 16584 { 16585 while (n--) 16586 { 16587 result <<= 8; 16588 result |= (where[n] & 255); 16589 } 16590 } 16591 16592 return result; 16593} 16594 16595/* MD interface: Sections. */ 16596 16597/* Estimate the size of a frag before relaxing. Assume everything fits in 16598 2 bytes. */ 16599 16600int 16601md_estimate_size_before_relax (fragS * fragp, 16602 segT segtype ATTRIBUTE_UNUSED) 16603{ 16604 fragp->fr_var = 2; 16605 return 2; 16606} 16607 16608/* Convert a machine dependent frag. */ 16609 16610void 16611md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) 16612{ 16613 unsigned long insn; 16614 unsigned long old_op; 16615 char *buf; 16616 expressionS exp; 16617 fixS *fixp; 16618 int reloc_type; 16619 int pc_rel; 16620 int opcode; 16621 16622 buf = fragp->fr_literal + fragp->fr_fix; 16623 16624 old_op = bfd_get_16(abfd, buf); 16625 if (fragp->fr_symbol) { 16626 exp.X_op = O_symbol; 16627 exp.X_add_symbol = fragp->fr_symbol; 16628 } else { 16629 exp.X_op = O_constant; 16630 } 16631 exp.X_add_number = fragp->fr_offset; 16632 opcode = fragp->fr_subtype; 16633 switch (opcode) 16634 { 16635 case T_MNEM_ldr_pc: 16636 case T_MNEM_ldr_pc2: 16637 case T_MNEM_ldr_sp: 16638 case T_MNEM_str_sp: 16639 case T_MNEM_ldr: 16640 case T_MNEM_ldrb: 16641 case T_MNEM_ldrh: 16642 case T_MNEM_str: 16643 case T_MNEM_strb: 16644 case T_MNEM_strh: 16645 if (fragp->fr_var == 4) 16646 { 16647 insn = THUMB_OP32(opcode); 16648 if ((old_op >> 12) == 4 || (old_op >> 12) == 9) 16649 { 16650 insn |= (old_op & 0x700) << 4; 16651 } 16652 else 16653 { 16654 insn |= (old_op & 7) << 12; 16655 insn |= (old_op & 0x38) << 13; 16656 } 16657 insn |= 0x00000c00; 16658 put_thumb32_insn (buf, insn); 16659 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; 16660 } 16661 else 16662 { 16663 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; 16664 } 16665 pc_rel = (opcode == T_MNEM_ldr_pc2); 16666 break; 16667 case T_MNEM_adr: 16668 if (fragp->fr_var == 4) 16669 { 16670 insn = THUMB_OP32 (opcode); 16671 insn |= (old_op & 0xf0) << 4; 16672 put_thumb32_insn (buf, insn); 16673 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; 16674 } 16675 else 16676 { 16677 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 16678 exp.X_add_number -= 4; 16679 } 16680 pc_rel = 1; 16681 break; 16682 case T_MNEM_mov: 16683 case T_MNEM_movs: 16684 case T_MNEM_cmp: 16685 case T_MNEM_cmn: 16686 if (fragp->fr_var == 4) 16687 { 16688 int r0off = (opcode == T_MNEM_mov 16689 || opcode == T_MNEM_movs) ? 0 : 8; 16690 insn = THUMB_OP32 (opcode); 16691 insn = (insn & 0xe1ffffff) | 0x10000000; 16692 insn |= (old_op & 0x700) << r0off; 16693 put_thumb32_insn (buf, insn); 16694 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; 16695 } 16696 else 16697 { 16698 reloc_type = BFD_RELOC_ARM_THUMB_IMM; 16699 } 16700 pc_rel = 0; 16701 break; 16702 case T_MNEM_b: 16703 if (fragp->fr_var == 4) 16704 { 16705 insn = THUMB_OP32(opcode); 16706 put_thumb32_insn (buf, insn); 16707 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; 16708 } 16709 else 16710 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; 16711 pc_rel = 1; 16712 break; 16713 case T_MNEM_bcond: 16714 if (fragp->fr_var == 4) 16715 { 16716 insn = THUMB_OP32(opcode); 16717 insn |= (old_op & 0xf00) << 14; 16718 put_thumb32_insn (buf, insn); 16719 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; 16720 } 16721 else 16722 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; 16723 pc_rel = 1; 16724 break; 16725 case T_MNEM_add_sp: 16726 case T_MNEM_add_pc: 16727 case T_MNEM_inc_sp: 16728 case T_MNEM_dec_sp: 16729 if (fragp->fr_var == 4) 16730 { 16731 /* ??? Choose between add and addw. */ 16732 insn = THUMB_OP32 (opcode); 16733 insn |= (old_op & 0xf0) << 4; 16734 put_thumb32_insn (buf, insn); 16735 if (opcode == T_MNEM_add_pc) 16736 reloc_type = BFD_RELOC_ARM_T32_IMM12; 16737 else 16738 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; 16739 } 16740 else 16741 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 16742 pc_rel = 0; 16743 break; 16744 16745 case T_MNEM_addi: 16746 case T_MNEM_addis: 16747 case T_MNEM_subi: 16748 case T_MNEM_subis: 16749 if (fragp->fr_var == 4) 16750 { 16751 insn = THUMB_OP32 (opcode); 16752 insn |= (old_op & 0xf0) << 4; 16753 insn |= (old_op & 0xf) << 16; 16754 put_thumb32_insn (buf, insn); 16755 if (insn & (1 << 20)) 16756 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; 16757 else 16758 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; 16759 } 16760 else 16761 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 16762 pc_rel = 0; 16763 break; 16764 default: 16765 abort(); 16766 } 16767 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, 16768 reloc_type); 16769 fixp->fx_file = fragp->fr_file; 16770 fixp->fx_line = fragp->fr_line; 16771 fragp->fr_fix += fragp->fr_var; 16772} 16773 16774/* Return the size of a relaxable immediate operand instruction. 16775 SHIFT and SIZE specify the form of the allowable immediate. */ 16776static int 16777relax_immediate (fragS *fragp, int size, int shift) 16778{ 16779 offsetT offset; 16780 offsetT mask; 16781 offsetT low; 16782 16783 /* ??? Should be able to do better than this. */ 16784 if (fragp->fr_symbol) 16785 return 4; 16786 16787 low = (1 << shift) - 1; 16788 mask = (1 << (shift + size)) - (1 << shift); 16789 offset = fragp->fr_offset; 16790 /* Force misaligned offsets to 32-bit variant. */ 16791 if (offset & low) 16792 return 4; 16793 if (offset & ~mask) 16794 return 4; 16795 return 2; 16796} 16797 16798/* Get the address of a symbol during relaxation. */ 16799static addressT 16800relaxed_symbol_addr(fragS *fragp, long stretch) 16801{ 16802 fragS *sym_frag; 16803 addressT addr; 16804 symbolS *sym; 16805 16806 sym = fragp->fr_symbol; 16807 sym_frag = symbol_get_frag (sym); 16808 know (S_GET_SEGMENT (sym) != absolute_section 16809 || sym_frag == &zero_address_frag); 16810 addr = S_GET_VALUE (sym) + fragp->fr_offset; 16811 16812 /* If frag has yet to be reached on this pass, assume it will 16813 move by STRETCH just as we did. If this is not so, it will 16814 be because some frag between grows, and that will force 16815 another pass. */ 16816 16817 if (stretch != 0 16818 && sym_frag->relax_marker != fragp->relax_marker) 16819 addr += stretch; 16820 16821 return addr; 16822} 16823 16824/* Return the size of a relaxable adr pseudo-instruction or PC-relative 16825 load. */ 16826static int 16827relax_adr (fragS *fragp, asection *sec, long stretch) 16828{ 16829 addressT addr; 16830 offsetT val; 16831 16832 /* Assume worst case for symbols not known to be in the same section. */ 16833 if (!S_IS_DEFINED(fragp->fr_symbol) 16834 || sec != S_GET_SEGMENT (fragp->fr_symbol)) 16835 return 4; 16836 16837 val = relaxed_symbol_addr(fragp, stretch); 16838 addr = fragp->fr_address + fragp->fr_fix; 16839 addr = (addr + 4) & ~3; 16840 /* Force misaligned targets to 32-bit variant. */ 16841 if (val & 3) 16842 return 4; 16843 val -= addr; 16844 if (val < 0 || val > 1020) 16845 return 4; 16846 return 2; 16847} 16848 16849/* Return the size of a relaxable add/sub immediate instruction. */ 16850static int 16851relax_addsub (fragS *fragp, asection *sec) 16852{ 16853 char *buf; 16854 int op; 16855 16856 buf = fragp->fr_literal + fragp->fr_fix; 16857 op = bfd_get_16(sec->owner, buf); 16858 if ((op & 0xf) == ((op >> 4) & 0xf)) 16859 return relax_immediate (fragp, 8, 0); 16860 else 16861 return relax_immediate (fragp, 3, 0); 16862} 16863 16864 16865/* Return the size of a relaxable branch instruction. BITS is the 16866 size of the offset field in the narrow instruction. */ 16867 16868static int 16869relax_branch (fragS *fragp, asection *sec, int bits, long stretch) 16870{ 16871 addressT addr; 16872 offsetT val; 16873 offsetT limit; 16874 16875 /* Assume worst case for symbols not known to be in the same section. */ 16876 if (!S_IS_DEFINED(fragp->fr_symbol) 16877 || sec != S_GET_SEGMENT (fragp->fr_symbol)) 16878 return 4; 16879 16880 val = relaxed_symbol_addr(fragp, stretch); 16881 addr = fragp->fr_address + fragp->fr_fix + 4; 16882 val -= addr; 16883 16884 /* Offset is a signed value *2 */ 16885 limit = 1 << bits; 16886 if (val >= limit || val < -limit) 16887 return 4; 16888 return 2; 16889} 16890 16891 16892/* Relax a machine dependent frag. This returns the amount by which 16893 the current size of the frag should change. */ 16894 16895int 16896arm_relax_frag (asection *sec, fragS *fragp, long stretch) 16897{ 16898 int oldsize; 16899 int newsize; 16900 16901 oldsize = fragp->fr_var; 16902 switch (fragp->fr_subtype) 16903 { 16904 case T_MNEM_ldr_pc2: 16905 newsize = relax_adr(fragp, sec, stretch); 16906 break; 16907 case T_MNEM_ldr_pc: 16908 case T_MNEM_ldr_sp: 16909 case T_MNEM_str_sp: 16910 newsize = relax_immediate(fragp, 8, 2); 16911 break; 16912 case T_MNEM_ldr: 16913 case T_MNEM_str: 16914 newsize = relax_immediate(fragp, 5, 2); 16915 break; 16916 case T_MNEM_ldrh: 16917 case T_MNEM_strh: 16918 newsize = relax_immediate(fragp, 5, 1); 16919 break; 16920 case T_MNEM_ldrb: 16921 case T_MNEM_strb: 16922 newsize = relax_immediate(fragp, 5, 0); 16923 break; 16924 case T_MNEM_adr: 16925 newsize = relax_adr(fragp, sec, stretch); 16926 break; 16927 case T_MNEM_mov: 16928 case T_MNEM_movs: 16929 case T_MNEM_cmp: 16930 case T_MNEM_cmn: 16931 newsize = relax_immediate(fragp, 8, 0); 16932 break; 16933 case T_MNEM_b: 16934 newsize = relax_branch(fragp, sec, 11, stretch); 16935 break; 16936 case T_MNEM_bcond: 16937 newsize = relax_branch(fragp, sec, 8, stretch); 16938 break; 16939 case T_MNEM_add_sp: 16940 case T_MNEM_add_pc: 16941 newsize = relax_immediate (fragp, 8, 2); 16942 break; 16943 case T_MNEM_inc_sp: 16944 case T_MNEM_dec_sp: 16945 newsize = relax_immediate (fragp, 7, 2); 16946 break; 16947 case T_MNEM_addi: 16948 case T_MNEM_addis: 16949 case T_MNEM_subi: 16950 case T_MNEM_subis: 16951 newsize = relax_addsub (fragp, sec); 16952 break; 16953 default: 16954 abort(); 16955 } 16956 16957 fragp->fr_var = newsize; 16958 /* Freeze wide instructions that are at or before the same location as 16959 in the previous pass. This avoids infinite loops. 16960 Don't freeze them unconditionally because targets may be artificialy 16961 misaligned by the expansion of preceeding frags. */ 16962 if (stretch <= 0 && newsize > 2) 16963 { 16964 md_convert_frag (sec->owner, sec, fragp); 16965 frag_wane(fragp); 16966 } 16967 16968 return newsize - oldsize; 16969} 16970 16971/* Round up a section size to the appropriate boundary. */ 16972 16973valueT 16974md_section_align (segT segment ATTRIBUTE_UNUSED, 16975 valueT size) 16976{ 16977#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 16978 if (OUTPUT_FLAVOR == bfd_target_aout_flavour) 16979 { 16980 /* For a.out, force the section size to be aligned. If we don't do 16981 this, BFD will align it for us, but it will not write out the 16982 final bytes of the section. This may be a bug in BFD, but it is 16983 easier to fix it here since that is how the other a.out targets 16984 work. */ 16985 int align; 16986 16987 align = bfd_get_section_alignment (stdoutput, segment); 16988 size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); 16989 } 16990#endif 16991 16992 return size; 16993} 16994 16995/* This is called from HANDLE_ALIGN in write.c. Fill in the contents 16996 of an rs_align_code fragment. */ 16997 16998void 16999arm_handle_align (fragS * fragP) 17000{ 17001 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 }; 17002 static char const thumb_noop[2] = { 0xc0, 0x46 }; 17003 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 }; 17004 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 }; 17005 17006 int bytes, fix, noop_size; 17007 char * p; 17008 const char * noop; 17009 17010 if (fragP->fr_type != rs_align_code) 17011 return; 17012 17013 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; 17014 p = fragP->fr_literal + fragP->fr_fix; 17015 fix = 0; 17016 17017 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) 17018 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; 17019 17020 if (fragP->tc_frag_data) 17021 { 17022 if (target_big_endian) 17023 noop = thumb_bigend_noop; 17024 else 17025 noop = thumb_noop; 17026 noop_size = sizeof (thumb_noop); 17027 } 17028 else 17029 { 17030 if (target_big_endian) 17031 noop = arm_bigend_noop; 17032 else 17033 noop = arm_noop; 17034 noop_size = sizeof (arm_noop); 17035 } 17036 17037 if (bytes & (noop_size - 1)) 17038 { 17039 fix = bytes & (noop_size - 1); 17040 memset (p, 0, fix); 17041 p += fix; 17042 bytes -= fix; 17043 } 17044 17045 while (bytes >= noop_size) 17046 { 17047 memcpy (p, noop, noop_size); 17048 p += noop_size; 17049 bytes -= noop_size; 17050 fix += noop_size; 17051 } 17052 17053 fragP->fr_fix += fix; 17054 fragP->fr_var = noop_size; 17055} 17056 17057/* Called from md_do_align. Used to create an alignment 17058 frag in a code section. */ 17059 17060void 17061arm_frag_align_code (int n, int max) 17062{ 17063 char * p; 17064 17065 /* We assume that there will never be a requirement 17066 to support alignments greater than 32 bytes. */ 17067 if (max > MAX_MEM_FOR_RS_ALIGN_CODE) 17068 as_fatal (_("alignments greater than 32 bytes not supported in .text sections.")); 17069 17070 p = frag_var (rs_align_code, 17071 MAX_MEM_FOR_RS_ALIGN_CODE, 17072 1, 17073 (relax_substateT) max, 17074 (symbolS *) NULL, 17075 (offsetT) n, 17076 (char *) NULL); 17077 *p = 0; 17078} 17079 17080/* Perform target specific initialisation of a frag. */ 17081 17082void 17083arm_init_frag (fragS * fragP) 17084{ 17085 /* Record whether this frag is in an ARM or a THUMB area. */ 17086 fragP->tc_frag_data = thumb_mode; 17087} 17088 17089#ifdef OBJ_ELF 17090/* When we change sections we need to issue a new mapping symbol. */ 17091 17092void 17093arm_elf_change_section (void) 17094{ 17095 flagword flags; 17096 segment_info_type *seginfo; 17097 17098 /* Link an unlinked unwind index table section to the .text section. */ 17099 if (elf_section_type (now_seg) == SHT_ARM_EXIDX 17100 && elf_linked_to_section (now_seg) == NULL) 17101 elf_linked_to_section (now_seg) = text_section; 17102 17103 if (!SEG_NORMAL (now_seg)) 17104 return; 17105 17106 flags = bfd_get_section_flags (stdoutput, now_seg); 17107 17108 /* We can ignore sections that only contain debug info. */ 17109 if ((flags & SEC_ALLOC) == 0) 17110 return; 17111 17112 seginfo = seg_info (now_seg); 17113 mapstate = seginfo->tc_segment_info_data.mapstate; 17114 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency; 17115} 17116 17117int 17118arm_elf_section_type (const char * str, size_t len) 17119{ 17120 if (len == 5 && strncmp (str, "exidx", 5) == 0) 17121 return SHT_ARM_EXIDX; 17122 17123 return -1; 17124} 17125 17126/* Code to deal with unwinding tables. */ 17127 17128static void add_unwind_adjustsp (offsetT); 17129 17130/* Cenerate and deferred unwind frame offset. */ 17131 17132static void 17133flush_pending_unwind (void) 17134{ 17135 offsetT offset; 17136 17137 offset = unwind.pending_offset; 17138 unwind.pending_offset = 0; 17139 if (offset != 0) 17140 add_unwind_adjustsp (offset); 17141} 17142 17143/* Add an opcode to this list for this function. Two-byte opcodes should 17144 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse 17145 order. */ 17146 17147static void 17148add_unwind_opcode (valueT op, int length) 17149{ 17150 /* Add any deferred stack adjustment. */ 17151 if (unwind.pending_offset) 17152 flush_pending_unwind (); 17153 17154 unwind.sp_restored = 0; 17155 17156 if (unwind.opcode_count + length > unwind.opcode_alloc) 17157 { 17158 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; 17159 if (unwind.opcodes) 17160 unwind.opcodes = xrealloc (unwind.opcodes, 17161 unwind.opcode_alloc); 17162 else 17163 unwind.opcodes = xmalloc (unwind.opcode_alloc); 17164 } 17165 while (length > 0) 17166 { 17167 length--; 17168 unwind.opcodes[unwind.opcode_count] = op & 0xff; 17169 op >>= 8; 17170 unwind.opcode_count++; 17171 } 17172} 17173 17174/* Add unwind opcodes to adjust the stack pointer. */ 17175 17176static void 17177add_unwind_adjustsp (offsetT offset) 17178{ 17179 valueT op; 17180 17181 if (offset > 0x200) 17182 { 17183 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ 17184 char bytes[5]; 17185 int n; 17186 valueT o; 17187 17188 /* Long form: 0xb2, uleb128. */ 17189 /* This might not fit in a word so add the individual bytes, 17190 remembering the list is built in reverse order. */ 17191 o = (valueT) ((offset - 0x204) >> 2); 17192 if (o == 0) 17193 add_unwind_opcode (0, 1); 17194 17195 /* Calculate the uleb128 encoding of the offset. */ 17196 n = 0; 17197 while (o) 17198 { 17199 bytes[n] = o & 0x7f; 17200 o >>= 7; 17201 if (o) 17202 bytes[n] |= 0x80; 17203 n++; 17204 } 17205 /* Add the insn. */ 17206 for (; n; n--) 17207 add_unwind_opcode (bytes[n - 1], 1); 17208 add_unwind_opcode (0xb2, 1); 17209 } 17210 else if (offset > 0x100) 17211 { 17212 /* Two short opcodes. */ 17213 add_unwind_opcode (0x3f, 1); 17214 op = (offset - 0x104) >> 2; 17215 add_unwind_opcode (op, 1); 17216 } 17217 else if (offset > 0) 17218 { 17219 /* Short opcode. */ 17220 op = (offset - 4) >> 2; 17221 add_unwind_opcode (op, 1); 17222 } 17223 else if (offset < 0) 17224 { 17225 offset = -offset; 17226 while (offset > 0x100) 17227 { 17228 add_unwind_opcode (0x7f, 1); 17229 offset -= 0x100; 17230 } 17231 op = ((offset - 4) >> 2) | 0x40; 17232 add_unwind_opcode (op, 1); 17233 } 17234} 17235 17236/* Finish the list of unwind opcodes for this function. */ 17237static void 17238finish_unwind_opcodes (void) 17239{ 17240 valueT op; 17241 17242 if (unwind.fp_used) 17243 { 17244 /* Adjust sp as necessary. */ 17245 unwind.pending_offset += unwind.fp_offset - unwind.frame_size; 17246 flush_pending_unwind (); 17247 17248 /* After restoring sp from the frame pointer. */ 17249 op = 0x90 | unwind.fp_reg; 17250 add_unwind_opcode (op, 1); 17251 } 17252 else 17253 flush_pending_unwind (); 17254} 17255 17256 17257/* Start an exception table entry. If idx is nonzero this is an index table 17258 entry. */ 17259 17260static void 17261start_unwind_section (const segT text_seg, int idx) 17262{ 17263 const char * text_name; 17264 const char * prefix; 17265 const char * prefix_once; 17266 const char * group_name; 17267 size_t prefix_len; 17268 size_t text_len; 17269 char * sec_name; 17270 size_t sec_name_len; 17271 int type; 17272 int flags; 17273 int linkonce; 17274 17275 if (idx) 17276 { 17277 prefix = ELF_STRING_ARM_unwind; 17278 prefix_once = ELF_STRING_ARM_unwind_once; 17279 type = SHT_ARM_EXIDX; 17280 } 17281 else 17282 { 17283 prefix = ELF_STRING_ARM_unwind_info; 17284 prefix_once = ELF_STRING_ARM_unwind_info_once; 17285 type = SHT_PROGBITS; 17286 } 17287 17288 text_name = segment_name (text_seg); 17289 if (streq (text_name, ".text")) 17290 text_name = ""; 17291 17292 if (strncmp (text_name, ".gnu.linkonce.t.", 17293 strlen (".gnu.linkonce.t.")) == 0) 17294 { 17295 prefix = prefix_once; 17296 text_name += strlen (".gnu.linkonce.t."); 17297 } 17298 17299 prefix_len = strlen (prefix); 17300 text_len = strlen (text_name); 17301 sec_name_len = prefix_len + text_len; 17302 sec_name = xmalloc (sec_name_len + 1); 17303 memcpy (sec_name, prefix, prefix_len); 17304 memcpy (sec_name + prefix_len, text_name, text_len); 17305 sec_name[prefix_len + text_len] = '\0'; 17306 17307 flags = SHF_ALLOC; 17308 linkonce = 0; 17309 group_name = 0; 17310 17311 /* Handle COMDAT group. */ 17312 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) 17313 { 17314 group_name = elf_group_name (text_seg); 17315 if (group_name == NULL) 17316 { 17317 as_bad ("Group section `%s' has no group signature", 17318 segment_name (text_seg)); 17319 ignore_rest_of_line (); 17320 return; 17321 } 17322 flags |= SHF_GROUP; 17323 linkonce = 1; 17324 } 17325 17326 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); 17327 17328 /* Set the setion link for index tables. */ 17329 if (idx) 17330 elf_linked_to_section (now_seg) = text_seg; 17331} 17332 17333 17334/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional 17335 personality routine data. Returns zero, or the index table value for 17336 and inline entry. */ 17337 17338static valueT 17339create_unwind_entry (int have_data) 17340{ 17341 int size; 17342 addressT where; 17343 char *ptr; 17344 /* The current word of data. */ 17345 valueT data; 17346 /* The number of bytes left in this word. */ 17347 int n; 17348 17349 finish_unwind_opcodes (); 17350 17351 /* Remember the current text section. */ 17352 unwind.saved_seg = now_seg; 17353 unwind.saved_subseg = now_subseg; 17354 17355 start_unwind_section (now_seg, 0); 17356 17357 if (unwind.personality_routine == NULL) 17358 { 17359 if (unwind.personality_index == -2) 17360 { 17361 if (have_data) 17362 as_bad (_("handerdata in cantunwind frame")); 17363 return 1; /* EXIDX_CANTUNWIND. */ 17364 } 17365 17366 /* Use a default personality routine if none is specified. */ 17367 if (unwind.personality_index == -1) 17368 { 17369 if (unwind.opcode_count > 3) 17370 unwind.personality_index = 1; 17371 else 17372 unwind.personality_index = 0; 17373 } 17374 17375 /* Space for the personality routine entry. */ 17376 if (unwind.personality_index == 0) 17377 { 17378 if (unwind.opcode_count > 3) 17379 as_bad (_("too many unwind opcodes for personality routine 0")); 17380 17381 if (!have_data) 17382 { 17383 /* All the data is inline in the index table. */ 17384 data = 0x80; 17385 n = 3; 17386 while (unwind.opcode_count > 0) 17387 { 17388 unwind.opcode_count--; 17389 data = (data << 8) | unwind.opcodes[unwind.opcode_count]; 17390 n--; 17391 } 17392 17393 /* Pad with "finish" opcodes. */ 17394 while (n--) 17395 data = (data << 8) | 0xb0; 17396 17397 return data; 17398 } 17399 size = 0; 17400 } 17401 else 17402 /* We get two opcodes "free" in the first word. */ 17403 size = unwind.opcode_count - 2; 17404 } 17405 else 17406 /* An extra byte is required for the opcode count. */ 17407 size = unwind.opcode_count + 1; 17408 17409 size = (size + 3) >> 2; 17410 if (size > 0xff) 17411 as_bad (_("too many unwind opcodes")); 17412 17413 frag_align (2, 0, 0); 17414 record_alignment (now_seg, 2); 17415 unwind.table_entry = expr_build_dot (); 17416 17417 /* Allocate the table entry. */ 17418 ptr = frag_more ((size << 2) + 4); 17419 memset(ptr, 0, (size << 2) + 4); 17420 where = frag_now_fix () - ((size << 2) + 4); 17421 17422 switch (unwind.personality_index) 17423 { 17424 case -1: 17425 /* ??? Should this be a PLT generating relocation? */ 17426 /* Custom personality routine. */ 17427 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, 17428 BFD_RELOC_ARM_PREL31); 17429 17430 where += 4; 17431 ptr += 4; 17432 17433 /* Set the first byte to the number of additional words. */ 17434 data = size - 1; 17435 n = 3; 17436 break; 17437 17438 /* ABI defined personality routines. */ 17439 case 0: 17440 /* Three opcodes bytes are packed into the first word. */ 17441 data = 0x80; 17442 n = 3; 17443 break; 17444 17445 case 1: 17446 case 2: 17447 /* The size and first two opcode bytes go in the first word. */ 17448 data = ((0x80 + unwind.personality_index) << 8) | size; 17449 n = 2; 17450 break; 17451 17452 default: 17453 /* Should never happen. */ 17454 abort (); 17455 } 17456 17457 /* Pack the opcodes into words (MSB first), reversing the list at the same 17458 time. */ 17459 while (unwind.opcode_count > 0) 17460 { 17461 if (n == 0) 17462 { 17463 md_number_to_chars (ptr, data, 4); 17464 ptr += 4; 17465 n = 4; 17466 data = 0; 17467 } 17468 unwind.opcode_count--; 17469 n--; 17470 data = (data << 8) | unwind.opcodes[unwind.opcode_count]; 17471 } 17472 17473 /* Finish off the last word. */ 17474 if (n < 4) 17475 { 17476 /* Pad with "finish" opcodes. */ 17477 while (n--) 17478 data = (data << 8) | 0xb0; 17479 17480 md_number_to_chars (ptr, data, 4); 17481 } 17482 17483 if (!have_data) 17484 { 17485 /* Add an empty descriptor if there is no user-specified data. */ 17486 ptr = frag_more (4); 17487 md_number_to_chars (ptr, 0, 4); 17488 } 17489 17490 return 0; 17491} 17492 17493 17494/* Initialize the DWARF-2 unwind information for this procedure. */ 17495 17496void 17497tc_arm_frame_initial_instructions (void) 17498{ 17499 cfi_add_CFA_def_cfa (REG_SP, 0); 17500} 17501#endif /* OBJ_ELF */ 17502 17503/* Convert REGNAME to a DWARF-2 register number. */ 17504 17505int 17506tc_arm_regname_to_dw2regnum (char *regname) 17507{ 17508 int reg = arm_reg_parse (®name, REG_TYPE_RN); 17509 17510 if (reg == FAIL) 17511 return -1; 17512 17513 return reg; 17514} 17515 17516#ifdef TE_PE 17517void 17518tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) 17519{ 17520 expressionS expr; 17521 17522 expr.X_op = O_secrel; 17523 expr.X_add_symbol = symbol; 17524 expr.X_add_number = 0; 17525 emit_expr (&expr, size); 17526} 17527#endif 17528 17529/* MD interface: Symbol and relocation handling. */ 17530 17531/* Return the address within the segment that a PC-relative fixup is 17532 relative to. For ARM, PC-relative fixups applied to instructions 17533 are generally relative to the location of the fixup plus 8 bytes. 17534 Thumb branches are offset by 4, and Thumb loads relative to PC 17535 require special handling. */ 17536 17537long 17538md_pcrel_from_section (fixS * fixP, segT seg) 17539{ 17540 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; 17541 17542 /* If this is pc-relative and we are going to emit a relocation 17543 then we just want to put out any pipeline compensation that the linker 17544 will need. Otherwise we want to use the calculated base. 17545 For WinCE we skip the bias for externals as well, since this 17546 is how the MS ARM-CE assembler behaves and we want to be compatible. */ 17547 if (fixP->fx_pcrel 17548 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) 17549 || (arm_force_relocation (fixP) 17550#ifdef TE_WINCE 17551 && !S_IS_EXTERNAL (fixP->fx_addsy) 17552#endif 17553 ))) 17554 base = 0; 17555 17556 switch (fixP->fx_r_type) 17557 { 17558 /* PC relative addressing on the Thumb is slightly odd as the 17559 bottom two bits of the PC are forced to zero for the 17560 calculation. This happens *after* application of the 17561 pipeline offset. However, Thumb adrl already adjusts for 17562 this, so we need not do it again. */ 17563 case BFD_RELOC_ARM_THUMB_ADD: 17564 return base & ~3; 17565 17566 case BFD_RELOC_ARM_THUMB_OFFSET: 17567 case BFD_RELOC_ARM_T32_OFFSET_IMM: 17568 case BFD_RELOC_ARM_T32_ADD_PC12: 17569 case BFD_RELOC_ARM_T32_CP_OFF_IMM: 17570 return (base + 4) & ~3; 17571 17572 /* Thumb branches are simply offset by +4. */ 17573 case BFD_RELOC_THUMB_PCREL_BRANCH7: 17574 case BFD_RELOC_THUMB_PCREL_BRANCH9: 17575 case BFD_RELOC_THUMB_PCREL_BRANCH12: 17576 case BFD_RELOC_THUMB_PCREL_BRANCH20: 17577 case BFD_RELOC_THUMB_PCREL_BRANCH23: 17578 case BFD_RELOC_THUMB_PCREL_BRANCH25: 17579 case BFD_RELOC_THUMB_PCREL_BLX: 17580 return base + 4; 17581 17582 /* ARM mode branches are offset by +8. However, the Windows CE 17583 loader expects the relocation not to take this into account. */ 17584 case BFD_RELOC_ARM_PCREL_BRANCH: 17585 case BFD_RELOC_ARM_PCREL_CALL: 17586 case BFD_RELOC_ARM_PCREL_JUMP: 17587 case BFD_RELOC_ARM_PCREL_BLX: 17588 case BFD_RELOC_ARM_PLT32: 17589#ifdef TE_WINCE 17590 /* When handling fixups immediately, because we have already 17591 discovered the value of a symbol, or the address of the frag involved 17592 we must account for the offset by +8, as the OS loader will never see the reloc. 17593 see fixup_segment() in write.c 17594 The S_IS_EXTERNAL test handles the case of global symbols. 17595 Those need the calculated base, not just the pipe compensation the linker will need. */ 17596 if (fixP->fx_pcrel 17597 && fixP->fx_addsy != NULL 17598 && (S_GET_SEGMENT (fixP->fx_addsy) == seg) 17599 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) 17600 return base + 8; 17601 return base; 17602#else 17603 return base + 8; 17604#endif 17605 17606 /* ARM mode loads relative to PC are also offset by +8. Unlike 17607 branches, the Windows CE loader *does* expect the relocation 17608 to take this into account. */ 17609 case BFD_RELOC_ARM_OFFSET_IMM: 17610 case BFD_RELOC_ARM_OFFSET_IMM8: 17611 case BFD_RELOC_ARM_HWLITERAL: 17612 case BFD_RELOC_ARM_LITERAL: 17613 case BFD_RELOC_ARM_CP_OFF_IMM: 17614 return base + 8; 17615 17616 17617 /* Other PC-relative relocations are un-offset. */ 17618 default: 17619 return base; 17620 } 17621} 17622 17623/* Under ELF we need to default _GLOBAL_OFFSET_TABLE. 17624 Otherwise we have no need to default values of symbols. */ 17625 17626symbolS * 17627md_undefined_symbol (char * name ATTRIBUTE_UNUSED) 17628{ 17629#ifdef OBJ_ELF 17630 if (name[0] == '_' && name[1] == 'G' 17631 && streq (name, GLOBAL_OFFSET_TABLE_NAME)) 17632 { 17633 if (!GOT_symbol) 17634 { 17635 if (symbol_find (name)) 17636 as_bad ("GOT already in the symbol table"); 17637 17638 GOT_symbol = symbol_new (name, undefined_section, 17639 (valueT) 0, & zero_address_frag); 17640 } 17641 17642 return GOT_symbol; 17643 } 17644#endif 17645 17646 return 0; 17647} 17648 17649/* Subroutine of md_apply_fix. Check to see if an immediate can be 17650 computed as two separate immediate values, added together. We 17651 already know that this value cannot be computed by just one ARM 17652 instruction. */ 17653 17654static unsigned int 17655validate_immediate_twopart (unsigned int val, 17656 unsigned int * highpart) 17657{ 17658 unsigned int a; 17659 unsigned int i; 17660 17661 for (i = 0; i < 32; i += 2) 17662 if (((a = rotate_left (val, i)) & 0xff) != 0) 17663 { 17664 if (a & 0xff00) 17665 { 17666 if (a & ~ 0xffff) 17667 continue; 17668 * highpart = (a >> 8) | ((i + 24) << 7); 17669 } 17670 else if (a & 0xff0000) 17671 { 17672 if (a & 0xff000000) 17673 continue; 17674 * highpart = (a >> 16) | ((i + 16) << 7); 17675 } 17676 else 17677 { 17678 assert (a & 0xff000000); 17679 * highpart = (a >> 24) | ((i + 8) << 7); 17680 } 17681 17682 return (a & 0xff) | (i << 7); 17683 } 17684 17685 return FAIL; 17686} 17687 17688static int 17689validate_offset_imm (unsigned int val, int hwse) 17690{ 17691 if ((hwse && val > 255) || val > 4095) 17692 return FAIL; 17693 return val; 17694} 17695 17696/* Subroutine of md_apply_fix. Do those data_ops which can take a 17697 negative immediate constant by altering the instruction. A bit of 17698 a hack really. 17699 MOV <-> MVN 17700 AND <-> BIC 17701 ADC <-> SBC 17702 by inverting the second operand, and 17703 ADD <-> SUB 17704 CMP <-> CMN 17705 by negating the second operand. */ 17706 17707static int 17708negate_data_op (unsigned long * instruction, 17709 unsigned long value) 17710{ 17711 int op, new_inst; 17712 unsigned long negated, inverted; 17713 17714 negated = encode_arm_immediate (-value); 17715 inverted = encode_arm_immediate (~value); 17716 17717 op = (*instruction >> DATA_OP_SHIFT) & 0xf; 17718 switch (op) 17719 { 17720 /* First negates. */ 17721 case OPCODE_SUB: /* ADD <-> SUB */ 17722 new_inst = OPCODE_ADD; 17723 value = negated; 17724 break; 17725 17726 case OPCODE_ADD: 17727 new_inst = OPCODE_SUB; 17728 value = negated; 17729 break; 17730 17731 case OPCODE_CMP: /* CMP <-> CMN */ 17732 new_inst = OPCODE_CMN; 17733 value = negated; 17734 break; 17735 17736 case OPCODE_CMN: 17737 new_inst = OPCODE_CMP; 17738 value = negated; 17739 break; 17740 17741 /* Now Inverted ops. */ 17742 case OPCODE_MOV: /* MOV <-> MVN */ 17743 new_inst = OPCODE_MVN; 17744 value = inverted; 17745 break; 17746 17747 case OPCODE_MVN: 17748 new_inst = OPCODE_MOV; 17749 value = inverted; 17750 break; 17751 17752 case OPCODE_AND: /* AND <-> BIC */ 17753 new_inst = OPCODE_BIC; 17754 value = inverted; 17755 break; 17756 17757 case OPCODE_BIC: 17758 new_inst = OPCODE_AND; 17759 value = inverted; 17760 break; 17761 17762 case OPCODE_ADC: /* ADC <-> SBC */ 17763 new_inst = OPCODE_SBC; 17764 value = inverted; 17765 break; 17766 17767 case OPCODE_SBC: 17768 new_inst = OPCODE_ADC; 17769 value = inverted; 17770 break; 17771 17772 /* We cannot do anything. */ 17773 default: 17774 return FAIL; 17775 } 17776 17777 if (value == (unsigned) FAIL) 17778 return FAIL; 17779 17780 *instruction &= OPCODE_MASK; 17781 *instruction |= new_inst << DATA_OP_SHIFT; 17782 return value; 17783} 17784 17785/* Like negate_data_op, but for Thumb-2. */ 17786 17787static unsigned int 17788thumb32_negate_data_op (offsetT *instruction, unsigned int value) 17789{ 17790 int op, new_inst; 17791 int rd; 17792 unsigned int negated, inverted; 17793 17794 negated = encode_thumb32_immediate (-value); 17795 inverted = encode_thumb32_immediate (~value); 17796 17797 rd = (*instruction >> 8) & 0xf; 17798 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; 17799 switch (op) 17800 { 17801 /* ADD <-> SUB. Includes CMP <-> CMN. */ 17802 case T2_OPCODE_SUB: 17803 new_inst = T2_OPCODE_ADD; 17804 value = negated; 17805 break; 17806 17807 case T2_OPCODE_ADD: 17808 new_inst = T2_OPCODE_SUB; 17809 value = negated; 17810 break; 17811 17812 /* ORR <-> ORN. Includes MOV <-> MVN. */ 17813 case T2_OPCODE_ORR: 17814 new_inst = T2_OPCODE_ORN; 17815 value = inverted; 17816 break; 17817 17818 case T2_OPCODE_ORN: 17819 new_inst = T2_OPCODE_ORR; 17820 value = inverted; 17821 break; 17822 17823 /* AND <-> BIC. TST has no inverted equivalent. */ 17824 case T2_OPCODE_AND: 17825 new_inst = T2_OPCODE_BIC; 17826 if (rd == 15) 17827 value = FAIL; 17828 else 17829 value = inverted; 17830 break; 17831 17832 case T2_OPCODE_BIC: 17833 new_inst = T2_OPCODE_AND; 17834 value = inverted; 17835 break; 17836 17837 /* ADC <-> SBC */ 17838 case T2_OPCODE_ADC: 17839 new_inst = T2_OPCODE_SBC; 17840 value = inverted; 17841 break; 17842 17843 case T2_OPCODE_SBC: 17844 new_inst = T2_OPCODE_ADC; 17845 value = inverted; 17846 break; 17847 17848 /* We cannot do anything. */ 17849 default: 17850 return FAIL; 17851 } 17852 17853 if (value == (unsigned int)FAIL) 17854 return FAIL; 17855 17856 *instruction &= T2_OPCODE_MASK; 17857 *instruction |= new_inst << T2_DATA_OP_SHIFT; 17858 return value; 17859} 17860 17861/* Read a 32-bit thumb instruction from buf. */ 17862static unsigned long 17863get_thumb32_insn (char * buf) 17864{ 17865 unsigned long insn; 17866 insn = md_chars_to_number (buf, THUMB_SIZE) << 16; 17867 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 17868 17869 return insn; 17870} 17871 17872 17873/* We usually want to set the low bit on the address of thumb function 17874 symbols. In particular .word foo - . should have the low bit set. 17875 Generic code tries to fold the difference of two symbols to 17876 a constant. Prevent this and force a relocation when the first symbols 17877 is a thumb function. */ 17878int 17879arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) 17880{ 17881 if (op == O_subtract 17882 && l->X_op == O_symbol 17883 && r->X_op == O_symbol 17884 && THUMB_IS_FUNC (l->X_add_symbol)) 17885 { 17886 l->X_op = O_subtract; 17887 l->X_op_symbol = r->X_add_symbol; 17888 l->X_add_number -= r->X_add_number; 17889 return 1; 17890 } 17891 /* Process as normal. */ 17892 return 0; 17893} 17894 17895void 17896md_apply_fix (fixS * fixP, 17897 valueT * valP, 17898 segT seg) 17899{ 17900 offsetT value = * valP; 17901 offsetT newval; 17902 unsigned int newimm; 17903 unsigned long temp; 17904 int sign; 17905 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; 17906 17907 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); 17908 17909 /* Note whether this will delete the relocation. */ 17910 17911 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 17912 fixP->fx_done = 1; 17913 17914 /* On a 64-bit host, silently truncate 'value' to 32 bits for 17915 consistency with the behavior on 32-bit hosts. Remember value 17916 for emit_reloc. */ 17917 value &= 0xffffffff; 17918 value ^= 0x80000000; 17919 value -= 0x80000000; 17920 17921 *valP = value; 17922 fixP->fx_addnumber = value; 17923 17924 /* Same treatment for fixP->fx_offset. */ 17925 fixP->fx_offset &= 0xffffffff; 17926 fixP->fx_offset ^= 0x80000000; 17927 fixP->fx_offset -= 0x80000000; 17928 17929 switch (fixP->fx_r_type) 17930 { 17931 case BFD_RELOC_NONE: 17932 /* This will need to go in the object file. */ 17933 fixP->fx_done = 0; 17934 break; 17935 17936 case BFD_RELOC_ARM_IMMEDIATE: 17937 /* We claim that this fixup has been processed here, 17938 even if in fact we generate an error because we do 17939 not have a reloc for it, so tc_gen_reloc will reject it. */ 17940 fixP->fx_done = 1; 17941 17942 if (fixP->fx_addsy 17943 && ! S_IS_DEFINED (fixP->fx_addsy)) 17944 { 17945 as_bad_where (fixP->fx_file, fixP->fx_line, 17946 _("undefined symbol %s used as an immediate value"), 17947 S_GET_NAME (fixP->fx_addsy)); 17948 break; 17949 } 17950 17951 newimm = encode_arm_immediate (value); 17952 temp = md_chars_to_number (buf, INSN_SIZE); 17953 17954 /* If the instruction will fail, see if we can fix things up by 17955 changing the opcode. */ 17956 if (newimm == (unsigned int) FAIL 17957 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) 17958 { 17959 as_bad_where (fixP->fx_file, fixP->fx_line, 17960 _("invalid constant (%lx) after fixup"), 17961 (unsigned long) value); 17962 break; 17963 } 17964 17965 newimm |= (temp & 0xfffff000); 17966 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); 17967 break; 17968 17969 case BFD_RELOC_ARM_ADRL_IMMEDIATE: 17970 { 17971 unsigned int highpart = 0; 17972 unsigned int newinsn = 0xe1a00000; /* nop. */ 17973 17974 newimm = encode_arm_immediate (value); 17975 temp = md_chars_to_number (buf, INSN_SIZE); 17976 17977 /* If the instruction will fail, see if we can fix things up by 17978 changing the opcode. */ 17979 if (newimm == (unsigned int) FAIL 17980 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) 17981 { 17982 /* No ? OK - try using two ADD instructions to generate 17983 the value. */ 17984 newimm = validate_immediate_twopart (value, & highpart); 17985 17986 /* Yes - then make sure that the second instruction is 17987 also an add. */ 17988 if (newimm != (unsigned int) FAIL) 17989 newinsn = temp; 17990 /* Still No ? Try using a negated value. */ 17991 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) 17992 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; 17993 /* Otherwise - give up. */ 17994 else 17995 { 17996 as_bad_where (fixP->fx_file, fixP->fx_line, 17997 _("unable to compute ADRL instructions for PC offset of 0x%lx"), 17998 (long) value); 17999 break; 18000 } 18001 18002 /* Replace the first operand in the 2nd instruction (which 18003 is the PC) with the destination register. We have 18004 already added in the PC in the first instruction and we 18005 do not want to do it again. */ 18006 newinsn &= ~ 0xf0000; 18007 newinsn |= ((newinsn & 0x0f000) << 4); 18008 } 18009 18010 newimm |= (temp & 0xfffff000); 18011 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); 18012 18013 highpart |= (newinsn & 0xfffff000); 18014 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); 18015 } 18016 break; 18017 18018 case BFD_RELOC_ARM_OFFSET_IMM: 18019 if (!fixP->fx_done && seg->use_rela_p) 18020 value = 0; 18021 18022 case BFD_RELOC_ARM_LITERAL: 18023 sign = value >= 0; 18024 18025 if (value < 0) 18026 value = - value; 18027 18028 if (validate_offset_imm (value, 0) == FAIL) 18029 { 18030 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) 18031 as_bad_where (fixP->fx_file, fixP->fx_line, 18032 _("invalid literal constant: pool needs to be closer")); 18033 else 18034 as_bad_where (fixP->fx_file, fixP->fx_line, 18035 _("bad immediate value for offset (%ld)"), 18036 (long) value); 18037 break; 18038 } 18039 18040 newval = md_chars_to_number (buf, INSN_SIZE); 18041 newval &= 0xff7ff000; 18042 newval |= value | (sign ? INDEX_UP : 0); 18043 md_number_to_chars (buf, newval, INSN_SIZE); 18044 break; 18045 18046 case BFD_RELOC_ARM_OFFSET_IMM8: 18047 case BFD_RELOC_ARM_HWLITERAL: 18048 sign = value >= 0; 18049 18050 if (value < 0) 18051 value = - value; 18052 18053 if (validate_offset_imm (value, 1) == FAIL) 18054 { 18055 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) 18056 as_bad_where (fixP->fx_file, fixP->fx_line, 18057 _("invalid literal constant: pool needs to be closer")); 18058 else 18059 as_bad (_("bad immediate value for 8-bit offset (%ld)"), 18060 (long) value); 18061 break; 18062 } 18063 18064 newval = md_chars_to_number (buf, INSN_SIZE); 18065 newval &= 0xff7ff0f0; 18066 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); 18067 md_number_to_chars (buf, newval, INSN_SIZE); 18068 break; 18069 18070 case BFD_RELOC_ARM_T32_OFFSET_U8: 18071 if (value < 0 || value > 1020 || value % 4 != 0) 18072 as_bad_where (fixP->fx_file, fixP->fx_line, 18073 _("bad immediate value for offset (%ld)"), (long) value); 18074 value /= 4; 18075 18076 newval = md_chars_to_number (buf+2, THUMB_SIZE); 18077 newval |= value; 18078 md_number_to_chars (buf+2, newval, THUMB_SIZE); 18079 break; 18080 18081 case BFD_RELOC_ARM_T32_OFFSET_IMM: 18082 /* This is a complicated relocation used for all varieties of Thumb32 18083 load/store instruction with immediate offset: 18084 18085 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, 18086 *4, optional writeback(W) 18087 (doubleword load/store) 18088 18089 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel 18090 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit 18091 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) 18092 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit 18093 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit 18094 18095 Uppercase letters indicate bits that are already encoded at 18096 this point. Lowercase letters are our problem. For the 18097 second block of instructions, the secondary opcode nybble 18098 (bits 8..11) is present, and bit 23 is zero, even if this is 18099 a PC-relative operation. */ 18100 newval = md_chars_to_number (buf, THUMB_SIZE); 18101 newval <<= 16; 18102 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); 18103 18104 if ((newval & 0xf0000000) == 0xe0000000) 18105 { 18106 /* Doubleword load/store: 8-bit offset, scaled by 4. */ 18107 if (value >= 0) 18108 newval |= (1 << 23); 18109 else 18110 value = -value; 18111 if (value % 4 != 0) 18112 { 18113 as_bad_where (fixP->fx_file, fixP->fx_line, 18114 _("offset not a multiple of 4")); 18115 break; 18116 } 18117 value /= 4; 18118 if (value > 0xff) 18119 { 18120 as_bad_where (fixP->fx_file, fixP->fx_line, 18121 _("offset out of range")); 18122 break; 18123 } 18124 newval &= ~0xff; 18125 } 18126 else if ((newval & 0x000f0000) == 0x000f0000) 18127 { 18128 /* PC-relative, 12-bit offset. */ 18129 if (value >= 0) 18130 newval |= (1 << 23); 18131 else 18132 value = -value; 18133 if (value > 0xfff) 18134 { 18135 as_bad_where (fixP->fx_file, fixP->fx_line, 18136 _("offset out of range")); 18137 break; 18138 } 18139 newval &= ~0xfff; 18140 } 18141 else if ((newval & 0x00000100) == 0x00000100) 18142 { 18143 /* Writeback: 8-bit, +/- offset. */ 18144 if (value >= 0) 18145 newval |= (1 << 9); 18146 else 18147 value = -value; 18148 if (value > 0xff) 18149 { 18150 as_bad_where (fixP->fx_file, fixP->fx_line, 18151 _("offset out of range")); 18152 break; 18153 } 18154 newval &= ~0xff; 18155 } 18156 else if ((newval & 0x00000f00) == 0x00000e00) 18157 { 18158 /* T-instruction: positive 8-bit offset. */ 18159 if (value < 0 || value > 0xff) 18160 { 18161 as_bad_where (fixP->fx_file, fixP->fx_line, 18162 _("offset out of range")); 18163 break; 18164 } 18165 newval &= ~0xff; 18166 newval |= value; 18167 } 18168 else 18169 { 18170 /* Positive 12-bit or negative 8-bit offset. */ 18171 int limit; 18172 if (value >= 0) 18173 { 18174 newval |= (1 << 23); 18175 limit = 0xfff; 18176 } 18177 else 18178 { 18179 value = -value; 18180 limit = 0xff; 18181 } 18182 if (value > limit) 18183 { 18184 as_bad_where (fixP->fx_file, fixP->fx_line, 18185 _("offset out of range")); 18186 break; 18187 } 18188 newval &= ~limit; 18189 } 18190 18191 newval |= value; 18192 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); 18193 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); 18194 break; 18195 18196 case BFD_RELOC_ARM_SHIFT_IMM: 18197 newval = md_chars_to_number (buf, INSN_SIZE); 18198 if (((unsigned long) value) > 32 18199 || (value == 32 18200 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) 18201 { 18202 as_bad_where (fixP->fx_file, fixP->fx_line, 18203 _("shift expression is too large")); 18204 break; 18205 } 18206 18207 if (value == 0) 18208 /* Shifts of zero must be done as lsl. */ 18209 newval &= ~0x60; 18210 else if (value == 32) 18211 value = 0; 18212 newval &= 0xfffff07f; 18213 newval |= (value & 0x1f) << 7; 18214 md_number_to_chars (buf, newval, INSN_SIZE); 18215 break; 18216 18217 case BFD_RELOC_ARM_T32_IMMEDIATE: 18218 case BFD_RELOC_ARM_T32_ADD_IMM: 18219 case BFD_RELOC_ARM_T32_IMM12: 18220 case BFD_RELOC_ARM_T32_ADD_PC12: 18221 /* We claim that this fixup has been processed here, 18222 even if in fact we generate an error because we do 18223 not have a reloc for it, so tc_gen_reloc will reject it. */ 18224 fixP->fx_done = 1; 18225 18226 if (fixP->fx_addsy 18227 && ! S_IS_DEFINED (fixP->fx_addsy)) 18228 { 18229 as_bad_where (fixP->fx_file, fixP->fx_line, 18230 _("undefined symbol %s used as an immediate value"), 18231 S_GET_NAME (fixP->fx_addsy)); 18232 break; 18233 } 18234 18235 newval = md_chars_to_number (buf, THUMB_SIZE); 18236 newval <<= 16; 18237 newval |= md_chars_to_number (buf+2, THUMB_SIZE); 18238 18239 newimm = FAIL; 18240 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE 18241 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) 18242 { 18243 newimm = encode_thumb32_immediate (value); 18244 if (newimm == (unsigned int) FAIL) 18245 newimm = thumb32_negate_data_op (&newval, value); 18246 } 18247 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE 18248 && newimm == (unsigned int) FAIL) 18249 { 18250 /* Turn add/sum into addw/subw. */ 18251 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) 18252 newval = (newval & 0xfeffffff) | 0x02000000; 18253 18254 /* 12 bit immediate for addw/subw. */ 18255 if (value < 0) 18256 { 18257 value = -value; 18258 newval ^= 0x00a00000; 18259 } 18260 if (value > 0xfff) 18261 newimm = (unsigned int) FAIL; 18262 else 18263 newimm = value; 18264 } 18265 18266 if (newimm == (unsigned int)FAIL) 18267 { 18268 as_bad_where (fixP->fx_file, fixP->fx_line, 18269 _("invalid constant (%lx) after fixup"), 18270 (unsigned long) value); 18271 break; 18272 } 18273 18274 newval |= (newimm & 0x800) << 15; 18275 newval |= (newimm & 0x700) << 4; 18276 newval |= (newimm & 0x0ff); 18277 18278 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); 18279 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); 18280 break; 18281 18282 case BFD_RELOC_ARM_SMC: 18283 if (((unsigned long) value) > 0xffff) 18284 as_bad_where (fixP->fx_file, fixP->fx_line, 18285 _("invalid smc expression")); 18286 newval = md_chars_to_number (buf, INSN_SIZE); 18287 newval |= (value & 0xf) | ((value & 0xfff0) << 4); 18288 md_number_to_chars (buf, newval, INSN_SIZE); 18289 break; 18290 18291 case BFD_RELOC_ARM_SWI: 18292 if (fixP->tc_fix_data != 0) 18293 { 18294 if (((unsigned long) value) > 0xff) 18295 as_bad_where (fixP->fx_file, fixP->fx_line, 18296 _("invalid swi expression")); 18297 newval = md_chars_to_number (buf, THUMB_SIZE); 18298 newval |= value; 18299 md_number_to_chars (buf, newval, THUMB_SIZE); 18300 } 18301 else 18302 { 18303 if (((unsigned long) value) > 0x00ffffff) 18304 as_bad_where (fixP->fx_file, fixP->fx_line, 18305 _("invalid swi expression")); 18306 newval = md_chars_to_number (buf, INSN_SIZE); 18307 newval |= value; 18308 md_number_to_chars (buf, newval, INSN_SIZE); 18309 } 18310 break; 18311 18312 case BFD_RELOC_ARM_MULTI: 18313 if (((unsigned long) value) > 0xffff) 18314 as_bad_where (fixP->fx_file, fixP->fx_line, 18315 _("invalid expression in load/store multiple")); 18316 newval = value | md_chars_to_number (buf, INSN_SIZE); 18317 md_number_to_chars (buf, newval, INSN_SIZE); 18318 break; 18319 18320#ifdef OBJ_ELF 18321 case BFD_RELOC_ARM_PCREL_CALL: 18322 newval = md_chars_to_number (buf, INSN_SIZE); 18323 if ((newval & 0xf0000000) == 0xf0000000) 18324 temp = 1; 18325 else 18326 temp = 3; 18327 goto arm_branch_common; 18328 18329 case BFD_RELOC_ARM_PCREL_JUMP: 18330 case BFD_RELOC_ARM_PLT32: 18331#endif 18332 case BFD_RELOC_ARM_PCREL_BRANCH: 18333 temp = 3; 18334 goto arm_branch_common; 18335 18336 case BFD_RELOC_ARM_PCREL_BLX: 18337 temp = 1; 18338 arm_branch_common: 18339 /* We are going to store value (shifted right by two) in the 18340 instruction, in a 24 bit, signed field. Bits 26 through 32 either 18341 all clear or all set and bit 0 must be clear. For B/BL bit 1 must 18342 also be be clear. */ 18343 if (value & temp) 18344 as_bad_where (fixP->fx_file, fixP->fx_line, 18345 _("misaligned branch destination")); 18346 if ((value & (offsetT)0xfe000000) != (offsetT)0 18347 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) 18348 as_bad_where (fixP->fx_file, fixP->fx_line, 18349 _("branch out of range")); 18350 18351 if (fixP->fx_done || !seg->use_rela_p) 18352 { 18353 newval = md_chars_to_number (buf, INSN_SIZE); 18354 newval |= (value >> 2) & 0x00ffffff; 18355 /* Set the H bit on BLX instructions. */ 18356 if (temp == 1) 18357 { 18358 if (value & 2) 18359 newval |= 0x01000000; 18360 else 18361 newval &= ~0x01000000; 18362 } 18363 md_number_to_chars (buf, newval, INSN_SIZE); 18364 } 18365 break; 18366 18367 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ 18368 /* CBZ can only branch forward. */ 18369 18370 /* Attempts to use CBZ to branch to the next instruction 18371 (which, strictly speaking, are prohibited) will be turned into 18372 no-ops. 18373 18374 FIXME: It may be better to remove the instruction completely and 18375 perform relaxation. */ 18376 if (value == -2) 18377 { 18378 newval = md_chars_to_number (buf, THUMB_SIZE); 18379 newval = 0xbf00; /* NOP encoding T1 */ 18380 md_number_to_chars (buf, newval, THUMB_SIZE); 18381 } 18382 else 18383 { 18384 if (value & ~0x7e) 18385 as_bad_where (fixP->fx_file, fixP->fx_line, 18386 _("branch out of range")); 18387 18388 if (fixP->fx_done || !seg->use_rela_p) 18389 { 18390 newval = md_chars_to_number (buf, THUMB_SIZE); 18391 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); 18392 md_number_to_chars (buf, newval, THUMB_SIZE); 18393 } 18394 } 18395 break; 18396 18397 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ 18398 if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) 18399 as_bad_where (fixP->fx_file, fixP->fx_line, 18400 _("branch out of range")); 18401 18402 if (fixP->fx_done || !seg->use_rela_p) 18403 { 18404 newval = md_chars_to_number (buf, THUMB_SIZE); 18405 newval |= (value & 0x1ff) >> 1; 18406 md_number_to_chars (buf, newval, THUMB_SIZE); 18407 } 18408 break; 18409 18410 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ 18411 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) 18412 as_bad_where (fixP->fx_file, fixP->fx_line, 18413 _("branch out of range")); 18414 18415 if (fixP->fx_done || !seg->use_rela_p) 18416 { 18417 newval = md_chars_to_number (buf, THUMB_SIZE); 18418 newval |= (value & 0xfff) >> 1; 18419 md_number_to_chars (buf, newval, THUMB_SIZE); 18420 } 18421 break; 18422 18423 case BFD_RELOC_THUMB_PCREL_BRANCH20: 18424 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) 18425 as_bad_where (fixP->fx_file, fixP->fx_line, 18426 _("conditional branch out of range")); 18427 18428 if (fixP->fx_done || !seg->use_rela_p) 18429 { 18430 offsetT newval2; 18431 addressT S, J1, J2, lo, hi; 18432 18433 S = (value & 0x00100000) >> 20; 18434 J2 = (value & 0x00080000) >> 19; 18435 J1 = (value & 0x00040000) >> 18; 18436 hi = (value & 0x0003f000) >> 12; 18437 lo = (value & 0x00000ffe) >> 1; 18438 18439 newval = md_chars_to_number (buf, THUMB_SIZE); 18440 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 18441 newval |= (S << 10) | hi; 18442 newval2 |= (J1 << 13) | (J2 << 11) | lo; 18443 md_number_to_chars (buf, newval, THUMB_SIZE); 18444 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); 18445 } 18446 break; 18447 18448 case BFD_RELOC_THUMB_PCREL_BLX: 18449 case BFD_RELOC_THUMB_PCREL_BRANCH23: 18450 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) 18451 as_bad_where (fixP->fx_file, fixP->fx_line, 18452 _("branch out of range")); 18453 18454 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) 18455 /* For a BLX instruction, make sure that the relocation is rounded up 18456 to a word boundary. This follows the semantics of the instruction 18457 which specifies that bit 1 of the target address will come from bit 18458 1 of the base address. */ 18459 value = (value + 1) & ~ 1; 18460 18461 if (fixP->fx_done || !seg->use_rela_p) 18462 { 18463 offsetT newval2; 18464 18465 newval = md_chars_to_number (buf, THUMB_SIZE); 18466 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 18467 newval |= (value & 0x7fffff) >> 12; 18468 newval2 |= (value & 0xfff) >> 1; 18469 md_number_to_chars (buf, newval, THUMB_SIZE); 18470 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); 18471 } 18472 break; 18473 18474 case BFD_RELOC_THUMB_PCREL_BRANCH25: 18475 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) 18476 as_bad_where (fixP->fx_file, fixP->fx_line, 18477 _("branch out of range")); 18478 18479 if (fixP->fx_done || !seg->use_rela_p) 18480 { 18481 offsetT newval2; 18482 addressT S, I1, I2, lo, hi; 18483 18484 S = (value & 0x01000000) >> 24; 18485 I1 = (value & 0x00800000) >> 23; 18486 I2 = (value & 0x00400000) >> 22; 18487 hi = (value & 0x003ff000) >> 12; 18488 lo = (value & 0x00000ffe) >> 1; 18489 18490 I1 = !(I1 ^ S); 18491 I2 = !(I2 ^ S); 18492 18493 newval = md_chars_to_number (buf, THUMB_SIZE); 18494 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 18495 newval |= (S << 10) | hi; 18496 newval2 |= (I1 << 13) | (I2 << 11) | lo; 18497 md_number_to_chars (buf, newval, THUMB_SIZE); 18498 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); 18499 } 18500 break; 18501 18502 case BFD_RELOC_8: 18503 if (fixP->fx_done || !seg->use_rela_p) 18504 md_number_to_chars (buf, value, 1); 18505 break; 18506 18507 case BFD_RELOC_16: 18508 if (fixP->fx_done || !seg->use_rela_p) 18509 md_number_to_chars (buf, value, 2); 18510 break; 18511 18512#ifdef OBJ_ELF 18513 case BFD_RELOC_ARM_TLS_GD32: 18514 case BFD_RELOC_ARM_TLS_LE32: 18515 case BFD_RELOC_ARM_TLS_IE32: 18516 case BFD_RELOC_ARM_TLS_LDM32: 18517 case BFD_RELOC_ARM_TLS_LDO32: 18518 S_SET_THREAD_LOCAL (fixP->fx_addsy); 18519 /* fall through */ 18520 18521 case BFD_RELOC_ARM_GOT32: 18522 case BFD_RELOC_ARM_GOTOFF: 18523 case BFD_RELOC_ARM_TARGET2: 18524 if (fixP->fx_done || !seg->use_rela_p) 18525 md_number_to_chars (buf, 0, 4); 18526 break; 18527#endif 18528 18529 case BFD_RELOC_RVA: 18530 case BFD_RELOC_32: 18531 case BFD_RELOC_ARM_TARGET1: 18532 case BFD_RELOC_ARM_ROSEGREL32: 18533 case BFD_RELOC_ARM_SBREL32: 18534 case BFD_RELOC_32_PCREL: 18535#ifdef TE_PE 18536 case BFD_RELOC_32_SECREL: 18537#endif 18538 if (fixP->fx_done || !seg->use_rela_p) 18539#ifdef TE_WINCE 18540 /* For WinCE we only do this for pcrel fixups. */ 18541 if (fixP->fx_done || fixP->fx_pcrel) 18542#endif 18543 md_number_to_chars (buf, value, 4); 18544 break; 18545 18546#ifdef OBJ_ELF 18547 case BFD_RELOC_ARM_PREL31: 18548 if (fixP->fx_done || !seg->use_rela_p) 18549 { 18550 newval = md_chars_to_number (buf, 4) & 0x80000000; 18551 if ((value ^ (value >> 1)) & 0x40000000) 18552 { 18553 as_bad_where (fixP->fx_file, fixP->fx_line, 18554 _("rel31 relocation overflow")); 18555 } 18556 newval |= value & 0x7fffffff; 18557 md_number_to_chars (buf, newval, 4); 18558 } 18559 break; 18560#endif 18561 18562 case BFD_RELOC_ARM_CP_OFF_IMM: 18563 case BFD_RELOC_ARM_T32_CP_OFF_IMM: 18564 if (value < -1023 || value > 1023 || (value & 3)) 18565 as_bad_where (fixP->fx_file, fixP->fx_line, 18566 _("co-processor offset out of range")); 18567 cp_off_common: 18568 sign = value >= 0; 18569 if (value < 0) 18570 value = -value; 18571 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM 18572 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) 18573 newval = md_chars_to_number (buf, INSN_SIZE); 18574 else 18575 newval = get_thumb32_insn (buf); 18576 newval &= 0xff7fff00; 18577 newval |= (value >> 2) | (sign ? INDEX_UP : 0); 18578 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM 18579 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) 18580 md_number_to_chars (buf, newval, INSN_SIZE); 18581 else 18582 put_thumb32_insn (buf, newval); 18583 break; 18584 18585 case BFD_RELOC_ARM_CP_OFF_IMM_S2: 18586 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: 18587 if (value < -255 || value > 255) 18588 as_bad_where (fixP->fx_file, fixP->fx_line, 18589 _("co-processor offset out of range")); 18590 value *= 4; 18591 goto cp_off_common; 18592 18593 case BFD_RELOC_ARM_THUMB_OFFSET: 18594 newval = md_chars_to_number (buf, THUMB_SIZE); 18595 /* Exactly what ranges, and where the offset is inserted depends 18596 on the type of instruction, we can establish this from the 18597 top 4 bits. */ 18598 switch (newval >> 12) 18599 { 18600 case 4: /* PC load. */ 18601 /* Thumb PC loads are somewhat odd, bit 1 of the PC is 18602 forced to zero for these loads; md_pcrel_from has already 18603 compensated for this. */ 18604 if (value & 3) 18605 as_bad_where (fixP->fx_file, fixP->fx_line, 18606 _("invalid offset, target not word aligned (0x%08lX)"), 18607 (((unsigned long) fixP->fx_frag->fr_address 18608 + (unsigned long) fixP->fx_where) & ~3) 18609 + (unsigned long) value); 18610 18611 if (value & ~0x3fc) 18612 as_bad_where (fixP->fx_file, fixP->fx_line, 18613 _("invalid offset, value too big (0x%08lX)"), 18614 (long) value); 18615 18616 newval |= value >> 2; 18617 break; 18618 18619 case 9: /* SP load/store. */ 18620 if (value & ~0x3fc) 18621 as_bad_where (fixP->fx_file, fixP->fx_line, 18622 _("invalid offset, value too big (0x%08lX)"), 18623 (long) value); 18624 newval |= value >> 2; 18625 break; 18626 18627 case 6: /* Word load/store. */ 18628 if (value & ~0x7c) 18629 as_bad_where (fixP->fx_file, fixP->fx_line, 18630 _("invalid offset, value too big (0x%08lX)"), 18631 (long) value); 18632 newval |= value << 4; /* 6 - 2. */ 18633 break; 18634 18635 case 7: /* Byte load/store. */ 18636 if (value & ~0x1f) 18637 as_bad_where (fixP->fx_file, fixP->fx_line, 18638 _("invalid offset, value too big (0x%08lX)"), 18639 (long) value); 18640 newval |= value << 6; 18641 break; 18642 18643 case 8: /* Halfword load/store. */ 18644 if (value & ~0x3e) 18645 as_bad_where (fixP->fx_file, fixP->fx_line, 18646 _("invalid offset, value too big (0x%08lX)"), 18647 (long) value); 18648 newval |= value << 5; /* 6 - 1. */ 18649 break; 18650 18651 default: 18652 as_bad_where (fixP->fx_file, fixP->fx_line, 18653 "Unable to process relocation for thumb opcode: %lx", 18654 (unsigned long) newval); 18655 break; 18656 } 18657 md_number_to_chars (buf, newval, THUMB_SIZE); 18658 break; 18659 18660 case BFD_RELOC_ARM_THUMB_ADD: 18661 /* This is a complicated relocation, since we use it for all of 18662 the following immediate relocations: 18663 18664 3bit ADD/SUB 18665 8bit ADD/SUB 18666 9bit ADD/SUB SP word-aligned 18667 10bit ADD PC/SP word-aligned 18668 18669 The type of instruction being processed is encoded in the 18670 instruction field: 18671 18672 0x8000 SUB 18673 0x00F0 Rd 18674 0x000F Rs 18675 */ 18676 newval = md_chars_to_number (buf, THUMB_SIZE); 18677 { 18678 int rd = (newval >> 4) & 0xf; 18679 int rs = newval & 0xf; 18680 int subtract = !!(newval & 0x8000); 18681 18682 /* Check for HI regs, only very restricted cases allowed: 18683 Adjusting SP, and using PC or SP to get an address. */ 18684 if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) 18685 || (rs > 7 && rs != REG_SP && rs != REG_PC)) 18686 as_bad_where (fixP->fx_file, fixP->fx_line, 18687 _("invalid Hi register with immediate")); 18688 18689 /* If value is negative, choose the opposite instruction. */ 18690 if (value < 0) 18691 { 18692 value = -value; 18693 subtract = !subtract; 18694 if (value < 0) 18695 as_bad_where (fixP->fx_file, fixP->fx_line, 18696 _("immediate value out of range")); 18697 } 18698 18699 if (rd == REG_SP) 18700 { 18701 if (value & ~0x1fc) 18702 as_bad_where (fixP->fx_file, fixP->fx_line, 18703 _("invalid immediate for stack address calculation")); 18704 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; 18705 newval |= value >> 2; 18706 } 18707 else if (rs == REG_PC || rs == REG_SP) 18708 { 18709 if (subtract || value & ~0x3fc) 18710 as_bad_where (fixP->fx_file, fixP->fx_line, 18711 _("invalid immediate for address calculation (value = 0x%08lX)"), 18712 (unsigned long) value); 18713 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); 18714 newval |= rd << 8; 18715 newval |= value >> 2; 18716 } 18717 else if (rs == rd) 18718 { 18719 if (value & ~0xff) 18720 as_bad_where (fixP->fx_file, fixP->fx_line, 18721 _("immediate value out of range")); 18722 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; 18723 newval |= (rd << 8) | value; 18724 } 18725 else 18726 { 18727 if (value & ~0x7) 18728 as_bad_where (fixP->fx_file, fixP->fx_line, 18729 _("immediate value out of range")); 18730 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; 18731 newval |= rd | (rs << 3) | (value << 6); 18732 } 18733 } 18734 md_number_to_chars (buf, newval, THUMB_SIZE); 18735 break; 18736 18737 case BFD_RELOC_ARM_THUMB_IMM: 18738 newval = md_chars_to_number (buf, THUMB_SIZE); 18739 if (value < 0 || value > 255) 18740 as_bad_where (fixP->fx_file, fixP->fx_line, 18741 _("invalid immediate: %ld is too large"), 18742 (long) value); 18743 newval |= value; 18744 md_number_to_chars (buf, newval, THUMB_SIZE); 18745 break; 18746 18747 case BFD_RELOC_ARM_THUMB_SHIFT: 18748 /* 5bit shift value (0..32). LSL cannot take 32. */ 18749 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; 18750 temp = newval & 0xf800; 18751 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) 18752 as_bad_where (fixP->fx_file, fixP->fx_line, 18753 _("invalid shift value: %ld"), (long) value); 18754 /* Shifts of zero must be encoded as LSL. */ 18755 if (value == 0) 18756 newval = (newval & 0x003f) | T_OPCODE_LSL_I; 18757 /* Shifts of 32 are encoded as zero. */ 18758 else if (value == 32) 18759 value = 0; 18760 newval |= value << 6; 18761 md_number_to_chars (buf, newval, THUMB_SIZE); 18762 break; 18763 18764 case BFD_RELOC_VTABLE_INHERIT: 18765 case BFD_RELOC_VTABLE_ENTRY: 18766 fixP->fx_done = 0; 18767 return; 18768 18769 case BFD_RELOC_ARM_MOVW: 18770 case BFD_RELOC_ARM_MOVT: 18771 case BFD_RELOC_ARM_THUMB_MOVW: 18772 case BFD_RELOC_ARM_THUMB_MOVT: 18773 if (fixP->fx_done || !seg->use_rela_p) 18774 { 18775 /* REL format relocations are limited to a 16-bit addend. */ 18776 if (!fixP->fx_done) 18777 { 18778 if (value < -0x1000 || value > 0xffff) 18779 as_bad_where (fixP->fx_file, fixP->fx_line, 18780 _("offset too big")); 18781 } 18782 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT 18783 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) 18784 { 18785 value >>= 16; 18786 } 18787 18788 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW 18789 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) 18790 { 18791 newval = get_thumb32_insn (buf); 18792 newval &= 0xfbf08f00; 18793 newval |= (value & 0xf000) << 4; 18794 newval |= (value & 0x0800) << 15; 18795 newval |= (value & 0x0700) << 4; 18796 newval |= (value & 0x00ff); 18797 put_thumb32_insn (buf, newval); 18798 } 18799 else 18800 { 18801 newval = md_chars_to_number (buf, 4); 18802 newval &= 0xfff0f000; 18803 newval |= value & 0x0fff; 18804 newval |= (value & 0xf000) << 4; 18805 md_number_to_chars (buf, newval, 4); 18806 } 18807 } 18808 return; 18809 18810 case BFD_RELOC_ARM_ALU_PC_G0_NC: 18811 case BFD_RELOC_ARM_ALU_PC_G0: 18812 case BFD_RELOC_ARM_ALU_PC_G1_NC: 18813 case BFD_RELOC_ARM_ALU_PC_G1: 18814 case BFD_RELOC_ARM_ALU_PC_G2: 18815 case BFD_RELOC_ARM_ALU_SB_G0_NC: 18816 case BFD_RELOC_ARM_ALU_SB_G0: 18817 case BFD_RELOC_ARM_ALU_SB_G1_NC: 18818 case BFD_RELOC_ARM_ALU_SB_G1: 18819 case BFD_RELOC_ARM_ALU_SB_G2: 18820 assert (!fixP->fx_done); 18821 if (!seg->use_rela_p) 18822 { 18823 bfd_vma insn; 18824 bfd_vma encoded_addend; 18825 bfd_vma addend_abs = abs (value); 18826 18827 /* Check that the absolute value of the addend can be 18828 expressed as an 8-bit constant plus a rotation. */ 18829 encoded_addend = encode_arm_immediate (addend_abs); 18830 if (encoded_addend == (unsigned int) FAIL) 18831 as_bad_where (fixP->fx_file, fixP->fx_line, 18832 _("the offset 0x%08lX is not representable"), 18833 (unsigned long) addend_abs); 18834 18835 /* Extract the instruction. */ 18836 insn = md_chars_to_number (buf, INSN_SIZE); 18837 18838 /* If the addend is positive, use an ADD instruction. 18839 Otherwise use a SUB. Take care not to destroy the S bit. */ 18840 insn &= 0xff1fffff; 18841 if (value < 0) 18842 insn |= 1 << 22; 18843 else 18844 insn |= 1 << 23; 18845 18846 /* Place the encoded addend into the first 12 bits of the 18847 instruction. */ 18848 insn &= 0xfffff000; 18849 insn |= encoded_addend; 18850 18851 /* Update the instruction. */ 18852 md_number_to_chars (buf, insn, INSN_SIZE); 18853 } 18854 break; 18855 18856 case BFD_RELOC_ARM_LDR_PC_G0: 18857 case BFD_RELOC_ARM_LDR_PC_G1: 18858 case BFD_RELOC_ARM_LDR_PC_G2: 18859 case BFD_RELOC_ARM_LDR_SB_G0: 18860 case BFD_RELOC_ARM_LDR_SB_G1: 18861 case BFD_RELOC_ARM_LDR_SB_G2: 18862 assert (!fixP->fx_done); 18863 if (!seg->use_rela_p) 18864 { 18865 bfd_vma insn; 18866 bfd_vma addend_abs = abs (value); 18867 18868 /* Check that the absolute value of the addend can be 18869 encoded in 12 bits. */ 18870 if (addend_abs >= 0x1000) 18871 as_bad_where (fixP->fx_file, fixP->fx_line, 18872 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), 18873 (unsigned long) addend_abs); 18874 18875 /* Extract the instruction. */ 18876 insn = md_chars_to_number (buf, INSN_SIZE); 18877 18878 /* If the addend is negative, clear bit 23 of the instruction. 18879 Otherwise set it. */ 18880 if (value < 0) 18881 insn &= ~(1 << 23); 18882 else 18883 insn |= 1 << 23; 18884 18885 /* Place the absolute value of the addend into the first 12 bits 18886 of the instruction. */ 18887 insn &= 0xfffff000; 18888 insn |= addend_abs; 18889 18890 /* Update the instruction. */ 18891 md_number_to_chars (buf, insn, INSN_SIZE); 18892 } 18893 break; 18894 18895 case BFD_RELOC_ARM_LDRS_PC_G0: 18896 case BFD_RELOC_ARM_LDRS_PC_G1: 18897 case BFD_RELOC_ARM_LDRS_PC_G2: 18898 case BFD_RELOC_ARM_LDRS_SB_G0: 18899 case BFD_RELOC_ARM_LDRS_SB_G1: 18900 case BFD_RELOC_ARM_LDRS_SB_G2: 18901 assert (!fixP->fx_done); 18902 if (!seg->use_rela_p) 18903 { 18904 bfd_vma insn; 18905 bfd_vma addend_abs = abs (value); 18906 18907 /* Check that the absolute value of the addend can be 18908 encoded in 8 bits. */ 18909 if (addend_abs >= 0x100) 18910 as_bad_where (fixP->fx_file, fixP->fx_line, 18911 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), 18912 (unsigned long) addend_abs); 18913 18914 /* Extract the instruction. */ 18915 insn = md_chars_to_number (buf, INSN_SIZE); 18916 18917 /* If the addend is negative, clear bit 23 of the instruction. 18918 Otherwise set it. */ 18919 if (value < 0) 18920 insn &= ~(1 << 23); 18921 else 18922 insn |= 1 << 23; 18923 18924 /* Place the first four bits of the absolute value of the addend 18925 into the first 4 bits of the instruction, and the remaining 18926 four into bits 8 .. 11. */ 18927 insn &= 0xfffff0f0; 18928 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); 18929 18930 /* Update the instruction. */ 18931 md_number_to_chars (buf, insn, INSN_SIZE); 18932 } 18933 break; 18934 18935 case BFD_RELOC_ARM_LDC_PC_G0: 18936 case BFD_RELOC_ARM_LDC_PC_G1: 18937 case BFD_RELOC_ARM_LDC_PC_G2: 18938 case BFD_RELOC_ARM_LDC_SB_G0: 18939 case BFD_RELOC_ARM_LDC_SB_G1: 18940 case BFD_RELOC_ARM_LDC_SB_G2: 18941 assert (!fixP->fx_done); 18942 if (!seg->use_rela_p) 18943 { 18944 bfd_vma insn; 18945 bfd_vma addend_abs = abs (value); 18946 18947 /* Check that the absolute value of the addend is a multiple of 18948 four and, when divided by four, fits in 8 bits. */ 18949 if (addend_abs & 0x3) 18950 as_bad_where (fixP->fx_file, fixP->fx_line, 18951 _("bad offset 0x%08lX (must be word-aligned)"), 18952 (unsigned long) addend_abs); 18953 18954 if ((addend_abs >> 2) > 0xff) 18955 as_bad_where (fixP->fx_file, fixP->fx_line, 18956 _("bad offset 0x%08lX (must be an 8-bit number of words)"), 18957 (unsigned long) addend_abs); 18958 18959 /* Extract the instruction. */ 18960 insn = md_chars_to_number (buf, INSN_SIZE); 18961 18962 /* If the addend is negative, clear bit 23 of the instruction. 18963 Otherwise set it. */ 18964 if (value < 0) 18965 insn &= ~(1 << 23); 18966 else 18967 insn |= 1 << 23; 18968 18969 /* Place the addend (divided by four) into the first eight 18970 bits of the instruction. */ 18971 insn &= 0xfffffff0; 18972 insn |= addend_abs >> 2; 18973 18974 /* Update the instruction. */ 18975 md_number_to_chars (buf, insn, INSN_SIZE); 18976 } 18977 break; 18978 18979 case BFD_RELOC_UNUSED: 18980 default: 18981 as_bad_where (fixP->fx_file, fixP->fx_line, 18982 _("bad relocation fixup type (%d)"), fixP->fx_r_type); 18983 } 18984} 18985 18986/* Translate internal representation of relocation info to BFD target 18987 format. */ 18988 18989arelent * 18990tc_gen_reloc (asection *section, fixS *fixp) 18991{ 18992 arelent * reloc; 18993 bfd_reloc_code_real_type code; 18994 18995 reloc = xmalloc (sizeof (arelent)); 18996 18997 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); 18998 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 18999 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 19000 19001 if (fixp->fx_pcrel) 19002 { 19003 if (section->use_rela_p) 19004 fixp->fx_offset -= md_pcrel_from_section (fixp, section); 19005 else 19006 fixp->fx_offset = reloc->address; 19007 } 19008 reloc->addend = fixp->fx_offset; 19009 19010 switch (fixp->fx_r_type) 19011 { 19012 case BFD_RELOC_8: 19013 if (fixp->fx_pcrel) 19014 { 19015 code = BFD_RELOC_8_PCREL; 19016 break; 19017 } 19018 19019 case BFD_RELOC_16: 19020 if (fixp->fx_pcrel) 19021 { 19022 code = BFD_RELOC_16_PCREL; 19023 break; 19024 } 19025 19026 case BFD_RELOC_32: 19027 if (fixp->fx_pcrel) 19028 { 19029 code = BFD_RELOC_32_PCREL; 19030 break; 19031 } 19032 19033 case BFD_RELOC_ARM_MOVW: 19034 if (fixp->fx_pcrel) 19035 { 19036 code = BFD_RELOC_ARM_MOVW_PCREL; 19037 break; 19038 } 19039 19040 case BFD_RELOC_ARM_MOVT: 19041 if (fixp->fx_pcrel) 19042 { 19043 code = BFD_RELOC_ARM_MOVT_PCREL; 19044 break; 19045 } 19046 19047 case BFD_RELOC_ARM_THUMB_MOVW: 19048 if (fixp->fx_pcrel) 19049 { 19050 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; 19051 break; 19052 } 19053 19054 case BFD_RELOC_ARM_THUMB_MOVT: 19055 if (fixp->fx_pcrel) 19056 { 19057 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; 19058 break; 19059 } 19060 19061 case BFD_RELOC_NONE: 19062 case BFD_RELOC_ARM_PCREL_BRANCH: 19063 case BFD_RELOC_ARM_PCREL_BLX: 19064 case BFD_RELOC_RVA: 19065 case BFD_RELOC_THUMB_PCREL_BRANCH7: 19066 case BFD_RELOC_THUMB_PCREL_BRANCH9: 19067 case BFD_RELOC_THUMB_PCREL_BRANCH12: 19068 case BFD_RELOC_THUMB_PCREL_BRANCH20: 19069 case BFD_RELOC_THUMB_PCREL_BRANCH23: 19070 case BFD_RELOC_THUMB_PCREL_BRANCH25: 19071 case BFD_RELOC_THUMB_PCREL_BLX: 19072 case BFD_RELOC_VTABLE_ENTRY: 19073 case BFD_RELOC_VTABLE_INHERIT: 19074#ifdef TE_PE 19075 case BFD_RELOC_32_SECREL: 19076#endif 19077 code = fixp->fx_r_type; 19078 break; 19079 19080 case BFD_RELOC_ARM_LITERAL: 19081 case BFD_RELOC_ARM_HWLITERAL: 19082 /* If this is called then the a literal has 19083 been referenced across a section boundary. */ 19084 as_bad_where (fixp->fx_file, fixp->fx_line, 19085 _("literal referenced across section boundary")); 19086 return NULL; 19087 19088#ifdef OBJ_ELF 19089 case BFD_RELOC_ARM_GOT32: 19090 case BFD_RELOC_ARM_GOTOFF: 19091 case BFD_RELOC_ARM_PLT32: 19092 case BFD_RELOC_ARM_TARGET1: 19093 case BFD_RELOC_ARM_ROSEGREL32: 19094 case BFD_RELOC_ARM_SBREL32: 19095 case BFD_RELOC_ARM_PREL31: 19096 case BFD_RELOC_ARM_TARGET2: 19097 case BFD_RELOC_ARM_TLS_LE32: 19098 case BFD_RELOC_ARM_TLS_LDO32: 19099 case BFD_RELOC_ARM_PCREL_CALL: 19100 case BFD_RELOC_ARM_PCREL_JUMP: 19101 case BFD_RELOC_ARM_ALU_PC_G0_NC: 19102 case BFD_RELOC_ARM_ALU_PC_G0: 19103 case BFD_RELOC_ARM_ALU_PC_G1_NC: 19104 case BFD_RELOC_ARM_ALU_PC_G1: 19105 case BFD_RELOC_ARM_ALU_PC_G2: 19106 case BFD_RELOC_ARM_LDR_PC_G0: 19107 case BFD_RELOC_ARM_LDR_PC_G1: 19108 case BFD_RELOC_ARM_LDR_PC_G2: 19109 case BFD_RELOC_ARM_LDRS_PC_G0: 19110 case BFD_RELOC_ARM_LDRS_PC_G1: 19111 case BFD_RELOC_ARM_LDRS_PC_G2: 19112 case BFD_RELOC_ARM_LDC_PC_G0: 19113 case BFD_RELOC_ARM_LDC_PC_G1: 19114 case BFD_RELOC_ARM_LDC_PC_G2: 19115 case BFD_RELOC_ARM_ALU_SB_G0_NC: 19116 case BFD_RELOC_ARM_ALU_SB_G0: 19117 case BFD_RELOC_ARM_ALU_SB_G1_NC: 19118 case BFD_RELOC_ARM_ALU_SB_G1: 19119 case BFD_RELOC_ARM_ALU_SB_G2: 19120 case BFD_RELOC_ARM_LDR_SB_G0: 19121 case BFD_RELOC_ARM_LDR_SB_G1: 19122 case BFD_RELOC_ARM_LDR_SB_G2: 19123 case BFD_RELOC_ARM_LDRS_SB_G0: 19124 case BFD_RELOC_ARM_LDRS_SB_G1: 19125 case BFD_RELOC_ARM_LDRS_SB_G2: 19126 case BFD_RELOC_ARM_LDC_SB_G0: 19127 case BFD_RELOC_ARM_LDC_SB_G1: 19128 case BFD_RELOC_ARM_LDC_SB_G2: 19129 code = fixp->fx_r_type; 19130 break; 19131 19132 case BFD_RELOC_ARM_TLS_GD32: 19133 case BFD_RELOC_ARM_TLS_IE32: 19134 case BFD_RELOC_ARM_TLS_LDM32: 19135 /* BFD will include the symbol's address in the addend. 19136 But we don't want that, so subtract it out again here. */ 19137 if (!S_IS_COMMON (fixp->fx_addsy)) 19138 reloc->addend -= (*reloc->sym_ptr_ptr)->value; 19139 code = fixp->fx_r_type; 19140 break; 19141#endif 19142 19143 case BFD_RELOC_ARM_IMMEDIATE: 19144 as_bad_where (fixp->fx_file, fixp->fx_line, 19145 _("internal relocation (type: IMMEDIATE) not fixed up")); 19146 return NULL; 19147 19148 case BFD_RELOC_ARM_ADRL_IMMEDIATE: 19149 as_bad_where (fixp->fx_file, fixp->fx_line, 19150 _("ADRL used for a symbol not defined in the same file")); 19151 return NULL; 19152 19153 case BFD_RELOC_ARM_OFFSET_IMM: 19154 if (section->use_rela_p) 19155 { 19156 code = fixp->fx_r_type; 19157 break; 19158 } 19159 19160 if (fixp->fx_addsy != NULL 19161 && !S_IS_DEFINED (fixp->fx_addsy) 19162 && S_IS_LOCAL (fixp->fx_addsy)) 19163 { 19164 as_bad_where (fixp->fx_file, fixp->fx_line, 19165 _("undefined local label `%s'"), 19166 S_GET_NAME (fixp->fx_addsy)); 19167 return NULL; 19168 } 19169 19170 as_bad_where (fixp->fx_file, fixp->fx_line, 19171 _("internal_relocation (type: OFFSET_IMM) not fixed up")); 19172 return NULL; 19173 19174 default: 19175 { 19176 char * type; 19177 19178 switch (fixp->fx_r_type) 19179 { 19180 case BFD_RELOC_NONE: type = "NONE"; break; 19181 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; 19182 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; 19183 case BFD_RELOC_ARM_SMC: type = "SMC"; break; 19184 case BFD_RELOC_ARM_SWI: type = "SWI"; break; 19185 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; 19186 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; 19187 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; 19188 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; 19189 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; 19190 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; 19191 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; 19192 default: type = _("<unknown>"); break; 19193 } 19194 as_bad_where (fixp->fx_file, fixp->fx_line, 19195 _("cannot represent %s relocation in this object file format"), 19196 type); 19197 return NULL; 19198 } 19199 } 19200 19201#ifdef OBJ_ELF 19202 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) 19203 && GOT_symbol 19204 && fixp->fx_addsy == GOT_symbol) 19205 { 19206 code = BFD_RELOC_ARM_GOTPC; 19207 reloc->addend = fixp->fx_offset = reloc->address; 19208 } 19209#endif 19210 19211 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 19212 19213 if (reloc->howto == NULL) 19214 { 19215 as_bad_where (fixp->fx_file, fixp->fx_line, 19216 _("cannot represent %s relocation in this object file format"), 19217 bfd_get_reloc_code_name (code)); 19218 return NULL; 19219 } 19220 19221 /* HACK: Since arm ELF uses Rel instead of Rela, encode the 19222 vtable entry to be used in the relocation's section offset. */ 19223 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 19224 reloc->address = fixp->fx_offset; 19225 19226 return reloc; 19227} 19228 19229/* This fix_new is called by cons via TC_CONS_FIX_NEW. */ 19230 19231void 19232cons_fix_new_arm (fragS * frag, 19233 int where, 19234 int size, 19235 expressionS * exp) 19236{ 19237 bfd_reloc_code_real_type type; 19238 int pcrel = 0; 19239 19240 /* Pick a reloc. 19241 FIXME: @@ Should look at CPU word size. */ 19242 switch (size) 19243 { 19244 case 1: 19245 type = BFD_RELOC_8; 19246 break; 19247 case 2: 19248 type = BFD_RELOC_16; 19249 break; 19250 case 4: 19251 default: 19252 type = BFD_RELOC_32; 19253 break; 19254 case 8: 19255 type = BFD_RELOC_64; 19256 break; 19257 } 19258 19259#ifdef TE_PE 19260 if (exp->X_op == O_secrel) 19261 { 19262 exp->X_op = O_symbol; 19263 type = BFD_RELOC_32_SECREL; 19264 } 19265#endif 19266 19267 fix_new_exp (frag, where, (int) size, exp, pcrel, type); 19268} 19269 19270#if defined OBJ_COFF || defined OBJ_ELF 19271void 19272arm_validate_fix (fixS * fixP) 19273{ 19274 /* If the destination of the branch is a defined symbol which does not have 19275 the THUMB_FUNC attribute, then we must be calling a function which has 19276 the (interfacearm) attribute. We look for the Thumb entry point to that 19277 function and change the branch to refer to that function instead. */ 19278 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 19279 && fixP->fx_addsy != NULL 19280 && S_IS_DEFINED (fixP->fx_addsy) 19281 && ! THUMB_IS_FUNC (fixP->fx_addsy)) 19282 { 19283 fixP->fx_addsy = find_real_start (fixP->fx_addsy); 19284 } 19285} 19286#endif 19287 19288int 19289arm_force_relocation (struct fix * fixp) 19290{ 19291#if defined (OBJ_COFF) && defined (TE_PE) 19292 if (fixp->fx_r_type == BFD_RELOC_RVA) 19293 return 1; 19294#endif 19295 19296 /* Resolve these relocations even if the symbol is extern or weak. */ 19297 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE 19298 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM 19299 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE 19300 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM 19301 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE 19302 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 19303 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12) 19304 return 0; 19305 19306 /* Always leave these relocations for the linker. */ 19307 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC 19308 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) 19309 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) 19310 return 1; 19311 19312 /* Always generate relocations against function symbols. */ 19313 if (fixp->fx_r_type == BFD_RELOC_32 19314 && fixp->fx_addsy 19315 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) 19316 return 1; 19317 19318 return generic_force_reloc (fixp); 19319} 19320 19321#if defined (OBJ_ELF) || defined (OBJ_COFF) 19322/* Relocations against function names must be left unadjusted, 19323 so that the linker can use this information to generate interworking 19324 stubs. The MIPS version of this function 19325 also prevents relocations that are mips-16 specific, but I do not 19326 know why it does this. 19327 19328 FIXME: 19329 There is one other problem that ought to be addressed here, but 19330 which currently is not: Taking the address of a label (rather 19331 than a function) and then later jumping to that address. Such 19332 addresses also ought to have their bottom bit set (assuming that 19333 they reside in Thumb code), but at the moment they will not. */ 19334 19335bfd_boolean 19336arm_fix_adjustable (fixS * fixP) 19337{ 19338 if (fixP->fx_addsy == NULL) 19339 return 1; 19340 19341 /* Preserve relocations against symbols with function type. */ 19342 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) 19343 return 0; 19344 19345 if (THUMB_IS_FUNC (fixP->fx_addsy) 19346 && fixP->fx_subsy == NULL) 19347 return 0; 19348 19349 /* We need the symbol name for the VTABLE entries. */ 19350 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 19351 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 19352 return 0; 19353 19354 /* Don't allow symbols to be discarded on GOT related relocs. */ 19355 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 19356 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 19357 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF 19358 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 19359 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 19360 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 19361 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 19362 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 19363 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) 19364 return 0; 19365 19366 /* Similarly for group relocations. */ 19367 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC 19368 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) 19369 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) 19370 return 0; 19371 19372 return 1; 19373} 19374#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ 19375 19376#ifdef OBJ_ELF 19377 19378const char * 19379elf32_arm_target_format (void) 19380{ 19381#ifdef TE_SYMBIAN 19382 return (target_big_endian 19383 ? "elf32-bigarm-symbian" 19384 : "elf32-littlearm-symbian"); 19385#elif defined (TE_VXWORKS) 19386 return (target_big_endian 19387 ? "elf32-bigarm-vxworks" 19388 : "elf32-littlearm-vxworks"); 19389#else 19390 if (target_big_endian) 19391 return "elf32-bigarm"; 19392 else 19393 return "elf32-littlearm"; 19394#endif 19395} 19396 19397void 19398armelf_frob_symbol (symbolS * symp, 19399 int * puntp) 19400{ 19401 elf_frob_symbol (symp, puntp); 19402} 19403#endif 19404 19405/* MD interface: Finalization. */ 19406 19407/* A good place to do this, although this was probably not intended 19408 for this kind of use. We need to dump the literal pool before 19409 references are made to a null symbol pointer. */ 19410 19411void 19412arm_cleanup (void) 19413{ 19414 literal_pool * pool; 19415 19416 for (pool = list_of_pools; pool; pool = pool->next) 19417 { 19418 /* Put it at the end of the relevent section. */ 19419 subseg_set (pool->section, pool->sub_section); 19420#ifdef OBJ_ELF 19421 arm_elf_change_section (); 19422#endif 19423 s_ltorg (0); 19424 } 19425} 19426 19427/* Adjust the symbol table. This marks Thumb symbols as distinct from 19428 ARM ones. */ 19429 19430void 19431arm_adjust_symtab (void) 19432{ 19433#ifdef OBJ_COFF 19434 symbolS * sym; 19435 19436 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 19437 { 19438 if (ARM_IS_THUMB (sym)) 19439 { 19440 if (THUMB_IS_FUNC (sym)) 19441 { 19442 /* Mark the symbol as a Thumb function. */ 19443 if ( S_GET_STORAGE_CLASS (sym) == C_STAT 19444 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ 19445 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); 19446 19447 else if (S_GET_STORAGE_CLASS (sym) == C_EXT) 19448 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); 19449 else 19450 as_bad (_("%s: unexpected function type: %d"), 19451 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); 19452 } 19453 else switch (S_GET_STORAGE_CLASS (sym)) 19454 { 19455 case C_EXT: 19456 S_SET_STORAGE_CLASS (sym, C_THUMBEXT); 19457 break; 19458 case C_STAT: 19459 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); 19460 break; 19461 case C_LABEL: 19462 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); 19463 break; 19464 default: 19465 /* Do nothing. */ 19466 break; 19467 } 19468 } 19469 19470 if (ARM_IS_INTERWORK (sym)) 19471 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; 19472 } 19473#endif 19474#ifdef OBJ_ELF 19475 symbolS * sym; 19476 char bind; 19477 19478 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 19479 { 19480 if (ARM_IS_THUMB (sym)) 19481 { 19482 elf_symbol_type * elf_sym; 19483 19484 elf_sym = elf_symbol (symbol_get_bfdsym (sym)); 19485 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); 19486 19487 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, 19488 BFD_ARM_SPECIAL_SYM_TYPE_ANY)) 19489 { 19490 /* If it's a .thumb_func, declare it as so, 19491 otherwise tag label as .code 16. */ 19492 if (THUMB_IS_FUNC (sym)) 19493 elf_sym->internal_elf_sym.st_info = 19494 ELF_ST_INFO (bind, STT_ARM_TFUNC); 19495 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) 19496 elf_sym->internal_elf_sym.st_info = 19497 ELF_ST_INFO (bind, STT_ARM_16BIT); 19498 } 19499 } 19500 } 19501#endif 19502} 19503 19504/* MD interface: Initialization. */ 19505 19506static void 19507set_constant_flonums (void) 19508{ 19509 int i; 19510 19511 for (i = 0; i < NUM_FLOAT_VALS; i++) 19512 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) 19513 abort (); 19514} 19515 19516/* Auto-select Thumb mode if it's the only available instruction set for the 19517 given architecture. */ 19518 19519static void 19520autoselect_thumb_from_cpu_variant (void) 19521{ 19522 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 19523 opcode_select (16); 19524} 19525 19526void 19527md_begin (void) 19528{ 19529 unsigned mach; 19530 unsigned int i; 19531 19532 if ( (arm_ops_hsh = hash_new ()) == NULL 19533 || (arm_cond_hsh = hash_new ()) == NULL 19534 || (arm_shift_hsh = hash_new ()) == NULL 19535 || (arm_psr_hsh = hash_new ()) == NULL 19536 || (arm_v7m_psr_hsh = hash_new ()) == NULL 19537 || (arm_reg_hsh = hash_new ()) == NULL 19538 || (arm_reloc_hsh = hash_new ()) == NULL 19539 || (arm_barrier_opt_hsh = hash_new ()) == NULL) 19540 as_fatal (_("virtual memory exhausted")); 19541 19542 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) 19543 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i)); 19544 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) 19545 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i)); 19546 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) 19547 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i)); 19548 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) 19549 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i)); 19550 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) 19551 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template, (PTR) (v7m_psrs + i)); 19552 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) 19553 hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i)); 19554 for (i = 0; 19555 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); 19556 i++) 19557 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template, 19558 (PTR) (barrier_opt_names + i)); 19559#ifdef OBJ_ELF 19560 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++) 19561 hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i)); 19562#endif 19563 19564 set_constant_flonums (); 19565 19566 /* Set the cpu variant based on the command-line options. We prefer 19567 -mcpu= over -march= if both are set (as for GCC); and we prefer 19568 -mfpu= over any other way of setting the floating point unit. 19569 Use of legacy options with new options are faulted. */ 19570 if (legacy_cpu) 19571 { 19572 if (mcpu_cpu_opt || march_cpu_opt) 19573 as_bad (_("use of old and new-style options to set CPU type")); 19574 19575 mcpu_cpu_opt = legacy_cpu; 19576 } 19577 else if (!mcpu_cpu_opt) 19578 mcpu_cpu_opt = march_cpu_opt; 19579 19580 if (legacy_fpu) 19581 { 19582 if (mfpu_opt) 19583 as_bad (_("use of old and new-style options to set FPU type")); 19584 19585 mfpu_opt = legacy_fpu; 19586 } 19587 else if (!mfpu_opt) 19588 { 19589#if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS)) 19590 /* Some environments specify a default FPU. If they don't, infer it 19591 from the processor. */ 19592 if (mcpu_fpu_opt) 19593 mfpu_opt = mcpu_fpu_opt; 19594 else 19595 mfpu_opt = march_fpu_opt; 19596#else 19597 mfpu_opt = &fpu_default; 19598#endif 19599 } 19600 19601 if (!mfpu_opt) 19602 { 19603 if (mcpu_cpu_opt != NULL) 19604 mfpu_opt = &fpu_default; 19605 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) 19606 mfpu_opt = &fpu_arch_vfp_v2; 19607 else 19608 mfpu_opt = &fpu_arch_fpa; 19609 } 19610 19611#ifdef CPU_DEFAULT 19612 if (!mcpu_cpu_opt) 19613 { 19614 mcpu_cpu_opt = &cpu_default; 19615 selected_cpu = cpu_default; 19616 } 19617#else 19618 if (mcpu_cpu_opt) 19619 selected_cpu = *mcpu_cpu_opt; 19620 else 19621 mcpu_cpu_opt = &arm_arch_any; 19622#endif 19623 19624 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 19625 19626 autoselect_thumb_from_cpu_variant (); 19627 19628 arm_arch_used = thumb_arch_used = arm_arch_none; 19629 19630#if defined OBJ_COFF || defined OBJ_ELF 19631 { 19632 unsigned int flags = 0; 19633 19634#if defined OBJ_ELF 19635 flags = meabi_flags; 19636 19637 switch (meabi_flags) 19638 { 19639 case EF_ARM_EABI_UNKNOWN: 19640#endif 19641 /* Set the flags in the private structure. */ 19642 if (uses_apcs_26) flags |= F_APCS26; 19643 if (support_interwork) flags |= F_INTERWORK; 19644 if (uses_apcs_float) flags |= F_APCS_FLOAT; 19645 if (pic_code) flags |= F_PIC; 19646 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) 19647 flags |= F_SOFT_FLOAT; 19648 19649 switch (mfloat_abi_opt) 19650 { 19651 case ARM_FLOAT_ABI_SOFT: 19652 case ARM_FLOAT_ABI_SOFTFP: 19653 flags |= F_SOFT_FLOAT; 19654 break; 19655 19656 case ARM_FLOAT_ABI_HARD: 19657 if (flags & F_SOFT_FLOAT) 19658 as_bad (_("hard-float conflicts with specified fpu")); 19659 break; 19660 } 19661 19662 /* Using pure-endian doubles (even if soft-float). */ 19663 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) 19664 flags |= F_VFP_FLOAT; 19665 19666#if defined OBJ_ELF 19667 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) 19668 flags |= EF_ARM_MAVERICK_FLOAT; 19669 break; 19670 19671 case EF_ARM_EABI_VER4: 19672 case EF_ARM_EABI_VER5: 19673 /* No additional flags to set. */ 19674 break; 19675 19676 default: 19677 abort (); 19678 } 19679#endif 19680 bfd_set_private_flags (stdoutput, flags); 19681 19682 /* We have run out flags in the COFF header to encode the 19683 status of ATPCS support, so instead we create a dummy, 19684 empty, debug section called .arm.atpcs. */ 19685 if (atpcs) 19686 { 19687 asection * sec; 19688 19689 sec = bfd_make_section (stdoutput, ".arm.atpcs"); 19690 19691 if (sec != NULL) 19692 { 19693 bfd_set_section_flags 19694 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); 19695 bfd_set_section_size (stdoutput, sec, 0); 19696 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); 19697 } 19698 } 19699 } 19700#endif 19701 19702 /* Record the CPU type as well. */ 19703 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) 19704 mach = bfd_mach_arm_iWMMXt2; 19705 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) 19706 mach = bfd_mach_arm_iWMMXt; 19707 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) 19708 mach = bfd_mach_arm_XScale; 19709 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) 19710 mach = bfd_mach_arm_ep9312; 19711 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) 19712 mach = bfd_mach_arm_5TE; 19713 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) 19714 { 19715 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 19716 mach = bfd_mach_arm_5T; 19717 else 19718 mach = bfd_mach_arm_5; 19719 } 19720 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) 19721 { 19722 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 19723 mach = bfd_mach_arm_4T; 19724 else 19725 mach = bfd_mach_arm_4; 19726 } 19727 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) 19728 mach = bfd_mach_arm_3M; 19729 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) 19730 mach = bfd_mach_arm_3; 19731 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) 19732 mach = bfd_mach_arm_2a; 19733 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) 19734 mach = bfd_mach_arm_2; 19735 else 19736 mach = bfd_mach_arm_unknown; 19737 19738 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); 19739} 19740 19741/* Command line processing. */ 19742 19743/* md_parse_option 19744 Invocation line includes a switch not recognized by the base assembler. 19745 See if it's a processor-specific option. 19746 19747 This routine is somewhat complicated by the need for backwards 19748 compatibility (since older releases of gcc can't be changed). 19749 The new options try to make the interface as compatible as 19750 possible with GCC. 19751 19752 New options (supported) are: 19753 19754 -mcpu=<cpu name> Assemble for selected processor 19755 -march=<architecture name> Assemble for selected architecture 19756 -mfpu=<fpu architecture> Assemble for selected FPU. 19757 -EB/-mbig-endian Big-endian 19758 -EL/-mlittle-endian Little-endian 19759 -k Generate PIC code 19760 -mthumb Start in Thumb mode 19761 -mthumb-interwork Code supports ARM/Thumb interworking 19762 19763 For now we will also provide support for: 19764 19765 -mapcs-32 32-bit Program counter 19766 -mapcs-26 26-bit Program counter 19767 -macps-float Floats passed in FP registers 19768 -mapcs-reentrant Reentrant code 19769 -matpcs 19770 (sometime these will probably be replaced with -mapcs=<list of options> 19771 and -matpcs=<list of options>) 19772 19773 The remaining options are only supported for back-wards compatibility. 19774 Cpu variants, the arm part is optional: 19775 -m[arm]1 Currently not supported. 19776 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor 19777 -m[arm]3 Arm 3 processor 19778 -m[arm]6[xx], Arm 6 processors 19779 -m[arm]7[xx][t][[d]m] Arm 7 processors 19780 -m[arm]8[10] Arm 8 processors 19781 -m[arm]9[20][tdmi] Arm 9 processors 19782 -mstrongarm[110[0]] StrongARM processors 19783 -mxscale XScale processors 19784 -m[arm]v[2345[t[e]]] Arm architectures 19785 -mall All (except the ARM1) 19786 FP variants: 19787 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions 19788 -mfpe-old (No float load/store multiples) 19789 -mvfpxd VFP Single precision 19790 -mvfp All VFP 19791 -mno-fpu Disable all floating point instructions 19792 19793 The following CPU names are recognized: 19794 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, 19795 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, 19796 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, 19797 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, 19798 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, 19799 arm10t arm10e, arm1020t, arm1020e, arm10200e, 19800 strongarm, strongarm110, strongarm1100, strongarm1110, xscale. 19801 19802 */ 19803 19804const char * md_shortopts = "m:k"; 19805 19806#ifdef ARM_BI_ENDIAN 19807#define OPTION_EB (OPTION_MD_BASE + 0) 19808#define OPTION_EL (OPTION_MD_BASE + 1) 19809#else 19810#if TARGET_BYTES_BIG_ENDIAN 19811#define OPTION_EB (OPTION_MD_BASE + 0) 19812#else 19813#define OPTION_EL (OPTION_MD_BASE + 1) 19814#endif 19815#endif 19816 19817struct option md_longopts[] = 19818{ 19819#ifdef OPTION_EB 19820 {"EB", no_argument, NULL, OPTION_EB}, 19821#endif 19822#ifdef OPTION_EL 19823 {"EL", no_argument, NULL, OPTION_EL}, 19824#endif 19825 {NULL, no_argument, NULL, 0} 19826}; 19827 19828size_t md_longopts_size = sizeof (md_longopts); 19829 19830struct arm_option_table 19831{ 19832 char *option; /* Option name to match. */ 19833 char *help; /* Help information. */ 19834 int *var; /* Variable to change. */ 19835 int value; /* What to change it to. */ 19836 char *deprecated; /* If non-null, print this message. */ 19837}; 19838 19839struct arm_option_table arm_opts[] = 19840{ 19841 {"k", N_("generate PIC code"), &pic_code, 1, NULL}, 19842 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, 19843 {"mthumb-interwork", N_("support ARM/Thumb interworking"), 19844 &support_interwork, 1, NULL}, 19845 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, 19846 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, 19847 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, 19848 1, NULL}, 19849 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, 19850 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, 19851 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, 19852 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, 19853 NULL}, 19854 19855 /* These are recognized by the assembler, but have no affect on code. */ 19856 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, 19857 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, 19858 {NULL, NULL, NULL, 0, NULL} 19859}; 19860 19861struct arm_legacy_option_table 19862{ 19863 char *option; /* Option name to match. */ 19864 const arm_feature_set **var; /* Variable to change. */ 19865 const arm_feature_set value; /* What to change it to. */ 19866 char *deprecated; /* If non-null, print this message. */ 19867}; 19868 19869const struct arm_legacy_option_table arm_legacy_opts[] = 19870{ 19871 /* DON'T add any new processors to this list -- we want the whole list 19872 to go away... Add them to the processors table instead. */ 19873 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, 19874 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, 19875 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, 19876 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, 19877 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, 19878 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, 19879 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, 19880 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, 19881 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, 19882 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, 19883 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, 19884 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, 19885 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, 19886 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, 19887 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, 19888 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, 19889 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, 19890 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, 19891 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, 19892 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, 19893 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, 19894 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, 19895 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, 19896 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, 19897 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, 19898 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, 19899 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, 19900 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, 19901 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, 19902 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, 19903 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, 19904 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, 19905 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, 19906 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, 19907 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, 19908 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, 19909 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, 19910 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, 19911 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, 19912 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, 19913 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, 19914 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, 19915 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, 19916 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, 19917 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, 19918 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, 19919 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19920 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19921 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19922 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19923 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, 19924 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, 19925 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, 19926 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, 19927 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, 19928 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, 19929 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, 19930 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, 19931 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, 19932 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, 19933 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, 19934 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, 19935 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, 19936 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, 19937 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, 19938 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, 19939 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, 19940 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, 19941 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, 19942 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, 19943 N_("use -mcpu=strongarm110")}, 19944 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, 19945 N_("use -mcpu=strongarm1100")}, 19946 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, 19947 N_("use -mcpu=strongarm1110")}, 19948 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, 19949 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, 19950 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, 19951 19952 /* Architecture variants -- don't add any more to this list either. */ 19953 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, 19954 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, 19955 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, 19956 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, 19957 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, 19958 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, 19959 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, 19960 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, 19961 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, 19962 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, 19963 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, 19964 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, 19965 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, 19966 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, 19967 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, 19968 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, 19969 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, 19970 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, 19971 19972 /* Floating point variants -- don't add any more to this list either. */ 19973 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, 19974 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, 19975 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, 19976 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, 19977 N_("use either -mfpu=softfpa or -mfpu=softvfp")}, 19978 19979 {NULL, NULL, ARM_ARCH_NONE, NULL} 19980}; 19981 19982struct arm_cpu_option_table 19983{ 19984 char *name; 19985 const arm_feature_set value; 19986 /* For some CPUs we assume an FPU unless the user explicitly sets 19987 -mfpu=... */ 19988 const arm_feature_set default_fpu; 19989 /* The canonical name of the CPU, or NULL to use NAME converted to upper 19990 case. */ 19991 const char *canonical_name; 19992}; 19993 19994/* This list should, at a minimum, contain all the cpu names 19995 recognized by GCC. */ 19996static const struct arm_cpu_option_table arm_cpus[] = 19997{ 19998 {"all", ARM_ANY, FPU_ARCH_FPA, NULL}, 19999 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL}, 20000 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL}, 20001 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, 20002 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, 20003 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20004 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20005 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20006 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20007 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20008 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20009 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 20010 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20011 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 20012 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20013 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 20014 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20015 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20016 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20017 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20018 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20019 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20020 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20021 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20022 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20023 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20024 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20025 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20026 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20027 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20028 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20029 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20030 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20031 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20032 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20033 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20034 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20035 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20036 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20037 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"}, 20038 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20039 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20040 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20041 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20042 /* For V5 or later processors we default to using VFP; but the user 20043 should really set the FPU type explicitly. */ 20044 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 20045 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20046 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, 20047 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, 20048 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, 20049 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 20050 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"}, 20051 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20052 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 20053 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"}, 20054 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20055 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20056 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 20057 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 20058 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20059 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"}, 20060 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 20061 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20062 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20063 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"}, 20064 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, 20065 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"}, 20066 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL}, 20067 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"}, 20068 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL}, 20069 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL}, 20070 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL}, 20071 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL}, 20072 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL}, 20073 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL}, 20074 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL}, 20075 {"cortex-a8", ARM_ARCH_V7A, ARM_FEATURE(0, FPU_VFP_V3 20076 | FPU_NEON_EXT_V1), 20077 NULL}, 20078 {"cortex-a9", ARM_ARCH_V7A, ARM_FEATURE(0, FPU_VFP_V3 20079 | FPU_NEON_EXT_V1), 20080 NULL}, 20081 {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, NULL}, 20082 {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, NULL}, 20083 /* ??? XSCALE is really an architecture. */ 20084 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, 20085 /* ??? iwmmxt is not a processor. */ 20086 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL}, 20087 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL}, 20088 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, 20089 /* Maverick */ 20090 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"}, 20091 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL} 20092}; 20093 20094struct arm_arch_option_table 20095{ 20096 char *name; 20097 const arm_feature_set value; 20098 const arm_feature_set default_fpu; 20099}; 20100 20101/* This list should, at a minimum, contain all the architecture names 20102 recognized by GCC. */ 20103static const struct arm_arch_option_table arm_archs[] = 20104{ 20105 {"all", ARM_ANY, FPU_ARCH_FPA}, 20106 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA}, 20107 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA}, 20108 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA}, 20109 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA}, 20110 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA}, 20111 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA}, 20112 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA}, 20113 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA}, 20114 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA}, 20115 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA}, 20116 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP}, 20117 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP}, 20118 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP}, 20119 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP}, 20120 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP}, 20121 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP}, 20122 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP}, 20123 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP}, 20124 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP}, 20125 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP}, 20126 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP}, 20127 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP}, 20128 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP}, 20129 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP}, 20130 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP}, 20131 {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP}, 20132 /* The official spelling of the ARMv7 profile variants is the dashed form. 20133 Accept the non-dashed form for compatibility with old toolchains. */ 20134 {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP}, 20135 {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP}, 20136 {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP}, 20137 {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP}, 20138 {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP}, 20139 {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP}, 20140 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP}, 20141 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP}, 20142 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP}, 20143 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE} 20144}; 20145 20146/* ISA extensions in the co-processor space. */ 20147struct arm_option_cpu_value_table 20148{ 20149 char *name; 20150 const arm_feature_set value; 20151}; 20152 20153static const struct arm_option_cpu_value_table arm_extensions[] = 20154{ 20155 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)}, 20156 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)}, 20157 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)}, 20158 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2)}, 20159 {"sec", ARM_FEATURE (ARM_EXT_V6Z, 0)}, 20160 {NULL, ARM_ARCH_NONE} 20161}; 20162 20163/* This list should, at a minimum, contain all the fpu names 20164 recognized by GCC. */ 20165static const struct arm_option_cpu_value_table arm_fpus[] = 20166{ 20167 {"softfpa", FPU_NONE}, 20168 {"fpe", FPU_ARCH_FPE}, 20169 {"fpe2", FPU_ARCH_FPE}, 20170 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ 20171 {"fpa", FPU_ARCH_FPA}, 20172 {"fpa10", FPU_ARCH_FPA}, 20173 {"fpa11", FPU_ARCH_FPA}, 20174 {"arm7500fe", FPU_ARCH_FPA}, 20175 {"softvfp", FPU_ARCH_VFP}, 20176 {"softvfp+vfp", FPU_ARCH_VFP_V2}, 20177 {"vfp", FPU_ARCH_VFP_V2}, 20178 {"vfpv2", FPU_ARCH_VFP_V2}, 20179 {"vfp9", FPU_ARCH_VFP_V2}, 20180 {"vfp3", FPU_ARCH_VFP_V3}, 20181 {"vfpv3", FPU_ARCH_VFP_V3}, 20182 {"vfp10", FPU_ARCH_VFP_V2}, 20183 {"vfp10-r0", FPU_ARCH_VFP_V1}, 20184 {"vfpxd", FPU_ARCH_VFP_V1xD}, 20185 {"arm1020t", FPU_ARCH_VFP_V1}, 20186 {"arm1020e", FPU_ARCH_VFP_V2}, 20187 {"arm1136jfs", FPU_ARCH_VFP_V2}, 20188 {"arm1136jf-s", FPU_ARCH_VFP_V2}, 20189 {"maverick", FPU_ARCH_MAVERICK}, 20190 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, 20191 {NULL, ARM_ARCH_NONE} 20192}; 20193 20194struct arm_option_value_table 20195{ 20196 char *name; 20197 long value; 20198}; 20199 20200static const struct arm_option_value_table arm_float_abis[] = 20201{ 20202 {"hard", ARM_FLOAT_ABI_HARD}, 20203 {"softfp", ARM_FLOAT_ABI_SOFTFP}, 20204 {"soft", ARM_FLOAT_ABI_SOFT}, 20205 {NULL, 0} 20206}; 20207 20208#ifdef OBJ_ELF 20209/* We only know how to output GNU and ver 4/5 (AAELF) formats. */ 20210static const struct arm_option_value_table arm_eabis[] = 20211{ 20212 {"gnu", EF_ARM_EABI_UNKNOWN}, 20213 {"4", EF_ARM_EABI_VER4}, 20214 {"5", EF_ARM_EABI_VER5}, 20215 {NULL, 0} 20216}; 20217#endif 20218 20219struct arm_long_option_table 20220{ 20221 char * option; /* Substring to match. */ 20222 char * help; /* Help information. */ 20223 int (* func) (char * subopt); /* Function to decode sub-option. */ 20224 char * deprecated; /* If non-null, print this message. */ 20225}; 20226 20227static int 20228arm_parse_extension (char * str, const arm_feature_set **opt_p) 20229{ 20230 arm_feature_set *ext_set = xmalloc (sizeof (arm_feature_set)); 20231 20232 /* Copy the feature set, so that we can modify it. */ 20233 *ext_set = **opt_p; 20234 *opt_p = ext_set; 20235 20236 while (str != NULL && *str != 0) 20237 { 20238 const struct arm_option_cpu_value_table * opt; 20239 char * ext; 20240 int optlen; 20241 20242 if (*str != '+') 20243 { 20244 as_bad (_("invalid architectural extension")); 20245 return 0; 20246 } 20247 20248 str++; 20249 ext = strchr (str, '+'); 20250 20251 if (ext != NULL) 20252 optlen = ext - str; 20253 else 20254 optlen = strlen (str); 20255 20256 if (optlen == 0) 20257 { 20258 as_bad (_("missing architectural extension")); 20259 return 0; 20260 } 20261 20262 for (opt = arm_extensions; opt->name != NULL; opt++) 20263 if (strncmp (opt->name, str, optlen) == 0) 20264 { 20265 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); 20266 break; 20267 } 20268 20269 if (opt->name == NULL) 20270 { 20271 as_bad (_("unknown architectural extnsion `%s'"), str); 20272 return 0; 20273 } 20274 20275 str = ext; 20276 }; 20277 20278 return 1; 20279} 20280 20281static int 20282arm_parse_cpu (char * str) 20283{ 20284 const struct arm_cpu_option_table * opt; 20285 char * ext = strchr (str, '+'); 20286 int optlen; 20287 20288 if (ext != NULL) 20289 optlen = ext - str; 20290 else 20291 optlen = strlen (str); 20292 20293 if (optlen == 0) 20294 { 20295 as_bad (_("missing cpu name `%s'"), str); 20296 return 0; 20297 } 20298 20299 for (opt = arm_cpus; opt->name != NULL; opt++) 20300 if (strncmp (opt->name, str, optlen) == 0) 20301 { 20302 mcpu_cpu_opt = &opt->value; 20303 mcpu_fpu_opt = &opt->default_fpu; 20304 if (opt->canonical_name) 20305 strcpy(selected_cpu_name, opt->canonical_name); 20306 else 20307 { 20308 int i; 20309 for (i = 0; i < optlen; i++) 20310 selected_cpu_name[i] = TOUPPER (opt->name[i]); 20311 selected_cpu_name[i] = 0; 20312 } 20313 20314 if (ext != NULL) 20315 return arm_parse_extension (ext, &mcpu_cpu_opt); 20316 20317 return 1; 20318 } 20319 20320 as_bad (_("unknown cpu `%s'"), str); 20321 return 0; 20322} 20323 20324static int 20325arm_parse_arch (char * str) 20326{ 20327 const struct arm_arch_option_table *opt; 20328 char *ext = strchr (str, '+'); 20329 int optlen; 20330 20331 if (ext != NULL) 20332 optlen = ext - str; 20333 else 20334 optlen = strlen (str); 20335 20336 if (optlen == 0) 20337 { 20338 as_bad (_("missing architecture name `%s'"), str); 20339 return 0; 20340 } 20341 20342 for (opt = arm_archs; opt->name != NULL; opt++) 20343 if (strncmp (opt->name, str, optlen) == 0) 20344 { 20345 march_cpu_opt = &opt->value; 20346 march_fpu_opt = &opt->default_fpu; 20347 strcpy(selected_cpu_name, opt->name); 20348 20349 if (ext != NULL) 20350 return arm_parse_extension (ext, &march_cpu_opt); 20351 20352 return 1; 20353 } 20354 20355 as_bad (_("unknown architecture `%s'\n"), str); 20356 return 0; 20357} 20358 20359static int 20360arm_parse_fpu (char * str) 20361{ 20362 const struct arm_option_cpu_value_table * opt; 20363 20364 for (opt = arm_fpus; opt->name != NULL; opt++) 20365 if (streq (opt->name, str)) 20366 { 20367 mfpu_opt = &opt->value; 20368 return 1; 20369 } 20370 20371 as_bad (_("unknown floating point format `%s'\n"), str); 20372 return 0; 20373} 20374 20375static int 20376arm_parse_float_abi (char * str) 20377{ 20378 const struct arm_option_value_table * opt; 20379 20380 for (opt = arm_float_abis; opt->name != NULL; opt++) 20381 if (streq (opt->name, str)) 20382 { 20383 mfloat_abi_opt = opt->value; 20384 return 1; 20385 } 20386 20387 as_bad (_("unknown floating point abi `%s'\n"), str); 20388 return 0; 20389} 20390 20391#ifdef OBJ_ELF 20392static int 20393arm_parse_eabi (char * str) 20394{ 20395 const struct arm_option_value_table *opt; 20396 20397 for (opt = arm_eabis; opt->name != NULL; opt++) 20398 if (streq (opt->name, str)) 20399 { 20400 meabi_flags = opt->value; 20401 return 1; 20402 } 20403 as_bad (_("unknown EABI `%s'\n"), str); 20404 return 0; 20405} 20406#endif 20407 20408struct arm_long_option_table arm_long_opts[] = 20409{ 20410 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), 20411 arm_parse_cpu, NULL}, 20412 {"march=", N_("<arch name>\t assemble for architecture <arch name>"), 20413 arm_parse_arch, NULL}, 20414 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), 20415 arm_parse_fpu, NULL}, 20416 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), 20417 arm_parse_float_abi, NULL}, 20418#ifdef OBJ_ELF 20419 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"), 20420 arm_parse_eabi, NULL}, 20421#endif 20422 {NULL, NULL, 0, NULL} 20423}; 20424 20425int 20426md_parse_option (int c, char * arg) 20427{ 20428 struct arm_option_table *opt; 20429 const struct arm_legacy_option_table *fopt; 20430 struct arm_long_option_table *lopt; 20431 20432 switch (c) 20433 { 20434#ifdef OPTION_EB 20435 case OPTION_EB: 20436 target_big_endian = 1; 20437 break; 20438#endif 20439 20440#ifdef OPTION_EL 20441 case OPTION_EL: 20442 target_big_endian = 0; 20443 break; 20444#endif 20445 20446 case 'a': 20447 /* Listing option. Just ignore these, we don't support additional 20448 ones. */ 20449 return 0; 20450 20451 default: 20452 for (opt = arm_opts; opt->option != NULL; opt++) 20453 { 20454 if (c == opt->option[0] 20455 && ((arg == NULL && opt->option[1] == 0) 20456 || streq (arg, opt->option + 1))) 20457 { 20458#if WARN_DEPRECATED 20459 /* If the option is deprecated, tell the user. */ 20460 if (opt->deprecated != NULL) 20461 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, 20462 arg ? arg : "", _(opt->deprecated)); 20463#endif 20464 20465 if (opt->var != NULL) 20466 *opt->var = opt->value; 20467 20468 return 1; 20469 } 20470 } 20471 20472 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) 20473 { 20474 if (c == fopt->option[0] 20475 && ((arg == NULL && fopt->option[1] == 0) 20476 || streq (arg, fopt->option + 1))) 20477 { 20478#if WARN_DEPRECATED 20479 /* If the option is deprecated, tell the user. */ 20480 if (fopt->deprecated != NULL) 20481 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, 20482 arg ? arg : "", _(fopt->deprecated)); 20483#endif 20484 20485 if (fopt->var != NULL) 20486 *fopt->var = &fopt->value; 20487 20488 return 1; 20489 } 20490 } 20491 20492 for (lopt = arm_long_opts; lopt->option != NULL; lopt++) 20493 { 20494 /* These options are expected to have an argument. */ 20495 if (c == lopt->option[0] 20496 && arg != NULL 20497 && strncmp (arg, lopt->option + 1, 20498 strlen (lopt->option + 1)) == 0) 20499 { 20500#if WARN_DEPRECATED 20501 /* If the option is deprecated, tell the user. */ 20502 if (lopt->deprecated != NULL) 20503 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, 20504 _(lopt->deprecated)); 20505#endif 20506 20507 /* Call the sup-option parser. */ 20508 return lopt->func (arg + strlen (lopt->option) - 1); 20509 } 20510 } 20511 20512 return 0; 20513 } 20514 20515 return 1; 20516} 20517 20518void 20519md_show_usage (FILE * fp) 20520{ 20521 struct arm_option_table *opt; 20522 struct arm_long_option_table *lopt; 20523 20524 fprintf (fp, _(" ARM-specific assembler options:\n")); 20525 20526 for (opt = arm_opts; opt->option != NULL; opt++) 20527 if (opt->help != NULL) 20528 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); 20529 20530 for (lopt = arm_long_opts; lopt->option != NULL; lopt++) 20531 if (lopt->help != NULL) 20532 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); 20533 20534#ifdef OPTION_EB 20535 fprintf (fp, _("\ 20536 -EB assemble code for a big-endian cpu\n")); 20537#endif 20538 20539#ifdef OPTION_EL 20540 fprintf (fp, _("\ 20541 -EL assemble code for a little-endian cpu\n")); 20542#endif 20543} 20544 20545 20546#ifdef OBJ_ELF 20547typedef struct 20548{ 20549 int val; 20550 arm_feature_set flags; 20551} cpu_arch_ver_table; 20552 20553/* Mapping from CPU features to EABI CPU arch values. Table must be sorted 20554 least features first. */ 20555static const cpu_arch_ver_table cpu_arch_ver[] = 20556{ 20557 {1, ARM_ARCH_V4}, 20558 {2, ARM_ARCH_V4T}, 20559 {3, ARM_ARCH_V5}, 20560 {4, ARM_ARCH_V5TE}, 20561 {5, ARM_ARCH_V5TEJ}, 20562 {6, ARM_ARCH_V6}, 20563 {7, ARM_ARCH_V6Z}, 20564 {8, ARM_ARCH_V6K}, 20565 {9, ARM_ARCH_V6T2}, 20566 {10, ARM_ARCH_V7A}, 20567 {10, ARM_ARCH_V7R}, 20568 {10, ARM_ARCH_V7M}, 20569 {0, ARM_ARCH_NONE} 20570}; 20571 20572/* Set the public EABI object attributes. */ 20573static void 20574aeabi_set_public_attributes (void) 20575{ 20576 int arch; 20577 arm_feature_set flags; 20578 arm_feature_set tmp; 20579 const cpu_arch_ver_table *p; 20580 20581 /* Choose the architecture based on the capabilities of the requested cpu 20582 (if any) and/or the instructions actually used. */ 20583 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); 20584 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); 20585 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); 20586 /*Allow the user to override the reported architecture. */ 20587 if (object_arch) 20588 { 20589 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); 20590 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); 20591 } 20592 20593 tmp = flags; 20594 arch = 0; 20595 for (p = cpu_arch_ver; p->val; p++) 20596 { 20597 if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) 20598 { 20599 arch = p->val; 20600 ARM_CLEAR_FEATURE (tmp, tmp, p->flags); 20601 } 20602 } 20603 20604 /* Tag_CPU_name. */ 20605 if (selected_cpu_name[0]) 20606 { 20607 char *p; 20608 20609 p = selected_cpu_name; 20610 if (strncmp(p, "armv", 4) == 0) 20611 { 20612 int i; 20613 20614 p += 4; 20615 for (i = 0; p[i]; i++) 20616 p[i] = TOUPPER (p[i]); 20617 } 20618 bfd_elf_add_proc_attr_string (stdoutput, 5, p); 20619 } 20620 /* Tag_CPU_arch. */ 20621 bfd_elf_add_proc_attr_int (stdoutput, 6, arch); 20622 /* Tag_CPU_arch_profile. */ 20623 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) 20624 bfd_elf_add_proc_attr_int (stdoutput, 7, 'A'); 20625 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) 20626 bfd_elf_add_proc_attr_int (stdoutput, 7, 'R'); 20627 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)) 20628 bfd_elf_add_proc_attr_int (stdoutput, 7, 'M'); 20629 /* Tag_ARM_ISA_use. */ 20630 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full)) 20631 bfd_elf_add_proc_attr_int (stdoutput, 8, 1); 20632 /* Tag_THUMB_ISA_use. */ 20633 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full)) 20634 bfd_elf_add_proc_attr_int (stdoutput, 9, 20635 ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1); 20636 /* Tag_VFP_arch. */ 20637 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v3) 20638 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v3)) 20639 bfd_elf_add_proc_attr_int (stdoutput, 10, 3); 20640 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v2) 20641 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v2)) 20642 bfd_elf_add_proc_attr_int (stdoutput, 10, 2); 20643 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1) 20644 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1) 20645 || ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1xd) 20646 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1xd)) 20647 bfd_elf_add_proc_attr_int (stdoutput, 10, 1); 20648 /* Tag_WMMX_arch. */ 20649 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt) 20650 || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt)) 20651 bfd_elf_add_proc_attr_int (stdoutput, 11, 1); 20652 /* Tag_NEON_arch. */ 20653 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_neon_ext_v1) 20654 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_neon_ext_v1)) 20655 bfd_elf_add_proc_attr_int (stdoutput, 12, 1); 20656} 20657 20658/* Add the default contents for the .ARM.attributes section. */ 20659void 20660arm_md_end (void) 20661{ 20662 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) 20663 return; 20664 20665 aeabi_set_public_attributes (); 20666} 20667#endif /* OBJ_ELF */ 20668 20669 20670/* Parse a .cpu directive. */ 20671 20672static void 20673s_arm_cpu (int ignored ATTRIBUTE_UNUSED) 20674{ 20675 const struct arm_cpu_option_table *opt; 20676 char *name; 20677 char saved_char; 20678 20679 name = input_line_pointer; 20680 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20681 input_line_pointer++; 20682 saved_char = *input_line_pointer; 20683 *input_line_pointer = 0; 20684 20685 /* Skip the first "all" entry. */ 20686 for (opt = arm_cpus + 1; opt->name != NULL; opt++) 20687 if (streq (opt->name, name)) 20688 { 20689 mcpu_cpu_opt = &opt->value; 20690 selected_cpu = opt->value; 20691 if (opt->canonical_name) 20692 strcpy(selected_cpu_name, opt->canonical_name); 20693 else 20694 { 20695 int i; 20696 for (i = 0; opt->name[i]; i++) 20697 selected_cpu_name[i] = TOUPPER (opt->name[i]); 20698 selected_cpu_name[i] = 0; 20699 } 20700 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 20701 *input_line_pointer = saved_char; 20702 demand_empty_rest_of_line (); 20703 return; 20704 } 20705 as_bad (_("unknown cpu `%s'"), name); 20706 *input_line_pointer = saved_char; 20707 ignore_rest_of_line (); 20708} 20709 20710 20711/* Parse a .arch directive. */ 20712 20713static void 20714s_arm_arch (int ignored ATTRIBUTE_UNUSED) 20715{ 20716 const struct arm_arch_option_table *opt; 20717 char saved_char; 20718 char *name; 20719 20720 name = input_line_pointer; 20721 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20722 input_line_pointer++; 20723 saved_char = *input_line_pointer; 20724 *input_line_pointer = 0; 20725 20726 /* Skip the first "all" entry. */ 20727 for (opt = arm_archs + 1; opt->name != NULL; opt++) 20728 if (streq (opt->name, name)) 20729 { 20730 mcpu_cpu_opt = &opt->value; 20731 selected_cpu = opt->value; 20732 strcpy(selected_cpu_name, opt->name); 20733 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 20734 *input_line_pointer = saved_char; 20735 demand_empty_rest_of_line (); 20736 return; 20737 } 20738 20739 as_bad (_("unknown architecture `%s'\n"), name); 20740 *input_line_pointer = saved_char; 20741 ignore_rest_of_line (); 20742} 20743 20744/* Parse a .arch_extension directive. */ 20745 20746static void 20747s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED) 20748{ 20749 const struct arm_option_cpu_value_table *opt; 20750 char saved_char; 20751 char *name; 20752 20753 name = input_line_pointer; 20754 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20755 input_line_pointer++; 20756 saved_char = *input_line_pointer; 20757 *input_line_pointer = 0; 20758 20759 for (opt = arm_extensions; opt->name != NULL; opt++) 20760 if (streq (opt->name, name)) 20761 { 20762 ARM_MERGE_FEATURE_SETS (cpu_variant, cpu_variant, opt->value); 20763 *input_line_pointer = saved_char; 20764 demand_empty_rest_of_line (); 20765 return; 20766 } 20767 20768 as_bad (_("unknown architecture `%s'\n"), name); 20769 *input_line_pointer = saved_char; 20770 ignore_rest_of_line (); 20771} 20772 20773/* Parse a .object_arch directive. */ 20774 20775static void 20776s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) 20777{ 20778 const struct arm_arch_option_table *opt; 20779 char saved_char; 20780 char *name; 20781 20782 name = input_line_pointer; 20783 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20784 input_line_pointer++; 20785 saved_char = *input_line_pointer; 20786 *input_line_pointer = 0; 20787 20788 /* Skip the first "all" entry. */ 20789 for (opt = arm_archs + 1; opt->name != NULL; opt++) 20790 if (streq (opt->name, name)) 20791 { 20792 object_arch = &opt->value; 20793 *input_line_pointer = saved_char; 20794 demand_empty_rest_of_line (); 20795 return; 20796 } 20797 20798 as_bad (_("unknown architecture `%s'\n"), name); 20799 *input_line_pointer = saved_char; 20800 ignore_rest_of_line (); 20801} 20802 20803 20804/* Parse a .fpu directive. */ 20805 20806static void 20807s_arm_fpu (int ignored ATTRIBUTE_UNUSED) 20808{ 20809 const struct arm_option_cpu_value_table *opt; 20810 char saved_char; 20811 char *name; 20812 20813 name = input_line_pointer; 20814 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20815 input_line_pointer++; 20816 saved_char = *input_line_pointer; 20817 *input_line_pointer = 0; 20818 20819 for (opt = arm_fpus; opt->name != NULL; opt++) 20820 if (streq (opt->name, name)) 20821 { 20822 mfpu_opt = &opt->value; 20823 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 20824 *input_line_pointer = saved_char; 20825 demand_empty_rest_of_line (); 20826 return; 20827 } 20828 20829 as_bad (_("unknown floating point format `%s'\n"), name); 20830 *input_line_pointer = saved_char; 20831 ignore_rest_of_line (); 20832} 20833 20834/* Copy symbol information. */ 20835void 20836arm_copy_symbol_attributes (symbolS *dest, symbolS *src) 20837{ 20838 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); 20839} 20840