1/*
2 * Copyright (c) 1997 Zubin D. Dittia.  All rights reserved.
3 * Copyright (c) 1995, 1996, 1998
4 *	Christopher G. Demetriou.  All rights reserved.
5 * Copyright (c) 1994 Charles M. Hannum.  All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 *    must display the following acknowledgement:
17 *	This product includes software developed by Charles M. Hannum.
18 * 4. The name of the author may not be used to endorse or promote products
19 *    derived from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/*
34 * PCI autoconfiguration support functions.
35 */
36
37#include "cfe.h"
38
39#ifndef CFG_PCI_VERBOSE
40# if (CFG_PCIDEVICE || CFG_MINIMAL_SIZE)
41#  define CFG_PCI_VERBOSE 0
42# else
43#  define CFG_PCI_VERBOSE 1
44# endif
45#endif
46
47#include "pcireg.h"
48#include "pcivar.h"
49#include "pci_internal.h"
50
51const char *pci_findvendor(pcireg_t id_reg);
52
53static void pci_conf_print_ids(pcireg_t rval, const char *prefix);
54static int pci_conf_print_bar (pcitag_t,
55    const pcireg_t *, int, const char *, int, int);
56
57/*
58 * Descriptions of known PCI classes and subclasses.
59 *
60 * Subclasses are described in the same way as classes, but have a
61 * NULL subclass pointer.
62 */
63struct pci_class {
64    char	*name;
65    int		val;		/* as wide as pci_{,sub}class_t */
66    struct pci_class *subclasses;
67};
68
69struct pci_class pci_subclass_prehistoric[] = {
70    { "miscellaneous",	PCI_SUBCLASS_PREHISTORIC_MISC,		},
71    { "VGA",		PCI_SUBCLASS_PREHISTORIC_VGA,		},
72    { 0 }
73};
74
75struct pci_class pci_subclass_mass_storage[] = {
76    { "SCSI",		PCI_SUBCLASS_MASS_STORAGE_SCSI,		},
77    { "IDE",		PCI_SUBCLASS_MASS_STORAGE_IDE,		},
78    { "floppy",		PCI_SUBCLASS_MASS_STORAGE_FLOPPY,	},
79    { "IPI",		PCI_SUBCLASS_MASS_STORAGE_IPI,		},
80    { "RAID",		PCI_SUBCLASS_MASS_STORAGE_RAID,		},
81    { "miscellaneous",	PCI_SUBCLASS_MASS_STORAGE_MISC,		},
82    { 0 },
83};
84
85struct pci_class pci_subclass_network[] = {
86    { "ethernet",	PCI_SUBCLASS_NETWORK_ETHERNET,		},
87    { "token ring",	PCI_SUBCLASS_NETWORK_TOKENRING,		},
88    { "FDDI",		PCI_SUBCLASS_NETWORK_FDDI,		},
89    { "ATM",		PCI_SUBCLASS_NETWORK_ATM,		},
90    { "ISDN",		PCI_SUBCLASS_NETWORK_ISDN,		},
91    { "WorldFip",	PCI_SUBCLASS_NETWORK_WORLDFIP,		},
92    { "PCMIG MultiComp", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP,	},
93    { "miscellaneous",	PCI_SUBCLASS_NETWORK_MISC,		},
94    { 0 },
95};
96
97struct pci_class pci_subclass_display[] = {
98    { "VGA",		PCI_SUBCLASS_DISPLAY_VGA,		},
99    { "XGA",		PCI_SUBCLASS_DISPLAY_XGA,		},
100    { "3D",		PCI_SUBCLASS_DISPLAY_3D,		},
101    { "miscellaneous",	PCI_SUBCLASS_DISPLAY_MISC,		},
102    { 0 },
103};
104
105struct pci_class pci_subclass_multimedia[] = {
106    { "video",		PCI_SUBCLASS_MULTIMEDIA_VIDEO,		},
107    { "audio",		PCI_SUBCLASS_MULTIMEDIA_AUDIO,		},
108    { "telephony",	PCI_SUBCLASS_MULTIMEDIA_TELEPHONY,	},
109    { "miscellaneous",	PCI_SUBCLASS_MULTIMEDIA_MISC,		},
110    { 0 },
111};
112
113struct pci_class pci_subclass_memory[] = {
114    { "RAM",		PCI_SUBCLASS_MEMORY_RAM,		},
115    { "flash",		PCI_SUBCLASS_MEMORY_FLASH,		},
116    { "miscellaneous",	PCI_SUBCLASS_MEMORY_MISC,		},
117    { 0 },
118};
119
120struct pci_class pci_subclass_bridge[] = {
121    { "host",		PCI_SUBCLASS_BRIDGE_HOST,		},
122    { "ISA",		PCI_SUBCLASS_BRIDGE_ISA,		},
123    { "EISA",		PCI_SUBCLASS_BRIDGE_EISA,		},
124    { "MicroChannel",	PCI_SUBCLASS_BRIDGE_MCA,		},
125    { "PCI",		PCI_SUBCLASS_BRIDGE_PCI,		},
126    { "PCMCIA",		PCI_SUBCLASS_BRIDGE_PCMCIA,		},
127    { "NuBus",		PCI_SUBCLASS_BRIDGE_NUBUS,		},
128    { "CardBus",	PCI_SUBCLASS_BRIDGE_CARDBUS,		},
129    { "RACEway",	PCI_SUBCLASS_BRIDGE_RACEWAY,		},
130    { "Semi-transparent PCI",	PCI_SUBCLASS_BRIDGE_STPCI,	},
131    { "InfiniBand",	PCI_SUBCLASS_BRIDGE_INFINIBAND,		},
132    { "miscellaneous",	PCI_SUBCLASS_BRIDGE_MISC,		},
133    { 0 },
134};
135
136struct pci_class pci_subclass_communications[] = {
137    { "serial",		PCI_SUBCLASS_COMMUNICATIONS_SERIAL,	},
138    { "parallel",	PCI_SUBCLASS_COMMUNICATIONS_PARALLEL,	},
139    { "multi-port serial",	PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL,	},
140    { "modem",		PCI_SUBCLASS_COMMUNICATIONS_MODEM,	},
141    { "miscellaneous",	PCI_SUBCLASS_COMMUNICATIONS_MISC,	},
142    { 0 },
143};
144
145struct pci_class pci_subclass_system[] = {
146    { "8259 PIC",	PCI_SUBCLASS_SYSTEM_PIC,		},
147    { "8237 DMA",	PCI_SUBCLASS_SYSTEM_DMA,		},
148    { "8254 timer",	PCI_SUBCLASS_SYSTEM_TIMER,		},
149    { "RTC",		PCI_SUBCLASS_SYSTEM_RTC,		},
150    { "PCI Hot-Plug",	PCI_SUBCLASS_SYSTEM_PCIHOTPLUG,		},
151    { "miscellaneous",	PCI_SUBCLASS_SYSTEM_MISC,		},
152    { 0 },
153};
154
155struct pci_class pci_subclass_input[] = {
156    { "keyboard",	PCI_SUBCLASS_INPUT_KEYBOARD,		},
157    { "digitizer",	PCI_SUBCLASS_INPUT_DIGITIZER,		},
158    { "mouse",		PCI_SUBCLASS_INPUT_MOUSE,		},
159    { "scanner",	PCI_SUBCLASS_INPUT_SCANNER,		},
160    { "game port",	PCI_SUBCLASS_INPUT_GAMEPORT,		},
161    { "miscellaneous",	PCI_SUBCLASS_INPUT_MISC,		},
162    { 0 },
163};
164
165struct pci_class pci_subclass_dock[] = {
166    { "generic",	PCI_SUBCLASS_DOCK_GENERIC,		},
167    { "miscellaneous",	PCI_SUBCLASS_DOCK_MISC,			},
168    { 0 },
169};
170
171struct pci_class pci_subclass_processor[] = {
172    { "386",		PCI_SUBCLASS_PROCESSOR_386,		},
173    { "486",		PCI_SUBCLASS_PROCESSOR_486,		},
174    { "Pentium",	PCI_SUBCLASS_PROCESSOR_PENTIUM,		},
175    { "Alpha",		PCI_SUBCLASS_PROCESSOR_ALPHA,		},
176    { "PowerPC",	PCI_SUBCLASS_PROCESSOR_POWERPC,		},
177    { "MIPS",		PCI_SUBCLASS_PROCESSOR_MIPS,		},
178    { "Co-processor",	PCI_SUBCLASS_PROCESSOR_COPROC,		},
179    { 0 },
180};
181
182struct pci_class pci_subclass_serialbus[] = {
183    { "Firewire",	PCI_SUBCLASS_SERIALBUS_FIREWIRE,	},
184    { "ACCESS.bus",	PCI_SUBCLASS_SERIALBUS_ACCESS,		},
185    { "SSA",		PCI_SUBCLASS_SERIALBUS_SSA,		},
186    { "USB",		PCI_SUBCLASS_SERIALBUS_USB,		},
187    /* XXX Fiber Channel/_FIBRECHANNEL */
188    { "Fiber Channel",	PCI_SUBCLASS_SERIALBUS_FIBER,		},
189    { "SMBus",		PCI_SUBCLASS_SERIALBUS_SMBUS,		},
190    { "InfiniBand",	PCI_SUBCLASS_SERIALBUS_INFINIBAND,	},
191    { "IPMI",		PCI_SUBCLASS_SERIALBUS_IPMI,		},
192    { "SERCOS",		PCI_SUBCLASS_SERIALBUS_SERCOS,		},
193    { "CANbus",		PCI_SUBCLASS_SERIALBUS_CANBUS,		},
194    { 0 },
195};
196
197struct pci_class pci_subclass_wireless[] = {
198    { "iRDA",		PCI_SUBCLASS_WIRELESS_IRDA,		},
199    { "Consumer IR",	PCI_SUBCLASS_WIRELESS_CONSUMERIR,	},
200    { "RF",		PCI_SUBCLASS_WIRELESS_RF,		},
201    { "miscellaneous",	PCI_SUBCLASS_WIRELESS_MISC,		},
202    { 0 },
203};
204
205struct pci_class pci_subclass_i2o[] = {
206    { "1.0",		PCI_SUBCLASS_I2O_STANDARD,		},
207    { 0 },
208};
209
210struct pci_class pci_subclass_satcom[] = {
211    { "TV",		PCI_SUBCLASS_SATCOM_TV,			},
212    { "audio",		PCI_SUBCLASS_SATCOM_AUDIO,		},
213    { "voice",		PCI_SUBCLASS_SATCOM_VOICE,		},
214    { "data",		PCI_SUBCLASS_SATCOM_DATA,		},
215    { 0 },
216};
217
218struct pci_class pci_subclass_crypto[] = {
219    { "network/computing",	PCI_SUBCLASS_CRYPTO_NETCOMP,	},
220    { "entertainment",	PCI_SUBCLASS_CRYPTO_ENTERTAINMENT,	},
221    { "miscellaneous",	PCI_SUBCLASS_CRYPTO_MISC,		},
222    { 0 },
223};
224
225struct pci_class pci_subclass_dasp[] = {
226    { "DPIO",		PCI_SUBCLASS_DASP_DPIO,			},
227    { "time and frequency",	PCI_SUBCLASS_DASP_TIMERFREQ,	},
228    { "miscellaneous",	PCI_SUBCLASS_DASP_MISC,			},
229    { 0 },
230};
231
232struct pci_class pci_class[] = {
233    { "prehistoric",	PCI_CLASS_PREHISTORIC,
234        pci_subclass_prehistoric,			},
235    { "mass storage",	PCI_CLASS_MASS_STORAGE,
236        pci_subclass_mass_storage,			},
237    { "network",	PCI_CLASS_NETWORK,
238        pci_subclass_network,				},
239    { "display",	PCI_CLASS_DISPLAY,
240        pci_subclass_display,				},
241    { "multimedia",	PCI_CLASS_MULTIMEDIA,
242        pci_subclass_multimedia,			},
243    { "memory",		PCI_CLASS_MEMORY,
244        pci_subclass_memory,				},
245    { "bridge",		PCI_CLASS_BRIDGE,
246        pci_subclass_bridge,				},
247    { "communications",	PCI_CLASS_COMMUNICATIONS,
248        pci_subclass_communications,			},
249    { "system",		PCI_CLASS_SYSTEM,
250        pci_subclass_system,				},
251    { "input",		PCI_CLASS_INPUT,
252        pci_subclass_input,				},
253    { "dock",		PCI_CLASS_DOCK,
254        pci_subclass_dock,				},
255    { "processor",	PCI_CLASS_PROCESSOR,
256        pci_subclass_processor,				},
257    { "serial bus",	PCI_CLASS_SERIALBUS,
258        pci_subclass_serialbus,				},
259    { "wireless",	PCI_CLASS_WIRELESS,
260        pci_subclass_wireless,				},
261    { "I2O",		PCI_CLASS_I2O,
262        pci_subclass_i2o,				},
263    { "satellite comm",	PCI_CLASS_SATCOM,
264        pci_subclass_satcom,				},
265    { "crypto",		PCI_CLASS_CRYPTO,
266        pci_subclass_crypto,				},
267    { "DASP",		PCI_CLASS_DASP,
268        pci_subclass_dasp,				},
269    { "undefined",	PCI_CLASS_UNDEFINED,
270        0,						},
271    { 0 },
272};
273
274#if CFG_PCI_VERBOSE
275/*
276 * Descriptions of of known vendors and devices ("products").
277 */
278#include "pcidevs.h"
279#include "pcidevs_data2.h"
280
281const char *
282pci_findvendor(pcireg_t id_reg)
283{
284    pci_vendor_id_t vendor = PCI_VENDOR(id_reg);
285    const struct pci_knowndev2 *kdp;
286
287    kdp = pci_knowndevs;
288    while (kdp->vendorname != PCI_STRING_NULL) {  /* all have vendor name */
289        if (kdp->vendor == vendor)
290            break;
291        kdp++;
292    }
293    if (kdp->vendorname == PCI_STRING_NULL) return NULL;
294    return PCI_STRING(kdp->vendorname);
295}
296#else
297const char *
298pci_findvendor(pcireg_t id_reg)
299{
300    return NULL;
301}
302#endif /* CFG_PCI_VERBOSE */
303
304void
305pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp)
306{
307    pci_vendor_id_t vendor;
308    pci_product_id_t product;
309    pci_class_t class;
310    pci_subclass_t subclass;
311    pci_interface_t interface;
312    pci_revision_t revision;
313    const char *vendor_namep, *product_namep;
314    struct pci_class *classp, *subclassp;
315#if CFG_PCI_VERBOSE
316    const struct pci_knowndev2 *kdp;
317    const char *unmatched = "unknown ";
318#else
319    const char *unmatched = "";
320#endif
321
322    vendor = PCI_VENDOR(id_reg);
323    product = PCI_PRODUCT(id_reg);
324
325    class = PCI_CLASS(class_reg);
326    subclass = PCI_SUBCLASS(class_reg);
327    interface = PCI_INTERFACE(class_reg);
328    revision = PCI_REVISION(class_reg);
329
330#if CFG_PCI_VERBOSE
331    kdp = pci_knowndevs;
332    while (kdp->vendorname != PCI_STRING_NULL) {  /* all have vendor name */
333        if (kdp->vendor == vendor &&
334	    (kdp->product == product || kdp->productname == PCI_STRING_NULL))
335            break;
336        kdp++;
337    }
338    if (kdp->vendorname == PCI_STRING_NULL)
339        vendor_namep = product_namep = NULL;
340    else {
341        vendor_namep = PCI_STRING(kdp->vendorname);
342        product_namep = (kdp->productname == PCI_STRING_NULL) ?
343			 NULL : PCI_STRING(kdp->productname);
344    }
345#else /* CFG_PCI_VERBOSE */
346    vendor_namep = product_namep = NULL;
347#endif /* CFG_PCI_VERBOSE */
348
349    classp = pci_class;
350    while (classp->name != NULL) {
351        if (class == classp->val)
352            break;
353        classp++;
354    }
355
356    subclassp = (classp->name != NULL) ? classp->subclasses : NULL;
357    while (subclassp && subclassp->name != NULL) {
358        if (subclass == subclassp->val)
359            break;
360        subclassp++;
361    }
362
363    if (vendor_namep == NULL)
364        cp += sprintf(cp, "%svendor 0x%04x product 0x%04x",
365		      unmatched, vendor, product);
366    else if (product_namep != NULL)
367        cp += sprintf(cp, "%s %s", vendor_namep, product_namep);
368    else
369        cp += sprintf(cp, "%s product 0x%04x", vendor_namep, product);
370    if (showclass) {
371        cp += sprintf(cp, " (");
372        if (classp->name == NULL)
373            cp += sprintf(cp, "class 0x%02x, subclass 0x%02x",
374			  class, subclass);
375        else {
376            if (subclassp == NULL || subclassp->name == NULL)
377                cp += sprintf(cp, "%s subclass 0x%02x",
378			      classp->name, subclass);
379            else
380                cp += sprintf(cp, "%s %s", subclassp->name, classp->name);
381        }
382        if (interface != 0)
383            cp += sprintf(cp, ", interface 0x%02x", interface);
384        if (revision != 0)
385            cp += sprintf(cp, ", rev 0x%02x", revision);
386        cp += sprintf(cp, ")");
387    }
388}
389
390
391/*
392 * Support routines for printing out PCI configuration registers.
393 */
394
395#define	i2o(i)	((i) * 4)
396#define	o2i(o)	((o) / 4)
397#define	onoff(str, bit)							\
398    do {								\
399        printf("      %s: %s\n", (str), (rval & (bit)) ? "on" : "off");	\
400    } while (0)
401
402#if CFG_PCI_VERBOSE
403static void
404pci_conf_print_ids(pcireg_t rval, const char *prefix)
405{
406    const struct pci_knowndev2 *kdp;
407
408    for (kdp = pci_knowndevs; kdp->vendorname != PCI_STRING_NULL; kdp++) {
409        if (kdp->vendor == PCI_VENDOR(rval) &&
410            (kdp->product == PCI_PRODUCT(rval) ||
411             kdp->productname == PCI_STRING_NULL)) {
412            break;
413        }
414    }
415    if (kdp->vendorname != PCI_STRING_NULL)
416        printf("%sVendor Name: %s (0x%04x)\n", prefix,
417	       PCI_STRING(kdp->vendorname), PCI_VENDOR(rval));
418    else
419        printf("%sVendor ID: 0x%04x\n", prefix, PCI_VENDOR(rval));
420    if (kdp->productname != PCI_STRING_NULL
421	&& kdp->productname != PCI_STRING_NULL)
422        printf("%sDevice Name: %s (0x%04x)\n", prefix,
423	       PCI_STRING(kdp->productname), PCI_PRODUCT(rval));
424    else
425        printf("%sDevice ID: 0x%04x\n", prefix, PCI_PRODUCT(rval));
426}
427#else
428static void
429pci_conf_print_ids(pcireg_t rval, const char *prefix)
430{
431    printf("%sVendor ID: 0x%04x\n", prefix, PCI_VENDOR(rval));
432    printf("%sDevice ID: 0x%04x\n", prefix, PCI_PRODUCT(rval));
433}
434#endif /* CFG_PCI_VERBOSE */
435
436static int
437pci_conf_print_bar(
438    pcitag_t tag, const pcireg_t *regs,
439    int reg, const char *name,
440    int sizebar, int onlyimpl)
441{
442    int width;
443    pcireg_t mask, rval;
444    pcireg_t mask64h, rval64h;
445
446#ifdef __GNUC__			/* XXX GCC -Wuninitialized inadequacies */
447    mask64h = rval64h = 0;
448#endif
449
450    width = 4;
451
452    /*
453     * Section 6.2.5.1, `Address Maps', tells us that:
454     *
455     * 1) The builtin software should have already mapped the
456     * device in a reasonable way.
457     *
458     * 2) A device which wants 2^n bytes of memory will hardwire
459     * the bottom n bits of the address to 0.  As recommended,
460     * we write all 1s and see what we get back.
461     */
462    rval = regs[o2i(reg)];
463    /* XXX don't size unknown memory type? */
464    if (rval != 0 && sizebar) {
465        uint32_t cmdreg;
466
467        /*
468         * The following sequence seems to make some devices
469         * (e.g. host bus bridges, which don't normally
470         * have their space mapped) very unhappy, to
471         * the point of crashing the system.
472         *
473         * Therefore, if the mapping register is zero to
474         * start out with, don't bother trying.
475         */
476
477        cmdreg = pci_conf_read(tag, PCI_COMMAND_STATUS_REG);
478	cmdreg &= (PCI_COMMAND_MASK << PCI_COMMAND_SHIFT);  /* keep status */
479        pci_conf_write(tag, PCI_COMMAND_STATUS_REG,
480            cmdreg & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE));
481
482        pci_conf_write(tag, reg, 0xffffffff);
483        mask = pci_conf_read(tag, reg);
484        pci_conf_write(tag, reg, rval);
485        if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM &&
486            PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) {
487            rval64h = regs[o2i(reg + 4)];
488            pci_conf_write(tag, reg + 4, 0xffffffff);
489            mask64h = pci_conf_read(tag, reg + 4);
490            pci_conf_write(tag, reg + 4, rval64h);
491            width = 8;
492        }
493
494        pci_conf_write(tag, PCI_COMMAND_STATUS_REG, cmdreg);
495    } else
496        mask = 0;
497
498    if (rval == 0 && onlyimpl)
499	return width;
500
501    printf("    Base Address Register at 0x%02x", reg);
502    if (name)
503        printf(" (%s)", name);
504    printf("\n      ");
505    if (rval == 0) {
506        printf("not implemented(?)\n");
507        return width;
508    }
509    printf("type: ");
510    if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) {
511        const char *type, *prefetch;
512
513        switch (PCI_MAPREG_MEM_TYPE(rval)) {
514        case PCI_MAPREG_MEM_TYPE_32BIT:
515            type = "32-bit";
516            break;
517        case PCI_MAPREG_MEM_TYPE_32BIT_1M:
518            type = "32-bit-1M";
519            break;
520        case PCI_MAPREG_MEM_TYPE_64BIT:
521            type = "64-bit";
522            break;
523        default:
524            type = "unknown (XXX)";
525            break;
526        }
527        if (PCI_MAPREG_MEM_PREFETCHABLE(rval))
528            prefetch = "";
529        else
530            prefetch = "non";
531        printf("%s %sprefetchable memory\n", type, prefetch);
532        switch (PCI_MAPREG_MEM_TYPE(rval)) {
533        case PCI_MAPREG_MEM_TYPE_64BIT:
534            printf("      base: 0x%016llx, ",
535		   PCI_MAPREG_MEM64_ADDR(
536                       ((((long long) rval64h) << 32) | rval)));
537            if (sizebar)
538                printf("size: 0x%016llx",
539		       PCI_MAPREG_MEM64_SIZE(
540                           ((((long long) mask64h) << 32) | mask)));
541            else
542                printf("not sized");
543            printf("\n");
544            break;
545        case PCI_MAPREG_MEM_TYPE_32BIT:
546        case PCI_MAPREG_MEM_TYPE_32BIT_1M:
547        default:
548            printf("      base: 0x%08x, ", PCI_MAPREG_MEM_ADDR(rval));
549            if (sizebar)
550                printf("size: 0x%08x", PCI_MAPREG_MEM_SIZE(mask));
551            else
552                printf("not sized");
553            printf("\n");
554            break;
555        }
556    } else {
557        if (sizebar)
558            printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16);
559        printf("i/o\n");
560        printf("      base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval));
561        if (sizebar)
562            printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask));
563        else
564            printf("not sized");
565        printf("\n");
566    }
567
568    return width;
569}
570
571
572/* Summary printing: Display device ID, status, memory map only. */
573
574#define on(str, bit)                                                    \
575    do { if (rval & (bit)) printf("    %s: on\n", (str)); } while (0)
576
577void
578pci_conf_print(pcitag_t tag)
579{
580    pcireg_t regs[o2i(256)];
581    int off, width;
582    pcireg_t rval;
583    uint32_t base, limit;
584    int sizebars;
585
586    if (!pci_probe_tag(tag)) {
587        printf("no device\n");
588        return;
589    }
590
591    for (off = 0; off < 256; off += 4)
592        regs[o2i(off)] = pci_conf_read(tag, off);
593
594    rval = regs[o2i(PCI_ID_REG)];
595    pci_conf_print_ids(rval, "  ");
596
597    rval = regs[o2i(PCI_COMMAND_STATUS_REG)];
598
599    printf("  Command: 0x%04x\n", rval & 0xffff);
600    on("I/O space accesses", PCI_COMMAND_IO_ENABLE);
601    on("Memory space accesses", PCI_COMMAND_MEM_ENABLE);
602    on("Bus mastering", PCI_COMMAND_MASTER_ENABLE);
603
604    printf("  Status: 0x%04x\n", PCI_STATUS(rval));
605    on("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT);
606    on("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT);
607    on("Master received Master Abort", PCI_STATUS_MASTER_ABORT);
608    on("Asserted System Error (SERR)", PCI_STATUS_SYSTEM_ERROR);
609    on("Parity error detected", PCI_STATUS_PARITY_DETECT);
610
611    switch (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)])) {
612    case 0:
613        /* Standard device header */
614        printf("  Type 0 (normal) header:\n");
615
616	/* sizing host BARs is often bad news */
617	sizebars = 1;
618	if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE &&
619	    PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST)
620	  sizebars = 0;
621	for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width)
622	  width = pci_conf_print_bar(tag, regs, off, NULL, sizebars, 1);
623
624	rval = regs[o2i(PCI_BPARAM_INTERRUPT_REG)];
625	printf("  Interrupt Line: 0x%02x\n", PCI_INTERRUPT_LINE(rval));
626        break;
627
628    case 1:
629        /* PCI-PCI bridge header */
630        printf("  Type 1 (PCI-PCI bridge) header:\n");
631
632	rval = regs[o2i(PPB_BUSINFO_REG)];
633	printf("    Buses:\n");
634	printf("      Primary: %d,", PPB_BUSINFO_PRIMARY(rval));
635	printf(" Secondary: %d,", PPB_BUSINFO_SECONDARY(rval));
636	printf(" Subordinate: %d\n", PPB_BUSINFO_SUBORD(rval));
637
638	rval = regs[o2i(PPB_IO_STATUS_REG)];
639	printf("    Secondary Status: 0x%04x\n", PPB_SECSTATUS(rval));
640	on("  Data parity error detected", PCI_STATUS_PARITY_ERROR);
641	on("  Signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT);
642	on("  Received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT);
643	on("  Received Master Abort", PCI_STATUS_MASTER_ABORT);
644	on("  System Error", PCI_STATUS_SYSTEM_ERROR);
645	on("  Parity Error", PCI_STATUS_PARITY_DETECT);
646
647	rval = regs[o2i(PPB_IO_STATUS_REG)];
648	base  = PPB_IO_BASE(rval);
649	limit = PPB_IO_LIMIT(rval);
650	if (base != 0 || limit != 0) {
651	    printf("    I/O Range:\n");
652
653	    if ((base & 0xf) != 0 || (limit & 0xf) != 0) {
654		base =  ((base & 0xf0)  << 8) | 0x000;
655		limit = ((limit & 0xf0) << 8) | 0xfff;
656		rval = regs[o2i(PPB_IO_UPPER_REG)];
657		base |= PPB_BASE(rval) << 16;
658	        limit |= PPB_LIMIT(rval) << 16;
659		printf("      base: 0x%08x, limit: 0x%08x\n", base, limit);
660	    } else {
661		base = (base << 8) | 0x000;
662		limit = (limit << 8) | 0xfff;
663		printf("      base: 0x%04x, limit: 0x%04x\n", base, limit);
664	    }
665	}
666
667	base  = PPB_BASE(regs[o2i(PPB_MEM_REG)])  & 0xfff0;
668	limit = PPB_LIMIT(regs[o2i(PPB_MEM_REG)]) & 0xfff0;
669	printf("    Memory Range:\n");
670	base = (base << 16) | 0x00000;
671	limit = (limit << 16) | 0xfffff;
672	printf("      base: 0x%08x, limit: 0x%08x\n", base, limit);
673
674	base  = PPB_BASE(regs[o2i(PPB_PREFMEM_REG)])  & 0xffff;
675	limit = PPB_LIMIT(regs[o2i(PPB_PREFMEM_REG)]) & 0xffff;
676	if (base != 0 || limit != 0
677	    || regs[o2i(PPB_PREFMEM_BASE_UPPER_REG)] != 0
678	    || regs[o2i(PPB_PREFMEM_LIMIT_UPPER_REG)] != 0) {
679	    printf("    Prefetchable Memory Range:\n");
680	    if ((base & 0xf) != 0 || (limit & 0xf) != 0) {
681		base = ((base & 0xfff0) << 16) | 0x00000;
682		limit = ((limit & 0xfff0) << 16) | 0xfffff;
683		printf("      base: 0x%08x%08x, limit: 0x%08x%08x\n",
684		       regs[o2i(PPB_PREFMEM_BASE_UPPER_REG)], base,
685		       regs[o2i(PPB_PREFMEM_LIMIT_UPPER_REG)], limit);
686	    } else {
687		base = (base << 16) | 0x00000;
688		limit = (limit << 16) | 0xfffff;
689		printf("      base: 0x%08x, limit: 0x%08x\n", base, limit);
690	    }
691	}
692
693	if (regs[o2i(PPB_MAPREG_ROM)] != 0)
694	    printf("    Expansion ROM Base Address: 0x%08x\n",
695		   regs[o2i(PPB_MAPREG_ROM)]);
696        break;
697
698    default:
699        break;
700    }
701}
702
703