1/* ********************************************************************* 2 * CFE Generic Board Support Package 3 * 4 * PCI configuration header formats File: pci_cfg.h 5 * 6 * This module contains constants and macros to describe 7 * the standard PCI/PCI-X/HyperTransport configuration header. 8 * PCI specification levels: 9 * PCI Local Bus Specification, Revisions 2.2 and 2.3 10 * PCI-to-PCI Bridge Architecture Specification, Revision 1.1 11 * PCI-X Addendum to the PCI Local Bus Specification, Revision 1.1 12 * HyperTransport I/O Link Specification, Revision 1.05 13 * 14 ********************************************************************* 15 * 16 * Copyright 2000,2001,2002,2003 17 * Broadcom Corporation. All rights reserved. 18 * 19 * This software is furnished under license and may be used and 20 * copied only in accordance with the following terms and 21 * conditions. Subject to these conditions, you may download, 22 * copy, install, use, modify and distribute modified or unmodified 23 * copies of this software in source and/or binary form. No title 24 * or ownership is transferred hereby. 25 * 26 * 1) Any source code used, modified or distributed must reproduce 27 * and retain this copyright notice and list of conditions 28 * as they appear in the source file. 29 * 30 * 2) No right is granted to use any trade name, trademark, or 31 * logo of Broadcom Corporation. The "Broadcom Corporation" 32 * name may not be used to endorse or promote products derived 33 * from this software without the prior written permission of 34 * Broadcom Corporation. 35 * 36 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 37 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 38 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 39 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 40 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 41 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 42 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 43 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 44 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 45 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 46 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 47 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 48 * THE POSSIBILITY OF SUCH DAMAGE. 49 ********************************************************************* */ 50 51 52#ifndef _PCI_CFG_H 53#define _PCI_CFG_H 54 55#if !defined(__ASSEMBLER__) 56#define _MAKE32(x) ((uint32_t)(x)) 57#else 58#define _MAKE32(x) (x) 59#endif 60 61#define _PCI_MAKEMASK1(n) (_MAKE32(1) << _MAKE32(n)) 62 63#define _PCI_MAKEMASK(v,n) (_MAKE32((_MAKE32(1)<<(v))-1) << _MAKE32(n)) 64#define _PCI_MAKEVALUE(v,n) (_MAKE32(v) << _MAKE32(n)) 65#define _PCI_GETVALUE(v,n,m) ((_MAKE32(v) & _MAKE32(m)) >> _MAKE32(n)) 66 67 68/* 69 * The following definitions refer to 32-bit PCI Configuration Space. 70 * Bit-field definitions assume that registers are accessed as 32-bit 71 * words on natural boundaries, even when unrelated functions are 72 * packed into the same 32 bits. 73 */ 74 75/* 76 * PCI Configuration Header Common Registers 77 */ 78 79#define R_PCI_DEVICEID 0x0000 80#define R_PCI_CMDSTATUS 0x0004 81#define R_PCI_CLASSREV 0x0008 82#define R_PCI_DEVHDR 0x000C 83 84/* 85 * PCI Configuration Header, Type 0 (Device) 86 */ 87 88#define R_PCI_BAR0 0x0010 89#define R_PCI_BAR1 0x0014 90#define R_PCI_BAR2 0x0018 91#define R_PCI_BAR3 0x001C 92#define R_PCI_BAR4 0x0020 93#define R_PCI_BAR5 0x0024 94#define R_PCI_CARDBUSCIS 0x0028 95#define R_PCI_SUBSYSID 0x002C 96#define R_PCI_ROMBASE 0x0030 97#define R_PCI_CAPPTR 0x0034 98#define R_PCI_RESERVED1 0x0038 99#define R_PCI_INTGRANT 0x003C 100 101/* 102 * PCI Configuration Header, Type 1 (Bridge) 103 */ 104 105#define R_PPB_BAR0 0x0010 106#define R_PPB_BAR1 0x0014 107#define R_PPB_BUSID 0x0018 108#define R_PPB_SECSTATUS 0x001C 109#define R_PPB_MEM 0x0020 110#define R_PPB_PREFETCH 0x0024 111#define R_PPB_PREFBASE 0x0028 112#define R_PPB_PREFLIMIT 0x002C 113#define R_PPB_IOUPPER 0x0030 114#define R_PPB_CAPPTR 0x0034 115#define R_PPB_ROMBASE 0x0038 116#define R_PPB_BRCTRL 0x003C 117 118/* 119 * PCI Device ID register 120 */ 121 122#define S_PCI_DEVICE_VENDORID 0 123#define M_PCI_DEVICE_VENDORID _PCI_MAKEMASK(16,S_PCI_DEVICE_VENDORID) 124#define V_PCI_DEVICE_VENDORID(x) _PCI_MAKEVALUE(x,S_PCI_DEVICE_VENDORID) 125#define G_PCI_DEVICE_VENDORID(x) _PCI_GETVALUE(x,S_PCI_DEVICE_VENDORID,M_PCI_DEVICE_VENDORID) 126 127#define S_PCI_DEVICE_DEVICEID 16 128#define M_PCI_DEVICE_DEVICEID _PCI_MAKEMASK(16,S_PCI_DEVICE_DEVICEID) 129#define V_PCI_DEVICE_DEVICEID(x) _PCI_MAKEVALUE(x,S_PCI_DEVICE_DEVICEID) 130#define G_PCI_DEVICE_DEVICEID(x) _PCI_GETVALUE(x,S_PCI_DEVICE_DEVICEID,M_PCI_DEVICE_DEVICEID) 131 132/* 133 * PCI Command Register 134 */ 135 136#define M_PCI_CMD_IOSPACE_EN _PCI_MAKEMASK1(0) 137#define M_PCI_CMD_MEMSPACE_EN _PCI_MAKEMASK1(1) 138#define M_PCI_CMD_MASTER_EN _PCI_MAKEMASK1(2) 139#define M_PCI_CMD_SPECCYC_EN _PCI_MAKEMASK1(3) 140#define M_PCI_CMD_MEMWRINV_EN _PCI_MAKEMASK1(4) 141#define M_PCI_CMD_VGAPALSNP_EN _PCI_MAKEMASK1(5) 142#define M_PCI_CMD_PARERRRESP _PCI_MAKEMASK1(6) 143#define M_PCI_CMD_DATAERRRESP M_PCI_CMD_PARERRRESP /* HT */ 144#define M_PCI_CMD_STEPCTRL _PCI_MAKEMASK1(7) 145#define M_PCI_CMD_SERR_EN _PCI_MAKEMASK1(8) 146#define M_PCI_CMD_FASTB2B_EN _PCI_MAKEMASK1(9) 147#define M_PCI_CMD_INTR_DIS _PCI_MAKEMASK1(10) /* PCI 2.3 */ 148 149/* 150 * PCI Status Register. Note that these constants 151 * assume you've read the command and status register together 152 * (32-bit read at offset 0x04) 153 */ 154 155#define M_PCI_STATUS_INTRSTAT _PCI_MAKEMASK1(19) /* PCI 2.3 */ 156#define M_PCI_STATUS_CAPLIST _PCI_MAKEMASK1(20) 157#define M_PCI_STATUS_66MHZCAP _PCI_MAKEMASK1(21) 158#define M_PCI_STATUS_FASTB2BCAP _PCI_MAKEMASK1(23) 159#define M_PCI_STATUS_MSTRDPARERR _PCI_MAKEMASK1(24) 160#define M_PCI_STATUS_MSTRDATAERR M_PCI_STATUS_MSTRDPARERR /* HT */ 161 162#define S_PCI_STATUS_DEVSELTIMING 25 163#define M_PCI_STATUS_DEVSELTIMING _PCI_MAKEMASK(2,S_PCI_STATUS_DEVSELTIMING) 164#define V_PCI_STATUS_DEVSELTIMING(x) _PCI_MAKEVALUE(x,S_PCI_STATUS_DEVSELTIMING) 165#define G_PCI_STATUS_DEVSELTIMING(x) _PCI_GETVALUE(x,S_PCI_STATUS_DEVSELTIMING,M_PCI_STATUS_DEVSELTIMING) 166 167#define M_PCI_STATUS_SIGDTGTABORT _PCI_MAKEMASK1(27) 168#define M_PCI_STATUS_RCVDTGTABORT _PCI_MAKEMASK1(28) 169#define M_PCI_STATUS_RCVDMSTRABORT _PCI_MAKEMASK1(29) 170#define M_PCI_STATUS_SIGDSERR _PCI_MAKEMASK1(30) 171#define M_PCI_STATUS_DETPARERR _PCI_MAKEMASK1(31) 172#define M_PCI_STATUS_DATAERRDET M_PCI_STATUS_DETPARERR /* HT */ 173 174/* 175 * PCI Class/Revision Register 176 */ 177 178#define S_PCI_CLASSREV_REVID 0 179#define M_PCI_CLASSREV_REVID _PCI_MAKEMASK(8,S_PCI_CLASSREV_REVID) 180#define V_PCI_CLASSREV_REVID(x) _PCI_MAKEVALUE(x,S_PCI_CLASSREV_REVID) 181#define G_PCI_CLASSREV_REVID(x) _PCI_GETVALUE(x,S_PCI_CLASSREV_REVID,M_PCI_CLASSREV_REVID) 182 183#define S_PCI_CLASSREV_CLASS 8 184#define M_PCI_CLASSREV_CLASS _PCI_MAKEMASK(24,S_PCI_CLASSREV_CLASS) 185#define V_PCI_CLASSREV_CLASS(x) _PCI_MAKEVALUE(x,S_PCI_CLASSREV_CLASS) 186#define G_PCI_CLASSREV_CLASS(x) _PCI_GETVALUE(x,S_PCI_CLASSREV_CLASS,M_PCI_CLASSREV_CLASS) 187 188/* 189 * PCI Device Header Register 190 */ 191 192#define S_PCI_DEVHDR_CLINESZ 0 193#define M_PCI_DEVHDR_CLINESZ _PCI_MAKEMASK(8,S_PCI_DEVHDR_CLINESZ) 194#define V_PCI_DEVHDR_CLINESZ(x) _PCI_MAKEVALUE(x,S_PCI_DEVHDR_CLINESZ) 195#define G_PCI_DEVHDR_CLINESZ(x) _PCI_GETVALUE(x,S_PCI_DEVHDR_CLINESZ,M_PCI_DEVHDR_CLINESZ) 196 197#define S_PCI_DEVHDR_LATTIMER 8 198#define M_PCI_DEVHDR_LATTIMER _PCI_MAKEMASK(8,S_PCI_DEVHDR_LATTIMER) 199#define V_PCI_DEVHDR_LATTIMER(x) _PCI_MAKEVALUE(x,S_PCI_DEVHDR_LATTIMER) 200#define G_PCI_DEVHDR_LATTIMER(x) _PCI_GETVALUE(x,S_PCI_DEVHDR_LATTIMER,M_PCI_DEVHDR_LATTIMER) 201 202#define S_PCI_DEVHDR_HDRTYPE 16 203#define M_PCI_DEVHDR_HDRTYPE _PCI_MAKEMASK(8,S_PCI_DEVHDR_HDRTYPE) 204#define V_PCI_DEVHDR_HDRTYPE(x) _PCI_MAKEVALUE(x,S_PCI_DEVHDR_HDRTYPE) 205#define G_PCI_DEVHDR_HDRTYPE(x) _PCI_GETVALUE(x,S_PCI_DEVHDR_HDRTYPE,M_PCI_DEVHDR_HDRTYPE) 206 207#define K_PCI_DEVHDR_HDRTYPE_TYPE0 0 208 209#define S_PCI_DEVHDR_BIST 24 210#define M_PCI_DEVHDR_BIST _PCI_MAKEMASK(8,S_PCI_DEVHDR_BIST) 211#define V_PCI_DEVHDR_BIST(x) _PCI_MAKEVALUE(x,S_PCI_DEVHDR_BIST) 212#define G_PCI_DEVHDR_BIST(x) _PCI_GETVALUE(x,S_PCI_DEVHDR_BIST,M_PCI_DEVHDR_BIST) 213 214 215/* 216 * PCI Device Interrupt/Grant Register (Type 0) 217 */ 218 219#define S_PCI_INTGRANT_INTLINE 0 220#define M_PCI_INTGRANT_INTLINE _PCI_MAKEMASK(8,S_PCI_INTGRANT_INTLINE) 221#define V_PCI_INTGRANT_INTLINE(x) _PCI_MAKEVALUE(x,S_PCI_INTGRANT_INTLINE) 222#define G_PCI_INTGRANT_INTLINE(x) _PCI_GETVALUE(x,S_PCI_INTGRANT_INTLINE,M_PCI_INTGRANT_INTLINE) 223 224#define S_PCI_INTGRANT_INTPIN 8 225#define M_PCI_INTGRANT_INTPIN _PCI_MAKEMASK(8,S_PCI_INTGRANT_INTPIN) 226#define V_PCI_INTGRANT_INTPIN(x) _PCI_MAKEVALUE(x,S_PCI_INTGRANT_INTPIN) 227#define G_PCI_INTGRANT_INTPIN(x) _PCI_GETVALUE(x,S_PCI_INTGRANT_INTPIN,M_PCI_INTGRANT_INTPIN) 228 229#define S_PCI_INTGRANT_MINGNT 16 230#define M_PCI_INTGRANT_MINGNT _PCI_MAKEMASK(8,S_PCI_INTGRANT_MINGNT) 231#define V_PCI_INTGRANT_MINGNT(x) _PCI_MAKEVALUE(x,S_PCI_INTGRANT_MINGNT) 232#define G_PCI_INTGRANT_MINGNT(x) _PCI_GETVALUE(x,S_PCI_INTGRANT_MINGNT,M_PCI_INTGRANT_MINGNT) 233 234#define S_PCI_INTGRANT_MAXLAT 24 235#define M_PCI_INTGRANT_MAXLAT _PCI_MAKEMASK(8,S_PCI_INTGRANT_MAXLAT) 236#define V_PCI_INTGRANT_MAXLAT(x) _PCI_MAKEVALUE(x,S_PCI_INTGRANT_MAXLAT) 237#define G_PCI_INTGRANT_MAXLAT(x) _PCI_GETVALUE(x,S_PCI_INTGRANT_MAXLAT,M_PCI_INTGRANT_MAXLAT) 238 239 240/* 241 * Bridge Bus Number/Sec Latency Register 242 */ 243 244#define S_PPB_BUSID_PRI 0 245#define M_PPB_BUSID_PRI _PCI_MAKEMASK(8,S_PPB_BUSID_PRI) 246#define V_PPB_BUSID_PRI(x) _PCI_MAKEVALUE(x,S_PPB_BUSID_PRI) 247#define G_PPB_BUSID_PRI(x) _PCI_GETVALUE(x,S_PPB_BUSID_PRI,M_PPB_BUSID_PRI) 248 249#define S_PPB_BUSID_SEC 8 250#define M_PPB_BUSID_SEC _PCI_MAKEMASK(8,S_PPB_BUSID_SEC) 251#define V_PPB_BUSID_SEC(x) _PCI_MAKEVALUE(x,S_PPB_BUSID_SEC) 252#define G_PPB_BUSID_SEC(x) _PCI_GETVALUE(x,S_PPB_BUSID_SEC,M_PPB_BUSID_SEC) 253 254#define S_PPB_BUSID_SUBORD 16 255#define M_PPB_BUSID_SUBORD _PCI_MAKEMASK(8,S_PPB_BUSID_SUBORD) 256#define V_PPB_BUSID_SUBORD(x) _PCI_MAKEVALUE(x,S_PPB_BUSID_SUBORD) 257#define G_PPB_BUSID_SUBORD(x) _PCI_GETVALUE(x,S_PPB_BUSID_SUBORD,M_PPB_BUSID_SUBORD) 258 259#define S_PPB_BUSID_SECLATTIMER 24 260#define M_PPB_BUSID_SECLATTIMER _PCI_MAKEMASK(8,S_PPB_BUSID_SECLATTIMER) 261#define V_PPB_BUSID_SECLATTIMER(x) _PCI_MAKEVALUE(x,S_PPB_BUSID_SECLATTIMER) 262#define G_PPB_BUSID_SECLATTIMER(x) _PCI_GETVALUE(x,S_PPB_BUSID_SECLATTIMER,M_PPB_BUSID_SECLATTIMER) 263 264/* 265 * Bridge I/O Base/Limit Register 266 */ 267 268#define S_PPB_IO_BASE 0 269#define M_PPB_IO_BASE _PCI_MAKEMASK(8,S_PPB_IO_BASE) 270#define V_PPB_IO_BASE(x) _PCI_MAKEVALUE(x,S_PPB_IO_BASE) 271#define G_PPB_IO_BASE(x) _PCI_GETVALUE(x,S_PPB_IO_BASE,M_PPB_IO_BASE) 272 273#define S_PPB_IO_LIMIT 8 274#define M_PPB_IO_LIMIT _PCI_MAKEMASK(8,S_PPB_IO_LIMIT) 275#define V_PPB_IO_LIMIT(x) _PCI_MAKEVALUE(x,S_PPB_IO_LIMIT) 276#define G_PPB_IO_LIMIT(x) _PCI_GETVALUE(x,S_PPB_IO_LIMIT,M_PPB_IO_LIMIT) 277 278/* 279 * Bridge Secondary Status Register. Note that these constants 280 * assume that the secondary status and i/o base/limit are read together 281 * (32-bit read at offset 0x1C) 282 */ 283 284#define M_PPB_SSTATUS_66MHZCAP M_PPB_STATUS_66MHZCAP 285#define M_PPB_SSTATUS_FASTB2BCAP M_PPB_SSTATUS_FASTB2BCAP 286#define M_PPB_SSTATUS_MSTRDATAERR M_PPB_SSTATUS_MSTRDATAERR 287 288#define S_PPB_SSTATUS_DEVSELTIMING S_PPB_STATUS_DEVSELTIMING 289#define M_PPB_SSTATUS_DEVSELTIMING M_PPB_STATUS_DEVSELTIMING 290#define V_PPB_SSTATUS_DEVSELTIMING(x) V_PPB_STATUS_DEVSELTIMING(x) 291#define G_PPB_SSTATUS_DEVSELTIMING(x) G_PPB_STATUS_DEVSELTIMING(x) 292 293#define M_PPB_SSTATUS_SIGDTGTABORT M_PPB_STATUS_SIGDTGTABORT 294#define M_PPB_SSTATUS_RCVDTGTABORT M_PPB_STATUS_RCVDTGTABORT 295#define M_PPB_SSTATUS_RCVDMSTRABORT M_PPB_STATUS_RCVDMSTRABORT 296#define M_PPB_SSTATUS_DETSERR _PCI_MAKEMASK1(30) 297#define M_PPB_SSTATUS_DATAERRDET M_PPB_STATUS_DATAERRDET 298 299/* 300 * Bridge Interrupt Line and Pin Register 301 */ 302 303#define S_PPB_INT_LINE 0 304#define M_PPB_INT_LINE _PCI_MAKEMASK(8,S_PPB_INT_LINE) 305#define V_PPB_INT_LINE(x) _PCI_MAKEVALUE(x,S_PPB_INT_LINE) 306#define G_PPB_INT_LINE(x) _PCI_GETVALUE(x,S_PPB_INT_LINE,M_PPB_INT_LINE) 307 308#define S_PPB_INT_PIN 8 309#define M_PPB_INT_PIN _PCI_MAKEMASK(8,S_PPB_INT_PIN) 310#define V_PPB_INT_PIN(x) _PCI_MAKEVALUE(x,S_PPB_INT_PIN) 311#define G_PPB_INT_PIN(x) _PCI_GETVALUE(x,S_PPB_INT_PIN,M_PPB_INT_PIN) 312 313/* 314 * Bridge Control Register. Note that these 315 * constants assume that the bridge control and interrupt registers 316 * are read together (32-bit read at offset 0x3C) 317 */ 318 319#define M_PPB_BRCTL_DATAERRRESP _PCI_MAKEMASK1(16) 320#define M_PPB_BRCTL_SERR_EN _PCI_MAKEMASK1(17) 321#define M_PPB_BRCTL_ISA_EN _PCI_MAKEMASK1(18) 322#define M_PPB_BRCTL_VGA_EN _PCI_MAKEMASK1(19) 323#define M_PPB_BRCTL_MSTRABORTMODE _PCI_MAKEMASK1(21) 324#define M_PPB_BRCTL_SECBUSRESET _PCI_MAKEMASK1(22) 325#define M_PPB_BRCTL_FASTB2B_EN _PCI_MAKEMASK1(23) 326#define M_PPB_BRCTL_PRIDISCARD _PCI_MAKEMASK1(24) 327#define M_PPB_BRCTL_SECDISCARD _PCI_MAKEMASK1(25) 328#define M_PPB_BRCTL_DISCARDSTAT _PCI_MAKEMASK1(26) 329#define M_PPB_BRCTL_DISCARDSERR_EN _PCI_MAKEMASK1(27) 330 331 332/* 333 * Power Management Capability 334 */ 335 336/* NYI */ 337 338 339/* 340 * PCI-X Capability 341 */ 342 343#define R_PCI_PCIXCMD (0x00) 344#define R_PCI_PCIXSTAT (0x04) 345 346 347/* 348 * Message-Signaled Interrupt (MSI) Capability 349 */ 350 351#define R_PCI_MSICTRL (0x00) 352#define R_PCI_MSIADDR (0x04) /* lower, upper */ 353#define R_PCI_MSIDATA (0x0C) 354 355 356/* 357 * HyperTransport Capabilities 358 */ 359 360/* 361 * The capability's Type is encoded in the high-order bits of the 362 * first word (Command) and distinguishes among variant capabilities. 363 */ 364 365#define S_HT_CMD_CAPTYPE 29 366#define M_HT_CMD_CAPTYPE _PCI_MAKEMASK(3,S_HT_CMD_CAPTYPE) 367#define V_HT_CMD_CAPTYPE(x) _PCI_MAKEVALUE(x,S_HT_CMD_CAPTYPE) 368#define G_HT_CMD_CAPTYPE(x) _PCI_GETVALUE(x,S_HT_CMD_CAPTYPE,M_HT_CMD_CAPTYPE) 369 370#define K_HT_CAPTYPE_SLAVE 0x0 371#define K_HT_CAPTYPE_HOST 0x1 372#define K_HT_CAPTYPE_SWITCH 0x2 373 374/* Switch subtypes */ 375#define S_HT_CMD_SUBTYPE 27 376#define M_HT_CMD_SUBTYPE _PCI_MAKEMASK(2,S_HT_CMD_SUBTYPE) 377#define V_HT_CMD_SUBTYPE(x) _PCI_MAKEVALUE(x,S_HT_CMD_SUBTYPE) 378#define G_HT_CMD_SUBTYPE(x) _PCI_GETVALUE(x,S_HT_CMD_SUBTYPE,M_HT_CMD_SUBTYPE) 379 380#define K_HT_SUBTYPE_SWITCH 0x0 381#define K_HT_SUBTYPE_VCSET 0x3 382 383 384/* 385 * Slave/Primary Interface Capability 386 */ 387 388#define R_HTP_CMD (0x00) 389#define R_HTP_LINKCTRL0 (0x04) 390#define R_HTP_LINKCTRL1 (0x08) 391#define R_HTP_LINKFREQ0 (0x0C) 392#define R_HTP_LINKFREQ1 (0x10) 393#define R_HTP_ERROR (0x14) 394#define R_HTP_MEMUPPER (0x18) 395 396/* 397 * Host/Secondary Interface Capability 398 */ 399 400#define R_HTS_CMD (0x00) 401#define R_HTS_LINKCTRL (0x04) 402#define R_HTS_LINKFREQ (0x08) 403#define R_HTS_FEATURE (0x0C) 404#define R_HTS_ERROR (0x10) 405#define R_HTS_MEMUPPER (0x14) 406 407 408/* 409 * HT Command Register. Note that these constants assume 410 * that the HT Command and Capability registers are read together 411 * (32-bit read at relative offset 0x00) 412 */ 413 414/* Primary/Device variant (relative offset 0x00) */ 415 416#define S_HT_CMD_BASEUNITID 16 417#define M_HT_CMD_BASEUNITID _PCI_MAKEMASK(5,S_HT_CMD_BASEUNITID) 418#define V_HT_CMD_BASEUNITID(x) _PCI_MAKEVALUE(x,S_HT_CMD_BASEUNITID) 419#define G_HT_CMD_BASEUNITID(x) _PCI_GETVALUE(x,S_HT_CMD_BASEUNITID,M_HT_CMD_BASEUNITID) 420 421#define S_HT_CMD_UNITCOUNT 21 422#define M_HT_CMD_UNITCOUNT _PCI_MAKEMASK(5,S_HT_CMD_UNITCOUNT) 423#define V_HT_CMD_UNITCOUNT(x) _PCI_MAKEVALUE(x,S_HT_CMD_UNITCOUNT) 424#define G_HT_CMD_UNITCOUNT(x) _PCI_GETVALUE(x,S_HT_CMD_UNITCOUNT,M_HT_CMD_UNITCOUNT) 425 426#define M_HT_CMD_MASTERHOST _PCI_MAKEMASK1(26) 427#define M_HT_CMD_DEFAULTDIR _PCI_MAKEMASK1(27) 428#define M_HT_CMD_DROPUNINIT _PCI_MAKEMASK1(28) 429 430/* Secondary/Host variant (relative offset 0x00) */ 431 432#define M_HTS_CMD_WARMRESET _SB_MAKEMASK1_32(16) 433#define M_HTS_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17) 434 435#define S_HTS_CMD_DEVICENUM 18 436#define M_HTS_CMD_DEVICENUM _SB_MAKEMASK_32(5,S_HTS_CMD_DEVICENUM) 437#define V_HTS_CMD_DEVICENUM(x) _SB_MAKEVALUE_32(x,S_HTS_CMD_DEVICENUM) 438#define G_HTS_CMD_DEVICENUM(x) _SB_GETVALUE_32(x,S_HTS_CMD_DEVICENUM,M_HTS_CMD_DEVICENUM) 439 440#define M_HTS_CMD_CHAINSIDE _SB_MAKEMASK1_32(23) 441#define M_HTS_CMD_HOSTHIDE _SB_MAKEMASK1_32(24) 442#define M_HTS_CMD_ACTASSLAVE _SB_MAKEMASK1_32(26) 443#define M_HTS_CMD_HOSTEOCERR _SB_MAKEMASK1_32(27) 444#define M_HTS_CMD_DROPUNINIT _SB_MAKEMASK1_32(28) 445 446/* 447 * HT Link Control Register 448 * Primary/Device: relative offsets 0x04, 0x08 449 * Secondary/host: relative offset 0x04 450 */ 451 452#define M_HT_LINKCTRL_CRCSYNCFLOOD_EN _PCI_MAKEMASK1(1) 453#define M_HT_LINKCTRL_CRCSTARTTEST _PCI_MAKEMASK1(2) 454#define M_HT_LINKCTRL_CRCFORCEERR _PCI_MAKEMASK1(3) 455#define M_HT_LINKCTRL_LINKFAIL _PCI_MAKEMASK1(4) 456#define M_HT_LINKCTRL_INITCOMPLETE _PCI_MAKEMASK1(5) 457#define M_HT_LINKCTRL_EOC _PCI_MAKEMASK1(6) 458#define M_HT_LINKCTRL_XMITOFF _PCI_MAKEMASK1(7) 459 460#define S_HT_LINKCTRL_CRCERR 8 461#define M_HT_LINKCTRL_CRCERR _PCI_MAKEMASK(4,S_HT_LINKCTRL_CRCERR) 462#define V_HT_LINKCTRL_CRCERR(x) _PCI_MAKEVALUE(x,S_HT_LINKCTRL_CRCERR) 463#define G_HT_LINKCTRL_CRCERR(x) _PCI_GETVALUE(x,S_HT_LINKCTRL_CRCERR,M_HT_LINKCTRL_CRCERR) 464 465#define M_HT_LINKCTRL_ISOCFC_EN _PCI_MAKEMASK1(12) 466#define M_HT_LINKCTRL_LDTSTOPTRI_EN _PCI_MAKEMASK1(13) 467#define M_HT_LINKCTRL_EXTCTLTIME _PCI_MAKEMASK1(14) 468#define M_HT_LINKCTRL_64BADDR_EN _PCI_MAKEMASK1(15) 469 470/* 471 * HT Link Configuration Register. Note that these 472 * constants assume that the HT Link Configuration and Control 473 * registers are read together. 474 * Primary/Device: relative offsets 0x04, 0x08 475 * Secondary/host: relative offset 0x04 476 */ 477 478#define S_HT_LINKCFG_MAXIN 16 479#define M_HT_LINKCFG_MAXIN _PCI_MAKEMASK(3,S_HT_LINKCFG_MAXIN) 480#define V_HT_LINKCFG_MAXIN(x) _PCI_MAKEVALUE(x,S_HT_LINKCFG_MAXIN) 481#define G_HT_LINKCFG_MAXIN(x) _PCI_GETVALUE(x,S_HT_LINKCFG_MAXIN,M_HT_LINKCFG_MAXIN) 482 483#define M_HT_LINKCFG_DWFCIN _PCI_MAKEMASK1(19) 484 485#define S_HT_LINKCFG_MAXOUT 20 486#define M_HT_LINKCFG_MAXOUT _PCI_MAKEMASK(3,S_HT_LINKCFG_MAXOUT) 487#define V_HT_LINKCFG_MAXOUT(x) _PCI_MAKEVALUE(x,S_HT_LINKCFG_MAXOUT) 488#define G_HT_LINKCFG_MAXOUT(x) _PCI_GETVALUE(x,S_HT_LINKCFG_MAXOUT,M_HT_LINKCFG_MAXOUT) 489 490#define M_HT_LINKCFG_DWFCOUT _PCI_MAKEMASK1(23) 491 492#define S_HT_LINKCFG_WIDTHIN 24 493#define M_HT_LINKCFG_WIDTHIN _PCI_MAKEMASK(3,S_HT_LINKCFG_WIDTHIN) 494#define V_HT_LINKCFG_WIDTHIN(x) _PCI_MAKEVALUE(x,S_HT_LINKCFG_WIDTHIN) 495#define G_HT_LINKCFG_WIDTHIN(x) _PCI_GETVALUE(x,S_HT_LINKCFG_WIDTHIN,M_HT_LINKCFG_WIDTHIN) 496 497#define M_HT_LINKCFG_DWFCIN_EN _PCI_MAKEMASK1(27) 498 499#define S_HT_LINKCFG_WIDTHOUT 28 500#define M_HT_LINKCFG_WIDTHOUT _PCI_MAKEMASK(3,S_HT_LINKCFG_WIDTHOUT) 501#define V_HT_LINKCFG_WIDTHOUT(x) _PCI_MAKEVALUE(x,S_HT_LINKCFG_WIDTHOUT) 502#define G_HT_LINKCFG_WIDTHOUT(x) _PCI_GETVALUE(x,S_HT_LINKCFG_WIDTHOUT,M_HT_LINKCFG_WIDTHOUT) 503 504#define M_HT_LINKCFG_DWFCOUT_EN _PCI_MAKEMASK1(31) 505 506/* 507 * HT Link Frequency/Error Register 508 * Primary/Device: relative offsets 0x0C, 0x10 509 * Secondary/host: relative offset 0x08, 0x0C 510 */ 511 512/* Link0 only */ 513#define S_HT_LINKFREQ_HTREVID 8 514#define M_HT_LINKFREQ_HTREVID _PCI_MAKEMASK(8,S_HT_LINKFREQ_HTREVID) 515#define V_HT_LINKFREQ_HTREVID(x) _PCI_MAKEVALUE(x,S_HT_LINKFREQ_HTREVID) 516#define G_HT_LINKFREQ_HTREVID(x) _PCI_GETVALUE(x,S_HT_LINKFREQ_HTREVID,M_HT_LINKFREQ_HTREVID) 517 518/* Link1 only (HTFeature) */ 519#define M_HT_LINKFREQ_ISOCFC _PCI_MAKEMASK1(0) 520#define M_HT_LINKFREQ_LDTSTOP _PCI_MAKEMASK1(1) 521#define M_HT_LINKFREQ_CRCTST _PCI_MAKEMASK1(2) 522#define M_HT_LINKFREQ_EXTCTL _PCI_MAKEMASK1(3) 523#define M_HT_LINKFREQ_64BADDR _PCI_MAKEMASK1(4) 524#define M_HT_LINKFREQ_UIDREODIS _PCI_MAKEMASK1(5) 525/* Secondary/host only */ 526#define M_HT_LINKFREQ_EXTREGSET _PCI_MAKEMASK1(8) 527#define M_HT_LINKFREQ_UPSTCFGEN _PCI_MAKEMASK1(9) 528 529/* Secondary/host Link0 only */ 530#define S_HT_LINKFREQ_FREQ 8 531#define M_HT_LINKFREQ_FREQ _PCI_MAKEMASK(4,S_HT_LINKFREQ_FREQ) 532#define V_HT_LINKFREQ_FREQ(x) _PCI_MAKEVALUE(x,S_HT_LINKFREQ_FREQ) 533#define G_HT_LINKFREQ_FREQ(x) _PCI_GETVALUE(x,S_HT_LINKFREQ_FREQ,M_HT_LINKFREQ_FREQ) 534 535#define K_HT_LINKFREQ_200MHZ 0 536#define K_HT_LINKFREQ_300MHZ 1 537#define K_HT_LINKFREQ_400MHZ 2 538#define K_HT_LINKFREQ_500MHZ 3 539#define K_HT_LINKFREQ_600MHZ 4 540#define K_HT_LINKFREQ_800MHZ 5 541#define K_HT_LINKFREQ_1000MHZ 6 542#define K_HT_LINKFREQ_VENDOR 15 543 544#define M_HT_LINKFREQ_PROTERR _PCI_MAKEMASK1(12) 545#define M_HT_LINKFREQ_OVFLERR _PCI_MAKEMASK1(13) 546#define M_HT_LINKFREQ_EOCERR _PCI_MAKEMASK1(14) 547#define M_HT_LINKFREQ_CTLTO _PCI_MAKEMASK1(15) 548 549/* Secondary/host Link0 only */ 550#define S_HT_LINKFREQ_CAP 16 551#define M_HT_LINKFREQ_CAP _PCI_MAKEMASK(16,S_HT_LINKFREQ_CAP) 552#define V_HT_LINKFREQ_CAP(x) _PCI_MAKEVALUE(x,S_HT_LINKFREQ_CAP) 553#define G_HT_LINKFREQ_CAP(x) _PCI_GETVALUE(x,S_HT_LINKFREQ_CAP,M_HT_LINKFREQ_CAP) 554 555/* 556 * HT Error Handling Register 557 * Primary/Device: relative offset 0x14 558 * Secondary/host: relative offset 0x10 559 */ 560 561#define S_HT_SCRATCHPAD 0 562#define M_HT_SCRATCHPAD _PCI_MAKEMASK(16,S_HT_SCRATCHPAD) 563#define V_HT_SCRATCHPAD(x) _PCI_MAKEVALUE(x,S_HT_SCRATCHPAD) 564#define G_HT_SCRATCHPAD(x) _PCI_GETVALUE(x,S_HT_SCRATCHPAD,M_HT_SCRATCHPAD) 565 566#define M_HT_ERRHNDL_PROFL_EN _PCI_MAKEMASK1(16) 567#define M_HT_ERRHNDL_OVFFL_EN _PCI_MAKEMASK1(17) 568#define M_HT_ERRHNDL_PROFT_EN _PCI_MAKEMASK1(18) 569#define M_HT_ERRHNDL_OVFFT_EN _PCI_MAKEMASK1(19) 570#define M_HT_ERRHNDL_EOCFT_EN _PCI_MAKEMASK1(20) 571#define M_HT_ERRHNDL_RSPFT_EN _PCI_MAKEMASK1(21) 572#define M_HT_ERRHNDL_CRCFT_EN _PCI_MAKEMASK1(22) 573#define M_HT_ERRHNDL_SYSFTL_EN _PCI_MAKEMASK1(23) 574#define M_HT_ERRHNDL_CHNFAIL _PCI_MAKEMASK1(24) 575#define M_HT_ERRHNDL_RSPERR _PCI_MAKEMASK1(25) 576#define M_HT_ERRHNDL_PRONF_EN _PCI_MAKEMASK1(26) 577#define M_HT_ERRHNDL_OVFNF_EN _PCI_MAKEMASK1(27) 578#define M_HT_ERRHNDL_EOCNF_EN _PCI_MAKEMASK1(28) 579#define M_HT_ERRHNDL_RSPNF_EN _PCI_MAKEMASK1(29) 580#define M_HT_ERRHNDL_CRCNF_EN _PCI_MAKEMASK1(30) 581#define M_HT_ERRHNDL_SYSNF_EN _PCI_MAKEMASK1(31) 582 583 584/* 585 * Switch Command Register 586 */ 587 588#define M_HT_SWCMD_VIBERR _PCI_MAKEMASK1(23) 589#define M_HT_SWCMD_VIBFI_EN _PCI_MAKEMASK1(23) 590#define M_HT_SWCMD_VIBFT_EN _PCI_MAKEMASK1(23) 591#define M_HT_SWCMD_VIBNF_EN _PCI_MAKEMASK1(23) 592 593/* Note: includes CapType and SubType above */ 594#define S_HT_SWCMD_CAPTYPE 27 595#define M_HT_SWCMD_CAPTYPE _PCI_MAKEMASK(5,S_HT_SWCMD_CAPTYPE) 596#define V_HT_SWCMD_CAPTYPE(x) _PCI_MAKEVALUE(x,S_HT_SWCMD_CAPTYPE) 597#define G_HT_SWCMD_CAPTYPE(x) _PCI_GETVALUE(x,S_HT_SWCMD_CAPTYPE,M_HT_SWCMD_CAPTYPE) 598 599/* 600 * Switch Partition Register 601 */ 602 603#define M_HT_SWPAR_PORT0INPARTITION _PCI_MAKEMASK1(0) 604#define M_HT_SWPAR_PORT1INPARTITION _PCI_MAKEMASK1(1) 605#define M_HT_SWPAR_PORT2INPARTITION _PCI_MAKEMASK1(2) 606 607/* 608 * Switch Info Register 609 */ 610 611#define S_HT_SWINFO_DEFPORT 0 612#define M_HT_SWINFO_DEFPORT _PCI_MAKEMASK(5,S_HT_SWINFO_DEFPORT) 613#define V_HT_SWINFO_DEFPORT(x) _PCI_MAKEVALUE(x,S_HT_SWINFO_DEFPORT) 614#define G_HT_SWINFO_DEFPORT(x) _PCI_GETVALUE(x,S_HT_SWINFO_DEFPORT,M_HT_SWINFO_DEFPORT) 615 616#define M_HT_SWINFO_DECODEEN _PCI_MAKEMASK1(5) 617#define M_HT_SWINFO_COLDRESET _PCI_MAKEMASK1(6) 618 619#define S_HT_SWINFO_PERFINDEX 8 620#define M_HT_SWINFO_PERFINDEX _PCI_MAKEMASK(4,S_HT_SWINFO_PERFINDEX) 621#define V_HT_SWINFO_PERFINDEX(x) _PCI_MAKEVALUE(x,S_HT_SWINFO_PERFINDEX) 622#define G_HT_SWINFO_PERFINDEX(x) _PCI_GETVALUE(x,S_HT_SWINFO_PERFINDEX,M_HT_SWINFO_PERFINDEX) 623 624#define S_HT_SWINFO_BLRINDEX 16 625#define M_HT_SWINFO_BLRINDEX _PCI_MAKEMASK(6,S_HT_SWINFO_BLRINDEX) 626#define V_HT_SWINFO_BLRINDEX(x) _PCI_MAKEVALUE(x,S_HT_SWINFO_BLRINDEX) 627#define G_HT_SWINFO_BLRINDEX(x) _PCI_GETVALUE(x,S_HT_SWINFO_BLRINDEX,M_HT_SWINFO_BLRINDEX) 628 629#define M_HT_SWINFO_HOTPLUG _PCI_MAKEMASK1(22) 630#define M_HT_SWINFO_HIDEPORT _PCI_MAKEMASK1(23) 631 632 633/* 634 * VCSet Command Register 635 */ 636 637/* Note: includes CapType and SubType above */ 638#define S_HT_VCCMD_CAPTYPE 27 639#define M_HT_VCCMD_CAPTYPE _PCI_MAKEMASK(5,S_HT_VCCMD_CAPTYPE) 640#define V_HT_VCCMD_CAPTYPE(x) _PCI_MAKEVALUE(x,S_HT_VCCMD_CAPTYPE) 641#define G_HT_VCCMD_CAPTYPE(x) _PCI_GETVALUE(x,S_HT_VCCMD_CAPTYPE,M_HT_VCCMD_CAPTYPE) 642 643/* 644 * VCSet Configuration and Capability Register 645 */ 646 647#define S_HT_VCCFG_VCSETSUP 0 648#define M_HT_VCCFG_VCSETSUP _PCI_MAKEMASK(8,S_HT_VCCFG_VCSETSUP) 649#define V_HT_VCCFG_VCSETSUP(x) _PCI_MAKEVALUE(x,S_HT_VCCFG_VCSETSUP) 650#define G_HT_VCCFG_VCSETSUP(x) _PCI_GETVALUE(x,S_HT_VCCFG_VCSETSUP,M_HT_VCCFG_VCSETSUP) 651 652#define S_HT_VCCFG_L1ENBVCSET 8 653#define M_HT_VCCFG_L1ENBVCSET _PCI_MAKEMASK(8,S_HT_VCCFG_L1ENBVCSET) 654#define V_HT_VCCFG_L1ENBVCSET(x) _PCI_MAKEVALUE(x,S_HT_VCCFG_L1ENBVCSET) 655#define G_HT_VCCFG_L1ENBVCSET(x) _PCI_GETVALUE(x,S_HT_VCCFG_L1ENBVCSET,M_HT_VCCFG_L1ENBVCSET) 656 657#define S_HT_VCCFG_L0ENBVCSET 16 658#define M_HT_VCCFG_L0ENBVCSET _PCI_MAKEMASK(8,S_HT_VCCFG_L0ENBVCSET) 659#define V_HT_VCCFG_L0ENBVCSET(x) _PCI_MAKEVALUE(x,S_HT_VCCFG_L0ENBVCSET) 660#define G_HT_VCCFG_L0ENBVCSET(x) _PCI_GETVALUE(x,S_HT_VCCFG_L0ENBVCSET,M_HT_VCCFG_L0ENBVCSET) 661 662#define S_HT_VCCFG_VCSETEOC 24 663#define M_HT_VCCFG_VCSETEOC _PCI_MAKEMASK(8,S_HT_VCCFG_VCSETEOC) 664#define V_HT_VCCFG_VCSETEOC(x) _PCI_MAKEVALUE(x,S_HT_VCCFG_VCSETEOC) 665#define G_HT_VCCFG_VCSETEOC(x) _PCI_GETVALUE(x,S_HT_VCCFG_VCSETEOC,M_HT_VCCFG_VCSETEOC) 666 667/* 668 * VCSet Stream Configuration Register 669 */ 670 671#define S_HT_VCSTRM_STRMBUCKDEPTH 0 672#define M_HT_VCSTRM_STRMBUCKDEPTH _PCI_MAKEMASK(8,S_HT_VCSTRM_STRMBUCKDEPTH) 673#define V_HT_VCSTRM_STRMBUCKDEPTH(x) _PCI_MAKEVALUE(x,S_HT_VCSTRM_STRMBUCKDEPTH) 674#define G_HT_VCSTRM_STRMBUCKDEPTH(x) _PCI_GETVALUE(x,S_HT_VCSTRM_STRMBUCKDEPTH,M_HT_VCSTRM_STRMBUCKDEPTH) 675 676#define S_HT_VCSTRM_STRMINTERVAL 8 677#define M_HT_VCSTRM_STRMINTERVAL _PCI_MAKEMASK(8,S_HT_VCSTRM_STRMINTERVAL) 678#define V_HT_VCSTRM_STRMINTERVAL(x) _PCI_MAKEVALUE(x,S_HT_VCSTRM_STRMINTERVAL) 679#define G_HT_VCSTRM_STRMINTERVAL(x) _PCI_GETVALUE(x,S_HT_VCSTRM_STRMINTERVAL,M_HT_VCSTRM_STRMINTERVAL) 680 681#define S_HT_VCSTRM_STRMSUP 16 682#define M_HT_VCSTRM_STRMSUP _PCI_MAKEMASK(8,S_HT_VCSTRM_STRMSUP) 683#define V_HT_VCSTRM_STRMSUP(x) _PCI_MAKEVALUE(x,S_HT_VCSTRM_STRMSUP) 684#define G_HT_VCSTRM_STRMSUP(x) _PCI_GETVALUE(x,S_HT_VCSTRM_STRMSUP,M_HT_VCSTRM_STRMSUP) 685 686/* 687 * VCSet NonFC Configuration Register 688 */ 689 690#define S_HT_VCNONFC_NONFCBUCKDEPTH 0 691#define M_HT_VCNONFC_NONFCBUCKDEPTH _PCI_MAKEMASK(8,S_HT_VCNONFC_NONFCBUCKDEPTH) 692#define V_HT_VCNONFC_NONFCBUCKDEPTH(x) _PCI_MAKEVALUE(x,S_HT_VCNONFC_NONFCBUCKDEPTH) 693#define G_HT_VCNONFC_NONFCBUCKDEPTH(x) _PCI_GETVALUE(x,S_HT_VCNONFC_NONFCBUCKDEPTH,M_HT_VCNONFC_NONFCBUCKDEPTH) 694 695#define S_HT_VCNONFC_NONFCINTERVAL 8 696#define M_HT_VCNONFC_NONFCINTERVAL _PCI_MAKEMASK(8,S_HT_VCNONFC_NONFCINTERVAL) 697#define V_HT_VCNONFC_NONFCINTERVAL(x) _PCI_MAKEVALUE(x,S_HT_VCNONFC_NONFCINTERVAL) 698#define G_HT_VCNONFC_NONFCINTERVAL(x) _PCI_GETVALUE(x,S_HT_VCNONFC_NONFCINTERVAL,M_HT_VCNONFC_NONFCINTERVAL) 699 700#endif /* _PCI_CFG_H */ 701