1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * MPC8240 Registers File: mpc8240.h 5 * 6 * Motorola MPC8240 SOC registers and values 7 * 8 * Author: Mitch Lichtenberg 9 * 10 ********************************************************************* 11 * 12 * Copyright 2000,2001,2002,2003 13 * Broadcom Corporation. All rights reserved. 14 * 15 * This software is furnished under license and may be used and 16 * copied only in accordance with the following terms and 17 * conditions. Subject to these conditions, you may download, 18 * copy, install, use, modify and distribute modified or unmodified 19 * copies of this software in source and/or binary form. No title 20 * or ownership is transferred hereby. 21 * 22 * 1) Any source code used, modified or distributed must reproduce 23 * and retain this copyright notice and list of conditions 24 * as they appear in the source file. 25 * 26 * 2) No right is granted to use any trade name, trademark, or 27 * logo of Broadcom Corporation. The "Broadcom Corporation" 28 * name may not be used to endorse or promote products derived 29 * from this software without the prior written permission of 30 * Broadcom Corporation. 31 * 32 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 33 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 34 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 35 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 36 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 37 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 38 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 39 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 40 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 41 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 42 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 43 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 44 * THE POSSIBILITY OF SUCH DAMAGE. 45 ********************************************************************* */ 46 47#if (!defined(_MPC8240_) && !defined(_MPC8245_)) 48#error "You must define either _MPC8240_ or _MPC8245_ in your makefile." 49#endif 50#if (defined(_MPC8240_) && defined(_MPC845_)) 51#error "You must make up your mind, 8240 or 8245, not both!" 52#endif 53 54/* 55 * This file is only concerned about Address Map "B" 56 */ 57 58#define A_MPC_CONFIG_ADDR 0xfec00000 /* PCI configuration space */ 59#define A_MPC_CONFIG_DATA 0xfee00000 60 61/* 62 * PCI config space registers 63 */ 64 65/* 66 * The first 40 bytes are a standard PCI Type 0 header, but the following 67 * registers need early initialization in some configurations. 68 */ 69 70#define MPC_VID 0x80000000 /* 16 bits */ 71#define MPC_DID 0x80000002 /* 16 bits */ 72 73#define MPC_LATTMR 0x8000000d /* 8 bits */ 74#define MPC_CLSIZE 0x8000000c /* 8 bits */ 75 76#define MPC_PCICMD 0x80000004 /* 16 bits */ 77#define MPC_PCISTS 0x80000006 /* 16 bits */ 78 79#ifdef _MPC8245_ 80#define MPC_PGCR 0x80000044 /* 16 bits, mpc8245 only */ 81#endif 82 83#define MPC_PACR 0x80000046 /* 16 bits */ 84 85#define MPC_PMCR1 0x80000070 /* 16 bits */ 86#define MPC_PMCR2 0x80000072 /* 8 bits */ 87#define MPC_ODCR 0x80000073 /* 8 bits */ 88#define MPC_CDCR 0x80000074 /* 16 bits */ 89 90#define MPC_EUMBBAR 0x80000078 /* 32 bits */ 91 92#define MPC_MSAR1 0x80000080 /* 32 bits */ 93#define MPC_MSAR2 0x80000084 /* 32 bits */ 94#define MPC_XMSAR1 0x80000088 /* 32 bits */ 95#define MPC_XMSAR2 0x8000008C /* 32 bits */ 96 97#define MPC_MEAR1 0x80000090 /* 32 bits */ 98#define MPC_MEAR2 0x80000094 /* 32 bits */ 99#define MPC_XMEAR1 0x80000098 /* 32 bits */ 100#define MPC_XMEAR2 0x8000009C /* 32 bits */ 101 102#define MPC_MBEN 0x800000A0 /* 8 bits */ 103#define MPC_PGMODE 0x800000A3 /* 8 bits */ 104 105#define MPC_PICR1 0x800000A8 /* 32 bits */ 106#define MPC_PICR2 0x800000AC /* 32 bits */ 107#define MPC_ECCSBC 0x800000B8 /* 8 bits */ 108#define MPC_ECCTRIG 0x800000B9 /* 8 bits */ 109#define MPC_ERRENR1 0x800000C0 /* 8 bits */ 110#define MPC_ERRDR1 0x800000C1 /* 8 bits */ 111#define MPC_IPBESR 0x800000C3 /* 8 bits */ 112#define MPC_ERRENR2 0x800000C4 /* 8 bits */ 113#define MPC_ERRDR2 0x800000C5 /* 8 bits */ 114#define MPC_PCIBSE 0x800000C7 /* 8 bits */ 115#define MPC_ERRADDR 0x800000C8 /* 32 bits */ 116#define MPC_AMBOR 0x800000E0 /* 8 bits */ 117#define MPC_MCCR1 0x800000F0 /* 32 bits */ 118#define MPC_MCCR2 0x800000F4 /* 32 bits */ 119#define MPC_MCCR3 0x800000F8 /* 32 bits */ 120#define MPC_MCCR4 0x800000FC /* 32 bits */ 121 122#ifdef _MPC8245_ 123#define MPC_PCR 0x800000e2 /* 8 bits, semi-documented, MPC8245 */ 124#define MPC_MIOCR1 0x80000076 /* 8 bits */ /* MPC8245 */ 125#define MPC_MIOCR2 0x80000077 /* 8 bits */ /* MPC8245 */ 126#define MPC_ERCR1 0x800000d0 /* 32 bits */ /* MPC8245 */ 127#define MPC_ERCR2 0x800000d4 /* 32 bits */ /* MPC8245 */ 128#define MPC_ERCR3 0x800000d8 /* 32 bits */ /* MPC8245 */ 129#define MPC_ERCR4 0x800000dc /* 32 bits */ /* MPC8245 */ 130#endif 131 132/* 133 * PCI command register 134 */ 135 136#define M_PCICMD_MEMENA _MMR_MAKEMASK1(1) 137#define M_PCICMD_BUSMASTER _MMR_MAKEMASK1(2) 138 139/* 140 * PCI General Control Register (mpc8245 only) 141 */ 142 143#ifdef _MPC8245_ 144#define S_PGCR_LAT_DISC_TMR 1 145#define M_PGCR_LAT_DISC_TMR _MMR_MAKEMASK(2,S_PGCR_LAT_DISC_TMR) 146#define V_PGCR_LAT_DISC_TMR(x) _MMR_MAKEVALUE(x,S_PGCR_LAT_DISC_TMR) 147#define G_PGCR_LAT_DISC_TMR(x) _MMR_GETVALUE(x,S_PGCR_LAT_DISC_TMR,M_PGCR_LAT_DISC_TMR) 148 149#define M_PGCR_LOCK_DIS _MMR_MAKEMASK1(4) 150#define M_PGCR_RETRY_RD_EN _MMR_MAKEMAKS1(5) 151#endif 152 153/* 154 * PCI Aribiter Control Register 155 */ 156 157#define S_PACR_EXTDEV_PRIO 0 158#define M_PACR_EXTDEV_PRIO _MMR_MAKEMASK(5,S_PACR_EXTDEV_PRIO) 159#define V_PACR_EXTDEV_PRIO(x) _MMR_MAKEVALUE(x,S_PACR_EXTDEV_PRIO) 160#define G_PACR_EXTDEV_PRIO(x) _MMR_GETVALUE(x,S_PACR_EXTDEV_PRIO,M_PACR_EXTDEV_PRIO) 161 162#define M_PACR_MPC_PRIO _MMR_MAKEMASK1(7) 163#define M_PACR_BRKN_MASTER_DIS _MMR_MAKEMASK1(12) 164#define M_PACR_CFG_RETRY _MMR_MAKEMASK1(10) 165 166#define S_PACR_PARK_MODE 13 167#define M_PACR_PARK_MODE _MMR_MAKEMASK(2,S_PACR_PARK_MODE) 168#define V_PACR_PARK_MODE(x) _MMR_MAKEVALUE(x,S_PACR_PARK_MODE) 169#define G_PACR_PARK_MODE(x) _MMR_GETVALUE(x,S_PACR_PARK_MODE,M_PACR_PARK_MODE) 170#define K_PACR_PARK_LAST 0 171#define K_PACR_PARK_0 1 172#define K_PACR_PARK_MPC 2 173 174#define M_PAC_ARB_EN _MMR_MAKEMASK1(15) 175 176/* 177 * Processor interface config 1 178 */ 179 180#define M_PIC1_RD_SPEC_EN _MMR_MAKEMASK1(2) 181#define M_PIC1_CF_APARK _MMR_MAKEMASK1(3) 182 183#ifdef _MPC8240_ 184#define M_PIC1_MBO (_MMR_MAKEMASK1(4) | 0xFF000000) 185#else 186#define M_PIC1_MBO (_MMR_MAKEMASK1(4)) 187#endif 188 189#define M_PIC1_LE_MODE _MMR_MAKEMASK1(5) 190#define M_PIC1_ST_GATH_EN _MMR_MAKEMASK1(6) 191 192#ifdef _MPC8245_ 193#define M_PIC1_RSVD _MMR_MAKEMASK1(7) 194#define M_PIC1_DEC _MMR_MAKEMASK1(8) 195#endif 196 197#define M_PIC1_CF_DPARK _MMR_MAKEMASK1(9) 198#define M_PIC1_MCP_EN _MMR_MAKEMASK1(11) 199#define M_PIC1_FLASH_WR_EN _MMR_MAKEMASK1(12) 200#define M_PIC1_ADDRESS_MAP _MMR_MAKEMASK1(16) 201 202#define S_PIC1_PROC_TYPE 17 203#define M_PIC1_PROC_TYPE _MMR_MAKEMASK(2,S_PIC1_PROC_TYPE) 204#define V_PIC1_PROC_TYPE(x) _MMR_MAKEVALUE(x,S_PIC1_PROC_TYPE) 205#define G_PIC1_PROC_TYPE(x) _MMR_GETVALUE(x,S_PIC1_PROC_TYPE,M_PIC1_PROC_TYPE) 206 207#define M_PIC1_RCS0 _MMR_MAKEMASK1(20) 208 209/* 210 * Processor interface config 2 211 */ 212 213#ifdef _MPC8240_ 214#define S_PIC2_CF_IP2 2 215#define M_PIC2_CF_IP2 _MMR_MAKEMASK(2,S_PIC2_CF_IP2) 216#define V_PIC2_CF_IP2(x) _MMR_MAKEVALUE(x,S_PIC2_CF_IP2) 217#define G_PIC2_CF_IP2(x) _MMR_GETVALUE(x,S_PIC2_CF_IP2,M_PIC2_CF_IP2) 218 219#define S_PIC2_CF_IP1 2 220#define M_PIC2_CF_IP1 _MMR_MAKEMASK(18,S_PIC2_CF_IP1) 221#define V_PIC2_CF_IP1(x) _MMR_MAKEVALUE(x,S_PIC2_CF_IP1) 222#define G_PIC2_CF_IP1(x) _MMR_GETVALUE(x,S_PIC2_CF_IP1,M_PIC2_CF_IP1) 223#endif 224 225#define M_PIC2_FLASH_WR_LOCKOUT _MMR_MAKEMASK1(25) 226#define M_PIC2_CF_FF0_LOCAL _MMR_MAKEMASK1(26) 227#define M_PIC2_NO_SNOOP_EN _MMR_MAKEMASK1(27) 228#define M_PIC2_NO_SERIAL_CFG _MMR_MAKEMASK1(29) 229 230/* 231 * Power Management Configuration Register 1 232 */ 233 234#define M_PMCR1_CKO_SEL _MMR_MAKEMASK1(0) 235 236#define S_PMCR1_CKO_MODE 1 237#define M_PMCR1_CKO_MODE _MMR_MAKEMASK(2,S_PMCR1_CKO_MODE) 238#define V_PMCR1_CKO_MODE(x) _MMR_MAKEVALUE(x,S_PMCR1_CKO_MODE) 239#define G_PMCR1_CKO_MODE(x) _MMR_GETVALUE(x,S_PMCR1_CKO_MODE,M_PMCR1_CKO_MODE) 240 241#define M_PMCR1_SLEEP _MMR_MAKEMASK1(3) 242#define M_PMCR1_NAP _MMR_MAKEMASK1(4) 243#define M_PMCR1_DOZE _MMR_MAKEMASK1(5) 244#define M_PMCR1_PM _MMR_MAKEMASK1(7) 245#define M_PMCR1_LP_REF_EN _MMR_MAKEMASK1(12) 246#define M_PMCR1_NO_SLEEP_MSG _MMR_MAKEMASK1(14) 247#define M_PMCR1_NO_NAP_MSG _MMR_MAKEMASK1(15) 248 249 250/* 251 * Power Management Configuration Register 2 252 */ 253 254#ifdef _MPC8240_ 255#define M_PMCR2_SHARED_MCP _MMR_MAKEMASK1(0) 256#endif 257 258#define M_PMCR2_PLL_SLEEP _MMR_MAKEMASK1(2) 259 260#ifdef _MPC8240_ 261#define S_PMCR2_PCI_HOLD 4 262#define M_PMCR2_PCI_HOLD _MMR_MAKEMASK(3,S_PMCR2_PCI_HOLD) 263#define V_PMCR2_PCI_HOLD(x) _MMR_MAKEVALUE(x,S_PMCR2_PCI_HOLD) 264#define G_PMCR2_PCI_HOLD(x) _MMR_GETVALUE(x,S_PMCR2_PCI_HOLD,M_PMCR2_PCI_HOLD) 265#endif 266 267#ifdef _MPC8245_ 268#define S_PMCR2_PCI_HOLD 4 269#define M_PMCR2_PCI_HOLD _MMR_MAKEMASK(2,S_PMCR2_PCI_HOLD) 270#define V_PMCR2_PCI_HOLD(x) _MMR_MAKEVALUE(x,S_PMCR2_PCI_HOLD) 271#define G_PMCR2_PCI_HOLD(x) _MMR_GETVALUE(x,S_PMCR2_PCI_HOLD,M_PMCR2_PCI_HOLD) 272#endif 273 274#define M_PMCR2_DLL_EXTEND _MMR_MAKEMASK1(7) 275 276/* 277 * Output drive control register 278 */ 279 280#define M_ODCR_PCI _MMR_MAKEMASK1(7) 281#define M_ODCR_STD _MMR_MAKEMASK1(6) 282#define M_ODCR_MEM_CTRL_1 _MMR_MAKEMASK1(5) 283#define M_ODCR_MEM_CTRL_2 _MMR_MAKEMASK1(4) 284#define M_ODCR_PCI_CLK_1 _MMR_MAKEMASK1(3) 285#define M_ODCR_PCI_CLK_2 _MMR_MAKEMASK1(2) 286#define M_ODCR_MEM_CLK_1 _MMR_MAKEMASK1(1) 287#define M_ODCR_MEM_CLK_2 _MMR_MAKEMASK1(0) 288 289/* 290 * Clock drive control register 291 */ 292 293#define M_CDCR_SDRAM_CLK3_DIS _MMR_MAKEMASK1(3) 294#define M_CDCR_SDRAM_CLK2_DIS _MMR_MAKEMASK1(4) 295#define M_CDCR_SDRAM_CLK1_DIS _MMR_MAKEMASK1(5) 296#define M_CDCR_SDRAM_CLK0_DIS _MMR_MAKEMASK1(6) 297 298#define M_CDCR_PCI_CLK4_DIS _MMR_MAKEMASK1(10) 299#define M_CDCR_PCI_CLK3_DIS _MMR_MAKEMASK1(11) 300#define M_CDCR_PCI_CLK2_DIS _MMR_MAKEMASK1(12) 301#define M_CDCR_PCI_CLK1_DIS _MMR_MAKEMASK1(13) 302#define M_CDCR_PCI_CLK0_DIS _MMR_MAKEMASK1(14) 303 304/* 305 * Memory boundary register 306 */ 307 308#define V_MBR_BANKn(b,x) _MMR_MAKEVALUE(x,(x)*8) 309#define V_XMBR_BANKn(b,x) _MMR_MAKEVALUE(x,(x)*8) 310 311#define M_MBER_BANKn(x) _MMR_MAKEMASK1(x) 312 313/* 314 * Error enable register 315 */ 316 317#define M_ERREN_PTERR _MMR_MAKEMASK1(0) 318#define M_ERREN_PCIABORT _MMR_MAKEMASK1(1) 319#define M_ERREN_PARECC _MMR_MAKEMASK1(2) 320#define M_ERREN_MSTPERR _MMR_MAKEMASK1(3) 321#define M_ERREN_REFOVL _MMR_MAKEMASK1(4) 322#define M_ERREN_MEMSEL _MMR_MAKEMASK1(5) 323#define M_ERREN_TGTPERR _MMR_MAKEMASK1(6) 324#define M_ERREN_RXSERR _MMR_MAKEMASK1(7) 325 326/* 327 * Error detect register 328 */ 329 330#define S_ERRDT_UPT 0 331#define M_ERRDT_UPT _MMR_MAKEMASK(2,S_ERRDT_UPT) 332#define V_ERRDT_UPT(x) _MMR_MAKEVALUE(x,S_ERRDT_UPT) 333#define G_ERRDT_UPT(x) _MMR_GETVALUE(x,S_ERRDT_UPT,M_ERRDT_UPT) 334 335#define M_ERRDT_PARECC _MMR_MAKEMASK1(2) 336#define M_ERRDT_PROCPCI _MMR_MAKEMASK1(3) 337#define M_ERRDT_REFOVL _MMR_MAKEMASK1(4) 338#define M_ERRDT_MEMSEL _MMR_MAKEMASK1(5) 339#define M_ERRDT_TGTPERR _MMR_MAKEMASK1(6) 340#define M_ERRDT_RXSERR _MMR_MAKEMASK1(7) 341 342/* 343 * Internal processor bus status register 344 */ 345 346#define M_PIBDT_ROMWRITE _MMR_MAKEMASK1(0) 347#define M_PIBDT_TGTABORT _MMR_MAKEMASK1(1) 348#define M_PIBDT_PARERR _MMR_MAKEMASK1(2) 349#define M_PIBDT_ECCERR _MMR_MAKEMASK1(3) 350#define M_PIBDT_ADDRPAR _MMR_MAKEMASK1(7) 351 352 353/* 354 * Internal processor bus error enable 355 */ 356 357#define M_PIBEN_ROMWRITE _MMR_MAKEMASK1(0) 358#define M_PIBEN_TGTABORT _MMR_MAKEMASK1(1) 359#define M_PIBEN_PARERR _MMR_MAKEMASK1(2) 360#define M_PIBEN_ECCERR _MMR_MAKEMASK1(3) 361#define M_PIBEN_PCISERR _MMR_MAKEMASK1(6) 362#define M_PIBEN_ADDRPAR _MMR_MAKEMASK1(7) 363 364/* 365 * Error detect register 2 366 */ 367 368#define M_ERRDT2_ROMWRITE _MMR_MAKEMASK1(0) 369#define M_ERRDT2_MEMWRPAR _MMR_MAKEMASK1(1) 370#define M_ERRDT2_ECCERR _MMR_MAKEMASK1(3) 371#define M_ERRDT2_INVERRADDR _MMR_MAKEMASK1(7) 372 373/* 374 * Address map B options register 375 */ 376 377#define M_AMBOR_PROCHOLE _MMR_MAKEMASK1(2) 378#define M_AMBOR_PCIHOLE _MMR_MAKEMASK1(3) 379#define M_AMBOR_DLLRESET _MMR_MAKEMASK1(5) 380#define M_AMBOR_PCI_FD_ALIAS _MMR_MAKEMASK1(6) 381#define M_AMBOR_CPU_FD_ALIAS _MMR_MAKEMASK1(7) 382 383/* 384 * Misc IO Control 1 (MPC8245) 385 */ 386 387#ifdef _MPC8245_ 388#define M_MIOCR1_CLK_FLIP _MMR_MAKEMASK1(1) 389#define M_MIOCR1_DLL_MAX_DELAY _MMR_MAKEMASK1(2) 390#define M_MIOCR1_MCP_OD_MODE _MMR_MAKEMASK1(7) 391#endif 392 393/* 394 * Misc IO Control 2 (MPC8245) 395 */ 396 397#define S_MIOCR2_SDRAM_DSCD 4 398#define M_MIOCR2_SDRAM_DSCD _MMR_MAKEMASK(2,S_MIOCR2_SDRAM_DSCD) 399#define V_MIOCR2_SDRAM_DSCD(x) _MMR_MAKEVALUE(x,S_MIOCR2_SDRAM_DSCD) 400#define G_MIOCR2_SDRAM_DSCD(x) _MMR_GETVALUE(x,S_MIOCR2_SDRAM_DSCD,M_MIOCR2_SDRAM_DSCD) 401 402/* 403 * Memory control configuration register 1 404 */ 405 406 407#define V_MCCR1_BANKnROW(b,x) _MMR_MAKEVALUE(x,(b)*2) 408#define K_MCCR1_ROW9 0 409#define K_MCCR1_ROW10 1 410#define K_MCCR1_ROW11 2 411#define K_MCCR1_ROW12 3 412 413#define M_MCCR1_PCKEN _MMR_MAKEMASK1(16) 414#define M_MCCR1_RAMTYPE _MMR_MAKEMASK1(17) 415#define M_MCCR1_SREN _MMR_MAKEMASK1(18) 416#define M_MCCR1_MEMGO _MMR_MAKEMASK1(19) 417#define M_MCCR1_BURST _MMR_MAKEMASK1(20) 418 419#define S_MCCR1_ROMFAL 23 420#define M_MCCR1_ROMFAL _MMR_MAKEMASK(5,S_MCCR1_ROMFAL) 421#define V_MCCR1_ROMFAL(x) _MMR_MAKEVALUE(x,S_MCCR1_ROMFAL) 422#define G_MCCR1_ROMFAL(x) _MMR_GETVALUE(x,S_MCCR1_ROMFAL,M_MCCR1_ROMFAL) 423 424#define S_MCCR1_ROMNAL 28 425#define M_MCCR1_ROMNAL _MMR_MAKEMASK(4,S_MCCR1_ROMNAL) 426#define V_MCCR1_ROMNAL(x) _MMR_MAKEVALUE(x,S_MCCR1_ROMNAL) 427#define G_MCCR1_ROMNAL(x) _MMR_GETVALUE(x,S_MCCR1_ROMNAL,M_MCCR1_ROMNAL) 428 429/* 430 * Memory control configuration register 2 431 */ 432 433#define M_MCCR2_RMWPAR _MMR_MAKEMASK1(0) 434#define M_MCCR2_RSVPG _MMR_MAKEMASK1(1) 435 436#define S_MCCR2_REFINT 2 437#define M_MCCR2_REFINT _MMR_MAKEMASK(14,S_MCCR2_REFINT) 438#define V_MCCR2_REFINT(x) _MMR_MAKEVALUE(x,S_MCCR2_REFINT) 439#define G_MCCR2_REFINT(x) _MMR_GETVALUE(x,S_MCCR2_REFINT,M_MCCR2_REFINT) 440 441#ifdef _MPC8240_ 442#define M_MCCR2_EDO _MMR_MAKEMASK1(16) 443#define M_MCCR2_ECCEN _MMR_MAKEMASK1(17) 444#endif 445 446#define M_MCCR2_INLINERD _MMR_MAKEMASK1(18) 447#define M_MCCR2_WPARCHK _MMR_MAKEMASK1(19) 448#define M_MCCR2_INLPARNOECC _MMR_MAKEMASK1(20) 449 450#define S_MCCR2_TSWAIT 29 451#define M_MCCR2_TSWAIT _MMR_MAKEMASK(3,S_MCCR2_TSWAIT) 452#define V_MCCR2_TSWAIT(x) _MMR_MAKEVALUE(x,S_MCCR2_TSWAIT) 453#define G_MCCR2_TSWAIT(x) _MMR_GETVALUE(x,S_MCCR2_TSWAIT,M_MCCR2_TSWAIT) 454 455#define S_MCCR2_ASRISE 25 456#define M_MCCR2_ASRISE _MMR_MAKEMASK(4,S_MCCR2_ASRISE) 457#define V_MCCR2_ASRISE(x) _MMR_MAKEVALUE(x,S_MCCR2_ASRISE) 458#define G_MCCR2_ASRISE(x) _MMR_GETVALUE(x,S_MCCR2_ASRISE,M_MCCR2_ASRISE) 459 460#define S_MCCR2_ASFALL 21 461#define M_MCCR2_ASFALL _MMR_MAKEMASK(4,S_MCCR2_ASFALL) 462#define V_MCCR2_ASFALL(x) _MMR_MAKEVALUE(x,S_MCCR2_ASFALL) 463#define G_MCCR2_ASFALL(x) _MMR_GETVALUE(x,S_MCCR2_ASFALL,M_MCCR2_ASFALL) 464 465/* 466 * Memory control configuration register 3 467 */ 468 469#ifdef _MPC8240_ 470#define S_MCCR3_RP1 0 471#define M_MCCR3_RP1 _MMR_MAKEMASK(3,S_MCCR3_RP1) 472#define V_MCCR3_RP1(x) _MMR_MAKEVALUE(x,S_MCCR3_RP1) 473#define G_MCCR3_RP1(x) _MMR_GETVALUE(x,S_MCCR3_RP1,M_MCCR3_RP1) 474 475#define S_MCCR3_RCD2 3 476#define M_MCCR3_RCD2 _MMR_MAKEMASK(3,S_MCCR3_RCD2) 477#define V_MCCR3_RCD2(x) _MMR_MAKEVALUE(x,S_MCCR3_RCD2) 478#define G_MCCR3_RCD2(x) _MMR_GETVALUE(x,S_MCCR3_RCD2,M_MCCR3_RCD2) 479 480#define S_MCCR3_CAS3 6 481#define M_MCCR3_CAS3 _MMR_MAKEMASK(3,S_MCCR3_CAS3) 482#define V_MCCR3_CAS3(x) _MMR_MAKEVALUE(x,S_MCCR3_CAS3) 483#define G_MCCR3_CAS3(x) _MMR_GETVALUE(x,S_MCCR3_CAS3,M_MCCR3_CAS3) 484 485#define S_MCCR3_CP4 9 486#define M_MCCR3_CP4 _MMR_MAKEMASK(4,S_MCCR3_CP4) 487#define V_MCCR3_CP4(x) _MMR_MAKEVALUE(3,S_MCCR3_CP4) 488#define G_MCCR3_CP4(x) _MMR_GETVALUE(x,S_MCCR3_CP4,M_MCCR3_CP4) 489 490#define S_MCCR3_CAS5 12 491#define M_MCCR3_CAS5 _MMR_MAKEMASK(3,S_MCCR3_CAS5) 492#define V_MCCR3_CAS5(x) _MMR_MAKEVALUE(x,S_MCCR3_CAS5) 493#define G_MCCR3_CAS5(x) _MMR_GETVALUE(x,S_MCCR3_CAS5,M_MCCR3_CAS5) 494 495#define S_MCCR3_RAS6 15 496#define M_MCCR3_RAS6 _MMR_MAKEMASK(4,S_MCCR3_RAS6) 497#define V_MCCR3_RAS6(x) _MMR_MAKEVALUE(x,S_MCCR3_RAS6) 498#define G_MCCR3_RAS6(x) _MMR_GETVALUE(x,S_MCCR3_RAS6,M_MCCR3_ASF 499 500#define M_MCCR3_CPX _MMR_MAKEMASK1(19) 501 502#define S_MCCR3_RDLAT 20 503#define M_MCCR3_RDLAT _MMR_MAKEMASK(4,S_MCCR3_RDLAT) 504#define V_MCCR3_RDLAT(x) _MMR_MAKEVALUE(x,S_MCCR3_RDLAT) 505#define G_MCCR3_RDLAT(x) _MMR_GETVALUE(x,S_MCCR3_RDLAT,M_MCCR3_RDLAT) 506#endif 507 508 509#define S_MCCR3_REFREC 24 510#define M_MCCR3_REFREC _MMR_MAKEMASK(4,S_MCCR3_REFREC) 511#define V_MCCR3_REFREC(x) _MMR_MAKEVALUE(x,S_MCCR3_REFREC) 512#define G_MCCR3_REFREC(x) _MMR_GETVALUE(x,S_MCCR3_REFREC,M_MCCR3_REFREC) 513 514#define S_MCCR3_BSTOPRE 28 515#define M_MCCR3_BSTOPRE _MMR_MAKEMASK(4,S_MCCR3_BSTOPRE) 516#define V_MCCR3_BSTOPRE(x) _MMR_MAKEVALUE(x,S_MCCR3_BSTOPRE) 517#define G_MCCR3_BSTOPRE(x) _MMR_GETVALUE(x,S_MCCR3_BSTOPRE,M_MCCR3_BSTOPRE) 518 519 520/* 521 * Memory control configuration register 4 522 */ 523 524#define S_MCCR4_BSTOPRE69 0 525#define M_MCCR4_BSTOPRE69 _MMR_MAKEMASK(4,S_MCCR4_BSTOPRE69) 526#define V_MCCR4_BSTOPRE69(x) _MMR_MAKEVALUE(x,S_MCCR4_BSTOPRE69) 527#define G_MCCR4_BSTOPRE69(x) _MMR_GETVALUE(x,S_MCCR4_BSTOPRE69,M_MCCR4_BSTOPRE69) 528 529#define S_MCCR4_ACTORW 4 530#define M_MCCR4_ACTORW _MMR_MAKEMASK(4,S_MCCR4_ACTORW) 531#define V_MCCR4_ACTORW(x) _MMR_MAKEVALUE(x,S_MCCR4_ACTORW) 532#define G_MCCR4_ACTORW(x) _MMR_GETVALUE(x,S_MCCR4_ACTORW,M_MCCR4_ACTORW) 533 534#define S_MCCR4_SDMODE 8 535#define M_MCCR4_SDMODE _MMR_MAKEMASK(7,S_MCCR4_SDMODE) 536#define V_MCCR4_SDMODE(x) _MMR_MAKEVALUE(x,S_MCCR4_SDMODE) 537#define G_MCCR4_SDMODE(x) _MMR_GETVALUE(x,S_MCCR4_SDMODE,M_MCCR4_SDMODE) 538 539#define S_MCCR4_SDMODE_CAS 12 540#define M_MCCR4_SDMODE_CAS _MMR_MAKEMASK(7,S_MCCR4_SDMODE) 541#define V_MCCR4_SDMODE_CAS(x) _MMR_MAKEVALUE(x,S_MCCR4_SDMODE) 542#define G_MCCR4_SDMODE_CAS(x) _MMR_GETVALUE(x,S_MCCR4_SDMODE,M_MCCR4_SDMODE) 543 544#define M_MCCR4_REGDIMM _MMR_MAKEMASK1(15) 545 546#ifdef _MPC8245_ 547#define M_MCCR4_DBUS_SIZE _MMR_MAKEMASK1(17) 548#endif 549 550#define S_MCCR4_BSTOPRE01 18 551#define M_MCCR4_BSTOPRE01 _MMR_MAKEMASK(2,S_MCCR4_BSTOPRE01) 552#define V_MCCR4_BSTOPRE01(x) _MMR_MAKEVALUE(x,S_MCCR4_BSTOPRE01) 553#define G_MCCR4_BSTOPRE01(x) _MMR_GETVALUE(x,S_MCCR4_BSTOPRE01,M_MCCR4_BSTOPRE01) 554 555#define M_MCCR4_BUFTYPE1 _MMR_MAKEMASK1(20) 556 557#ifdef _MPC8245_ 558#define M_MCCR4_EXTROM _MMR_MAKEMASK1(21) 559#endif 560 561#define M_MCCR4_BUFTYPE0 _MMR_MAKEMASK1(22) 562#define M_MCCR4_WMODE _MMR_MAKEMASK1(23) 563 564#define S_MCCR4_ACTOPRE 24 565#define M_MCCR4_ACTOPRE _MMR_MAKEMASK(4,S_MCCR4_ACTOPRE) 566#define V_MCCR4_ACTOPRE(x) _MMR_MAKEVALUE(x,S_MCCR4_ACTOPRE) 567#define G_MCCR4_ACTOPRE(x) _MMR_GETVALUE(x,S_MCCR4_ACTOPRE,M_MCCR4_ACTOPRE) 568 569#define S_MCCR4_PRETOACT 28 570#define M_MCCR4_PRETOACT _MMR_MAKEMASK(4,S_MCCR4_PRETOACT) 571#define V_MCCR4_PRETOACT(x) _MMR_MAKEVALUE(x,S_MCCR4_PRETOACT) 572#define G_MCCR4_PRETOACT(x) _MMR_GETVALUE(x,S_MCCR4_PRETOACT,M_MCCR4_PRETOACT) 573 574 575 576/* 577 * Extended ROM configuration registers (MPC8245) 578 */ 579 580#define M_ERCR12_EN _MMR_MAKEMASK1(31) 581#define M_ERCR12_BURST _MMR_MAKEMASK1(30) 582 583#define S_ERCR12_DBW 28 584#define M_ERCR12_DBW _MMR_MAKEMASK(2,S_ERCR12_DBW) 585#define V_ERCR12_DBW(x) _MMR_MAKEVALUE(x,S_ERCR12_DBW) 586#define G_ERCR12_DBW(x) _MMR_GETVALUE(x,S_ERCR12_DBW,M_ERCR12_DBW) 587 588#define K_ERCR12_DBW_8BIT 0 589#define K_ERCR12_DBW_16BIT 1 590#define K_ERCR12_DBW_32BIT 2 591#define K_ERCR12_DBW_WIDE 3 592 593#define S_ERCR12_CTL 26 594#define M_ERCR12_CTL _MMR_MAKEMASK(2,S_ERCR12_CTL) 595#define V_ERCR12_CTL(x) _MMR_MAKEVALUE(x,S_ERCR12_CTL) 596#define G_ERCR12_CTL(x) _MMR_GETVALUE(x,S_ERCR12_CTL,M_ERCR12_CTL) 597 598#define K_ERCR12_CTL_INDEP 0 599#define K_ERCR12_CTL_BASE 1 600#define K_ERCR12_CTL_PORTX_STROBE 2 601#define K_ERCR12_CTL_PORTX_HANDSHAKE 3 602 603#define S_ERCR12_ROMFAL 20 604#define M_ERCR12_ROMFAL _MMR_MAKEMASK(5,S_ERCR12_ROMFAL) 605#define V_ERCR12_ROMFAL(x) _MMR_MAKEVALUE(x,S_ERCR12_ROMFAL) 606#define G_ERCR12_ROMFAL(x) _MMR_GETVALUE(x,S_ERCR12_ROMFAL,M_ERCR12_ROMFAL) 607 608#define S_ERCR12_ROMNAL 15 609#define M_ERCR12_ROMNAL _MMR_MAKEMASK(5,S_ERCR12_ROMNAL) 610#define V_ERCR12_ROMNAL(x) _MMR_MAKEVALUE(x,S_ERCR12_ROMNAL) 611#define G_ERCR12_ROMNAL(x) _MMR_GETVALUE(x,S_ERCR12_ROMNAL,M_ERCR12_ROMNAL) 612 613#define S_ERCR12_ASFALL 10 614#define M_ERCR12_ASFALL _MMR_MAKEMASK(5,S_ERCR12_ASFALL) 615#define V_ERCR12_ASFALL(x) _MMR_MAKEVALUE(x,S_ERCR12_ASFALL) 616#define G_ERCR12_ASFALL(x) _MMR_GETVALUE(x,S_ERCR12_ASFALL,M_ERCR12_ASFALL) 617 618#define S_ERCR12_ASRISE 5 619#define M_ERCR12_ASRISE _MMR_MAKEMASK(5,S_ERCR12_ASRISE) 620#define V_ERCR12_ASRISE(x) _MMR_MAKEVALUE(x,S_ERCR12_ASRISE) 621#define G_ERCR12_ASRISE(x) _MMR_GETVALUE(x,S_ERCR12_ASRISE,M_ERCR12_ASRISE) 622 623#define S_ERCR12_TSWAIT 0 624#define M_ERCR12_TSWAIT _MMR_MAKEMASK(5,S_ERCR12_TSWAIT) 625#define V_ERCR12_TSWAIT(x) _MMR_MAKEVALUE(x,S_ERCR12_TSWAIT) 626#define G_ERCR12_TSWAIT(x) _MMR_GETVALUE(x,S_ERCR12_TSWAIT,M_ERCR12_TSWAIT) 627 628 629#define S_ERCR34_SADDR 12 630#define M_ERCR34_SADDR _MMR_MAKEMASK(16,S_ERCR34_SADDR) 631#define V_ERCR34_SADDR(x) _MMR_MAKEVALUE(x,S_ERCR34_SADDR) 632#define G_ERCR34_SADDR(x) _MMR_GETVALUE(x,S_ERCR34_SADDR,M_ERCR34_SADDR) 633 634#define S_ERCR34_SIZE 0 635#define M_ERCR34_SIZE _MMR_MAKEMASK(4,S_ERCR34_SIZE) 636#define V_ERCR34_SIZE(x) _MMR_MAKEVALUE(x,S_ERCR34_SIZE) 637#define G_ERCR34_SIZE(x) _MMR_GETVALUE(x,S_ERCR34_SIZE,M_ERCR34_SIZE) 638 639#define K_ERCR34_SIZE_4K 0 640#define K_ERCR34_SIZE_8K 1 641#define K_ERCR34_SIZE_16K 2 642#define K_ERCR34_SIZE_32K 3 643#define K_ERCR34_SIZE_64K 4 644#define K_ERCR34_SIZE_128K 5 645#define K_ERCR34_SIZE_256K 6 646#define K_ERCR34_SIZE_512K 7 647#define K_ERCR34_SIZE_1M 8 648#define K_ERCR34_SIZE_2M 9 649#define K_ERCR34_SIZE_4M 10 650#define K_ERCR34_SIZE_8M 11 651#define K_ERCR34_SIZE_16M 12 652#define K_ERCR34_SIZE_32M 13 653#define K_ERCR34_SIZE_64M 14 654#define K_ERCR34_SIZE_128M 15 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675