1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * BSP Configuration file File: bsp_config.h 5 * 6 * This module contains global parameters and conditional 7 * compilation settings for building CFE. 8 * 9 * Author: Mitch Lichtenberg 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48 49 50//#define CFG_CPU_SPEED 800000000 /* 800MHz */ 51#define CFG_CPU_SPEED 500000 /* 500KHz for the func simulator */ 52 53#define CFG_INIT_L1 1 /* initialize the L1 cache */ 54#define CFG_INIT_L2 1 /* initialize the L2 cache */ 55#define CFG_INIT_DRAM 1 /* initialize DRAM controller */ 56 57#define CFG_NETWORK 0 /* define to include network support */ 58 59#define CFG_UI 1 /* Define to enable user interface */ 60 61#define CFG_MULTI_CPUS 0 /* Define to include multiple CPU support */ 62 63#define CFG_HEAP_SIZE 32 /* heap size in kilobytes */ 64#define CFG_STACK_SIZE 1024 /* stack size in bytes */ 65 66 67/* 68 * These parameters control the flash driver's sector buffer. 69 * If you write environment variables or make small changes to 70 * flash sectors from user applications, you 71 * need to have the heap big enough to store a temporary sector 72 * for merging in small changes to flash sectors, so you 73 * should set CFG_FLASH_ALLOC_SECTOR_BUFFER in that case. 74 * Otherwise, you can provide an address in unallocated memory 75 * of where to place the sector buffer. 76 */ 77 78#define CFG_FLASH_ALLOC_SECTOR_BUFFER 0 /* '1' to allocate sector buffer from the heap */ 79#define CFG_FLASH_SECTOR_BUFFER_ADDR (100*1024*1024-128*1024) /* 100MB - 128K */ 80#define CFG_FLASH_SECTOR_BUFFER_SIZE (128*1024) 81 82/* 83 * The flash staging buffer is where we store a flash image before we write 84 * it to the flash. It's too big for the heap. 85 */ 86 87#define CFG_FLASH_STAGING_BUFFER_ADDR (100*1024*1024) 88#define CFG_FLASH_STAGING_BUFFER_SIZE (4*1024*1024) 89 90/* 91 * These parameters control the default DRAM init table 92 * inside of sb1250_draminit.c. 93 */ 94 95 96#define CFG_DRAM_ECC 0 /* Turn on to enable ECC */ 97#define CFG_DRAM_SMBUS_CHANNEL 0 /* SMBus channel for memory SPDs */ 98#define CFG_DRAM_SMBUS_BASE 0x54 /* starting SMBus device base */ 99#define CFG_DRAM_SMBUS_NDIMMS 4 /* total number of DIMM slots */ 100#define CFG_DRAM_BLOCK_SIZE 32 /* don't interleave columns */ 101#define CFG_DRAM_INTERLEAVE 0 102#define CFG_DRAM_CSINTERLEAVE 0 /* Use 0,1, or 2. Max number of address 103 bits allowed for chip select 104 interleaving. Only matching dimms 105 will be interleaved. 3 outcomes: 106 no interleaving, interleave CS 0 & 107 1, and interleave CS 0,1,2 & 3. */ 108 109#define CFG_SERIAL_BAUD_RATE 921600 /* really, really fast for verilog */ 110 111#ifndef _VERILOG_ 112#define _VERILOG_ 113#endif 114#ifndef _FASTEMUL_ 115#define _FASTEMUL_ 116#endif 117 118