1/* ********************************************************************* 2 * SB1125 Board Support Package 3 * 4 * BCM1112PCIX Board definitions File: bcm91125pcix.h 5 * 6 * This file contains I/O, chip select, and GPIO assignments 7 * for the BCM91125PCIX board. 8 * 9 * Author: Mitch Lichtenberg 10 * Binh Vo 11 * 12 ********************************************************************* 13 * 14 * Copyright 2000,2001,2002,2003 15 * Broadcom Corporation. All rights reserved. 16 * 17 * This software is furnished under license and may be used and 18 * copied only in accordance with the following terms and 19 * conditions. Subject to these conditions, you may download, 20 * copy, install, use, modify and distribute modified or unmodified 21 * copies of this software in source and/or binary form. No title 22 * or ownership is transferred hereby. 23 * 24 * 1) Any source code used, modified or distributed must reproduce 25 * and retain this copyright notice and list of conditions 26 * as they appear in the source file. 27 * 28 * 2) No right is granted to use any trade name, trademark, or 29 * logo of Broadcom Corporation. The "Broadcom Corporation" 30 * name may not be used to endorse or promote products derived 31 * from this software without the prior written permission of 32 * Broadcom Corporation. 33 * 34 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 35 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 36 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 37 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 38 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 39 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 40 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 41 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 42 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 43 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 44 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 45 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 46 * THE POSSIBILITY OF SUCH DAMAGE. 47 ********************************************************************* */ 48 49 50/* 51 * I/O Address assignments for the bcm91125pcix board 52 * 53 * Summary of address map: 54 * 55 * Address Size CSel Description 56 * --------------- ---- ------ -------------------------------- 57 * 0x1FC00000 2MB CS0 Boot ROM 58 * 0x1F800000 2MB CS1 Alternate boot ROM (PromICE) 59 * CS2 Unused 60 * 0x100A0000 64KB CS3 LED display 61 * 0x100B0000 64KB CS4 USB Channel 1 62 * 0x100C0000 64KB CS5 USB Channel 2 63 * 0x11000000 64MB CS6 PCMCIA 64 * CS7 Unused 65 * 66 * GPIO assignments 67 * 68 * GPIO# Direction Description 69 * ------- --------- ------------------------------------------ 70 * GPIO0 Input NMI (interrupt) 71 * GPIO1 Input RTC Out (interrupt) 72 * GPIO2 Input PHY interrupt (interrupt) 73 * GPIO3 Input USB1 interrupt (interrupt) 74 * GPIO4 Input USB2 interrupt (interrupt) 75 * GPIO5 Input Temperature Sensor Alert (interrupt) 76 * GPIO6 N/A PCMCIA interface 77 * GPIO7 N/A PCMCIA interface 78 * GPIO8 N/A PCMCIA interface 79 * GPIO9 N/A PCMCIA interface 80 * GPIO10 N/A PCMCIA interface 81 * GPIO11 N/A PCMCIA interface 82 * GPIO12 N/A PCMCIA interface 83 * GPIO13 N/A PCMCIA interface 84 * GPIO14 N/A PCMCIA interface 85 * GPIO15 N/A PCMCIA interface 86 */ 87 88/* ********************************************************************* 89 * Macros 90 ********************************************************************* */ 91 92#define MB (1024*1024) 93#define K64 65536 94#define NUM64K(x) (((x)+(K64-1))/K64) 95 96 97/* ********************************************************************* 98 * GPIO pins 99 ********************************************************************* */ 100 101#define GPIO_NMI_INT 0 102#define GPIO_RTC_INT 1 103#define GPIO_PHY_INT 2 104#define GPIO_USB1_INT 3 105#define GPIO_USB2_INT 4 106#define GPIO_TEMP_INT 5 107 108#define M_GPIO_NMI_INT _SB_MAKEMASK1(GPIO_NMI_INT) 109#define M_GPIO_RTC_INT _SB_MAKEMASK1(GPIO_RTC_INT) 110#define M_GPIO_PHY_INT _SB_MAKEMASK1(GPIO_PHY_INT) 111#define M_GPIO_USB1_INT _SB_MAKEMASK1(GPIO_USB1_INT) 112#define M_GPIO_USB2_INT _SB_MAKEMASK1(GPIO_USB2_INT) 113#define M_GPIO_TEMP_INT _SB_MAKEMASK1(GPIO_TEMP_INT) 114 115#define GPIO_OUTPUT_MASK (0) 116 117#define GPIO_INTERRUPT_MASK ((V_GPIO_INTR_TYPEX(GPIO_NMI_INT,K_GPIO_INTR_LEVEL)) | \ 118 (V_GPIO_INTR_TYPEX(GPIO_PHY_INT,K_GPIO_INTR_LEVEL)) | \ 119 (V_GPIO_INTR_TYPEX(GPIO_USB2_INT,K_GPIO_INTR_LEVEL))) 120 121 122/* ********************************************************************* 123 * Generic Bus 124 ********************************************************************* */ 125 126/* 127 * Boot ROM: non-multiplexed, byte width, no parity, no ack 128 * XXX: These are the (very slow) default parameters. This can be sped up! 129 */ 130#define BOOTROM_CS 0 131#define BOOTROM_PHYS 0x1FC00000 /* address of boot ROM (CS0) */ 132#define BOOTROM_SIZE NUM64K(2*MB) /* size of boot ROM */ 133#define BOOTROM_TIMING0 V_IO_ALE_WIDTH(4) | \ 134 V_IO_ALE_TO_CS(2) | \ 135 V_IO_CS_WIDTH(24) | \ 136 V_IO_RDY_SMPLE(1) 137#define BOOTROM_TIMING1 V_IO_ALE_TO_WRITE(7) | \ 138 V_IO_WRITE_WIDTH(7) | \ 139 V_IO_IDLE_CYCLE(6) | \ 140 V_IO_CS_TO_OE(0) | \ 141 V_IO_OE_TO_CS(0) 142#define BOOTROM_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 143 144/* 145 * Alternate Boot ROM: non-multiplexed, byte width, no parity, no ack 146 * XXX: These are the (very slow) default parameters. This can be sped up! 147 */ 148#define ALT_BOOTROM_CS 1 149#define ALT_BOOTROM_PHYS 0x1F800000 /* address of alternate boot ROM (CS1) */ 150#define ALT_BOOTROM_SIZE NUM64K(2*MB) /* size of alternate boot ROM */ 151#define ALT_BOOTROM_TIMING0 V_IO_ALE_WIDTH(4) | \ 152 V_IO_ALE_TO_CS(2) | \ 153 V_IO_CS_WIDTH(24) | \ 154 V_IO_RDY_SMPLE(1) 155#define ALT_BOOTROM_TIMING1 V_IO_ALE_TO_WRITE(7) | \ 156 V_IO_WRITE_WIDTH(7) | \ 157 V_IO_IDLE_CYCLE(6) | \ 158 V_IO_CS_TO_OE(0) | \ 159 V_IO_OE_TO_CS(0) 160#define ALT_BOOTROM_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 161 162 163 164/* 165 * LEDs: non-multiplexed, byte width, no parity, no ack 166 */ 167#define LEDS_CS 3 168#define LEDS_PHYS 0x100A0000 169#define LEDS_SIZE NUM64K(4) 170#define LEDS_TIMING0 V_IO_ALE_WIDTH(4) | \ 171 V_IO_ALE_TO_CS(2) | \ 172 V_IO_CS_WIDTH(13) | \ 173 V_IO_RDY_SMPLE(1) 174#define LEDS_TIMING1 V_IO_ALE_TO_WRITE(2) | \ 175 V_IO_WRITE_WIDTH(8) | \ 176 V_IO_IDLE_CYCLE(6) | \ 177 V_IO_CS_TO_OE(0) | \ 178 V_IO_OE_TO_CS(0) 179#define LEDS_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 180 181 182/* 183 * USB Channel 1: non-multiplexed, byte width, no parity, no ack 184 */ 185#define USB1_CS 4 186#define USB1_PHYS 0x100B0000 187#define USB1_SIZE NUM64K(4) 188#define USB1_TIMING0 V_IO_ALE_WIDTH(4) | \ 189 V_IO_ALE_TO_CS(2) | \ 190 V_IO_CS_WIDTH(13) | \ 191 V_IO_RDY_SMPLE(1) 192#define USB1_TIMING1 V_IO_ALE_TO_WRITE(2) | \ 193 V_IO_WRITE_WIDTH(8) | \ 194 V_IO_IDLE_CYCLE(6) | \ 195 V_IO_CS_TO_OE(0) | \ 196 V_IO_OE_TO_CS(0) 197#define USB1_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 198 199 200/* 201 * USB Channel 2: non-multiplexed, byte width, no parity, no ack 202 */ 203#define USB2_CS 5 204#define USB2_PHYS 0x100C0000 205#define USB2_SIZE NUM64K(4) 206#define USB2_TIMING0 V_IO_ALE_WIDTH(4) | \ 207 V_IO_ALE_TO_CS(2) | \ 208 V_IO_CS_WIDTH(13) | \ 209 V_IO_RDY_SMPLE(1) 210#define USB2_TIMING1 V_IO_ALE_TO_WRITE(2) | \ 211 V_IO_WRITE_WIDTH(8) | \ 212 V_IO_IDLE_CYCLE(6) | \ 213 V_IO_CS_TO_OE(0) | \ 214 V_IO_OE_TO_CS(0) 215#define USB2_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 216 217 218/* 219 * PCMCIA: this information was derived from chapter 12, table 12-5 220 */ 221#define PCMCIA_CS 6 222#define PCMCIA_PHYS 0x11000000 223#define PCMCIA_SIZE NUM64K(64*MB) 224#define PCMCIA_TIMING0 V_IO_ALE_WIDTH(3) | \ 225 V_IO_ALE_TO_CS(1) | \ 226 V_IO_CS_WIDTH(17) | \ 227 V_IO_RDY_SMPLE(1) 228#define PCMCIA_TIMING1 V_IO_ALE_TO_WRITE(8) | \ 229 V_IO_WRITE_WIDTH(8) | \ 230 V_IO_IDLE_CYCLE(2) | \ 231 V_IO_CS_TO_OE(0) | \ 232 V_IO_OE_TO_CS(0) 233#define PCMCIA_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_2) 234 235 236/* ********************************************************************* 237 * SMBus Devices 238 ********************************************************************* */ 239 240#define TEMPSENSOR_SMBUS_CHAN 0 241#define TEMPSENSOR_SMBUS_DEV 0x2A 242#define BIGEEPROM0_SMBUS_CHAN 0 243#define BIGEEPROM0_SMBUS_DEV 0x50 244 245#define M41T81_SMBUS_CHAN 1 246#define M41T81_SMBUS_DEV 0x68 247 248#define CY22393_SMBUS_CHAN 0 249#define CY22393_SMBUS_DEV 0x6A 250 251