1/* 2 * Copyright (c) 2017, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. 7 * Attn: Systems Group. 8 */ 9 10/** 11 * Interrupt map for TI OMAP4460 SoC 12 * 13 * This is derived from: 14 * OMAP4460 Multimedia Device Silicon Revision 1.x Technical Reference 15 * Manual Version Q 16 * 17 */ 18 19/* software generated interrupt domain (SGI) = 0-15 */ 20/* private peripheral interrupts domain (PPI) = 16-31 */ 21/* shared peripheral interrupts (SPI) = 32-.. */ 22 23 24A9_C0 is accept [ 25 0-1024 26] 27 28A9_C1 is accept [ 29 0-1024 30] 31 32A9_C0_IPI is map [ 33 0-15 to A9_C0 34] 35 36 37A9_C1_ipi is map [ 38 0-15 to A9_C1 39] 40 41GIC is map [ 42 32-1019 to A9_C0 43] 44 45/* Shared peripheral interrupts map */ 46SPIMap is map [ 47 0-987 to GIC at 32 48] 49 50/* M3 Subsystem */ 51 52M3INTC is accept [ 53 0-987 54] 55 56 57/* 58 * For A9: 59 * Section 17.3.1: Table 17-2. 60 * For M3: 61 * Section 17.3.3: Table 17-3. 62 */ 63L2_CACHE is map [ 64 0 to SPIMap at 0 65] 66 67CTI_0 is map [ 68 0 to SPIMap at 1 69] 70 71CTI_1 is map [ 72 0 to SPIMap at 2 73] 74 75ELM is map [ 76 0 to SPIMap at 4 77] 78 79CMU_P is map [ 80 0 to SPIMap at 5 81] 82 83 84SYS_NIRQ1 is map [ 85 0 to SPIMap at 7 86] 87 88 89L3_DBG is map [ 90 0 to SPIMap at 9 91] 92 93L3_APP is map [ 94 0 to SPIMap at 10 95] 96 97PRCM_MPU is map [ 98 0 to SPIMap at 11 99] 100 101/* four interrupts */ 102SDMA is map [ 103 0-3 to SPIMap at 12, M3INTC at 18 104] 105 106MCBSP4 is map [ 107 0 to SPIMap at 16 108] 109 110MCBSP1 is map [ 111 0 to SPIMap at 17 112] 113 114SR_MPU is map [ 115 0 to SPIMap at 18 116] 117 118SR_CORE is map [ 119 0 to SPIMap at 19 120] 121 122GPMC is map [ 123 0 to SPIMap at 20 124] 125 126SGX is map [ 127 0 to SPIMap at 21 128] 129 130MCBSP2 is map [ 131 0 to SPIMap at 22 132] 133 134MCBSP3 is map [ 135 0 to SPIMap at 23 136] 137 138ISS5 is map [ 139 0 to SPIMap at 24, M3INTC at 16 140] 141 142DSS_DISPC is map [ 143 0 to SPIMap at 25, M3INTC at 7 144] 145 146MAIL_U0_MPU is map [ 147 0 to SPIMap at 26 148] 149 150C2C_SSCM is map [ 151 0 to SPIMap at 27, M3INTC at 46 152 1 to SPIMap at 88, M3INTC at 47 153] 154 155DSP_MMU is map [ 156 0 to SPIMap at 28 157] 158 159GPIO1_MPU is map [ 160 0 to SPIMap at 29, M3INTC at 35 161] 162 163GPIO2_MPU is map [ 164 0 to SPIMap at 30, M3INTC at 36 165] 166 167GPIO3_MPU is map [ 168 0 to SPIMap at 31 169] 170 171GPIO4_MPU is map [ 172 0 to SPIMap at 32 173] 174 175GPIO5_MPU is map [ 176 0 to SPIMap at 33 177] 178 179GPIO6_MPU is map [ 180 0 to SPIMap at 34 181] 182 183 184WDT3 is map [ 185 0 to SPIMap at 36 186] 187 188GPT1 is map [ 189 0 to SPIMap at 37 190] 191 192GPT2 is map [ 193 0 to SPIMap at 38 194] 195 196GPT3 is map [ 197 0 to SPIMap at 39, M3INTC at 37 198] 199 200GPT4 is map [ 201 0 to SPIMap at 40, M3INTC at 38 202] 203 204GPT5 is map [ 205 0 to SPIMap at 41 206] 207 208GPT6 is map [ 209 0 to SPIMap at 42 210] 211 212GPT7 is map [ 213 0 to SPIMap at 43 214] 215 216GPT8 is map [ 217 0 to SPIMap at 44 218] 219 220GPT9 is map [ 221 0 to SPIMap at 45, M3INTC at 39 222] 223 224GPT10 is map [ 225 0 to SPIMap at 46 226] 227 228GPT11 is map [ 229 0 to SPIMap at 47, M3INTC at 40 230] 231 232DSS_DSI1 is map [ 233 0 to SPIMap at 53, M3INTC at 8 234] 235 236CORTEXA9_CPU0_PMU is map [ 237 0 to SPIMap at 54 238] 239 240CORTEXA9_CPU1_PMU is map [ 241 0 to SPIMap at 55 242] 243 244I2C is map [ 245 0 to SPIMap at 56, M3INTC at 25 246 1 to SPIMap at 57, M3INTC at 26 247 2 to SPIMap at 61, M3INTC at 27 248 3 to SPIMap at 62, M3INTC at 28 249] 250 251I2C2 is map [ 252] 253 254HDQ is map [ 255 0 to SPIMap at 58 256] 257 258MMC5 is map [ 259 0 to SPIMap at 59, M3INTC at 54 260] 261 262MCSPI is map [ 263 0 to SPIMap at 65, M3INTC at 41 264 1 to SPIMap at 66, M3INTC at 42 265 2 to SPIMap at 91 266 3 to SPIMap at 48 267] 268 269HSI_P1_MPU is map [ 270 0 to SPIMap at 67, M3INTC at 62 271] 272 273HSI_P2_MPU is map [ 274 0 to SPIMap at 68, M3INTC at 63 275] 276 277FDIF_3 is map [ 278 0 to SPIMap at 69 279] 280 281UART4 is map [ 282 0 to SPIMap at 70 283] 284 285HSI_DMA_MPU is map [ 286 0 to SPIMap at 71 287] 288 289UART1 is map [ 290 0 to SPIMap at 72 291] 292 293UART2 is map [ 294 0 to SPIMap at 73 295] 296 297UART3 is map [ 298 0 to SPIMap at 74, M3INTC at 29 299] 300 301PBIAS is map [ 302 0 to SPIMap at 75 303] 304 305HSUSB_OHCI is map [ 306 0 to SPIMap at 76 307] 308 309HSUSB_EHCI is map [ 310 0 to SPIMap at 77, M3INTC at 57 311] 312 313HSUSB_TLL is map [ 314 0 to SPIMap at 78, M3INTC at 58 315] 316 317 318WDT2 is map [ 319 0 to SPIMap at 80 320] 321 322 323 324MMC1 is map [ 325 0 to SPIMap at 83, M3INTC at 50 326] 327 328DSS_DSI2 is map [ 329 0 to SPIMap at 84, M3INTC at 9 330] 331 332 333MMC2 is map [ 334 0 to SPIMap at 86, M3INTC at 51 335] 336 337MPU_ICR is map [ 338 0 to SPIMap at 87 339] 340 341C2C_SSCM1 is map [ 342 0 to SPIMap at 88 343] 344 345FSUSB is map [ 346 0 to SPIMap at 89, M3INTC at 59 347] 348 349FSUSB_SMI is map [ 350 0 to SPIMap at 90, M3INTC at 56 351] 352 353HSUSB_OTG is map [ 354 0 to SPIMap at 92, M3INTC at 60 355] 356 357HSUSB_OTG_DMA is map [ 358 0 to SPIMap at 93, M3INTC at 61 359] 360 361MMC3 is map [ 362 0 to SPIMap at 94, M3INTC at 52 363] 364 365MMC4 is map [ 366 0 to SPIMap at 96, M3INTC at 53 367] 368 369SLIMBUS1 is map [ 370 0 to SPIMap at 97 371] 372 373SLIMBUS2 is map [ 374 0 to SPIMap at 98 375] 376 377ABE_MPU is map [ 378 0 to SPIMap at 99 379] 380 381CORTEXM3_MMU is map [ 382 0 to SPIMap at 100 383] 384 385DSS_HDMI is map [ 386 0 to SPIMap at 101, M3INTC at 10 387] 388 389SR_IVA is map [ 390 0 to SPIMap at 102 391] 392 393IVAHD2 is map [ 394 0 to SPIMap at 103, M3INTC at 23 395] 396 397IVAHD1 is map [ 398 0 to SPIMap at 104, M3INTC at 24 399] 400 401 402IVAHD_MAILBOX_0 is map [ 403 0 to SPIMap at 107 404] 405 406 407MCASP1_AXINT is map [ 408 0 to SPIMap at 109 409] 410 411EMIF1 is map [ 412 0 to SPIMap at 110 413] 414 415EMIF2 is map [ 416 0 to SPIMap at 111 417] 418 419MCPDM is map [ 420 0 to SPIMap at 112 421] 422 423DMM is map [ 424 0 to SPIMap at 113, M3INTC at 48 425] 426 427DMIC is map [ 428 0 to SPIMap at 114 429] 430 431SYS_NIRQ2 is map [ 432 0 to SPIMap at 119 433] 434 435KBD_CTL is map [ 436 0 to SPIMap at 120 437] 438 439THERMAL_ALERT is map [ 440 0 to SPIMap at 126 441] 442 443/* 444 * M3 Specific interrupts 445 */ 446XLATE_MMU_FAULT is map [ 447 0 to M3INTC at 0 448] 449 450SHARED_CACHE_MMU_CPU_INT is map [ 451 0 to M3INTC at 1 452] 453 454CTM_TIM_EVENT_1 is map [ 455 0 to M3INTC at 2 456] 457 458HWSEM_M3 is map [ 459 0 to M3INTC at 3 460] 461 462IC_NEMUINTR is map [ 463 0 to M3INTC at 4 464] 465 466IMP_FAULT is map [ 467 0 to M3INTC at 5 468] 469 470CTM_TIM_EVENT_2 is map [ 471 0 to M3INTC at 6 472] 473 474ISS0 is map [ 475 0 to M3INTC at 11 476] 477 478ISS1 is map [ 479 0 to M3INTC at 12 480] 481 482ISS2 is map [ 483 0 to M3INTC at 13 484] 485 486ISS3 is map [ 487 0 to M3INTC at 14 488] 489 490ISS4 is map [ 491 0 to M3INTC at 15 492] 493 494FDIF_1 is map [ 495 0(bla) to M3INTC at 17(blu) 496] 497 498IVAHD_MAILBOX_2 is map [ 499 0 to M3INTC at 22 500] 501 502PRCM_M3 is map [ 503 0 to M3INTC at 31 504] 505 506MAIL_U2_M3 is map [ 507 0 to M3INTC at 34 508] 509 510