1/* 2 * include/asm-mips/dec/kn05.h 3 * 4 * DECstation 5000/260 (4max+ or KN05) and DECsystem 5900-260 5 * definitions. 6 * 7 * Copyright (C) 2002 Maciej W. Rozycki 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 * 14 * WARNING! All this information is pure guesswork based on the 15 * ROM. It is provided here in hope it will give someone some 16 * food for thought. No documentation for the KN05 module has 17 * been located so far. 18 */ 19#ifndef __ASM_MIPS_DEC_KN05_H 20#define __ASM_MIPS_DEC_KN05_H 21 22#include <asm/dec/ioasic_addrs.h> 23 24/* 25 * The oncard MB (Memory Buffer) ASIC provides an additional address 26 * decoder. Certain address ranges within the "high" 16 slots are 27 * passed to the I/O ASIC's decoder like with the KN03. Others are 28 * handled locally. "Low" slots are always passed. 29 */ 30#define KN05_MB_ROM (16*IOASIC_SLOT_SIZE) /* KN05 card ROM */ 31#define KN05_IOCTL (17*IOASIC_SLOT_SIZE) /* I/O ASIC */ 32#define KN05_ESAR (18*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */ 33#define KN05_LANCE (19*IOASIC_SLOT_SIZE) /* LANCE Ethernet */ 34#define KN05_MB_INT (20*IOASIC_SLOT_SIZE) /* MB interrupt register? */ 35#define KN05_MB_UNKN_0 (21*IOASIC_SLOT_SIZE) /* MB unknown register */ 36#define KN05_MB_UNKN_1 (22*IOASIC_SLOT_SIZE) /* MB unknown register */ 37#define KN05_MB_CSR (23*IOASIC_SLOT_SIZE) /* MB control & status */ 38#define KN05_RESERVED_0 (24*IOASIC_SLOT_SIZE) /* unused? */ 39#define KN05_RESERVED_1 (25*IOASIC_SLOT_SIZE) /* unused? */ 40#define KN05_RESERVED_2 (26*IOASIC_SLOT_SIZE) /* unused? */ 41#define KN05_RESERVED_3 (27*IOASIC_SLOT_SIZE) /* unused? */ 42#define KN05_SCSI (28*IOASIC_SLOT_SIZE) /* ASC SCSI */ 43#define KN05_RESERVED_4 (29*IOASIC_SLOT_SIZE) /* unused? */ 44#define KN05_RESERVED_5 (30*IOASIC_SLOT_SIZE) /* unused? */ 45#define KN05_RESERVED_6 (31*IOASIC_SLOT_SIZE) /* unused? */ 46 47/* 48 * Bits for the MB interrupt (?) register. 49 * The register appears read-only. 50 */ 51#define KN05_MB_INT_TC (1<<0) /* TURBOchannel? */ 52#define KN05_MB_INT_RTC (1<<1) /* RTC? */ 53 54/* 55 * Bits for the MB control & status register. 56 * Set to 0x00bf8001 on my system by the ROM. 57 */ 58#define KN05_MB_CSR_PF (1<<0) /* ??? */ 59#define KN05_MB_CSR_F (1<<1) /* ??? */ 60#define KN05_MB_CSR_ECC (0xff<<2) /* ??? */ 61#define KN05_MB_CSR_OD (1<<10) /* ??? */ 62#define KN05_MB_CSR_CP (1<<11) /* ??? */ 63#define KN05_MB_CSR_UNC (1<<12) /* ??? */ 64#define KN05_MB_CSR_IM (1<<13) /* ??? */ 65#define KN05_MB_CSR_NC (1<<14) /* ??? */ 66#define KN05_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ 67#define KN05_MB_CSR_MSK (0x1f<<16) /* ??? */ 68#define KN05_MB_CSR_FW (1<<21) /* ??? */ 69 70#endif /* __ASM_MIPS_DEC_KN05_H */ 71