1/* $Id: intr.h,v 1.1.1.1 2008/10/15 03:27:17 james26_jang Exp $ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. 8 */ 9#ifndef _ASM_IA64_SN_SN1_INTR_H 10#define _ASM_IA64_SN_SN1_INTR_H 11 12/* Subnode wildcard */ 13#define SUBNODE_ANY (-1) 14 15/* Number of interrupt levels associated with each interrupt register. */ 16#define N_INTPEND_BITS 64 17 18#define INT_PEND0_BASELVL 0 19#define INT_PEND1_BASELVL 64 20 21#define N_INTPENDJUNK_BITS 8 22#define INTPENDJUNK_CLRBIT 0x80 23 24#include <asm/sn/intr_public.h> 25#include <asm/sn/driver.h> 26#include <asm/sn/xtalk/xtalk.h> 27#include <asm/sn/hack.h> 28 29#ifndef __ASSEMBLY__ 30#define II_NAMELEN 24 31 32/* 33 * Dispatch table entry - contains information needed to call an interrupt 34 * routine. 35 */ 36typedef struct intr_vector_s { 37 intr_func_t iv_func; /* Interrupt handler function */ 38 intr_func_t iv_prefunc; /* Interrupt handler prologue func */ 39 void *iv_arg; /* Argument to pass to handler */ 40 cpuid_t iv_mustruncpu; /* Where we must run. */ 41} intr_vector_t; 42 43/* Interrupt information table. */ 44typedef struct intr_info_s { 45 xtalk_intr_setfunc_t ii_setfunc; /* Function to set the interrupt 46 * destination and level register. 47 * It returns 0 (success) or an 48 * error code. 49 */ 50 void *ii_cookie; /* arg passed to setfunc */ 51 devfs_handle_t ii_owner_dev; /* device that owns this intr */ 52 char ii_name[II_NAMELEN]; /* Name of this intr. */ 53 int ii_flags; /* informational flags */ 54} intr_info_t; 55 56 57#define THD_CREATED 0x00000001 /* 58 * We've created a thread for this 59 * interrupt. 60 */ 61 62/* 63 * Bits for ii_flags: 64 */ 65#define II_UNRESERVE 0 66#define II_RESERVE 1 /* Interrupt reserved. */ 67#define II_INUSE 2 /* Interrupt connected */ 68#define II_ERRORINT 4 /* INterrupt is an error condition */ 69#define II_THREADED 8 /* Interrupt handler is threaded. */ 70 71/* 72 * Interrupt level wildcard 73 */ 74#define INTRCONNECT_ANYBIT (-1) 75 76/* 77 * This structure holds information needed both to call and to maintain 78 * interrupts. The two are in separate arrays for the locality benefits. 79 * Since there's only one set of vectors per hub chip (but more than one 80 * CPU, the lock to change the vector tables must be here rather than in 81 * the PDA. 82 */ 83 84typedef struct intr_vecblk_s { 85 intr_vector_t vectors[N_INTPEND_BITS]; /* information needed to 86 call an intr routine. */ 87 intr_info_t info[N_INTPEND_BITS]; /* information needed only 88 to maintain interrupts. */ 89 spinlock_t vector_lock; /* Lock for this and the 90 masks in the PDA. */ 91 splfunc_t vector_spl; /* vector_lock req'd spl */ 92 int vector_state; /* Initialized to zero. 93 Set to INTR_INITED 94 by hubintr_init. 95 */ 96 int vector_count; /* Number of vectors 97 * reserved. 98 */ 99 int cpu_count[CPUS_PER_SUBNODE]; /* How many interrupts are 100 * connected to each CPU 101 */ 102 int ithreads_enabled; /* Are interrupt threads 103 * initialized on this node. 104 * and block? 105 */ 106} intr_vecblk_t; 107 108/* Possible values for vector_state: */ 109#define VECTOR_UNINITED 0 110#define VECTOR_INITED 1 111#define VECTOR_SET 2 112 113#define hub_intrvect0 private.p_intmasks.dispatch0->vectors 114#define hub_intrvect1 private.p_intmasks.dispatch1->vectors 115#define hub_intrinfo0 private.p_intmasks.dispatch0->info 116#define hub_intrinfo1 private.p_intmasks.dispatch1->info 117 118/* 119 * Macros to manipulate the interrupt register on the calling hub chip. 120 */ 121 122#define LOCAL_HUB_SEND_INTR(_level) LOCAL_HUB_S(PI_INT_PEND_MOD, \ 123 (0x100|(_level))) 124#define REMOTE_HUB_PI_SEND_INTR(_hub, _sn, _level) \ 125 REMOTE_HUB_PI_S((_hub), _sn, PI_INT_PEND_MOD, (0x100|(_level))) 126 127#define REMOTE_CPU_SEND_INTR(_cpuid, _level) \ 128 REMOTE_HUB_PI_S(cpuid_to_nasid(_cpuid), \ 129 SUBNODE(cpuid_to_slice(_cpuid)), \ 130 PI_INT_PEND_MOD, (0x100|(_level))) 131 132/* 133 * When clearing the interrupt, make sure this clear does make it 134 * to the hub. Otherwise we could end up losing interrupts. 135 * We do an uncached load of the int_pend0 register to ensure this. 136 */ 137 138#define LOCAL_HUB_CLR_INTR(_level) \ 139 LOCAL_HUB_S(PI_INT_PEND_MOD, (_level)), \ 140 LOCAL_HUB_L(PI_INT_PEND0) 141#define REMOTE_HUB_PI_CLR_INTR(_hub, _sn, _level) \ 142 REMOTE_HUB_PI_S((_hub), (_sn), PI_INT_PEND_MOD, (_level)), \ 143 REMOTE_HUB_PI_L((_hub), (_sn), PI_INT_PEND0) 144 145/* Special support for use by gfx driver only. Supports special gfx hub interrupt. */ 146extern void install_gfxintr(cpuid_t cpu, ilvl_t swlevel, intr_func_t intr_func, void *intr_arg); 147 148void setrtvector(intr_func_t func); 149 150/* 151 * Interrupt blocking 152 */ 153extern void intr_block_bit(cpuid_t cpu, int bit); 154extern void intr_unblock_bit(cpuid_t cpu, int bit); 155 156#endif /* __ASSEMBLY__ */ 157 158/* 159 * Hard-coded interrupt levels: 160 */ 161 162/* 163 * L0 = SW1 164 * L1 = SW2 165 * L2 = INT_PEND0 166 * L3 = INT_PEND1 167 * L4 = RTC 168 * L5 = Profiling Timer 169 * L6 = Hub Errors 170 * L7 = Count/Compare (T5 counters) 171 */ 172 173 174/* INT_PEND0 hard-coded bits. */ 175#ifdef DEBUG_INTR_TSTAMP 176/* hard coded interrupt level for interrupt latency test interrupt */ 177#define CPU_INTRLAT_B 62 178#define CPU_INTRLAT_A 61 179#endif 180 181/* Hardcoded bits required by software. */ 182#define MSC_MESG_INTR 9 183#define CPU_ACTION_B 8 184#define CPU_ACTION_A 7 185 186/* These are determined by hardware: */ 187#define CC_PEND_B 6 188#define CC_PEND_A 5 189#define UART_INTR 4 190#define PG_MIG_INTR 3 191#define GFX_INTR_B 2 192#define GFX_INTR_A 1 193#define RESERVED_INTR 0 194 195/* INT_PEND1 hard-coded bits: */ 196#define MSC_PANIC_INTR 63 197#define NI_ERROR_INTR 62 198#define MD_COR_ERR_INTR 61 199#define COR_ERR_INTR_B 60 200#define COR_ERR_INTR_A 59 201#define CLK_ERR_INTR 58 202 203# define NACK_INT_B 57 204# define NACK_INT_A 56 205# define LB_ERROR 55 206# define XB_ERROR 54 207 208#define BRIDGE_ERROR_INTR 53 /* Setup by PROM to catch Bridge Errors */ 209 210#define IP27_INTR_0 52 /* Reserved for PROM use */ 211#define IP27_INTR_1 51 /* (do not use in Kernel) */ 212#define IP27_INTR_2 50 213#define IP27_INTR_3 49 214#define IP27_INTR_4 48 215#define IP27_INTR_5 47 216#define IP27_INTR_6 46 217#define IP27_INTR_7 45 218 219#define TLB_INTR_B 44 /* used for tlb flush random */ 220#define TLB_INTR_A 43 221 222#define LLP_PFAIL_INTR_B 42 /* see ml/SN/SN0/sysctlr.c */ 223#define LLP_PFAIL_INTR_A 41 224 225#define NI_BRDCAST_ERR_B 40 226#define NI_BRDCAST_ERR_A 39 227 228# define IO_ERROR_INTR 38 /* set up by prom */ 229# define DEBUG_INTR_B 37 /* used by symmon to stop all cpus */ 230# define DEBUG_INTR_A 36 231 232// These aren't strictly accurate or complete. See the 233// Synergy Spec. for details. 234#define SGI_UART_IRQ (65) 235#define SGI_HUB_ERROR_IRQ (182) 236 237#endif /* _ASM_IA64_SN_SN1_INTR_H */ 238