1/* $Id: pcibr.h,v 1.1.1.1 2008/10/15 03:27:17 james26_jang Exp $ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. 8 */ 9#ifndef _ASM_SN_PCI_PCIBR_H 10#define _ASM_SN_PCI_PCIBR_H 11 12#if defined(__KERNEL__) 13 14#include <asm/sn/dmamap.h> 15#include <asm/sn/driver.h> 16#include <asm/sn/pio.h> 17 18#include <asm/sn/pci/pciio.h> 19#include <asm/sn/pci/bridge.h> 20 21/* ===================================================================== 22 * symbolic constants used by pcibr's xtalk bus provider 23 */ 24 25#define PCIBR_PIOMAP_BUSY 0x80000000 26 27#define PCIBR_DMAMAP_BUSY 0x80000000 28#define PCIBR_DMAMAP_SSRAM 0x40000000 29 30#define PCIBR_INTR_BLOCKED 0x40000000 31#define PCIBR_INTR_BUSY 0x80000000 32 33#ifndef __ASSEMBLY__ 34 35/* ===================================================================== 36 * opaque types used by pcibr's xtalk bus provider 37 */ 38 39typedef struct pcibr_piomap_s *pcibr_piomap_t; 40typedef struct pcibr_dmamap_s *pcibr_dmamap_t; 41typedef struct pcibr_intr_s *pcibr_intr_t; 42 43/* ===================================================================== 44 * primary entry points: Bridge (pcibr) device driver 45 * 46 * These functions are normal device driver entry points 47 * and are called along with the similar entry points from 48 * other device drivers. They are included here as documentation 49 * of their existence and purpose. 50 * 51 * pcibr_init() is called to inform us that there is a pcibr driver 52 * configured into the kernel; it is responsible for registering 53 * as a crosstalk widget and providing a routine to be called 54 * when a widget with the proper part number is observed. 55 * 56 * pcibr_attach() is called for each vertex in the hardware graph 57 * corresponding to a crosstalk widget with the manufacturer 58 * code and part number registered by pcibr_init(). 59 */ 60 61extern void pcibr_init(void); 62 63extern int pcibr_attach(devfs_handle_t); 64 65/* ===================================================================== 66 * bus provider function table 67 * 68 * Normally, this table is only handed off explicitly 69 * during provider initialization, and the PCI generic 70 * layer will stash a pointer to it in the vertex; however, 71 * exporting it explicitly enables a performance hack in 72 * the generic PCI provider where if we know at compile 73 * time that the only possible PCI provider is a 74 * pcibr, we can go directly to this ops table. 75 */ 76 77extern pciio_provider_t pcibr_provider; 78 79/* ===================================================================== 80 * secondary entry points: pcibr PCI bus provider 81 * 82 * These functions are normally exported explicitly by 83 * a direct call from the pcibr initialization routine 84 * into the generic crosstalk provider; they are included 85 * here to enable a more aggressive performance hack in 86 * the generic crosstalk layer, where if we know that the 87 * only possible crosstalk provider is pcibr, and we can 88 * guarantee that all entry points are properly named, and 89 * we can deal with the implicit casting properly, then 90 * we can turn many of the generic provider routines into 91 * plain brances, or even eliminate them (given sufficient 92 * smarts on the part of the compilation system). 93 */ 94 95extern pcibr_piomap_t pcibr_piomap_alloc(devfs_handle_t dev, 96 device_desc_t dev_desc, 97 pciio_space_t space, 98 iopaddr_t pci_addr, 99 size_t byte_count, 100 size_t byte_count_max, 101 unsigned flags); 102 103extern void pcibr_piomap_free(pcibr_piomap_t piomap); 104 105extern caddr_t pcibr_piomap_addr(pcibr_piomap_t piomap, 106 iopaddr_t xtalk_addr, 107 size_t byte_count); 108 109extern void pcibr_piomap_done(pcibr_piomap_t piomap); 110 111extern caddr_t pcibr_piotrans_addr(devfs_handle_t dev, 112 device_desc_t dev_desc, 113 pciio_space_t space, 114 iopaddr_t pci_addr, 115 size_t byte_count, 116 unsigned flags); 117 118extern iopaddr_t pcibr_piospace_alloc(devfs_handle_t dev, 119 device_desc_t dev_desc, 120 pciio_space_t space, 121 size_t byte_count, 122 size_t alignment); 123extern void pcibr_piospace_free(devfs_handle_t dev, 124 pciio_space_t space, 125 iopaddr_t pciaddr, 126 size_t byte_count); 127 128extern pcibr_dmamap_t pcibr_dmamap_alloc(devfs_handle_t dev, 129 device_desc_t dev_desc, 130 size_t byte_count_max, 131 unsigned flags); 132 133extern void pcibr_dmamap_free(pcibr_dmamap_t dmamap); 134 135extern iopaddr_t pcibr_dmamap_addr(pcibr_dmamap_t dmamap, 136 paddr_t paddr, 137 size_t byte_count); 138 139extern alenlist_t pcibr_dmamap_list(pcibr_dmamap_t dmamap, 140 alenlist_t palenlist, 141 unsigned flags); 142 143extern void pcibr_dmamap_done(pcibr_dmamap_t dmamap); 144 145/* 146 * pcibr_get_dmatrans_node() will return the compact node id to which 147 * all 32-bit Direct Mapping memory accesses will be directed. 148 * (This node id can be different for each PCI bus.) 149 */ 150 151extern cnodeid_t pcibr_get_dmatrans_node(devfs_handle_t pconn_vhdl); 152 153extern iopaddr_t pcibr_dmatrans_addr(devfs_handle_t dev, 154 device_desc_t dev_desc, 155 paddr_t paddr, 156 size_t byte_count, 157 unsigned flags); 158 159extern alenlist_t pcibr_dmatrans_list(devfs_handle_t dev, 160 device_desc_t dev_desc, 161 alenlist_t palenlist, 162 unsigned flags); 163 164extern void pcibr_dmamap_drain(pcibr_dmamap_t map); 165 166extern void pcibr_dmaaddr_drain(devfs_handle_t vhdl, 167 paddr_t addr, 168 size_t bytes); 169 170extern void pcibr_dmalist_drain(devfs_handle_t vhdl, 171 alenlist_t list); 172 173typedef unsigned pcibr_intr_ibit_f(pciio_info_t info, 174 pciio_intr_line_t lines); 175 176extern void pcibr_intr_ibit_set(devfs_handle_t, pcibr_intr_ibit_f *); 177 178extern pcibr_intr_t pcibr_intr_alloc(devfs_handle_t dev, 179 device_desc_t dev_desc, 180 pciio_intr_line_t lines, 181 devfs_handle_t owner_dev); 182 183extern void pcibr_intr_free(pcibr_intr_t intr); 184 185extern int pcibr_intr_connect(pcibr_intr_t intr); 186 187extern void pcibr_intr_disconnect(pcibr_intr_t intr); 188 189extern devfs_handle_t pcibr_intr_cpu_get(pcibr_intr_t intr); 190 191extern void pcibr_provider_startup(devfs_handle_t pcibr); 192 193extern void pcibr_provider_shutdown(devfs_handle_t pcibr); 194 195extern int pcibr_reset(devfs_handle_t dev); 196 197extern int pcibr_write_gather_flush(devfs_handle_t dev); 198 199extern pciio_endian_t pcibr_endian_set(devfs_handle_t dev, 200 pciio_endian_t device_end, 201 pciio_endian_t desired_end); 202 203extern pciio_priority_t pcibr_priority_set(devfs_handle_t dev, 204 pciio_priority_t device_prio); 205 206extern uint64_t pcibr_config_get(devfs_handle_t conn, 207 unsigned reg, 208 unsigned size); 209 210extern void pcibr_config_set(devfs_handle_t conn, 211 unsigned reg, 212 unsigned size, 213 uint64_t value); 214 215extern int pcibr_error_devenable(devfs_handle_t pconn_vhdl, 216 int error_code); 217 218extern pciio_slot_t pcibr_error_extract(devfs_handle_t pcibr_vhdl, 219 pciio_space_t *spacep, 220 iopaddr_t *addrp); 221 222extern int pcibr_wrb_flush(devfs_handle_t pconn_vhdl); 223extern int pcibr_rrb_check(devfs_handle_t pconn_vhdl, 224 int *count_vchan0, 225 int *count_vchan1, 226 int *count_reserved, 227 int *count_pool); 228 229extern int pcibr_alloc_all_rrbs(devfs_handle_t vhdl, int even_odd, 230 int dev_1_rrbs, int virt1, 231 int dev_2_rrbs, int virt2, 232 int dev_3_rrbs, int virt3, 233 int dev_4_rrbs, int virt4); 234 235typedef void 236rrb_alloc_funct_f (devfs_handle_t xconn_vhdl, 237 int *vendor_list); 238 239typedef rrb_alloc_funct_f *rrb_alloc_funct_t; 240 241void pcibr_set_rrb_callback(devfs_handle_t xconn_vhdl, 242 rrb_alloc_funct_f *func); 243 244extern int pcibr_device_unregister(devfs_handle_t); 245extern int pcibr_dma_enabled(devfs_handle_t); 246/* 247 * Bridge-specific flags that can be set via pcibr_device_flags_set 248 * and cleared via pcibr_device_flags_clear. Other flags are 249 * more generic and are maniuplated through PCI-generic interfaces. 250 * 251 * Note that all PCI implementation-specific flags (Bridge flags, in 252 * this case) are in bits 15-31. The lower 15 bits are reserved 253 * for PCI-generic flags. 254 * 255 * Some of these flags have been "promoted" to the 256 * generic layer, so they can be used without having 257 * to "know" that the PCI bus is hosted by a Bridge. 258 * 259 * PCIBR_NO_ATE_ROUNDUP: Request that no rounding up be done when 260 * allocating ATE's. ATE count computation will assume that the 261 * address to be mapped will start on a page boundary. 262 */ 263#define PCIBR_NO_ATE_ROUNDUP 0x00008000 264#define PCIBR_WRITE_GATHER 0x00010000 /* please use PCIIO version */ 265#define PCIBR_NOWRITE_GATHER 0x00020000 /* please use PCIIO version */ 266#define PCIBR_PREFETCH 0x00040000 /* please use PCIIO version */ 267#define PCIBR_NOPREFETCH 0x00080000 /* please use PCIIO version */ 268#define PCIBR_PRECISE 0x00100000 269#define PCIBR_NOPRECISE 0x00200000 270#define PCIBR_BARRIER 0x00400000 271#define PCIBR_NOBARRIER 0x00800000 272#define PCIBR_VCHAN0 0x01000000 273#define PCIBR_VCHAN1 0x02000000 274#define PCIBR_64BIT 0x04000000 275#define PCIBR_NO64BIT 0x08000000 276#define PCIBR_SWAP 0x10000000 277#define PCIBR_NOSWAP 0x20000000 278 279#define PCIBR_EXTERNAL_ATES 0x40000000 /* uses external ATEs */ 280#define PCIBR_ACTIVE 0x80000000 /* need a "done" */ 281 282/* Flags that have meaning to pcibr_device_flags_{set,clear} */ 283#define PCIBR_DEVICE_FLAGS ( \ 284 PCIBR_WRITE_GATHER |\ 285 PCIBR_NOWRITE_GATHER |\ 286 PCIBR_PREFETCH |\ 287 PCIBR_NOPREFETCH |\ 288 PCIBR_PRECISE |\ 289 PCIBR_NOPRECISE |\ 290 PCIBR_BARRIER |\ 291 PCIBR_NOBARRIER \ 292) 293 294/* Flags that have meaning to *_dmamap_alloc, *_dmatrans_{addr,list} */ 295#define PCIBR_DMA_FLAGS ( \ 296 PCIBR_PREFETCH |\ 297 PCIBR_NOPREFETCH |\ 298 PCIBR_PRECISE |\ 299 PCIBR_NOPRECISE |\ 300 PCIBR_BARRIER |\ 301 PCIBR_NOBARRIER |\ 302 PCIBR_VCHAN0 |\ 303 PCIBR_VCHAN1 \ 304) 305 306typedef int pcibr_device_flags_t; 307 308/* 309 * Set bits in the Bridge Device(x) register for this device. 310 * "flags" are defined above. NOTE: this includes turning 311 * things *OFF* as well as turning them *ON* ... 312 */ 313extern int pcibr_device_flags_set(devfs_handle_t dev, 314 pcibr_device_flags_t flags); 315 316/* 317 * Allocate Read Response Buffers for use by the specified device. 318 * count_vchan0 is the total number of buffers desired for the 319 * "normal" channel. count_vchan1 is the total number of buffers 320 * desired for the "virtual" channel. Returns 0 on success, or 321 * <0 on failure, which occurs when we're unable to allocate any 322 * buffers to a channel that desires at least one buffer. 323 */ 324extern int pcibr_rrb_alloc(devfs_handle_t pconn_vhdl, 325 int *count_vchan0, 326 int *count_vchan1); 327 328/* 329 * Get the starting PCIbus address out of the given DMA map. 330 * This function is supposed to be used by a close friend of PCI bridge 331 * since it relies on the fact that the starting address of the map is fixed at 332 * the allocation time in the current implementation of PCI bridge. 333 */ 334extern iopaddr_t pcibr_dmamap_pciaddr_get(pcibr_dmamap_t); 335 336extern xwidget_intr_preset_f pcibr_xintr_preset; 337 338extern void pcibr_hints_fix_rrbs(devfs_handle_t); 339extern void pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t); 340extern void pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, ulong); 341extern void pcibr_hints_handsoff(devfs_handle_t); 342 343typedef unsigned pcibr_intr_bits_f(pciio_info_t, pciio_intr_line_t); 344extern void pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *); 345 346extern int pcibr_asic_rev(devfs_handle_t); 347 348#endif /* __ASSEMBLY__ */ 349#endif /* #if defined(__KERNEL__) */ 350/* 351 * Some useful ioctls into the pcibr driver 352 */ 353#define PCIBR 'p' 354#define _PCIBR(x) ((PCIBR << 8) | (x)) 355 356#define PCIBR_SLOT_STARTUP _PCIBR(1) 357#define PCIBR_SLOT_SHUTDOWN _PCIBR(2) 358#define PCIBR_SLOT_QUERY _PCIBR(3) 359 360/* 361 * Bit defintions for variable slot_status in struct 362 * pcibr_soft_slot_s. They are here so that both 363 * the pcibr driver and the pciconfig command can 364 * reference them. 365 */ 366#define SLOT_STARTUP_CMPLT 0x01 367#define SLOT_STARTUP_INCMPLT 0x02 368#define SLOT_SHUTDOWN_CMPLT 0x04 369#define SLOT_SHUTDOWN_INCMPLT 0x08 370#define SLOT_POWER_UP 0x10 371#define SLOT_POWER_DOWN 0x20 372#define SLOT_IS_SYS_CRITICAL 0x40 373 374#define SLOT_STATUS_MASK (SLOT_STARTUP_CMPLT | SLOT_STARTUP_INCMPLT | \ 375 SLOT_SHUTDOWN_CMPLT | SLOT_SHUTDOWN_INCMPLT) 376#define SLOT_POWER_MASK (SLOT_POWER_UP | SLOT_POWER_DOWN) 377 378/* 379 * Bit definitions for variable resp_f_staus. 380 * They are here so that both the pcibr driver 381 * and the pciconfig command can reference them. 382 */ 383#define FUNC_IS_VALID 0x01 384#define FUNC_IS_SYS_CRITICAL 0x02 385 386/* 387 * Structures for requesting PCI bridge information and receiving a response 388 */ 389typedef struct pcibr_slot_req_s *pcibr_slot_req_t; 390typedef struct pcibr_slot_up_resp_s *pcibr_slot_up_resp_t; 391typedef struct pcibr_slot_down_resp_s *pcibr_slot_down_resp_t; 392typedef struct pcibr_slot_info_resp_s *pcibr_slot_info_resp_t; 393typedef struct pcibr_slot_func_info_resp_s *pcibr_slot_func_info_resp_t; 394 395#define L1_QSIZE 128 /* our L1 message buffer size */ 396struct pcibr_slot_req_s { 397 int req_slot; 398 union { 399 pcibr_slot_up_resp_t up; 400 pcibr_slot_down_resp_t down; 401 pcibr_slot_info_resp_t query; 402 void *any; 403 } req_respp; 404 int req_size; 405}; 406 407struct pcibr_slot_up_resp_s { 408 int resp_sub_errno; 409 char resp_l1_msg[L1_QSIZE + 1]; 410}; 411 412struct pcibr_slot_down_resp_s { 413 int resp_sub_errno; 414 char resp_l1_msg[L1_QSIZE + 1]; 415}; 416 417struct pcibr_slot_info_req_s { 418 int req_slot; 419 pcibr_slot_info_resp_t req_respp; 420 int req_size; 421}; 422 423struct pcibr_slot_info_resp_s { 424 int resp_has_host; 425 char resp_host_slot; 426 devfs_handle_t resp_slot_conn; 427 char resp_slot_conn_name[MAXDEVNAME]; 428 int resp_slot_status; 429 int resp_l1_bus_num; 430 int resp_bss_ninfo; 431 char resp_bss_devio_bssd_space[16]; 432 iopaddr_t resp_bss_devio_bssd_base; 433 bridgereg_t resp_bss_device; 434 int resp_bss_pmu_uctr; 435 int resp_bss_d32_uctr; 436 int resp_bss_d64_uctr; 437 iopaddr_t resp_bss_d64_base; 438 unsigned resp_bss_d64_flags; 439 iopaddr_t resp_bss_d32_base; 440 unsigned resp_bss_d32_flags; 441 int resp_bss_ext_ates_active; 442 volatile unsigned *resp_bss_cmd_pointer; 443 unsigned resp_bss_cmd_shadow; 444 int resp_bs_rrb_valid; 445 int resp_bs_rrb_valid_v; 446 int resp_bs_rrb_res; 447 bridgereg_t resp_b_resp; 448 bridgereg_t resp_b_int_device; 449 bridgereg_t resp_b_int_enable; 450 bridgereg_t resp_b_int_host; 451 452 struct pcibr_slot_func_info_resp_s { 453 int resp_f_status; 454 char resp_f_slot_name[MAXDEVNAME]; 455 char resp_f_bus; 456 char resp_f_slot; 457 char resp_f_func; 458 char resp_f_master_name[MAXDEVNAME]; 459 void *resp_f_pops; 460 error_handler_f *resp_f_efunc; 461 error_handler_arg_t resp_f_einfo; 462 int resp_f_vendor; 463 int resp_f_device; 464 465 struct { 466 char resp_w_space[16]; 467 iopaddr_t resp_w_base; 468 size_t resp_w_size; 469 } resp_f_window[6]; 470 471 unsigned resp_f_rbase; 472 unsigned resp_f_rsize; 473 int resp_f_ibit[4]; 474 int resp_f_att_det_error; 475 476 } resp_func[8]; 477}; 478 479 480/* 481 * PCI specific errors, interpreted by pciconfig command 482 */ 483 484/* EPERM 1 */ 485#define PCI_SLOT_ALREADY_UP 2 /* slot already up */ 486#define PCI_SLOT_ALREADY_DOWN 3 /* slot already down */ 487#define PCI_IS_SYS_CRITICAL 4 /* slot is system critical */ 488/* EIO 5 */ 489/* ENXIO 6 */ 490#define PCI_L1_ERR 7 /* L1 console command error */ 491#define PCI_NOT_A_BRIDGE 8 /* device is not a bridge */ 492#define PCI_SLOT_IN_SHOEHORN 9 /* slot is in a shorhorn */ 493#define PCI_NOT_A_SLOT 10 /* slot is invalid */ 494#define PCI_RESP_AREA_TOO_SMALL 11 /* slot is invalid */ 495/* ENOMEM 12 */ 496#define PCI_NO_DRIVER 13 /* no driver for device */ 497/* EFAULT 14 */ 498#define PCI_EMPTY_33MHZ 15 /* empty 33 MHz bus */ 499/* EBUSY 16 */ 500#define PCI_SLOT_RESET_ERR 17 /* slot reset error */ 501#define PCI_SLOT_INFO_INIT_ERR 18 /* slot info init error */ 502/* ENODEV 19 */ 503#define PCI_SLOT_ADDR_INIT_ERR 20 /* slot addr space init error */ 504#define PCI_SLOT_DEV_INIT_ERR 21 /* slot device init error */ 505/* EINVAL 22 */ 506#define PCI_SLOT_GUEST_INIT_ERR 23 /* slot guest info init error */ 507#define PCI_SLOT_RRB_ALLOC_ERR 24 /* slot initial rrb alloc error */ 508#define PCI_SLOT_DRV_ATTACH_ERR 25 /* driver attach error */ 509#define PCI_SLOT_DRV_DETACH_ERR 26 /* driver detach error */ 510/* ERANGE 34 */ 511/* EUNATCH 42 */ 512 513#endif /* _ASM_SN_PCI_PCIBR_H */ 514