1/* 2 * linux/drivers/ide/serverworks.c Version 0.3 26 Oct 2001 3 * 4 * May be copied or modified under the terms of the GNU General Public License 5 * 6 * Copyright (C) 1998-2000 Michel Aubry 7 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz 8 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 9 * Portions copyright (c) 2001 Sun Microsystems 10 * 11 * 12 * RCC/ServerWorks IDE driver for Linux 13 * 14 * OSB4: `Open South Bridge' IDE Interface (fn 1) 15 * supports UDMA mode 2 (33 MB/s) 16 * 17 * CSB5: `Champion South Bridge' IDE Interface (fn 1) 18 * all revisions support UDMA mode 4 (66 MB/s) 19 * revision A2.0 and up support UDMA mode 5 (100 MB/s) 20 * 21 * *** The CSB5 does not provide ANY register *** 22 * *** to detect 80-conductor cable presence. *** 23 * 24 * 25 * here's the default lspci: 26 * 27 * 00:0f.1 IDE interface: ServerWorks: Unknown device 0211 (prog-if 8a [Master SecP PriP]) 28 * Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- 29 * Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- 30 * Latency: 255 31 * Region 4: I/O ports at c200 32 * 00: 66 11 11 02 05 01 00 02 00 8a 01 01 00 ff 80 00 33 * 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 34 * 20: 01 c2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 35 * 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 36 * 40: 99 99 99 99 ff ff ff ff 0c 0c 00 00 00 00 00 00 37 * 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 38 * 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 39 * 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 * 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 41 * 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 42 * a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 43 * b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 44 * c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 45 * d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 46 * e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 47 * f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 48 * 49 * 00:0f.1 IDE interface: ServerWorks: Unknown device 0212 (rev 92) (prog-if 8a [Master SecP PriP]) 50 * Subsystem: ServerWorks: Unknown device 0212 51 * Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- 52 * Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- 53 * Latency: 64, cache line size 08 54 * Region 0: I/O ports at 01f0 55 * Region 1: I/O ports at 03f4 56 * Region 2: I/O ports at 0170 57 * Region 3: I/O ports at 0374 58 * Region 4: I/O ports at 08b0 59 * Region 5: I/O ports at 1000 60 * 61 * 00:0f.1 IDE interface: ServerWorks: Unknown device 0212 (rev 92) 62 * 00: 66 11 12 02 05 00 00 02 92 8a 01 01 08 40 80 00 63 * 10: f1 01 00 00 f5 03 00 00 71 01 00 00 75 03 00 00 64 * 20: b1 08 00 00 01 10 00 00 00 00 00 00 66 11 12 02 65 * 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 66 * 40: 4f 4f 4f 4f 20 ff ff ff f0 50 44 44 00 00 00 00 67 * 50: 00 00 00 00 07 00 44 02 0f 04 03 00 00 00 00 00 68 * 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 69 * 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 * 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 71 * 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 72 * a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 73 * b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 74 * c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 75 * d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 76 * e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 77 * f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 78 * 79 * 80 */ 81 82#include <linux/config.h> 83#include <linux/types.h> 84#include <linux/kernel.h> 85#include <linux/ioport.h> 86#include <linux/pci.h> 87#include <linux/hdreg.h> 88#include <linux/ide.h> 89#include <linux/init.h> 90#include <linux/delay.h> 91 92#include <asm/io.h> 93 94#include "ide_modes.h" 95 96#define DISPLAY_SVWKS_TIMINGS 1 97#undef SVWKS_DEBUG_DRIVE_INFO 98 99#if defined(DISPLAY_SVWKS_TIMINGS) && defined(CONFIG_PROC_FS) 100#include <linux/stat.h> 101#include <linux/proc_fs.h> 102 103static struct pci_dev *bmide_dev; 104static byte svwks_revision = 0; 105 106static int svwks_get_info(char *, char **, off_t, int); 107extern int (*svwks_display_info)(char *, char **, off_t, int); /* ide-proc.c */ 108extern char *ide_media_verbose(ide_drive_t *); 109 110static int svwks_get_info (char *buffer, char **addr, off_t offset, int count) 111{ 112 char *p = buffer; 113 u32 bibma = pci_resource_start(bmide_dev, 4); 114 u32 reg40, reg44; 115 u16 reg48, reg56; 116 u8 reg54, c0=0, c1=0; 117 118 pci_read_config_dword(bmide_dev, 0x40, ®40); 119 pci_read_config_dword(bmide_dev, 0x44, ®44); 120 pci_read_config_word(bmide_dev, 0x48, ®48); 121 pci_read_config_byte(bmide_dev, 0x54, ®54); 122 pci_read_config_word(bmide_dev, 0x56, ®56); 123 124 /* 125 * at that point bibma+0x2 et bibma+0xa are byte registers 126 * to investigate: 127 */ 128 c0 = inb_p((unsigned short)bibma + 0x02); 129 c1 = inb_p((unsigned short)bibma + 0x0a); 130 131 switch(bmide_dev->device) { 132 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: 133 p += sprintf(p, "\n " 134 "ServerWorks CSB5 Chipset (rev %02x)\n", 135 svwks_revision); 136 break; 137 case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE: 138 p += sprintf(p, "\n " 139 "ServerWorks OSB4 Chipset (rev %02x)\n", 140 svwks_revision); 141 break; 142 default: 143 p += sprintf(p, "\n " 144 "ServerWorks %04x Chipset (rev %02x)\n", 145 bmide_dev->device, svwks_revision); 146 break; 147 } 148 149 p += sprintf(p, "------------------------------- General Status ---------------------------------\n"); 150 p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n"); 151 p += sprintf(p, " %sabled %sabled\n", 152 (c0&0x80) ? "dis" : " en", 153 (c1&0x80) ? "dis" : " en"); 154 p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n"); 155 p += sprintf(p, "DMA enabled: %s %s %s %s\n", 156 (c0&0x20) ? "yes" : "no ", 157 (c0&0x40) ? "yes" : "no ", 158 (c1&0x20) ? "yes" : "no ", 159 (c1&0x40) ? "yes" : "no " ); 160 p += sprintf(p, "UDMA enabled: %s %s %s %s\n", 161 (reg54 & 0x01) ? "yes" : "no ", 162 (reg54 & 0x02) ? "yes" : "no ", 163 (reg54 & 0x04) ? "yes" : "no ", 164 (reg54 & 0x08) ? "yes" : "no " ); 165 p += sprintf(p, "UDMA enabled: %s %s %s %s\n", 166 ((reg56&0x0005)==0x0005)?"5": 167 ((reg56&0x0004)==0x0004)?"4": 168 ((reg56&0x0003)==0x0003)?"3": 169 ((reg56&0x0002)==0x0002)?"2": 170 ((reg56&0x0001)==0x0001)?"1": 171 ((reg56&0x000F))?"?":"0", 172 ((reg56&0x0050)==0x0050)?"5": 173 ((reg56&0x0040)==0x0040)?"4": 174 ((reg56&0x0030)==0x0030)?"3": 175 ((reg56&0x0020)==0x0020)?"2": 176 ((reg56&0x0010)==0x0010)?"1": 177 ((reg56&0x00F0))?"?":"0", 178 ((reg56&0x0500)==0x0500)?"5": 179 ((reg56&0x0400)==0x0400)?"4": 180 ((reg56&0x0300)==0x0300)?"3": 181 ((reg56&0x0200)==0x0200)?"2": 182 ((reg56&0x0100)==0x0100)?"1": 183 ((reg56&0x0F00))?"?":"0", 184 ((reg56&0x5000)==0x5000)?"5": 185 ((reg56&0x4000)==0x4000)?"4": 186 ((reg56&0x3000)==0x3000)?"3": 187 ((reg56&0x2000)==0x2000)?"2": 188 ((reg56&0x1000)==0x1000)?"1": 189 ((reg56&0xF000))?"?":"0"); 190 p += sprintf(p, "DMA enabled: %s %s %s %s\n", 191 ((reg44&0x00002000)==0x00002000)?"2": 192 ((reg44&0x00002100)==0x00002100)?"1": 193 ((reg44&0x00007700)==0x00007700)?"0": 194 ((reg44&0x0000FF00)==0x0000FF00)?"X":"?", 195 ((reg44&0x00000020)==0x00000020)?"2": 196 ((reg44&0x00000021)==0x00000021)?"1": 197 ((reg44&0x00000077)==0x00000077)?"0": 198 ((reg44&0x000000FF)==0x000000FF)?"X":"?", 199 ((reg44&0x20000000)==0x20000000)?"2": 200 ((reg44&0x21000000)==0x21000000)?"1": 201 ((reg44&0x77000000)==0x77000000)?"0": 202 ((reg44&0xFF000000)==0xFF000000)?"X":"?", 203 ((reg44&0x00200000)==0x00200000)?"2": 204 ((reg44&0x00210000)==0x00210000)?"1": 205 ((reg44&0x00770000)==0x00770000)?"0": 206 ((reg44&0x00FF0000)==0x00FF0000)?"X":"?"); 207 208 p += sprintf(p, "PIO enabled: %s %s %s %s\n", 209 ((reg40&0x00002000)==0x00002000)?"4": 210 ((reg40&0x00002200)==0x00002200)?"3": 211 ((reg40&0x00003400)==0x00003400)?"2": 212 ((reg40&0x00004700)==0x00004700)?"1": 213 ((reg40&0x00005D00)==0x00005D00)?"0":"?", 214 ((reg40&0x00000020)==0x00000020)?"4": 215 ((reg40&0x00000022)==0x00000022)?"3": 216 ((reg40&0x00000034)==0x00000034)?"2": 217 ((reg40&0x00000047)==0x00000047)?"1": 218 ((reg40&0x0000005D)==0x0000005D)?"0":"?", 219 ((reg40&0x20000000)==0x20000000)?"4": 220 ((reg40&0x22000000)==0x22000000)?"3": 221 ((reg40&0x34000000)==0x34000000)?"2": 222 ((reg40&0x47000000)==0x47000000)?"1": 223 ((reg40&0x5D000000)==0x5D000000)?"0":"?", 224 ((reg40&0x00200000)==0x00200000)?"4": 225 ((reg40&0x00220000)==0x00220000)?"3": 226 ((reg40&0x00340000)==0x00340000)?"2": 227 ((reg40&0x00470000)==0x00470000)?"1": 228 ((reg40&0x005D0000)==0x005D0000)?"0":"?"); 229 return p-buffer; /* => must be less than 4k! */ 230} 231#endif /* defined(DISPLAY_SVWKS_TIMINGS) && defined(CONFIG_PROC_FS) */ 232 233#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */ 234 235byte svwks_proc = 0; 236 237extern char *ide_xfer_verbose (byte xfer_rate); 238 239static struct pci_dev *isa_dev; 240 241static int svwks_tune_chipset (ide_drive_t *drive, byte speed) 242{ 243 byte udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 }; 244 byte dma_modes[] = { 0x77, 0x21, 0x20 }; 245 byte pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; 246 247 ide_hwif_t *hwif = HWIF(drive); 248 struct pci_dev *dev = hwif->pci_dev; 249 byte unit = (drive->select.b.unit & 0x01); 250 byte csb5 = (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ? 1 : 0; 251 252#ifdef CONFIG_BLK_DEV_IDEDMA 253 unsigned long dma_base = hwif->dma_base; 254#endif /* CONFIG_BLK_DEV_IDEDMA */ 255 int err; 256 257 byte drive_pci = 0x00; 258 byte drive_pci2 = 0x00; 259 byte drive_pci3 = hwif->channel ? 0x57 : 0x56; 260 261 byte ultra_enable = 0x00; 262 byte ultra_timing = 0x00; 263 byte dma_timing = 0x00; 264 byte pio_timing = 0x00; 265 unsigned short csb5_pio = 0x00; 266 267 byte pio = ide_get_best_pio_mode(drive, 255, 5, NULL); 268 269 switch (drive->dn) { 270 case 0: drive_pci = 0x41; drive_pci2 = 0x45; break; 271 case 1: drive_pci = 0x40; drive_pci2 = 0x44; break; 272 case 2: drive_pci = 0x43; drive_pci2 = 0x47; break; 273 case 3: drive_pci = 0x42; drive_pci2 = 0x46; break; 274 default: 275 return -1; 276 } 277 278 pci_read_config_byte(dev, drive_pci, &pio_timing); 279 pci_read_config_byte(dev, drive_pci2, &dma_timing); 280 pci_read_config_byte(dev, drive_pci3, &ultra_timing); 281 pci_read_config_word(dev, 0x4A, &csb5_pio); 282 pci_read_config_byte(dev, 0x54, &ultra_enable); 283 284#ifdef DEBUG 285 printk("%s: UDMA 0x%02x DMAPIO 0x%02x PIO 0x%02x ", 286 drive->name, ultra_timing, dma_timing, pio_timing); 287#endif 288 289 pio_timing &= ~0xFF; 290 dma_timing &= ~0xFF; 291 ultra_timing &= ~(0x0F << (4*unit)); 292 ultra_enable &= ~(0x01 << drive->dn); 293 csb5_pio &= ~(0x0F << (4*drive->dn)); 294 295 switch(speed) { 296 case XFER_PIO_4: 297 case XFER_PIO_3: 298 case XFER_PIO_2: 299 case XFER_PIO_1: 300 case XFER_PIO_0: 301 pio_timing |= pio_modes[speed - XFER_PIO_0]; 302 csb5_pio |= ((speed - XFER_PIO_0) << (4*drive->dn)); 303 break; 304 305#ifdef CONFIG_BLK_DEV_IDEDMA 306 case XFER_MW_DMA_2: 307 case XFER_MW_DMA_1: 308 case XFER_MW_DMA_0: 309 pio_timing |= pio_modes[pio]; 310 csb5_pio |= (pio << (4*drive->dn)); 311 dma_timing |= dma_modes[speed - XFER_MW_DMA_0]; 312 break; 313 314 case XFER_UDMA_5: 315 case XFER_UDMA_4: 316 case XFER_UDMA_3: 317 case XFER_UDMA_2: 318 case XFER_UDMA_1: 319 case XFER_UDMA_0: 320 pio_timing |= pio_modes[pio]; 321 csb5_pio |= (pio << (4*drive->dn)); 322 dma_timing |= dma_modes[2]; 323 ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit)); 324 ultra_enable |= (0x01 << drive->dn); 325#endif 326 default: 327 break; 328 } 329 330#ifdef DEBUG 331 printk("%s: UDMA 0x%02x DMAPIO 0x%02x PIO 0x%02x ", 332 drive->name, ultra_timing, dma_timing, pio_timing); 333#endif 334 335#if SVWKS_DEBUG_DRIVE_INFO 336 printk("%s: %s drive%d\n", drive->name, ide_xfer_verbose(speed), drive->dn); 337#endif /* SVWKS_DEBUG_DRIVE_INFO */ 338 339 if (!drive->init_speed) 340 drive->init_speed = speed; 341 342 pci_write_config_byte(dev, drive_pci, pio_timing); 343 if (csb5) 344 pci_write_config_word(dev, 0x4A, csb5_pio); 345 346#ifdef CONFIG_BLK_DEV_IDEDMA 347 pci_write_config_byte(dev, drive_pci2, dma_timing); 348 pci_write_config_byte(dev, drive_pci3, ultra_timing); 349 pci_write_config_byte(dev, 0x54, ultra_enable); 350 351 if (speed > XFER_PIO_4) 352 outb(inb(dma_base+2)|(1<<(5+unit)), dma_base+2); 353 else 354 outb(inb(dma_base+2) & ~(1<<(5+unit)), dma_base+2); 355#endif /* CONFIG_BLK_DEV_IDEDMA */ 356 357 err = ide_config_drive_speed(drive, speed); 358 drive->current_speed = speed; 359 return err; 360} 361 362static void config_chipset_for_pio (ide_drive_t *drive) 363{ 364 unsigned short eide_pio_timing[6] = {960, 480, 240, 180, 120, 90}; 365 unsigned short xfer_pio = drive->id->eide_pio_modes; 366 byte timing, speed, pio; 367 368 pio = ide_get_best_pio_mode(drive, 255, 5, NULL); 369 370 if (xfer_pio> 4) 371 xfer_pio = 0; 372 373 if (drive->id->eide_pio_iordy > 0) 374 for (xfer_pio = 5; 375 xfer_pio>0 && 376 drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio]; 377 xfer_pio--); 378 else 379 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 : 380 (drive->id->eide_pio_modes & 2) ? 0x04 : 381 (drive->id->eide_pio_modes & 1) ? 0x03 : 382 (drive->id->tPIO & 2) ? 0x02 : 383 (drive->id->tPIO & 1) ? 0x01 : xfer_pio; 384 385 timing = (xfer_pio >= pio) ? xfer_pio : pio; 386 387 switch(timing) { 388 case 4: speed = XFER_PIO_4;break; 389 case 3: speed = XFER_PIO_3;break; 390 case 2: speed = XFER_PIO_2;break; 391 case 1: speed = XFER_PIO_1;break; 392 default: 393 speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW; 394 break; 395 } 396 (void) svwks_tune_chipset(drive, speed); 397 drive->current_speed = speed; 398} 399 400static void svwks_tune_drive (ide_drive_t *drive, byte pio) 401{ 402 byte speed; 403 switch(pio) { 404 case 4: speed = XFER_PIO_4;break; 405 case 3: speed = XFER_PIO_3;break; 406 case 2: speed = XFER_PIO_2;break; 407 case 1: speed = XFER_PIO_1;break; 408 default: speed = XFER_PIO_0;break; 409 } 410 (void) svwks_tune_chipset(drive, speed); 411} 412 413#ifdef CONFIG_BLK_DEV_IDEDMA 414static int config_chipset_for_dma (ide_drive_t *drive) 415{ 416 struct hd_driveid *id = drive->id; 417 struct pci_dev *dev = HWIF(drive)->pci_dev; 418 byte udma_66 = eighty_ninty_three(drive); 419 int ultra66 = (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ? 1 : 0; 420 int ultra100 = (ultra66 && svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 1 : 0; 421 byte speed; 422 423 if ((id->dma_ultra & 0x0020) && (udma_66) && (ultra100)) { 424 speed = XFER_UDMA_5; 425 } else if (id->dma_ultra & 0x0010) { 426 speed = ((udma_66) && (ultra66)) ? XFER_UDMA_4 : XFER_UDMA_2; 427 } else if (id->dma_ultra & 0x0008) { 428 speed = ((udma_66) && (ultra66)) ? XFER_UDMA_3 : XFER_UDMA_1; 429 } else if (id->dma_ultra & 0x0004) { 430 speed = XFER_UDMA_2; 431 } else if (id->dma_ultra & 0x0002) { 432 speed = XFER_UDMA_1; 433 } else if (id->dma_ultra & 0x0001) { 434 speed = XFER_UDMA_0; 435 } else if (id->dma_mword & 0x0004) { 436 speed = XFER_MW_DMA_2; 437 } else if (id->dma_mword & 0x0002) { 438 speed = XFER_MW_DMA_1; 439 } else if (id->dma_1word & 0x0004) { 440 speed = XFER_SW_DMA_2; 441 } else { 442 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL); 443 } 444 445 (void) svwks_tune_chipset(drive, speed); 446 447 return ((int) ((id->dma_ultra >> 11) & 7) ? ide_dma_on : 448 ((id->dma_ultra >> 8) & 7) ? ide_dma_on : 449 ((id->dma_mword >> 8) & 7) ? ide_dma_on : 450 ((id->dma_1word >> 8) & 7) ? ide_dma_on : 451 ide_dma_off_quietly); 452} 453 454static int config_drive_xfer_rate (ide_drive_t *drive) 455{ 456 struct hd_driveid *id = drive->id; 457 ide_dma_action_t dma_func = ide_dma_on; 458 459 if (id && (id->capability & 1) && HWIF(drive)->autodma) { 460 /* Consult the list of known "bad" drives */ 461 if (ide_dmaproc(ide_dma_bad_drive, drive)) { 462 dma_func = ide_dma_off; 463 goto fast_ata_pio; 464 } 465 dma_func = ide_dma_off_quietly; 466 if (id->field_valid & 4) { 467 if (id->dma_ultra & 0x003F) { 468 /* Force if Capable UltraDMA */ 469 dma_func = config_chipset_for_dma(drive); 470 if ((id->field_valid & 2) && 471 (dma_func != ide_dma_on)) 472 goto try_dma_modes; 473 } 474 } else if (id->field_valid & 2) { 475try_dma_modes: 476 if ((id->dma_mword & 0x0007) || 477 (id->dma_1word & 0x007)) { 478 /* Force if Capable regular DMA modes */ 479 dma_func = config_chipset_for_dma(drive); 480 if (dma_func != ide_dma_on) 481 goto no_dma_set; 482 } 483 } else if (ide_dmaproc(ide_dma_good_drive, drive)) { 484 if (id->eide_dma_time > 150) { 485 goto no_dma_set; 486 } 487 /* Consult the list of known "good" drives */ 488 dma_func = config_chipset_for_dma(drive); 489 if (dma_func != ide_dma_on) 490 goto no_dma_set; 491 } else { 492 goto fast_ata_pio; 493 } 494 } else if ((id->capability & 8) || (id->field_valid & 2)) { 495fast_ata_pio: 496 dma_func = ide_dma_off_quietly; 497no_dma_set: 498 config_chipset_for_pio(drive); 499 } 500 return HWIF(drive)->dmaproc(dma_func, drive); 501} 502 503static int svwks_dmaproc(ide_dma_action_t func, ide_drive_t *drive) 504{ 505 switch (func) { 506 case ide_dma_check: 507 return config_drive_xfer_rate(drive); 508 case ide_dma_end: 509 { 510 ide_hwif_t *hwif = HWIF(drive); 511 unsigned long dma_base = hwif->dma_base; 512 513 if(inb(dma_base+0x02)&1) 514 { 515 printk(KERN_CRIT "Serverworks OSB4 in impossible state.\n"); 516 printk(KERN_CRIT "Disable UDMA or if you are using Seagate then try switching disk types\n"); 517 printk(KERN_CRIT "on this controller. Please report this event to osb4-bug@ide.cabal.tm\n"); 518 printk(KERN_CRIT "OSB4: continuing might cause disk corruption.\n"); 519 while(1) 520 cpu_relax(); 521 } 522 /* and drop through */ 523 } 524 default: 525 break; 526 } 527 /* Other cases are done by generic IDE-DMA code. */ 528 return ide_dmaproc(func, drive); 529} 530#endif /* CONFIG_BLK_DEV_IDEDMA */ 531 532unsigned int __init pci_init_svwks (struct pci_dev *dev, const char *name) 533{ 534 unsigned int reg; 535 byte btr; 536 537 /* save revision id to determine DMA capability */ 538 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision); 539 540 /* force Master Latency Timer value to 64 PCICLKs */ 541 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40); 542 543 /* OSB4 : South Bridge and IDE */ 544 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { 545 isa_dev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS, 546 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL); 547 if (isa_dev) { 548 pci_read_config_dword(isa_dev, 0x64, ®); 549 reg &= ~0x00002000; /* disable 600ns interrupt mask */ 550 reg |= 0x00004000; /* enable UDMA/33 support */ 551 pci_write_config_dword(isa_dev, 0x64, reg); 552 } 553 } 554 555 /* setup CSB5 : South Bridge and IDE */ 556 else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) { 557 /* setup the UDMA Control register 558 * 559 * 1. clear bit 6 to enable DMA 560 * 2. enable DMA modes with bits 0-1 561 * 00 : legacy 562 * 01 : udma2 563 * 10 : udma2/udma4 564 * 11 : udma2/udma4/udma5 565 */ 566 pci_read_config_byte(dev, 0x5A, &btr); 567 btr &= ~0x40; 568 btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2; 569 pci_write_config_byte(dev, 0x5A, btr); 570 } 571 572#if defined(DISPLAY_SVWKS_TIMINGS) && defined(CONFIG_PROC_FS) 573 if (!svwks_proc) { 574 svwks_proc = 1; 575 bmide_dev = dev; 576 svwks_display_info = &svwks_get_info; 577 } 578#endif /* DISPLAY_SVWKS_TIMINGS && CONFIG_PROC_FS */ 579 return 0; 580} 581 582/* On Dell PowerEdge servers with a CSB5, the top two bits of the subsystem 583 * device ID indicate presence of an 80-pin cable. 584 * Bit 15 clear = secondary IDE channel does not have 80-pin cable. 585 * Bit 15 set = secondary IDE channel has 80-pin cable. 586 * Bit 14 clear = primary IDE channel does not have 80-pin cable. 587 * Bit 14 set = primary IDE channel has 80-pin cable. 588 */ 589static unsigned int __init ata66_svwks_dell (ide_hwif_t *hwif) 590{ 591 struct pci_dev *dev = hwif->pci_dev; 592 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL && 593 dev->vendor == PCI_VENDOR_ID_SERVERWORKS && 594 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) 595 return ((1 << (hwif->channel + 14)) & 596 dev->subsystem_device) ? 1 : 0; 597 return 0; 598} 599 600/* Sun Cobalt Alpine hardware avoids the 80-pin cable 601 * detect issue by attaching the drives directly to the board. 602 * This check follows the Dell precedent (how scary is that?!) 603 * 604 * WARNING: this only works on Alpine hardware! 605 */ 606static unsigned int __init ata66_svwks_cobalt (ide_hwif_t *hwif) 607{ 608 struct pci_dev *dev = hwif->pci_dev; 609 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN && 610 dev->vendor == PCI_VENDOR_ID_SERVERWORKS && 611 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) 612 return ((1 << (hwif->channel + 14)) & 613 dev->subsystem_device) ? 1 : 0; 614 return 0; 615} 616 617unsigned int __init ata66_svwks (ide_hwif_t *hwif) 618{ 619 struct pci_dev *dev = hwif->pci_dev; 620 621 /* Dell PowerEdge */ 622 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL) 623 return ata66_svwks_dell (hwif); 624 625 /* Cobalt Alpine */ 626 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN) 627 return ata66_svwks_cobalt (hwif); 628 629 return 0; 630} 631 632void __init ide_init_svwks (ide_hwif_t *hwif) 633{ 634 if (!hwif->irq) 635 hwif->irq = hwif->channel ? 15 : 14; 636 637 hwif->tuneproc = &svwks_tune_drive; 638 hwif->speedproc = &svwks_tune_chipset; 639 640#ifndef CONFIG_BLK_DEV_IDEDMA 641 hwif->drives[0].autotune = 1; 642 hwif->drives[1].autotune = 1; 643 hwif->autodma = 0; 644#else /* CONFIG_BLK_DEV_IDEDMA */ 645 if (hwif->dma_base) { 646#ifdef CONFIG_IDEDMA_AUTO 647 if (!noautodma) 648 hwif->autodma = 1; 649#endif 650 hwif->dmaproc = &svwks_dmaproc; 651 } else { 652 hwif->autodma = 0; 653 hwif->drives[0].autotune = 1; 654 hwif->drives[1].autotune = 1; 655 } 656#endif /* !CONFIG_BLK_DEV_IDEDMA */ 657} 658