1/* $Id: pcic.c,v 1.1.1.1 2008/10/15 03:26:18 james26_jang Exp $ 2 * pcic.c: Sparc/PCI controller support 3 * 4 * Copyright (C) 1998 V. Roganov and G. Raiko 5 * 6 * Code is derived from Ultra/PCI PSYCHO controller support, see that 7 * for author info. 8 * 9 * Support for diverse IIep based platforms by Pete Zaitcev. 10 * CP-1200 by Eric Brower. 11 */ 12 13#include <linux/config.h> 14#include <linux/kernel.h> 15#include <linux/types.h> 16#include <linux/init.h> 17#include <linux/mm.h> 18#include <linux/slab.h> 19 20#include <asm/ebus.h> 21#include <asm/sbus.h> /* for sanity check... */ 22#include <asm/swift.h> /* for cache flushing. */ 23#include <asm/io.h> 24 25#include <linux/ctype.h> 26#include <linux/pci.h> 27#include <linux/timex.h> 28#include <linux/interrupt.h> 29 30#include <asm/irq.h> 31#include <asm/oplib.h> 32#include <asm/pcic.h> 33#include <asm/timer.h> 34#include <asm/uaccess.h> 35 36#ifndef CONFIG_PCI 37 38asmlinkage int sys_pciconfig_read(unsigned long bus, 39 unsigned long dfn, 40 unsigned long off, 41 unsigned long len, 42 unsigned char *buf) 43{ 44 return -EINVAL; 45} 46 47asmlinkage int sys_pciconfig_write(unsigned long bus, 48 unsigned long dfn, 49 unsigned long off, 50 unsigned long len, 51 unsigned char *buf) 52{ 53 return -EINVAL; 54} 55 56#else 57 58#ifdef CONFIG_SUN_JSFLASH 59extern int jsflash_init(void); 60#endif 61 62struct pci_fixup pcibios_fixups[] = { 63 { 0 } 64}; 65 66unsigned int pcic_pin_to_irq(unsigned int pin, char *name); 67 68/* 69 * I studied different documents and many live PROMs both from 2.30 70 * family and 3.xx versions. I came to the amazing conclusion: there is 71 * absolutely no way to route interrupts in IIep systems relying on 72 * information which PROM presents. We must hardcode interrupt routing 73 * schematics. And this actually sucks. -- zaitcev 1999/05/12 74 * 75 * To find irq for a device we determine which routing map 76 * is in effect or, in other words, on which machine we are running. 77 * We use PROM name for this although other techniques may be used 78 * in special cases (Gleb reports a PROMless IIep based system). 79 * Once we know the map we take device configuration address and 80 * find PCIC pin number where INT line goes. Then we may either program 81 * preferred irq into the PCIC or supply the preexisting irq to the device. 82 */ 83struct pcic_ca2irq { 84 unsigned char busno; /* PCI bus number */ 85 unsigned char devfn; /* Configuration address */ 86 unsigned char pin; /* PCIC external interrupt pin */ 87 unsigned char irq; /* Preferred IRQ (mappable in PCIC) */ 88 unsigned int force; /* Enforce preferred IRQ */ 89}; 90 91struct pcic_sn2list { 92 char *sysname; 93 struct pcic_ca2irq *intmap; 94 int mapdim; 95}; 96 97/* 98 * JavaEngine-1 apparently has different versions. 99 * 100 * According to communications with Sun folks, for P2 build 501-4628-03: 101 * pin 0 - parallel, audio; 102 * pin 1 - Ethernet; 103 * pin 2 - su; 104 * pin 3 - PS/2 kbd and mouse. 105 * 106 * OEM manual (805-1486): 107 * pin 0: Ethernet 108 * pin 1: All EBus 109 * pin 2: IGA (unused) 110 * pin 3: Not connected 111 * OEM manual says that 501-4628 & 501-4811 are the same thing, 112 * only the latter has NAND flash in place. 113 * 114 * So far unofficial Sun wins over the OEM manual. Poor OEMs... 115 */ 116static struct pcic_ca2irq pcic_i_je1a[] = { /* 501-4811-03 */ 117 { 0, 0x00, 2, 12, 0 }, /* EBus: hogs all */ 118 { 0, 0x01, 1, 6, 1 }, /* Happy Meal */ 119 { 0, 0x80, 0, 7, 0 }, /* IGA (unused) */ 120}; 121 122static struct pcic_ca2irq pcic_i_jse[] = { 123 { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */ 124 { 0, 0x01, 1, 6, 0 }, /* hme */ 125 { 0, 0x08, 2, 9, 0 }, /* VGA - we hope not used :) */ 126 { 0, 0x10, 6, 8, 0 }, /* PCI INTA# in Slot 1 */ 127 { 0, 0x18, 7, 12, 0 }, /* PCI INTA# in Slot 2, shared w. RTC */ 128 { 0, 0x38, 4, 9, 0 }, /* All ISA devices. Read 8259. */ 129 { 0, 0x80, 5, 11, 0 }, /* EIDE */ 130 /* {0,0x88, 0,0,0} - unknown device... PMU? Probably no interrupt. */ 131 { 0, 0xA0, 4, 9, 0 }, /* USB */ 132 /* 133 * Some pins belong to non-PCI devices, we hardcode them in drivers. 134 * sun4m timers - irq 10, 14 135 * PC style RTC - pin 7, irq 4 ? 136 * Smart card, Parallel - pin 4 shared with USB, ISA 137 * audio - pin 3, irq 5 ? 138 */ 139}; 140 141/* SPARCengine-6 was the original release name of CP1200. 142 * The documentation differs between the two versions 143 */ 144static struct pcic_ca2irq pcic_i_se6[] = { 145 { 0, 0x08, 0, 2, 0 }, /* SCSI */ 146 { 0, 0x01, 1, 6, 0 }, /* HME */ 147 { 0, 0x00, 3, 13, 0 }, /* EBus */ 148}; 149 150/* 151 * Krups (courtesy of Varol Kaptan) 152 * No documentation available, but it was easy to guess 153 * because it was very similar to Espresso. 154 * 155 * pin 0 - kbd, mouse, serial; 156 * pin 1 - Ethernet; 157 * pin 2 - igs (we do not use it); 158 * pin 3 - audio; 159 * pin 4,5,6 - unused; 160 * pin 7 - RTC (from P2 onwards as David B. says). 161 */ 162static struct pcic_ca2irq pcic_i_jk[] = { 163 { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */ 164 { 0, 0x01, 1, 6, 0 }, /* hme */ 165}; 166 167/* 168 * Several entries in this list may point to the same routing map 169 * as several PROMs may be installed on the same physical board. 170 */ 171#define SN2L_INIT(name, map) \ 172 { name, map, sizeof(map)/sizeof(struct pcic_ca2irq) } 173 174static struct pcic_sn2list pcic_known_sysnames[] = { 175 SN2L_INIT("SUNW,JavaEngine1", pcic_i_je1a), /* JE1, PROM 2.32 */ 176 SN2L_INIT("SUNW,JS-E", pcic_i_jse), /* PROLL JavaStation-E */ 177 SN2L_INIT("SUNW,SPARCengine-6", pcic_i_se6), /* SPARCengine-6/CP-1200 */ 178 SN2L_INIT("SUNW,JS-NC", pcic_i_jk), /* PROLL JavaStation-NC */ 179 SN2L_INIT("SUNW,JSIIep", pcic_i_jk), /* OBP JavaStation-NC */ 180 { NULL, NULL, 0 } 181}; 182 183/* 184 * Only one PCIC per IIep, 185 * and since we have no SMP IIep, only one per system. 186 */ 187static int pcic0_up; 188static struct linux_pcic pcic0; 189 190unsigned int pcic_regs; 191volatile int pcic_speculative; 192volatile int pcic_trapped; 193 194static void pci_do_gettimeofday(struct timeval *tv); 195static void pci_do_settimeofday(struct timeval *tv); 196 197#define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3)) 198 199static int pcic_read_config_dword(struct pci_dev *dev, int where, u32 *value); 200static int pcic_write_config_dword(struct pci_dev *dev, int where, u32 value); 201 202static int pcic_read_config_byte(struct pci_dev *dev, int where, u8 *value) 203{ 204 unsigned int v; 205 206 pcic_read_config_dword(dev, where&~3, &v); 207 *value = 0xff & (v >> (8*(where & 3))); 208 return PCIBIOS_SUCCESSFUL; 209} 210 211static int pcic_read_config_word(struct pci_dev *dev, int where, u16 *value) 212{ 213 unsigned int v; 214 if (where&1) return PCIBIOS_BAD_REGISTER_NUMBER; 215 216 pcic_read_config_dword(dev, where&~3, &v); 217 *value = 0xffff & (v >> (8*(where & 3))); 218 return PCIBIOS_SUCCESSFUL; 219} 220 221static int pcic_read_config_dword(struct pci_dev *dev, int where, u32 *value) 222{ 223 unsigned char bus = dev->bus->number; 224 unsigned char device_fn = dev->devfn; 225 /* unsigned char where; */ 226 227 struct linux_pcic *pcic; 228 unsigned long flags; 229 230 if (where&3) return PCIBIOS_BAD_REGISTER_NUMBER; 231 if (bus != 0) return PCIBIOS_DEVICE_NOT_FOUND; 232 pcic = &pcic0; 233 234 save_and_cli(flags); 235 writel(CONFIG_CMD(bus,device_fn,where), pcic->pcic_config_space_addr); 236 pcic_speculative = 2; 237 pcic_trapped = 0; 238 *value = readl(pcic->pcic_config_space_data + (where&4)); 239 nop(); 240 if (pcic_trapped) { 241 pcic_speculative = 0; 242 restore_flags(flags); 243 *value = ~0; 244 return PCIBIOS_SUCCESSFUL; 245 } 246 pcic_speculative = 0; 247 restore_flags(flags); 248 return PCIBIOS_SUCCESSFUL; 249} 250 251static int pcic_write_config_byte(struct pci_dev *dev, int where, u8 value) 252{ 253 unsigned int v; 254 255 pcic_read_config_dword(dev, where&~3, &v); 256 v = (v & ~(0xff << (8*(where&3)))) | 257 ((0xff&(unsigned)value) << (8*(where&3))); 258 return pcic_write_config_dword(dev, where&~3, v); 259} 260 261static int pcic_write_config_word(struct pci_dev *dev, int where, u16 value) 262{ 263 unsigned int v; 264 265 if (where&1) return PCIBIOS_BAD_REGISTER_NUMBER; 266 pcic_read_config_dword(dev, where&~3, &v); 267 v = (v & ~(0xffff << (8*(where&3)))) | 268 ((0xffff&(unsigned)value) << (8*(where&3))); 269 return pcic_write_config_dword(dev, where&~3, v); 270} 271 272static int pcic_write_config_dword(struct pci_dev *dev, int where, u32 value) 273{ 274 unsigned char bus = dev->bus->number; 275 unsigned char devfn = dev->devfn; 276 struct linux_pcic *pcic; 277 unsigned long flags; 278 279 if (where&3) return PCIBIOS_BAD_REGISTER_NUMBER; 280 if (bus != 0) return PCIBIOS_DEVICE_NOT_FOUND; 281 pcic = &pcic0; 282 283 save_and_cli(flags); 284 writel(CONFIG_CMD(bus,devfn,where), pcic->pcic_config_space_addr); 285 writel(value, pcic->pcic_config_space_data + (where&4)); 286 restore_flags(flags); 287 return PCIBIOS_SUCCESSFUL; 288} 289 290static struct pci_ops pcic_ops = { 291 pcic_read_config_byte, 292 pcic_read_config_word, 293 pcic_read_config_dword, 294 pcic_write_config_byte, 295 pcic_write_config_word, 296 pcic_write_config_dword, 297}; 298 299/* 300 * On sparc64 pcibios_init() calls pci_controller_probe(). 301 * We want PCIC probed little ahead so that interrupt controller 302 * would be operational. 303 */ 304int __init pcic_probe(void) 305{ 306 struct linux_pcic *pcic; 307 struct linux_prom_registers regs[PROMREG_MAX]; 308 struct linux_pbm_info* pbm; 309 char namebuf[64]; 310 int node; 311 int err; 312 313 if (pcic0_up) { 314 prom_printf("PCIC: called twice!\n"); 315 prom_halt(); 316 } 317 pcic = &pcic0; 318 319 node = prom_getchild (prom_root_node); 320 node = prom_searchsiblings (node, "pci"); 321 if (node == 0) 322 return -ENODEV; 323 /* 324 * Map in PCIC register set, config space, and IO base 325 */ 326 err = prom_getproperty(node, "reg", (char*)regs, sizeof(regs)); 327 if (err == 0 || err == -1) { 328 prom_printf("PCIC: Error, cannot get PCIC registers " 329 "from PROM.\n"); 330 prom_halt(); 331 } 332 333 pcic0_up = 1; 334 335 pcic->pcic_res_regs.name = "pcic_registers"; 336 pcic->pcic_regs = (unsigned long) 337 ioremap(regs[0].phys_addr, regs[0].reg_size); 338 if (!pcic->pcic_regs) { 339 prom_printf("PCIC: Error, cannot map PCIC registers.\n"); 340 prom_halt(); 341 } 342 343 pcic->pcic_res_io.name = "pcic_io"; 344 if ((pcic->pcic_io = (unsigned long) 345 ioremap(regs[1].phys_addr, 0x10000)) == 0) { 346 prom_printf("PCIC: Error, cannot map PCIC IO Base.\n"); 347 prom_halt(); 348 } 349 350 pcic->pcic_res_cfg_addr.name = "pcic_cfg_addr"; 351 if ((pcic->pcic_config_space_addr = (unsigned long) 352 ioremap(regs[2].phys_addr, regs[2].reg_size * 2)) == 0) { 353 prom_printf("PCIC: Error, cannot map" 354 "PCI Configuration Space Address.\n"); 355 prom_halt(); 356 } 357 358 /* 359 * Docs say three least significant bits in address and data 360 * must be the same. Thus, we need adjust size of data. 361 */ 362 pcic->pcic_res_cfg_data.name = "pcic_cfg_data"; 363 if ((pcic->pcic_config_space_data = (unsigned long) 364 ioremap(regs[3].phys_addr, regs[3].reg_size * 2)) == 0) { 365 prom_printf("PCIC: Error, cannot map" 366 "PCI Configuration Space Data.\n"); 367 prom_halt(); 368 } 369 370 pbm = &pcic->pbm; 371 pbm->prom_node = node; 372 prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0; 373 strcpy(pbm->prom_name, namebuf); 374 375 { 376 extern volatile int t_nmi[1]; 377 extern int pcic_nmi_trap_patch[1]; 378 379 t_nmi[0] = pcic_nmi_trap_patch[0]; 380 t_nmi[1] = pcic_nmi_trap_patch[1]; 381 t_nmi[2] = pcic_nmi_trap_patch[2]; 382 t_nmi[3] = pcic_nmi_trap_patch[3]; 383 swift_flush_dcache(); 384 pcic_regs = pcic->pcic_regs; 385 } 386 387 prom_getstring(prom_root_node, "name", namebuf, 63); namebuf[63] = 0; 388 { 389 struct pcic_sn2list *p; 390 391 for (p = pcic_known_sysnames; p->sysname != NULL; p++) { 392 if (strcmp(namebuf, p->sysname) == 0) 393 break; 394 } 395 pcic->pcic_imap = p->intmap; 396 pcic->pcic_imdim = p->mapdim; 397 } 398 if (pcic->pcic_imap == NULL) { 399 /* 400 * We do not panic here for the sake of embedded systems. 401 */ 402 printk("PCIC: System %s is unknown, cannot route interrupts\n", 403 namebuf); 404 } 405 406 return 0; 407} 408 409static void __init pcic_pbm_scan_bus(struct linux_pcic *pcic) 410{ 411 struct linux_pbm_info *pbm = &pcic->pbm; 412 413 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, &pcic_ops, pbm); 414} 415 416/* 417 * Main entry point from the PCI subsystem. 418 */ 419void __init pcibios_init(void) 420{ 421 struct linux_pcic *pcic; 422 423 /* 424 * PCIC should be initialized at start of the timer. 425 * So, here we report the presence of PCIC and do some magic passes. 426 */ 427 if(!pcic0_up) 428 return; 429 pcic = &pcic0; 430 431 /* 432 * Switch off IOTLB translation. 433 */ 434 writeb(PCI_DVMA_CONTROL_IOTLB_DISABLE, 435 pcic->pcic_regs+PCI_DVMA_CONTROL); 436 437 writel(0xF0000000UL, pcic->pcic_regs+PCI_SIZE_0); 438 writel(0+PCI_BASE_ADDRESS_SPACE_MEMORY, 439 pcic->pcic_regs+PCI_BASE_ADDRESS_0); 440 441 pcic_pbm_scan_bus(pcic); 442 443 ebus_init(); 444#ifdef CONFIG_SUN_JSFLASH 445 jsflash_init(); 446#endif 447} 448 449int pcic_present(void) 450{ 451 return pcic0_up; 452} 453 454static int __init pdev_to_pnode(struct linux_pbm_info *pbm, 455 struct pci_dev *pdev) 456{ 457 struct linux_prom_pci_registers regs[PROMREG_MAX]; 458 int err; 459 int node = prom_getchild(pbm->prom_node); 460 461 while(node) { 462 err = prom_getproperty(node, "reg", 463 (char *)®s[0], sizeof(regs)); 464 if(err != 0 && err != -1) { 465 unsigned long devfn = (regs[0].which_io >> 8) & 0xff; 466 if(devfn == pdev->devfn) 467 return node; 468 } 469 node = prom_getsibling(node); 470 } 471 return 0; 472} 473 474static inline struct pcidev_cookie *pci_devcookie_alloc(void) 475{ 476 return kmalloc(sizeof(struct pcidev_cookie), GFP_ATOMIC); 477} 478 479static void pcic_map_pci_device(struct linux_pcic *pcic, 480 struct pci_dev *dev, int node) 481{ 482 char namebuf[64]; 483 unsigned long address; 484 unsigned long flags; 485 int j; 486 487 if (node == 0 || node == -1) { 488 strcpy(namebuf, "???"); 489 } else { 490 prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0; 491 } 492 493 for (j = 0; j < 6; j++) { 494 address = dev->resource[j].start; 495 if (address == 0) break; /* are sequential */ 496 flags = dev->resource[j].flags; 497 if ((flags & IORESOURCE_IO) != 0) { 498 if (address < 0x10000) { 499 dev->resource[j].start = 500 pcic->pcic_io + address; 501 dev->resource[j].end = 1; 502 dev->resource[j].flags = 503 (flags & ~IORESOURCE_IO) | IORESOURCE_MEM; 504 } else { 505 printk("PCIC: Skipping I/O space at 0x%lx," 506 "this will Oops if a driver attaches;" 507 "device '%s' at %02x:%02x)\n", address, 508 namebuf, dev->bus->number, dev->devfn); 509 } 510 } 511 } 512} 513 514static void 515pcic_fill_irq(struct linux_pcic *pcic, struct pci_dev *dev, int node) 516{ 517 struct pcic_ca2irq *p; 518 int i, ivec; 519 char namebuf[64]; 520 521 if (node == 0 || node == -1) { 522 strcpy(namebuf, "???"); 523 } else { 524 prom_getstring(node, "name", namebuf, sizeof(namebuf)); 525 } 526 527 if ((p = pcic->pcic_imap) == 0) { 528 dev->irq = 0; 529 return; 530 } 531 for (i = 0; i < pcic->pcic_imdim; i++) { 532 if (p->busno == dev->bus->number && p->devfn == dev->devfn) 533 break; 534 p++; 535 } 536 if (i >= pcic->pcic_imdim) { 537 printk("PCIC: device %s devfn %02x:%02x not found in %d\n", 538 namebuf, dev->bus->number, dev->devfn, pcic->pcic_imdim); 539 dev->irq = 0; 540 return; 541 } 542 543 i = p->pin; 544 if (i >= 0 && i < 4) { 545 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO); 546 dev->irq = ivec >> (i << 2) & 0xF; 547 } else if (i >= 4 && i < 8) { 548 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI); 549 dev->irq = ivec >> ((i-4) << 2) & 0xF; 550 } else { /* Corrupted map */ 551 printk("PCIC: BAD PIN %d\n", i); for (;;) {} 552 } 553/* P3 */ /* printk("PCIC: device %s pin %d ivec 0x%x irq %x\n", namebuf, i, ivec, dev->irq); */ 554 555 /* 556 * dev->irq=0 means PROM did not bother to program the upper 557 * half of PCIC. This happens on JS-E with PROM 3.11, for instance. 558 */ 559 if (dev->irq == 0 || p->force) { 560 if (p->irq == 0 || p->irq >= 15) { /* Corrupted map */ 561 printk("PCIC: BAD IRQ %d\n", p->irq); for (;;) {} 562 } 563 printk("PCIC: setting irq %d at pin %d for device %02x:%02x\n", 564 p->irq, p->pin, dev->bus->number, dev->devfn); 565 dev->irq = p->irq; 566 567 i = p->pin; 568 if (i >= 4) { 569 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI); 570 ivec &= ~(0xF << ((i - 4) << 2)); 571 ivec |= p->irq << ((i - 4) << 2); 572 writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_HI); 573 } else { 574 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO); 575 ivec &= ~(0xF << (i << 2)); 576 ivec |= p->irq << (i << 2); 577 writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_LO); 578 } 579 } 580 581 return; 582} 583 584/* 585 * Normally called from {do_}pci_scan_bus... 586 */ 587void __init pcibios_fixup_bus(struct pci_bus *bus) 588{ 589 struct list_head *walk; 590 int i, has_io, has_mem; 591 unsigned short cmd; 592 struct linux_pcic *pcic; 593 /* struct linux_pbm_info* pbm = &pcic->pbm; */ 594 int node; 595 struct pcidev_cookie *pcp; 596 597 if (!pcic0_up) { 598 printk("pcibios_fixup_bus: no PCIC\n"); 599 return; 600 } 601 pcic = &pcic0; 602 603 /* 604 * Next crud is an equivalent of pbm = pcic_bus_to_pbm(bus); 605 */ 606 if (bus->number != 0) { 607 printk("pcibios_fixup_bus: nonzero bus 0x%x\n", bus->number); 608 return; 609 } 610 611 walk = &bus->devices; 612 for (walk = walk->next; walk != &bus->devices; walk = walk->next) { 613 struct pci_dev *dev = pci_dev_b(walk); 614 615 /* 616 * Comment from i386 branch: 617 * There are buggy BIOSes that forget to enable I/O and memory 618 * access to PCI devices. We try to fix this, but we need to 619 * be sure that the BIOS didn't forget to assign an address 620 * to the device. [mj] 621 * OBP is a case of such BIOS :-) 622 */ 623 has_io = has_mem = 0; 624 for(i=0; i<6; i++) { 625 unsigned long f = dev->resource[i].flags; 626 if (f & IORESOURCE_IO) { 627 has_io = 1; 628 } else if (f & IORESOURCE_MEM) 629 has_mem = 1; 630 } 631 pcic_read_config_word(dev, PCI_COMMAND, &cmd); 632 if (has_io && !(cmd & PCI_COMMAND_IO)) { 633 printk("PCIC: Enabling I/O for device %02x:%02x\n", 634 dev->bus->number, dev->devfn); 635 cmd |= PCI_COMMAND_IO; 636 pcic_write_config_word(dev, PCI_COMMAND, cmd); 637 } 638 if (has_mem && !(cmd & PCI_COMMAND_MEMORY)) { 639 printk("PCIC: Enabling memory for device %02x:%02x\n", 640 dev->bus->number, dev->devfn); 641 cmd |= PCI_COMMAND_MEMORY; 642 pcic_write_config_word(dev, PCI_COMMAND, cmd); 643 } 644 645 node = pdev_to_pnode(&pcic->pbm, dev); 646 if(node == 0) 647 node = -1; 648 649 /* cookies */ 650 pcp = pci_devcookie_alloc(); 651 pcp->pbm = &pcic->pbm; 652 pcp->prom_node = node; 653 dev->sysdata = pcp; 654 655 /* fixing I/O to look like memory */ 656 if ((dev->class>>16) != PCI_BASE_CLASS_BRIDGE) 657 pcic_map_pci_device(pcic, dev, node); 658 659 pcic_fill_irq(pcic, dev, node); 660 } 661} 662 663/* 664 * pcic_pin_to_irq() is exported to ebus.c. 665 */ 666unsigned int 667pcic_pin_to_irq(unsigned int pin, char *name) 668{ 669 struct linux_pcic *pcic = &pcic0; 670 unsigned int irq; 671 unsigned int ivec; 672 673 if (pin < 4) { 674 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO); 675 irq = ivec >> (pin << 2) & 0xF; 676 } else if (pin < 8) { 677 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI); 678 irq = ivec >> ((pin-4) << 2) & 0xF; 679 } else { /* Corrupted map */ 680 printk("PCIC: BAD PIN %d FOR %s\n", pin, name); 681 for (;;) {} 682 } 683/* P3 */ /* printk("PCIC: dev %s pin %d ivec 0x%x irq %x\n", name, pin, ivec, irq); */ 684 return irq; 685} 686 687/* Makes compiler happy */ 688static volatile int pcic_timer_dummy; 689 690static void pcic_clear_clock_irq(void) 691{ 692 pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT); 693} 694 695static void pcic_timer_handler (int irq, void *h, struct pt_regs *regs) 696{ 697 pcic_clear_clock_irq(); 698 do_timer(regs); 699} 700 701#define USECS_PER_JIFFY 10000 /* We have 100HZ "standard" timer for sparc */ 702#define TICK_TIMER_LIMIT ((100*1000000/4)/100) 703 704void __init pci_time_init(void) 705{ 706 struct linux_pcic *pcic = &pcic0; 707 unsigned long v; 708 int timer_irq, irq; 709 710 /* A hack until do_gettimeofday prototype is moved to arch specific headers 711 and btfixupped. Patch do_gettimeofday with ba pci_do_gettimeofday; nop */ 712 ((unsigned int *)do_gettimeofday)[0] = 713 0x10800000 | ((((unsigned long)pci_do_gettimeofday - 714 (unsigned long)do_gettimeofday) >> 2) & 0x003fffff); 715 ((unsigned int *)do_gettimeofday)[1] = 0x01000000; 716 BTFIXUPSET_CALL(bus_do_settimeofday, pci_do_settimeofday, BTFIXUPCALL_NORM); 717 btfixup(); 718 719 writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT); 720 /* PROM should set appropriate irq */ 721 v = readb(pcic->pcic_regs+PCI_COUNTER_IRQ); 722 timer_irq = PCI_COUNTER_IRQ_SYS(v); 723 writel (PCI_COUNTER_IRQ_SET(timer_irq, 0), 724 pcic->pcic_regs+PCI_COUNTER_IRQ); 725 irq = request_irq(timer_irq, pcic_timer_handler, 726 (SA_INTERRUPT | SA_STATIC_ALLOC), "timer", NULL); 727 if (irq) { 728 prom_printf("time_init: unable to attach IRQ%d\n", timer_irq); 729 prom_halt(); 730 } 731 __sti(); 732} 733 734static __inline__ unsigned long do_gettimeoffset(void) 735{ 736 struct tasklet_struct *t; 737 unsigned long offset = 0; 738 739 /* 740 * We devide all to 100 741 * to have microsecond resolution and to avoid overflow 742 */ 743 unsigned long count = 744 readl(pcic0.pcic_regs+PCI_SYS_COUNTER) & ~PCI_SYS_COUNTER_OVERFLOW; 745 count = ((count/100)*USECS_PER_JIFFY) / (TICK_TIMER_LIMIT/100); 746 747 t = &bh_task_vec[TIMER_BH]; 748 if (test_bit(TASKLET_STATE_SCHED, &t->state)) 749 offset = 1000000; 750 return offset + count; 751} 752 753extern volatile unsigned long wall_jiffies; 754 755static void pci_do_gettimeofday(struct timeval *tv) 756{ 757 unsigned long flags; 758 759 save_and_cli(flags); 760 *tv = xtime; 761 tv->tv_usec += do_gettimeoffset(); 762 763 /* 764 * xtime is atomically updated in timer_bh. The difference 765 * between jiffies and wall_jiffies is nonzero if the timer 766 * bottom half hasnt executed yet. 767 */ 768 if ((jiffies - wall_jiffies) != 0) 769 tv->tv_usec += USECS_PER_JIFFY; 770 771 restore_flags(flags); 772 773 if (tv->tv_usec >= 1000000) { 774 tv->tv_usec -= 1000000; 775 tv->tv_sec++; 776 } 777} 778 779static void pci_do_settimeofday(struct timeval *tv) 780{ 781 cli(); 782 tv->tv_usec -= do_gettimeoffset(); 783 if(tv->tv_usec < 0) { 784 tv->tv_usec += 1000000; 785 tv->tv_sec--; 786 } 787 xtime = *tv; 788 time_adjust = 0; /* stop active adjtime() */ 789 time_status |= STA_UNSYNC; 790 time_maxerror = NTP_PHASE_LIMIT; 791 time_esterror = NTP_PHASE_LIMIT; 792 sti(); 793} 794 795 796/* 797 * Other archs parse arguments here. 798 */ 799char * __init pcibios_setup(char *str) 800{ 801 return str; 802} 803 804/* 805 */ 806void pcibios_update_resource(struct pci_dev *pdev, struct resource *res1, 807 struct resource *res2, int index) 808{ 809} 810 811void pcibios_align_resource(void *data, struct resource *res, 812 unsigned long size, unsigned long align) 813{ 814} 815 816int pcibios_enable_device(struct pci_dev *pdev, int mask) 817{ 818 return 0; 819} 820 821/* 822 * NMI 823 */ 824void pcic_nmi(unsigned int pend, struct pt_regs *regs) 825{ 826 827 pend = flip_dword(pend); 828 829 if (!pcic_speculative || (pend & PCI_SYS_INT_PENDING_PIO) == 0) { 830 printk("Aiee, NMI pend 0x%x pc 0x%x spec %d, hanging\n", 831 pend, (int)regs->pc, pcic_speculative); 832 for (;;) { } 833 } 834 pcic_speculative = 0; 835 pcic_trapped = 1; 836 regs->pc = regs->npc; 837 regs->npc += 4; 838} 839 840static inline unsigned long get_irqmask(int irq_nr) 841{ 842 return 1 << irq_nr; 843} 844 845static inline char *pcic_irq_itoa(unsigned int irq) 846{ 847 static char buff[16]; 848 sprintf(buff, "%d", irq); 849 return buff; 850} 851 852static void pcic_disable_irq(unsigned int irq_nr) 853{ 854 unsigned long mask, flags; 855 856 mask = get_irqmask(irq_nr); 857 save_and_cli(flags); 858 writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET); 859 restore_flags(flags); 860} 861 862static void pcic_enable_irq(unsigned int irq_nr) 863{ 864 unsigned long mask, flags; 865 866 mask = get_irqmask(irq_nr); 867 save_and_cli(flags); 868 writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR); 869 restore_flags(flags); 870} 871 872static void pcic_clear_profile_irq(int cpu) 873{ 874 printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__); 875} 876 877static void pcic_load_profile_irq(int cpu, unsigned int limit) 878{ 879 printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__); 880} 881 882/* We assume the caller is local cli()'d when these are called, or else 883 * very bizarre behavior will result. 884 */ 885static void pcic_disable_pil_irq(unsigned int pil) 886{ 887 writel(get_irqmask(pil), pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET); 888} 889 890static void pcic_enable_pil_irq(unsigned int pil) 891{ 892 writel(get_irqmask(pil), pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR); 893} 894 895void __init sun4m_pci_init_IRQ(void) 896{ 897 BTFIXUPSET_CALL(enable_irq, pcic_enable_irq, BTFIXUPCALL_NORM); 898 BTFIXUPSET_CALL(disable_irq, pcic_disable_irq, BTFIXUPCALL_NORM); 899 BTFIXUPSET_CALL(enable_pil_irq, pcic_enable_pil_irq, BTFIXUPCALL_NORM); 900 BTFIXUPSET_CALL(disable_pil_irq, pcic_disable_pil_irq, BTFIXUPCALL_NORM); 901 BTFIXUPSET_CALL(clear_clock_irq, pcic_clear_clock_irq, BTFIXUPCALL_NORM); 902 BTFIXUPSET_CALL(clear_profile_irq, pcic_clear_profile_irq, BTFIXUPCALL_NORM); 903 BTFIXUPSET_CALL(load_profile_irq, pcic_load_profile_irq, BTFIXUPCALL_NORM); 904 BTFIXUPSET_CALL(__irq_itoa, pcic_irq_itoa, BTFIXUPCALL_NORM); 905} 906 907int pcibios_assign_resource(struct pci_dev *pdev, int resource) 908{ 909 return -ENXIO; 910} 911 912/* 913 * This probably belongs here rather than ioport.c because 914 * we do not want this crud linked into SBus kernels. 915 * Also, think for a moment about likes of floppy.c that 916 * include architecture specific parts. They may want to redefine ins/outs. 917 * 918 * We do not use horroble macroses here because we want to 919 * advance pointer by sizeof(size). 920 */ 921void outsb(unsigned long addr, const void *src, unsigned long count) { 922 while (count) { 923 count -= 1; 924 writeb(*(const char *)src, addr); 925 src += 1; 926 addr += 1; 927 } 928} 929 930void outsw(unsigned long addr, const void *src, unsigned long count) { 931 while (count) { 932 count -= 2; 933 writew(*(const short *)src, addr); 934 src += 2; 935 addr += 2; 936 } 937} 938 939void outsl(unsigned long addr, const void *src, unsigned long count) { 940 while (count) { 941 count -= 4; 942 writel(*(const long *)src, addr); 943 src += 4; 944 addr += 4; 945 } 946} 947 948void insb(unsigned long addr, void *dst, unsigned long count) { 949 while (count) { 950 count -= 1; 951 *(unsigned char *)dst = readb(addr); 952 dst += 1; 953 addr += 1; 954 } 955} 956 957void insw(unsigned long addr, void *dst, unsigned long count) { 958 while (count) { 959 count -= 2; 960 *(unsigned short *)dst = readw(addr); 961 dst += 2; 962 addr += 2; 963 } 964} 965 966void insl(unsigned long addr, void *dst, unsigned long count) { 967 while (count) { 968 count -= 4; 969 *(unsigned long *)dst = readl(addr); 970 dst += 4; 971 addr += 4; 972 } 973} 974 975#endif 976