1/* 2 * BK Id: SCCS/s.mbx.h 1.11 08/17/01 15:23:17 paulus 3 */ 4/* 5 * A collection of structures, addresses, and values associated with 6 * the Motorola MBX boards. This was originally created for the 7 * MBX860, and probably needs revisions for other boards (like the 821). 8 * When this file gets out of control, we can split it up into more 9 * meaningful pieces. 10 * 11 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 12 */ 13#ifdef __KERNEL__ 14#ifndef __MACH_MBX_DEFS 15#define __MACH_MBX_DEFS 16 17#ifndef __ASSEMBLY__ 18/* A Board Information structure that is given to a program when 19 * EPPC-Bug starts it up. 20 */ 21typedef struct bd_info { 22 unsigned int bi_tag; /* Should be 0x42444944 "BDID" */ 23 unsigned int bi_size; /* Size of this structure */ 24 unsigned int bi_revision; /* revision of this structure */ 25 unsigned int bi_bdate; /* EPPCbug date, i.e. 0x11061997 */ 26 unsigned int bi_memstart; /* Memory start address */ 27 unsigned int bi_memsize; /* Memory (end) size in bytes */ 28 unsigned int bi_intfreq; /* Internal Freq, in Hz */ 29 unsigned int bi_busfreq; /* Bus Freq, in Hz */ 30 unsigned int bi_clun; /* Boot device controller */ 31 unsigned int bi_dlun; /* Boot device logical dev */ 32 33 /* These fields are not part of the board information structure 34 * provided by the boot rom. They are filled in by embed_config.c 35 * so we have the information consistent with other platforms. 36 */ 37 unsigned char bi_enetaddr[6]; 38 unsigned int bi_baudrate; 39} bd_t; 40 41/* Memory map for the MBX as configured by EPPC-Bug. We could reprogram 42 * The SIU and PCI bridge, and try to use larger MMU pages, but the 43 * performance gain is not measureable and it certainly complicates the 44 * generic MMU model. 45 * 46 * In a effort to minimize memory usage for embedded applications, any 47 * PCI driver or ISA driver must request or map the region required by 48 * the device. For convenience (and since we can map up to 4 Mbytes with 49 * a single page table page), the MMU initialization will map the 50 * NVRAM, Status/Control registers, CPM Dual Port RAM, and the PCI 51 * Bridge CSRs 1:1 into the kernel address space. 52 */ 53#define PCI_ISA_IO_ADDR ((unsigned)0x80000000) 54#define PCI_ISA_IO_SIZE ((uint)(512 * 1024 * 1024)) 55#define PCI_IDE_ADDR ((unsigned)0x81000000) 56#define PCI_ISA_MEM_ADDR ((unsigned)0xc0000000) 57#define PCI_ISA_MEM_SIZE ((uint)(512 * 1024 * 1024)) 58#define PCMCIA_MEM_ADDR ((uint)0xe0000000) 59#define PCMCIA_MEM_SIZE ((uint)(64 * 1024 * 1024)) 60#define PCMCIA_DMA_ADDR ((uint)0xe4000000) 61#define PCMCIA_DMA_SIZE ((uint)(64 * 1024 * 1024)) 62#define PCMCIA_ATTRB_ADDR ((uint)0xe8000000) 63#define PCMCIA_ATTRB_SIZE ((uint)(64 * 1024 * 1024)) 64#define PCMCIA_IO_ADDR ((uint)0xec000000) 65#define PCMCIA_IO_SIZE ((uint)(64 * 1024 * 1024)) 66#define NVRAM_ADDR ((uint)0xfa000000) 67#define NVRAM_SIZE ((uint)(1 * 1024 * 1024)) 68#define MBX_CSR_ADDR ((uint)0xfa100000) 69#define MBX_CSR_SIZE ((uint)(1 * 1024 * 1024)) 70#define IMAP_ADDR ((uint)0xfa200000) 71#define IMAP_SIZE ((uint)(64 * 1024)) 72#define PCI_CSR_ADDR ((uint)0xfa210000) 73#define PCI_CSR_SIZE ((uint)(64 * 1024)) 74 75/* Map additional physical space into well known virtual addresses. Due 76 * to virtual address mapping, these physical addresses are not accessible 77 * in a 1:1 virtual to physical mapping. 78 */ 79#define ISA_IO_VIRT_ADDR ((uint)0xfa220000) 80#define ISA_IO_VIRT_SIZE ((uint)64 * 1024) 81 82/* Interrupt assignments. 83 * These are defined (and fixed) by the MBX hardware implementation. 84 */ 85#define POWER_FAIL_INT SIU_IRQ0 /* Power fail */ 86#define TEMP_HILO_INT SIU_IRQ1 /* Temperature sensor */ 87#define QSPAN_INT SIU_IRQ2 /* PCI Bridge (DMA CTLR?) */ 88#define ISA_BRIDGE_INT SIU_IRQ3 /* All those PC things */ 89#define COMM_L_INT SIU_IRQ6 /* MBX Comm expansion connector pin */ 90#define STOP_ABRT_INT SIU_IRQ7 /* Stop/Abort header pin */ 91#endif /* !__ASSEMBLY__ */ 92 93/* The MBX uses the 8259. 94*/ 95#define NR_8259_INTS 16 96 97#endif 98#endif /* __KERNEL__ */ 99