1/*
2 * BK Id: %F% %I% %G% %U% %#%
3 */
4/*
5 * CHRP pci routines.
6 */
7
8#include <linux/config.h>
9#include <linux/kernel.h>
10#include <linux/pci.h>
11#include <linux/delay.h>
12#include <linux/string.h>
13#include <linux/init.h>
14#include <linux/ide.h>
15#include <linux/bootmem.h>
16
17#include <asm/io.h>
18#include <asm/pgtable.h>
19#include <asm/irq.h>
20#include <asm/hydra.h>
21#include <asm/prom.h>
22#include <asm/gg2.h>
23#include <asm/machdep.h>
24#include <asm/sections.h>
25#include <asm/pci-bridge.h>
26#include <asm/open_pic.h>
27
28/* LongTrail */
29unsigned long gg2_pci_config_base;
30
31#define pci_config_addr(dev, offset) \
32(gg2_pci_config_base | ((dev->bus->number)<<16) | ((dev->devfn)<<8) | (offset))
33
34volatile struct Hydra *Hydra = NULL;
35
36/*
37 * The VLSI Golden Gate II has only 512K of PCI configuration space, so we
38 * limit the bus number to 3 bits
39 */
40
41#define cfg_read(val, addr, type, op)	*val = op((type)(addr))
42#define cfg_write(val, addr, type, op)	op((type *)(addr), (val))
43
44#define cfg_read_bad(val, size)		*val = bad_##size;
45#define cfg_write_bad(val, size)
46
47#define bad_byte	0xff
48#define bad_word	0xffff
49#define bad_dword	0xffffffffU
50
51#define GG2_PCI_OP(rw, size, type, op)					    \
52int __chrp gg2_##rw##_config_##size(struct pci_dev *dev, int off, type val) \
53{									    \
54	if (dev->bus->number > 7) {					    \
55		cfg_##rw##_bad(val, size)				    \
56		return PCIBIOS_DEVICE_NOT_FOUND;			    \
57	}								    \
58	cfg_##rw(val, pci_config_addr(dev, off), type, op);		    \
59	return PCIBIOS_SUCCESSFUL;					    \
60}
61
62GG2_PCI_OP(read, byte, u8 *, in_8)
63GG2_PCI_OP(read, word, u16 *, in_le16)
64GG2_PCI_OP(read, dword, u32 *, in_le32)
65GG2_PCI_OP(write, byte, u8, out_8)
66GG2_PCI_OP(write, word, u16, out_le16)
67GG2_PCI_OP(write, dword, u32, out_le32)
68
69static struct pci_ops gg2_pci_ops =
70{
71	gg2_read_config_byte,
72	gg2_read_config_word,
73	gg2_read_config_dword,
74	gg2_write_config_byte,
75	gg2_write_config_word,
76	gg2_write_config_dword
77};
78
79/*
80 * Access functions for PCI config space on IBM "python" host bridges.
81 */
82#define PYTHON_CFA(b, d, o)	(0x80 | ((b) << 8) | ((d) << 16) \
83				 | (((o) & ~3) << 24))
84
85#define PYTHON_PCI_OP(rw, size, type, op, mask)			    	     \
86int __chrp								     \
87python_##rw##_config_##size(struct pci_dev *dev, int offset, type val) 	     \
88{									     \
89	struct pci_controller *hose = dev->sysdata;			     \
90									     \
91	out_be32(hose->cfg_addr,					     \
92		 PYTHON_CFA(dev->bus->number, dev->devfn, offset));	     \
93	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);   	     \
94	return PCIBIOS_SUCCESSFUL;					     \
95}
96
97PYTHON_PCI_OP(read, byte, u8 *, in_8, 3)
98PYTHON_PCI_OP(read, word, u16 *, in_le16, 2)
99PYTHON_PCI_OP(read, dword, u32 *, in_le32, 0)
100PYTHON_PCI_OP(write, byte, u8, out_8, 3)
101PYTHON_PCI_OP(write, word, u16, out_le16, 2)
102PYTHON_PCI_OP(write, dword, u32, out_le32, 0)
103
104static struct pci_ops python_pci_ops =
105{
106	python_read_config_byte,
107	python_read_config_word,
108	python_read_config_dword,
109	python_write_config_byte,
110	python_write_config_word,
111	python_write_config_dword
112};
113
114/*
115 * Access functions for PCI config space using RTAS calls.
116 */
117#define RTAS_PCI_READ_OP(size, type, nbytes)			    	  \
118int __chrp								  \
119rtas_read_config_##size(struct pci_dev *dev, int offset, type val) 	  \
120{									  \
121	unsigned long addr = (offset & 0xff) | ((dev->devfn & 0xff) << 8) \
122		| ((dev->bus->number & 0xff) << 16);			  \
123	unsigned long ret = ~0UL;					  \
124	int rval;							  \
125									  \
126	rval = call_rtas("read-pci-config", 2, 2, &ret, addr, nbytes);	  \
127	*val = ret;							  \
128	return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;    	  \
129}
130
131#define RTAS_PCI_WRITE_OP(size, type, nbytes)				  \
132int __chrp								  \
133rtas_write_config_##size(struct pci_dev *dev, int offset, type val)	  \
134{									  \
135	unsigned long addr = (offset & 0xff) | ((dev->devfn & 0xff) << 8) \
136		| ((dev->bus->number & 0xff) << 16);			  \
137	int rval;							  \
138									  \
139	rval = call_rtas("write-pci-config", 3, 1, NULL,		  \
140			 addr, nbytes, (ulong)val);			  \
141	return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;	  \
142}
143
144RTAS_PCI_READ_OP(byte, u8 *, 1)
145RTAS_PCI_READ_OP(word, u16 *, 2)
146RTAS_PCI_READ_OP(dword, u32 *, 4)
147RTAS_PCI_WRITE_OP(byte, u8, 1)
148RTAS_PCI_WRITE_OP(word, u16, 2)
149RTAS_PCI_WRITE_OP(dword, u32, 4)
150
151static struct pci_ops rtas_pci_ops =
152{
153	rtas_read_config_byte,
154	rtas_read_config_word,
155	rtas_read_config_dword,
156	rtas_write_config_byte,
157	rtas_write_config_word,
158	rtas_write_config_dword
159};
160
161int __init
162hydra_init(void)
163{
164	struct device_node *np;
165
166	np = find_devices("mac-io");
167	if (np == NULL || np->n_addrs == 0)
168		return 0;
169	Hydra = ioremap(np->addrs[0].address, np->addrs[0].size);
170	printk("Hydra Mac I/O at %x\n", np->addrs[0].address);
171	out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
172					   HYDRA_FC_SCSI_CELL_EN |
173					   HYDRA_FC_SCCA_ENABLE |
174					   HYDRA_FC_SCCB_ENABLE |
175					   HYDRA_FC_ARB_BYPASS |
176					   HYDRA_FC_MPIC_ENABLE |
177					   HYDRA_FC_SLOW_SCC_PCLK |
178					   HYDRA_FC_MPIC_IS_MASTER));
179	return 1;
180}
181
182void __init
183chrp_pcibios_fixup(void)
184{
185	struct pci_dev *dev;
186	struct device_node *np;
187
188	/* PCI interrupts are controlled by the OpenPIC */
189	pci_for_each_dev(dev) {
190		np = pci_device_to_OF_node(dev);
191		if ((np != 0) && (np->n_intrs > 0) && (np->intrs[0].line != 0))
192			dev->irq = np->intrs[0].line;
193		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
194	}
195}
196
197#define PRG_CL_RESET_VALID 0x00010000
198
199static void __init
200setup_python(struct pci_controller *hose, struct device_node *dev)
201{
202	u32 *reg, val;
203	volatile unsigned char *cfg;
204
205	hose->ops = &python_pci_ops;
206	cfg = ioremap(dev->addrs[0].address + 0xf8000, 0x20);
207	hose->cfg_addr = (volatile unsigned int *) cfg;
208	hose->cfg_data = cfg + 0x10;
209
210	/* Clear the magic go-slow bit */
211	reg = (u32 *) ioremap(dev->addrs[0].address + 0xf6000, 0x40);
212	val = in_be32(&reg[12]);
213	if (val & PRG_CL_RESET_VALID) {
214		out_be32(&reg[12], val & ~PRG_CL_RESET_VALID);
215		in_be32(&reg[12]);
216	}
217	iounmap(reg);
218}
219
220void __init
221chrp_find_bridges(void)
222{
223	struct device_node *dev;
224	int *bus_range;
225	int len, index = -1;
226	struct pci_controller *hose;
227	unsigned int *dma;
228	char *model, *machine;
229	int is_longtrail = 0, is_mot = 0;
230	struct device_node *root = find_path_device("/");
231
232	/*
233	 * The PCI host bridge nodes on some machines don't have
234	 * properties to adequately identify them, so we have to
235	 * look at what sort of machine this is as well.
236	 */
237	machine = get_property(root, "model", NULL);
238	if (machine != NULL) {
239		is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
240		is_mot = strncmp(machine, "MOT", 3) == 0;
241	}
242	for (dev = root->child; dev != NULL; dev = dev->sibling) {
243		if (dev->type == NULL || strcmp(dev->type, "pci") != 0)
244			continue;
245		++index;
246		/* The GG2 bridge on the LongTrail doesn't have an address */
247		if (dev->n_addrs < 1 && !is_longtrail) {
248			printk(KERN_WARNING "Can't use %s: no address\n",
249			       dev->full_name);
250			continue;
251		}
252		bus_range = (int *) get_property(dev, "bus-range", &len);
253		if (bus_range == NULL || len < 2 * sizeof(int)) {
254			printk(KERN_WARNING "Can't get bus-range for %s\n",
255				dev->full_name);
256			continue;
257		}
258		if (bus_range[1] == bus_range[0])
259			printk(KERN_INFO "PCI bus %d", bus_range[0]);
260		else
261			printk(KERN_INFO "PCI buses %d..%d",
262			       bus_range[0], bus_range[1]);
263		printk(" controlled by %s", dev->type);
264		if (dev->n_addrs > 0)
265			printk(" at %x", dev->addrs[0].address);
266		printk("\n");
267
268		hose = pcibios_alloc_controller();
269		if (!hose) {
270			printk("Can't allocate PCI controller structure for %s\n",
271				dev->full_name);
272			continue;
273		}
274		hose->arch_data = dev;
275		hose->first_busno = bus_range[0];
276		hose->last_busno = bus_range[1];
277
278		model = get_property(dev, "model", NULL);
279		if (model == NULL)
280			model = "<none>";
281		if (device_is_compatible(dev, "IBM,python")) {
282			setup_python(hose, dev);
283		} else if (is_mot
284			   || strncmp(model, "Motorola, Grackle", 17) == 0) {
285			setup_grackle(hose);
286		} else if (is_longtrail) {
287			hose->ops = &gg2_pci_ops;
288			gg2_pci_config_base = (unsigned long)
289				ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
290		} else if (!strncmp(model, "IBM,CPC710", 10)) {
291			setup_indirect_pci(hose,
292				dev->addrs[0].address + 0x000f8000,
293				dev->addrs[0].address + 0x000f8010);
294			if (index == 0) {
295				dma = (unsigned int *)
296					get_property(dev, "system-dma-base", &len);
297			 	if (dma && len >= sizeof(*dma)) {
298					dma = (unsigned int *)(((unsigned long)dma) +
299						len - sizeof(*dma));
300					pci_dram_offset = *dma;
301				}
302			}
303		} else {
304			printk("No methods for %s (model %s), using RTAS\n",
305			       dev->full_name, model);
306			hose->ops = &rtas_pci_ops;
307		}
308
309		pci_process_bridge_OF_ranges(hose, dev, index == 0);
310
311		/* check the first bridge for a property that we can
312		   use to set pci_dram_offset */
313		dma = (unsigned int *)
314			get_property(dev, "ibm,dma-ranges", &len);
315		if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
316			pci_dram_offset = dma[2] - dma[3];
317			printk("pci_dram_offset = %lx\n", pci_dram_offset);
318		}
319	}
320
321	ppc_md.pcibios_fixup = chrp_pcibios_fixup;
322}
323