1/* 2 * FILE NAME 3 * arch/mips/vr41xx/common/int-handler.S 4 * 5 * BRIEF MODULE DESCRIPTION 6 * Interrupt dispatcher for the NEC VR4100 series. 7 * 8 * Author: Yoichi Yuasa 9 * yyuasa@mvista.com or source@mvista.com 10 * 11 * Copyright 2001 MontaVista Software Inc. 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 * 18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 24 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 26 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 27 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * You should have received a copy of the GNU General Public License along 30 * with this program; if not, write to the Free Software Foundation, Inc., 31 * 675 Mass Ave, Cambridge, MA 02139, USA. 32 */ 33/* 34 * Changes: 35 * MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com> 36 * - New creation, NEC VR4100 series are supported. 37 */ 38#include <asm/asm.h> 39#include <asm/regdef.h> 40#include <asm/mipsregs.h> 41#include <asm/stackframe.h> 42 43 .text 44 .set noreorder 45 46 .align 5 47 NESTED(vr41xx_handle_interrupt, PT_SIZE, ra) 48 .set noat 49 SAVE_ALL 50 CLI 51 .set at 52 .set noreorder 53 54 /* 55 * Get the pending interrupts 56 */ 57 mfc0 t0, CP0_CAUSE 58 mfc0 t1, CP0_STATUS 59 andi t0, 0xff00 60 and t0, t0, t1 61 62 andi t1, t0, CAUSEF_IP7 # timer interrupt 63 beqz t1, 1f 64 li a0, 7 65 jal ll_timer_interrupt 66 move a1, sp 67 j ret_from_irq 68 691: 70 andi t1, t0, 0x7800 # check for IP3-6 71 beqz t1, 2f 72 73 andi t1, t0, CAUSEF_IP3 # check for IP3 74 bnez t1, handle_it 75 li a0, 3 76 77 andi t1, t0, CAUSEF_IP4 # check for IP4 78 bnez t1, handle_it 79 li a0, 4 80 81 andi t1, t0, CAUSEF_IP5 # check for IP5 82 bnez t1, handle_it 83 li a0, 5 84 85 andi t1, t0, CAUSEF_IP6 # check for IP6 86 bnez t1, handle_it 87 li a0, 6 88 892: 90 andi t1, t0, CAUSEF_IP2 # check for IP2 91 beqz t1, 3f 92 move a0, sp 93 jal icu_irqdispatch 94 nop 95 j ret_from_irq 96 nop 97 983: 99 andi t1, t0, CAUSEF_IP0 # check for IP0 100 bnez t1, handle_it 101 li a0, 0 102 103 andi t1, t0, CAUSEF_IP1 # check for IP1 104 bnez t1, handle_it 105 li a0, 1 106 107 j spurious_interrupt 108 nop 109 110handle_it: 111 jal do_IRQ 112 move a1, sp 113 j ret_from_irq 114 END(vr41xx_handle_interrupt) 115