1/*
2 *  linux/arch/mips/kernel/proc.c
3 *
4 *  Copyright (C) 1995, 1996, 2001  Ralf Baechle
5 *  Copyright (C) 2001  MIPS Technologies, Inc.
6 */
7#include <linux/config.h>
8#include <linux/delay.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/seq_file.h>
12#include <asm/bootinfo.h>
13#include <asm/cpu.h>
14#include <asm/mipsregs.h>
15#include <asm/processor.h>
16#include <asm/watch.h>
17
18unsigned int vced_count, vcei_count;
19
20#ifndef CONFIG_CPU_HAS_LLSC
21unsigned long ll_ops, sc_ops;
22#endif
23
24static const char *cpu_name[] = {
25	[CPU_UNKNOWN]	"unknown",
26	[CPU_R2000]	"R2000",
27	[CPU_R3000]	"R3000",
28	[CPU_R3000A]	"R3000A",
29	[CPU_R3041]	"R3041",
30	[CPU_R3051]	"R3051",
31	[CPU_R3052]	"R3052",
32	[CPU_R3081]	"R3081",
33	[CPU_R3081E]	"R3081E",
34	[CPU_R4000PC]	"R4000PC",
35	[CPU_R4000SC]	"R4000SC",
36	[CPU_R4000MC]	"R4000MC",
37        [CPU_R4200]	"R4200",
38	[CPU_R4400PC]	"R4400PC",
39	[CPU_R4400SC]	"R4400SC",
40	[CPU_R4400MC]	"R4400MC",
41	[CPU_R4600]	"R4600",
42	[CPU_R6000]	"R6000",
43        [CPU_R6000A]	"R6000A",
44	[CPU_R8000]	"R8000",
45	[CPU_R10000]	"R10000",
46	[CPU_R4300]	"R4300",
47	[CPU_R4650]	"R4650",
48	[CPU_R4700]	"R4700",
49	[CPU_R5000]	"R5000",
50        [CPU_R5000A]	"R5000A",
51	[CPU_R4640]	"R4640",
52	[CPU_NEVADA]	"Nevada",
53	[CPU_RM7000]	"RM7000",
54	[CPU_R5432]	"R5432",
55	[CPU_4KC]	"MIPS 4Kc",
56        [CPU_5KC]	"MIPS 5Kc",
57	[CPU_R4310]	"R4310",
58	[CPU_SB1]	"SiByte SB1",
59	[CPU_TX3912]	"TX3912",
60	[CPU_TX3922]	"TX3922",
61	[CPU_TX3927]	"TX3927",
62	[CPU_AU1000]	"Au1000",
63	[CPU_AU1500]	"Au1500",
64	[CPU_4KEC]	"MIPS 4KEc",
65	[CPU_4KSC]	"MIPS 4KSc",
66	[CPU_VR41XX]	"NEC Vr41xx",
67	[CPU_R5500]	"R5500",
68	[CPU_TX49XX]	"TX49xx",
69	[CPU_TX39XX]	"TX39xx",
70	[CPU_20KC]	"MIPS 20Kc",
71	[CPU_VR4111]	"NEC VR4111",
72	[CPU_VR4121]	"NEC VR4121",
73	[CPU_VR4122]	"NEC VR4122",
74	[CPU_VR4131]	"NEC VR4131",
75	[CPU_VR4181]	"NEC VR4181",
76	[CPU_VR4181A]	"NEC VR4181A",
77	[CPU_BCM4710]	"BCM4710",
78	[CPU_BCM3302]	"BCM3302",
79};
80
81extern unsigned long unaligned_instructions;
82
83static int show_cpuinfo(struct seq_file *m, void *v)
84{
85	unsigned int version = mips_cpu.processor_id;
86	unsigned int fp_vers = mips_cpu.fpu_id;
87	unsigned long n = (unsigned long) v - 1;
88	char fmt [64];
89
90#ifdef CONFIG_SMP
91	if (!CPUMASK_TSTB(cpu_online_map, n))
92		return 0;
93#endif
94
95	/*
96	 * For the first processor also print the system type
97	 */
98	if (n == 0)
99		seq_printf(m, "system type\t\t: %s\n", get_system_type());
100
101	seq_printf(m, "processor\t\t: %ld\n", n);
102	sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
103	        (mips_cpu.options & MIPS_CPU_FPU) ? "  FPU V%d.%d" : "");
104	seq_printf(m, fmt, cpu_name[mips_cpu.cputype <= CPU_LAST ?
105	                            mips_cpu.cputype : CPU_UNKNOWN],
106	                           (version >> 4) & 0x0f, version & 0x0f,
107	                           (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
108	seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n",
109	              loops_per_jiffy / (500000/HZ),
110	              (loops_per_jiffy / (5000/HZ)) % 100);
111	seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
112	seq_printf(m, "microsecond timers\t: %s\n",
113	              (mips_cpu.options & MIPS_CPU_COUNTER) ? "yes" : "no");
114	seq_printf(m, "tlb_entries\t\t: %d\n", mips_cpu.tlbsize);
115	seq_printf(m, "extra interrupt vector\t: %s\n",
116	              (mips_cpu.options & MIPS_CPU_DIVEC) ? "yes" : "no");
117	seq_printf(m, "hardware watchpoint\t: %s\n",
118	              watch_available ? "yes" : "no");
119
120	sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
121	        (mips_cpu.options & MIPS_CPU_VCE) ? "%d" : "not available");
122	seq_printf(m, fmt, 'D', vced_count);
123	seq_printf(m, fmt, 'I', vcei_count);
124
125#ifndef CONFIG_CPU_HAS_LLSC
126	seq_printf(m, "ll emulations\t\t: %lu\n", ll_ops);
127	seq_printf(m, "sc emulations\t\t: %lu\n", sc_ops);
128#endif
129
130	seq_printf(m, "unaligned_instructions\t: %u\n", unaligned_instructions);
131
132#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4704)
133	seq_printf(m, "dcache hits\t\t: %u\n",
134		   read_perf_cntr(0));
135	seq_printf(m, "dcache misses\t\t: %u\n",
136		   read_perf_cntr(1));
137	seq_printf(m, "icache hits\t\t: %u\n",
138		   read_perf_cntr(2));
139	seq_printf(m, "icache misses\t\t: %u\n",
140		   read_perf_cntr(3));
141	seq_printf(m, "instructions\t\t: %u\n",
142		   read_perf_cntr(4));
143#endif
144
145	return 0;
146}
147
148static void *c_start(struct seq_file *m, loff_t *pos)
149{
150	unsigned long i = *pos;
151
152	return i < NR_CPUS ? (void *) (i + 1) : NULL;
153}
154
155static void *c_next(struct seq_file *m, void *v, loff_t *pos)
156{
157	++*pos;
158	return c_start(m, pos);
159}
160
161static void c_stop(struct seq_file *m, void *v)
162{
163}
164
165struct seq_operations cpuinfo_op = {
166	.start	= c_start,
167	.next	= c_next,
168	.stop	= c_stop,
169	.show	= show_cpuinfo,
170};
171