1/* 2 * BRIEF MODULE DESCRIPTION 3 * Galileo Evaluation Boards PCI support. 4 * 5 * The general-purpose functions to read/write and configure the GT64120A's 6 * PCI registers (function names start with pci0 or pci1) are either direct 7 * copies of functions written by Galileo Technology, or are modifications 8 * of their functions to work with Linux 2.4 vs Linux 2.2. These functions 9 * are Copyright - Galileo Technology. 10 * 11 * Other functions are derived from other MIPS PCI implementations, or were 12 * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc. 13 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com 14 * 15 * Copyright 2001 MontaVista Software Inc. 16 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms of the GNU General Public License as published by the 20 * Free Software Foundation; either version 2 of the License, or (at your 21 * option) any later version. 22 * 23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * You should have received a copy of the GNU General Public License along 35 * with this program; if not, write to the Free Software Foundation, Inc., 36 * 675 Mass Ave, Cambridge, MA 02139, USA. 37 */ 38#include <linux/config.h> 39#include <linux/types.h> 40#include <linux/pci.h> 41#include <linux/kernel.h> 42#include <linux/slab.h> 43#include <linux/version.h> 44#include <asm/pci.h> 45#include <asm/io.h> 46#include <asm/gt64120/gt64120.h> 47 48#include <linux/init.h> 49 50#ifdef CONFIG_PCI 51 52#define SELF 0 53 54/* 55 * These functions and structures provide the BIOS scan and mapping of the PCI 56 * devices. 57 */ 58 59#define MAX_PCI_DEVS 10 60 61struct pci_device { 62 u32 slot; 63 u32 BARtype[6]; 64 u32 BARsize[6]; 65}; 66 67static void __init scan_and_initialize_pci(void); 68static u32 __init scan_pci_bus(struct pci_device *pci_devices); 69static void __init allocate_pci_space(struct pci_device *pci_devices); 70 71/* 72 * The functions that actually read and write to the controller. 73 * 74 * Copied from or modified from Galileo Technology code. 75 */ 76static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device); 77static void pci0WriteConfigReg(unsigned int offset, 78 struct pci_dev *device, unsigned int data); 79static unsigned int pci1ReadConfigReg(int offset, struct pci_dev *device); 80static void pci1WriteConfigReg(unsigned int offset, 81 struct pci_dev *device, unsigned int data); 82 83static void pci0MapIOspace(unsigned int pci0IoBase, 84 unsigned int pci0IoLength); 85static void pci1MapIOspace(unsigned int pci1IoBase, 86 unsigned int pci1IoLength); 87static void pci0MapMemory0space(unsigned int pci0Mem0Base, 88 unsigned int pci0Mem0Length); 89static void pci1MapMemory0space(unsigned int pci1Mem0Base, 90 unsigned int pci1Mem0Length); 91static void pci0MapMemory1space(unsigned int pci0Mem1Base, 92 unsigned int pci0Mem1Length); 93static void pci1MapMemory1space(unsigned int pci1Mem1Base, 94 unsigned int pci1Mem1Length); 95static unsigned int pci0GetIOspaceBase(void); 96static unsigned int pci0GetIOspaceSize(void); 97static unsigned int pci0GetMemory0Base(void); 98static unsigned int pci0GetMemory0Size(void); 99static unsigned int pci0GetMemory1Base(void); 100static unsigned int pci0GetMemory1Size(void); 101static unsigned int pci1GetIOspaceBase(void); 102static unsigned int pci1GetIOspaceSize(void); 103static unsigned int pci1GetMemory0Base(void); 104static unsigned int pci1GetMemory0Size(void); 105static unsigned int pci1GetMemory1Base(void); 106static unsigned int pci1GetMemory1Size(void); 107 108 109/* Functions to implement "pci ops" */ 110static int galileo_pcibios_read_config_word(struct pci_dev *dev, 111 int offset, u16 * val); 112static int galileo_pcibios_read_config_byte(struct pci_dev *dev, 113 int offset, u8 * val); 114static int galileo_pcibios_read_config_dword(struct pci_dev *dev, 115 int offset, u32 * val); 116static int galileo_pcibios_write_config_byte(struct pci_dev *dev, 117 int offset, u8 val); 118static int galileo_pcibios_write_config_word(struct pci_dev *dev, 119 int offset, u16 val); 120static int galileo_pcibios_write_config_dword(struct pci_dev *dev, 121 int offset, u32 val); 122static void galileo_pcibios_set_master(struct pci_dev *dev); 123 124/* 125 * General-purpose PCI functions. 126 */ 127 128/* 129 * pci0MapIOspace - Maps PCI0 IO space for the master. 130 * Inputs: base and length of pci0Io 131 */ 132 133static void pci0MapIOspace(unsigned int pci0IoBase, 134 unsigned int pci0IoLength) 135{ 136 unsigned int pci0IoTop = 137 (unsigned int) (pci0IoBase + pci0IoLength); 138 139 if (pci0IoLength == 0) 140 pci0IoTop++; 141 142 pci0IoBase = (unsigned int) (pci0IoBase >> 21); 143 pci0IoTop = (unsigned int) (((pci0IoTop - 1) & 0x0fffffff) >> 21); 144 GT_WRITE(GT_PCI0IOLD_OFS, pci0IoBase); 145 GT_WRITE(GT_PCI0IOHD_OFS, pci0IoTop); 146} 147 148/* 149 * pci1MapIOspace - Maps PCI1 IO space for the master. 150 * Inputs: base and length of pci1Io 151 */ 152 153static void pci1MapIOspace(unsigned int pci1IoBase, 154 unsigned int pci1IoLength) 155{ 156 unsigned int pci1IoTop = 157 (unsigned int) (pci1IoBase + pci1IoLength); 158 159 if (pci1IoLength == 0) 160 pci1IoTop++; 161 162 pci1IoBase = (unsigned int) (pci1IoBase >> 21); 163 pci1IoTop = (unsigned int) (((pci1IoTop - 1) & 0x0fffffff) >> 21); 164 GT_WRITE(GT_PCI1IOLD_OFS, pci1IoBase); 165 GT_WRITE(GT_PCI1IOHD_OFS, pci1IoTop); 166} 167 168/* 169 * pci0MapMemory0space - Maps PCI0 memory0 space for the master. 170 * Inputs: base and length of pci0Mem0 171 */ 172 173static void pci0MapMemory0space(unsigned int pci0Mem0Base, 174 unsigned int pci0Mem0Length) 175{ 176 unsigned int pci0Mem0Top = pci0Mem0Base + pci0Mem0Length; 177 178 if (pci0Mem0Length == 0) 179 pci0Mem0Top++; 180 181 pci0Mem0Base = pci0Mem0Base >> 21; 182 pci0Mem0Top = ((pci0Mem0Top - 1) & 0x0fffffff) >> 21; 183 GT_WRITE(GT_PCI0M0LD_OFS, pci0Mem0Base); 184 GT_WRITE(GT_PCI0M0HD_OFS, pci0Mem0Top); 185} 186 187/* 188 * pci1MapMemory0space - Maps PCI1 memory0 space for the master. 189 * Inputs: base and length of pci1Mem0 190 */ 191 192static void pci1MapMemory0space(unsigned int pci1Mem0Base, 193 unsigned int pci1Mem0Length) 194{ 195 unsigned int pci1Mem0Top = pci1Mem0Base + pci1Mem0Length; 196 197 if (pci1Mem0Length == 0) 198 pci1Mem0Top++; 199 200 pci1Mem0Base = pci1Mem0Base >> 21; 201 pci1Mem0Top = ((pci1Mem0Top - 1) & 0x0fffffff) >> 21; 202 GT_WRITE(GT_PCI1M0LD_OFS, pci1Mem0Base); 203 GT_WRITE(GT_PCI1M0HD_OFS, pci1Mem0Top); 204} 205 206/* 207 * pci0MapMemory1space - Maps PCI0 memory1 space for the master. 208 * Inputs: base and length of pci0Mem1 209 */ 210 211static void pci0MapMemory1space(unsigned int pci0Mem1Base, 212 unsigned int pci0Mem1Length) 213{ 214 unsigned int pci0Mem1Top = pci0Mem1Base + pci0Mem1Length; 215 216 if (pci0Mem1Length == 0) 217 pci0Mem1Top++; 218 219 pci0Mem1Base = pci0Mem1Base >> 21; 220 pci0Mem1Top = ((pci0Mem1Top - 1) & 0x0fffffff) >> 21; 221 GT_WRITE(GT_PCI0M1LD_OFS, pci0Mem1Base); 222 GT_WRITE(GT_PCI0M1HD_OFS, pci0Mem1Top); 223 224} 225 226/* 227 * pci1MapMemory1space - Maps PCI1 memory1 space for the master. 228 * Inputs: base and length of pci1Mem1 229 */ 230 231static void pci1MapMemory1space(unsigned int pci1Mem1Base, 232 unsigned int pci1Mem1Length) 233{ 234 unsigned int pci1Mem1Top = pci1Mem1Base + pci1Mem1Length; 235 236 if (pci1Mem1Length == 0) 237 pci1Mem1Top++; 238 239 pci1Mem1Base = pci1Mem1Base >> 21; 240 pci1Mem1Top = ((pci1Mem1Top - 1) & 0x0fffffff) >> 21; 241 GT_WRITE(GT_PCI1M1LD_OFS, pci1Mem1Base); 242 GT_WRITE(GT_PCI1M1HD_OFS, pci1Mem1Top); 243} 244 245/* 246 * pci0GetIOspaceBase - Return PCI0 IO Base Address. 247 * Inputs: N/A 248 * Returns: PCI0 IO Base Address. 249 */ 250 251static unsigned int pci0GetIOspaceBase(void) 252{ 253 unsigned int base; 254 GT_READ(GT_PCI0IOLD_OFS, &base); 255 base = base << 21; 256 return base; 257} 258 259/* 260 * pci0GetIOspaceSize - Return PCI0 IO Bar Size. 261 * Inputs: N/A 262 * Returns: PCI0 IO Bar Size. 263 */ 264 265static unsigned int pci0GetIOspaceSize(void) 266{ 267 unsigned int top, base, size; 268 GT_READ(GT_PCI0IOLD_OFS, &base); 269 base = base << 21; 270 GT_READ(GT_PCI0IOHD_OFS, &top); 271 top = (top << 21); 272 size = ((top - base) & 0xfffffff); 273 size = size | 0x1fffff; 274 return (size + 1); 275} 276 277/* 278 * pci0GetMemory0Base - Return PCI0 Memory 0 Base Address. 279 * Inputs: N/A 280 * Returns: PCI0 Memory 0 Base Address. 281 */ 282 283static unsigned int pci0GetMemory0Base(void) 284{ 285 unsigned int base; 286 GT_READ(GT_PCI0M0LD_OFS, &base); 287 base = base << 21; 288 return base; 289} 290 291/* 292 * pci0GetMemory0Size - Return PCI0 Memory 0 Bar Size. 293 * Inputs: N/A 294 * Returns: PCI0 Memory 0 Bar Size. 295 */ 296 297static unsigned int pci0GetMemory0Size(void) 298{ 299 unsigned int top, base, size; 300 GT_READ(GT_PCI0M0LD_OFS, &base); 301 base = base << 21; 302 GT_READ(GT_PCI0M0HD_OFS, &top); 303 top = (top << 21); 304 size = ((top - base) & 0xfffffff); 305 size = size | 0x1fffff; 306 return (size + 1); 307} 308 309/* 310 * pci0GetMemory1Base - Return PCI0 Memory 1 Base Address. 311 * Inputs: N/A 312 * Returns: PCI0 Memory 1 Base Address. 313 */ 314 315static unsigned int pci0GetMemory1Base(void) 316{ 317 unsigned int base; 318 GT_READ(GT_PCI0M1LD_OFS, &base); 319 base = base << 21; 320 return base; 321} 322 323/* 324 * pci0GetMemory1Size - Return PCI0 Memory 1 Bar Size. 325 * Inputs: N/A 326 * Returns: PCI0 Memory 1 Bar Size. 327 */ 328 329static unsigned int pci0GetMemory1Size(void) 330{ 331 unsigned int top, base, size; 332 GT_READ(GT_PCI0M1LD_OFS, &base); 333 base = base << 21; 334 GT_READ(GT_PCI0M1HD_OFS, &top); 335 top = (top << 21); 336 size = ((top - base) & 0xfffffff); 337 size = size | 0x1fffff; 338 return (size + 1); 339} 340 341/* 342 * pci1GetIOspaceBase - Return PCI1 IO Base Address. 343 * Inputs: N/A 344 * Returns: PCI1 IO Base Address. 345 */ 346 347static unsigned int pci1GetIOspaceBase(void) 348{ 349 unsigned int base; 350 GT_READ(GT_PCI1IOLD_OFS, &base); 351 base = base << 21; 352 return base; 353} 354 355/* 356 * pci1GetIOspaceSize - Return PCI1 IO Bar Size. 357 * Inputs: N/A 358 * Returns: PCI1 IO Bar Size. 359 */ 360 361static unsigned int pci1GetIOspaceSize(void) 362{ 363 unsigned int top, base, size; 364 GT_READ(GT_PCI1IOLD_OFS, &base); 365 base = base << 21; 366 GT_READ(GT_PCI1IOHD_OFS, &top); 367 top = (top << 21); 368 size = ((top - base) & 0xfffffff); 369 size = size | 0x1fffff; 370 return (size + 1); 371} 372 373/* 374 * pci1GetMemory0Base - Return PCI1 Memory 0 Base Address. 375 * Inputs: N/A 376 * Returns: PCI1 Memory 0 Base Address. 377 */ 378 379static unsigned int pci1GetMemory0Base(void) 380{ 381 unsigned int base; 382 GT_READ(GT_PCI1M0LD_OFS, &base); 383 base = base << 21; 384 return base; 385} 386 387/* 388 * pci1GetMemory0Size - Return PCI1 Memory 0 Bar Size. 389 * Inputs: N/A 390 * Returns: PCI1 Memory 0 Bar Size. 391 */ 392 393static unsigned int pci1GetMemory0Size(void) 394{ 395 unsigned int top, base, size; 396 GT_READ(GT_PCI1M1LD_OFS, &base); 397 base = base << 21; 398 GT_READ(GT_PCI1M1HD_OFS, &top); 399 top = (top << 21); 400 size = ((top - base) & 0xfffffff); 401 size = size | 0x1fffff; 402 return (size + 1); 403} 404 405/* 406 * pci1GetMemory1Base - Return PCI1 Memory 1 Base Address. 407 * Inputs: N/A 408 * Returns: PCI1 Memory 1 Base Address. 409 */ 410 411static unsigned int pci1GetMemory1Base(void) 412{ 413 unsigned int base; 414 GT_READ(GT_PCI1M1LD_OFS, &base); 415 base = base << 21; 416 return base; 417} 418 419/* 420 * pci1GetMemory1Size - Return PCI1 Memory 1 Bar Size. 421 * Inputs: N/A 422 * Returns: PCI1 Memory 1 Bar Size. 423 */ 424 425static unsigned int pci1GetMemory1Size(void) 426{ 427 unsigned int top, base, size; 428 GT_READ(GT_PCI1M1LD_OFS, &base); 429 base = base << 21; 430 GT_READ(GT_PCI1M1HD_OFS, &top); 431 top = (top << 21); 432 size = ((top - base) & 0xfffffff); 433 size = size | 0x1fffff; 434 return (size + 1); 435} 436 437 438 439/* 440 * pci_range_ck - 441 * 442 * Check if the pci device that are trying to access does really exists 443 * on the evaluation board. 444 * 445 * Inputs : 446 * bus - bus number (0 for PCI 0 ; 1 for PCI 1) 447 * dev - number of device on the specific pci bus 448 * 449 * Outpus : 450 * 0 - if OK , 1 - if failure 451 */ 452static __inline__ int pci_range_ck(unsigned char bus, unsigned char dev) 453{ 454 /* 455 * We don't even pretend to handle other busses than bus 0 correctly. 456 * Accessing device 31 crashes the CP7000 for some reason. 457 */ 458 if ((bus == 0) && (dev != 31)) 459 return 0; 460 return -1; 461} 462 463/* 464 * pciXReadConfigReg - Read from a PCI configuration register 465 * - Make sure the GT is configured as a master before 466 * reading from another device on the PCI. 467 * - The function takes care of Big/Little endian conversion. 468 * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI 469 * spec) 470 * pciDevNum: The device number needs to be addressed. 471 * RETURNS: data , if the data == 0xffffffff check the master abort bit in the 472 * cause register to make sure the data is valid 473 * 474 * Configuration Address 0xCF8: 475 * 476 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number 477 * |congif|Reserved| Bus |Device|Function|Register|00| 478 * |Enable| |Number|Number| Number | Number | | <=field Name 479 * 480 */ 481static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device) 482{ 483 unsigned int DataForRegCf8; 484 unsigned int data; 485 486 DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | 487 (PCI_FUNC(device->devfn) << 8) | 488 (offset & ~0x3)) | 0x80000000; 489 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); 490 491 /* 492 * The casual observer might wonder why the READ is duplicated here, 493 * rather than immediately following the WRITE, and just have the swap 494 * in the "if". That's because there is a latency problem with trying 495 * to read immediately after setting up the address register. The "if" 496 * check gives enough time for the address to stabilize, so the READ 497 * can work. 498 */ 499 if (PCI_SLOT(device->devfn) == SELF) { /* This board */ 500 GT_READ(GT_PCI0_CFGDATA_OFS, &data); 501 return data; 502 } else { /* The PCI is working in LE Mode so swap the Data. */ 503 GT_READ(GT_PCI0_CFGDATA_OFS, &data); 504 return cpu_to_le32(data); 505 } 506} 507 508static unsigned int pci1ReadConfigReg(int offset, struct pci_dev *device) 509{ 510 unsigned int DataForRegCf8; 511 unsigned int data; 512 513 DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | 514 (PCI_FUNC(device->devfn) << 8) | 515 (offset & ~0x3)) | 0x80000000; 516 /* 517 * The casual observer might wonder why the READ is duplicated here, 518 * rather than immediately following the WRITE, and just have the 519 * swap in the "if". That's because there is a latency problem 520 * with trying to read immediately after setting up the address 521 * register. The "if" check gives enough time for the address 522 * to stabilize, so the READ can work. 523 */ 524 if (PCI_SLOT(device->devfn) == SELF) { /* This board */ 525 /* when configurating our own PCI 1 L-unit the access is through 526 the PCI 0 interface with reg number = reg number + 0x80 */ 527 DataForRegCf8 |= 0x80; 528 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); 529 } else { /* The PCI is working in LE Mode so swap the Data. */ 530 GT_WRITE(GT_PCI1_CFGADDR_OFS, DataForRegCf8); 531 } 532 if (PCI_SLOT(device->devfn) == SELF) { /* This board */ 533 GT_READ(GT_PCI0_CFGDATA_OFS, &data); 534 return data; 535 } else { 536 GT_READ(GT_PCI1_CFGDATA_OFS, &data); 537 return cpu_to_le32(data); 538 } 539} 540 541 542 543/* 544 * pciXWriteConfigReg - Write to a PCI configuration register 545 * - Make sure the GT is configured as a master before 546 * writingto another device on the PCI. 547 * - The function takes care of Big/Little endian conversion. 548 * Inputs: unsigned int regOffset: The register offset as it apears in the 549 * GT spec 550 * (or any other PCI device spec) 551 * pciDevNum: The device number needs to be addressed. 552 * 553 * Configuration Address 0xCF8: 554 * 555 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number 556 * |congif|Reserved| Bus |Device|Function|Register|00| 557 * |Enable| |Number|Number| Number | Number | | <=field Name 558 * 559 */ 560static void pci0WriteConfigReg(unsigned int offset, 561 struct pci_dev *device, unsigned int data) 562{ 563 unsigned int DataForRegCf8; 564 565 DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | 566 (PCI_FUNC(device->devfn) << 8) | 567 (offset & ~0x3)) | 0x80000000; 568 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); 569 if (PCI_SLOT(device->devfn) == SELF) { /* This board */ 570 GT_WRITE(GT_PCI0_CFGDATA_OFS, data); 571 } else { /* configuration Transaction over the pci. */ 572 /* The PCI is working in LE Mode so swap the Data. */ 573 GT_WRITE(GT_PCI0_CFGDATA_OFS, le32_to_cpu(data)); 574 } 575} 576 577static void pci1WriteConfigReg(unsigned int offset, 578 struct pci_dev *device, unsigned int data) 579{ 580 unsigned int DataForRegCf8; 581 582 DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | 583 (PCI_FUNC(device->devfn) << 8) | 584 (offset & ~0x3)) | 0x80000000; 585 /* 586 * There is a latency problem 587 * with trying to read immediately after setting up the address 588 * register. The "if" check gives enough time for the address 589 * to stabilize, so the WRITE can work. 590 */ 591 if (PCI_SLOT(device->devfn) == SELF) { /* This board */ 592 /* 593 * when configurating our own PCI 1 L-unit the access is through 594 * the PCI 0 interface with reg number = reg number + 0x80 595 */ 596 DataForRegCf8 |= 0x80; 597 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); 598 } else { /* configuration Transaction over the pci. */ 599 /* The PCI is working in LE Mode so swap the Data. */ 600 GT_WRITE(GT_PCI1_CFGADDR_OFS, DataForRegCf8); 601 } 602 if (PCI_SLOT(device->devfn) == SELF) { /* This board */ 603 GT_WRITE(GT_PCI0_CFGDATA_OFS, data); 604 } else { /* configuration Transaction over the pci. */ 605 GT_WRITE(GT_PCI1_CFGADDR_OFS, le32_to_cpu(data)); 606 } 607} 608 609 610/* 611 * galileo_pcibios_(read/write)_config_(dword/word/byte) - 612 * 613 * reads/write a dword/word/byte register from the configuration space 614 * of a device. 615 * 616 * Inputs : 617 * bus - bus number 618 * dev - device number 619 * offset - register offset in the configuration space 620 * val - value to be written / read 621 * 622 * Outputs : 623 * PCIBIOS_SUCCESSFUL when operation was succesfull 624 * PCIBIOS_DEVICE_NOT_FOUND when the bus or dev is errorneous 625 * PCIBIOS_BAD_REGISTER_NUMBER when accessing non aligned 626 */ 627 628static int galileo_pcibios_read_config_dword(struct pci_dev *device, 629 int offset, u32 * val) 630{ 631 int dev, bus; 632 bus = device->bus->number; 633 dev = PCI_SLOT(device->devfn); 634 635 if (pci_range_ck(bus, dev)) { 636 *val = 0xffffffff; 637 return PCIBIOS_DEVICE_NOT_FOUND; 638 } 639 if (offset & 0x3) 640 return PCIBIOS_BAD_REGISTER_NUMBER; 641 if (bus == 0) 642 *val = pci0ReadConfigReg(offset, device); 643 644 /* This is so that the upper PCI layer will get the correct return value if 645 we're not attached to anything. */ 646 if ((offset == 0) && (*val == 0xffffffff)) { 647 return PCIBIOS_DEVICE_NOT_FOUND; 648 } 649 650 return PCIBIOS_SUCCESSFUL; 651} 652 653static int galileo_pcibios_read_config_word(struct pci_dev *device, 654 int offset, u16 * val) 655{ 656 int dev, bus; 657 658 bus = device->bus->number; 659 dev = PCI_SLOT(device->devfn); 660 661 if (pci_range_ck(bus, dev)) { 662 *val = 0xffff; 663 return PCIBIOS_DEVICE_NOT_FOUND; 664 } 665 if (offset & 0x1) 666 return PCIBIOS_BAD_REGISTER_NUMBER; 667 668 if (bus == 0) 669 *val = 670 (unsigned short) (pci0ReadConfigReg(offset, device) >> 671 ((offset & ~0x3) * 8)); 672 673 return PCIBIOS_SUCCESSFUL; 674} 675 676static int galileo_pcibios_read_config_byte(struct pci_dev *device, 677 int offset, u8 * val) 678{ 679 int dev, bus; 680 681 bus = device->bus->number; 682 dev = PCI_SLOT(device->devfn); 683 684 if (pci_range_ck(bus, dev)) { 685 *val = 0xff; 686 return PCIBIOS_DEVICE_NOT_FOUND; 687 } 688 689 if (bus == 0) 690 *val = 691 (unsigned char) (pci0ReadConfigReg(offset, device) >> 692 ((offset & ~0x3) * 8)); 693 694 /* 695 * This is so that the upper PCI layer will get the correct return 696 * value if we're not attached to anything. 697 */ 698 if ((offset == 0xe) && (*val == 0xff)) { 699 u32 MasterAbort; 700 GT_READ(GT_INTRCAUSE_OFS, &MasterAbort); 701 if (MasterAbort & 0x40000) { 702 GT_WRITE(GT_INTRCAUSE_OFS, 703 (MasterAbort & 0xfffbffff)); 704 return PCIBIOS_DEVICE_NOT_FOUND; 705 } 706 } 707 708 return PCIBIOS_SUCCESSFUL; 709} 710 711static int galileo_pcibios_write_config_dword(struct pci_dev *device, 712 int offset, u32 val) 713{ 714 int dev, bus; 715 716 bus = device->bus->number; 717 dev = PCI_SLOT(device->devfn); 718 719 if (pci_range_ck(bus, dev)) 720 return PCIBIOS_DEVICE_NOT_FOUND; 721 if (offset & 0x3) 722 return PCIBIOS_BAD_REGISTER_NUMBER; 723 if (bus == 0) 724 pci0WriteConfigReg(offset, device, val); 725// if (bus == 1) pci1WriteConfigReg (offset,device,val); 726 727 return PCIBIOS_SUCCESSFUL; 728} 729 730 731static int galileo_pcibios_write_config_word(struct pci_dev *device, 732 int offset, u16 val) 733{ 734 int dev, bus; 735 unsigned long tmp; 736 737 bus = device->bus->number; 738 dev = PCI_SLOT(device->devfn); 739 740 if (pci_range_ck(bus, dev)) 741 return PCIBIOS_DEVICE_NOT_FOUND; 742 if (offset & 0x1) 743 return PCIBIOS_BAD_REGISTER_NUMBER; 744 if (bus == 0) 745 tmp = pci0ReadConfigReg(offset, device); 746// if (bus == 1) tmp = pci1ReadConfigReg (offset,device); 747 748 if ((offset % 4) == 0) 749 tmp = (tmp & 0xffff0000) | (val & 0xffff); 750 if ((offset % 4) == 2) 751 tmp = (tmp & 0x0000ffff) | ((val & 0xffff) << 16); 752 753 if (bus == 0) 754 pci0WriteConfigReg(offset, device, tmp); 755// if (bus == 1) pci1WriteConfigReg (offset,device,tmp); 756 return PCIBIOS_SUCCESSFUL; 757} 758 759static int galileo_pcibios_write_config_byte(struct pci_dev *device, 760 int offset, u8 val) 761{ 762 int dev, bus; 763 unsigned long tmp; 764 765 bus = device->bus->number; 766 dev = PCI_SLOT(device->devfn); 767 768 if (pci_range_ck(bus, dev)) 769 return PCIBIOS_DEVICE_NOT_FOUND; 770 if (bus == 0) 771 tmp = pci0ReadConfigReg(offset, device); 772// if (bus == 1) tmp = pci1ReadConfigReg (offset,device); 773 774 if ((offset % 4) == 0) 775 tmp = (tmp & 0xffffff00) | (val & 0xff); 776 if ((offset % 4) == 1) 777 tmp = (tmp & 0xffff00ff) | ((val & 0xff) << 8); 778 if ((offset % 4) == 2) 779 tmp = (tmp & 0xff00ffff) | ((val & 0xff) << 16); 780 if ((offset % 4) == 3) 781 tmp = (tmp & 0x00ffffff) | ((val & 0xff) << 24); 782 783 if (bus == 0) 784 pci0WriteConfigReg(offset, device, tmp); 785// if (bus == 1) pci1WriteConfigReg (offset,device,tmp); 786 787 return PCIBIOS_SUCCESSFUL; 788} 789 790static void galileo_pcibios_set_master(struct pci_dev *dev) 791{ 792 u16 cmd; 793 794 galileo_pcibios_read_config_word(dev, PCI_COMMAND, &cmd); 795 cmd |= PCI_COMMAND_MASTER; 796 galileo_pcibios_write_config_word(dev, PCI_COMMAND, cmd); 797} 798 799/* Externally-expected functions. Do not change function names */ 800 801int pcibios_enable_resources(struct pci_dev *dev) 802{ 803 u16 cmd, old_cmd; 804 u8 tmp1; 805 int idx; 806 struct resource *r; 807 808 galileo_pcibios_read_config_word(dev, PCI_COMMAND, &cmd); 809 old_cmd = cmd; 810 for (idx = 0; idx < 6; idx++) { 811 r = &dev->resource[idx]; 812 if (!r->start && r->end) { 813 printk(KERN_ERR 814 "PCI: Device %s not available because of " 815 "resource collisions\n", dev->slot_name); 816 return -EINVAL; 817 } 818 if (r->flags & IORESOURCE_IO) 819 cmd |= PCI_COMMAND_IO; 820 if (r->flags & IORESOURCE_MEM) 821 cmd |= PCI_COMMAND_MEMORY; 822 } 823 if (cmd != old_cmd) { 824 galileo_pcibios_write_config_word(dev, PCI_COMMAND, cmd); 825 } 826 827 /* 828 * Let's fix up the latency timer and cache line size here. Cache 829 * line size = 32 bytes / sizeof dword (4) = 8. 830 * Latency timer must be > 8. 32 is random but appears to work. 831 */ 832 galileo_pcibios_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp1); 833 if (tmp1 != 8) { 834 printk(KERN_WARNING "PCI setting cache line size to 8 from " 835 "%d\n", tmp1); 836 galileo_pcibios_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 837 8); 838 } 839 galileo_pcibios_read_config_byte(dev, PCI_LATENCY_TIMER, &tmp1); 840 if (tmp1 < 32) { 841 printk(KERN_WARNING "PCI setting latency timer to 32 from %d\n", 842 tmp1); 843 galileo_pcibios_write_config_byte(dev, PCI_LATENCY_TIMER, 844 32); 845 } 846 847 return 0; 848} 849 850int pcibios_enable_device(struct pci_dev *dev, int mask) 851{ 852 return pcibios_enable_resources(dev); 853} 854 855void pcibios_update_resource(struct pci_dev *dev, struct resource *root, 856 struct resource *res, int resource) 857{ 858 u32 new, check; 859 int reg; 860 861 return; 862 863 new = res->start | (res->flags & PCI_REGION_FLAG_MASK); 864 if (resource < 6) { 865 reg = PCI_BASE_ADDRESS_0 + 4 * resource; 866 } else if (resource == PCI_ROM_RESOURCE) { 867 res->flags |= PCI_ROM_ADDRESS_ENABLE; 868 reg = dev->rom_base_reg; 869 } else { 870 /* 871 * Somebody might have asked allocation of a non-standard 872 * resource 873 */ 874 return; 875 } 876 877 pci_write_config_dword(dev, reg, new); 878 pci_read_config_dword(dev, reg, &check); 879 if ((new ^ check) & 880 ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : 881 PCI_BASE_ADDRESS_MEM_MASK)) { 882 printk(KERN_ERR "PCI: Error while updating region " 883 "%s/%d (%08x != %08x)\n", dev->slot_name, resource, 884 new, check); 885 } 886} 887 888void pcibios_align_resource(void *data, struct resource *res, 889 unsigned long size, unsigned long align) 890{ 891 struct pci_dev *dev = data; 892 893 if (res->flags & IORESOURCE_IO) { 894 unsigned long start = res->start; 895 896 /* We need to avoid collisions with `mirrored' VGA ports 897 and other strange ISA hardware, so we always want the 898 addresses kilobyte aligned. */ 899 if (size > 0x100) { 900 printk(KERN_ERR "PCI: I/O Region %s/%d too large" 901 " (%ld bytes)\n", dev->slot_name, 902 dev->resource - res, size); 903 } 904 905 start = (start + 1024 - 1) & ~(1024 - 1); 906 res->start = start; 907 } 908} 909 910struct pci_ops galileo_pci_ops = { 911 galileo_pcibios_read_config_byte, 912 galileo_pcibios_read_config_word, 913 galileo_pcibios_read_config_dword, 914 galileo_pcibios_write_config_byte, 915 galileo_pcibios_write_config_word, 916 galileo_pcibios_write_config_dword 917}; 918 919struct pci_fixup pcibios_fixups[] = { 920 {0} 921}; 922 923void __init pcibios_fixup_bus(struct pci_bus *c) 924{ 925 gt64120_board_pcibios_fixup_bus(c); 926} 927 928/* 929 * This code was derived from Galileo Technology's example 930 * and significantly reworked. 931 * 932 * This is very simple. It does not scan multiple function devices. It does 933 * not scan behind bridges. Those would be simple to implement, but we don't 934 * currently need this. 935 */ 936 937static void __init scan_and_initialize_pci(void) 938{ 939 struct pci_device pci_devices[MAX_PCI_DEVS]; 940 941 if (scan_pci_bus(pci_devices)) { 942 allocate_pci_space(pci_devices); 943 } 944} 945 946/* 947 * This is your basic PCI scan. It goes through each slot and checks to 948 * see if there's something that responds. If so, then get the size and 949 * type of each of the responding BARs. Save them for later. 950 */ 951 952static u32 __init scan_pci_bus(struct pci_device *pci_devices) 953{ 954 u32 arrayCounter = 0; 955 u32 memType; 956 u32 memSize; 957 u32 pci_slot, bar; 958 u32 id; 959 u32 c18RegValue; 960 struct pci_dev device; 961 962 /* 963 * According to PCI REV 2.1 MAX agents on the bus are 21. 964 * We don't bother scanning ourselves (slot 0). 965 */ 966 for (pci_slot = 1; pci_slot < 22; pci_slot++) { 967 968 device.devfn = PCI_DEVFN(pci_slot, 0); 969 id = pci0ReadConfigReg(PCI_VENDOR_ID, &device); 970 971 /* 972 * Check for a PCI Master Abort (nothing responds in the 973 * slot) 974 */ 975 GT_READ(GT_INTRCAUSE_OFS, &c18RegValue); 976 /* 977 * Clearing bit 18 of in the Cause Register 0xc18 by 978 * writting 0. 979 */ 980 GT_WRITE(GT_INTRCAUSE_OFS, (c18RegValue & 0xfffbffff)); 981 if ((id != 0xffffffff) && !(c18RegValue & 0x40000)) { 982 pci_devices[arrayCounter].slot = pci_slot; 983 for (bar = 0; bar < 6; bar++) { 984 memType = 985 pci0ReadConfigReg(PCI_BASE_ADDRESS_0 + 986 (bar * 4), &device); 987 pci_devices[arrayCounter].BARtype[bar] = 988 memType & 1; 989 pci0WriteConfigReg(PCI_BASE_ADDRESS_0 + 990 (bar * 4), &device, 991 0xffffffff); 992 memSize = 993 pci0ReadConfigReg(PCI_BASE_ADDRESS_0 + 994 (bar * 4), &device); 995 if (memType & 1) { /* IO space */ 996 pci_devices[arrayCounter]. 997 BARsize[bar] = 998 ~(memSize & 0xfffffffc) + 1; 999 } else { /* memory space */ 1000 pci_devices[arrayCounter]. 1001 BARsize[bar] = 1002 ~(memSize & 0xfffffff0) + 1; 1003 } 1004 } /* BAR counter */ 1005 1006 arrayCounter++; 1007 } 1008 /* found a device */ 1009 } /* slot counter */ 1010 1011 if (arrayCounter < MAX_PCI_DEVS) 1012 pci_devices[arrayCounter].slot = -1; 1013 1014 return arrayCounter; 1015} 1016 1017#define ALIGN(val,align) (((val) + ((align) - 1)) & ~((align) - 1)) 1018#define MAX(val1, val2) ((val1) > (val2) ? (val1) : (val2)) 1019 1020/* 1021 * This function goes through the list of devices and allocates the BARs in 1022 * either IO or MEM space. It does it in order of size, which will limit the 1023 * amount of fragmentation we have in the IO and MEM spaces. 1024 */ 1025 1026static void __init allocate_pci_space(struct pci_device *pci_devices) 1027{ 1028 u32 count, maxcount, bar; 1029 u32 maxSize, maxDevice, maxBAR; 1030 u32 alignto; 1031 u32 base; 1032 u32 pci0_mem_base = pci0GetMemory0Base(); 1033 u32 pci0_io_base = pci0GetIOspaceBase(); 1034 struct pci_dev device; 1035 1036 /* How many PCI devices do we have? */ 1037 maxcount = MAX_PCI_DEVS; 1038 for (count = 0; count < MAX_PCI_DEVS; count++) { 1039 if (pci_devices[count].slot == -1) { 1040 maxcount = count; 1041 break; 1042 } 1043 } 1044 1045 do { 1046 /* Find the largest size BAR we need to allocate */ 1047 maxSize = 0; 1048 for (count = 0; count < maxcount; count++) { 1049 for (bar = 0; bar < 6; bar++) { 1050 if (pci_devices[count].BARsize[bar] > 1051 maxSize) { 1052 maxSize = 1053 pci_devices[count]. 1054 BARsize[bar]; 1055 maxDevice = count; 1056 maxBAR = bar; 1057 } 1058 } 1059 } 1060 1061 /* 1062 * We've found the largest BAR. Allocate it into IO or 1063 * mem space. We don't idiot check the bases to make 1064 * sure they haven't overflowed the current size for that 1065 * aperture. 1066 * Don't bother to enable the device's IO or MEM space here. 1067 * That will be done in pci_enable_resources if the device is 1068 * activated by a driver. 1069 */ 1070 if (maxSize) { 1071 device.devfn = 1072 PCI_DEVFN(pci_devices[maxDevice].slot, 0); 1073 if (pci_devices[maxDevice].BARtype[maxBAR] == 1) { 1074 alignto = MAX(0x1000, maxSize); 1075 base = ALIGN(pci0_io_base, alignto); 1076 pci0WriteConfigReg(PCI_BASE_ADDRESS_0 + 1077 (maxBAR * 4), &device, 1078 base | 0x1); 1079 pci0_io_base = base + alignto; 1080 } else { 1081 alignto = MAX(0x1000, maxSize); 1082 base = ALIGN(pci0_mem_base, alignto); 1083 pci0WriteConfigReg(PCI_BASE_ADDRESS_0 + 1084 (maxBAR * 4), &device, 1085 base); 1086 pci0_mem_base = base + alignto; 1087 } 1088 /* 1089 * This entry is finished. Remove it from the list 1090 * we'll scan. 1091 */ 1092 pci_devices[maxDevice].BARsize[maxBAR] = 0; 1093 } 1094 } while (maxSize); 1095} 1096 1097void __init pcibios_init(void) 1098{ 1099 u32 tmp; 1100 struct pci_dev controller; 1101 1102 controller.devfn = SELF; 1103 1104 GT_READ(GT_PCI0_CMD_OFS, &tmp); 1105 GT_READ(GT_PCI0_BARE_OFS, &tmp); 1106 1107 /* 1108 * You have to enable bus mastering to configure any other 1109 * card on the bus. 1110 */ 1111 tmp = pci0ReadConfigReg(PCI_COMMAND, &controller); 1112 tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 1113 pci0WriteConfigReg(PCI_COMMAND, &controller, tmp); 1114 1115 /* This scans the PCI bus and sets up initial values. */ 1116 scan_and_initialize_pci(); 1117 1118 /* 1119 * Reset PCI I/O and PCI MEM values to ones supported by EVM. 1120 */ 1121 ioport_resource.start = GT_PCI_IO_BASE; 1122 ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1; 1123 iomem_resource.start = GT_PCI_MEM_BASE; 1124 iomem_resource.end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1; 1125 1126 pci_scan_bus(0, &galileo_pci_ops, NULL); 1127} 1128 1129/* 1130 * for parsing "pci=" kernel boot arguments. 1131 */ 1132char *pcibios_setup(char *str) 1133{ 1134 printk(KERN_INFO "rr: pcibios_setup\n"); 1135 /* Nothing to do for now. */ 1136 1137 return str; 1138} 1139 1140unsigned __init int pcibios_assign_all_busses(void) 1141{ 1142 return 1; 1143} 1144 1145#endif /* CONFIG_PCI */ 1146