1/* 2 * 3 * SNI64 specific PCI support for SNI IO. 4 * 5 * This file is subject to the terms and conditions of the GNU General Public 6 * License. See the file "COPYING" in the main directory of this archive 7 * for more details. 8 * 9 * Copyright (c) 1997, 1998, 2000-2002 Silicon Graphics, Inc. All rights reserved. 10 */ 11#include <linux/init.h> 12#include <linux/types.h> 13#include <linux/config.h> 14#include <linux/pci.h> 15#include <asm/sn/types.h> 16#include <asm/sn/sgi.h> 17#include <asm/sn/io.h> 18#include <asm/sn/driver.h> 19#include <asm/sn/iograph.h> 20#include <asm/param.h> 21#include <asm/sn/pio.h> 22#include <asm/sn/xtalk/xwidget.h> 23#include <asm/sn/sn_private.h> 24#include <asm/sn/addrs.h> 25#include <asm/sn/invent.h> 26#include <asm/sn/hcl.h> 27#include <asm/sn/hcl_util.h> 28#include <asm/sn/pci/pciio.h> 29#include <asm/sn/pci/pcibr.h> 30#include <asm/sn/pci/pcibr_private.h> 31#include <asm/sn/pci/bridge.h> 32 33#ifdef DEBUG_CONFIG 34#define DBG(x...) printk(x) 35#else 36#define DBG(x...) 37#endif 38 39 40 41#ifdef CONFIG_PCI 42 43extern devfs_handle_t pci_bus_to_vertex(unsigned char); 44extern devfs_handle_t devfn_to_vertex(unsigned char bus, unsigned char devfn); 45 46/* 47 * snia64_read_config_byte - Read a byte from the config area of the device. 48 */ 49static int snia64_read_config_byte (struct pci_dev *dev, 50 int where, unsigned char *val) 51{ 52 unsigned long res = 0; 53 unsigned size = 1; 54 devfs_handle_t device_vertex; 55 56 if ( (dev == (struct pci_dev *)0) || (val == (unsigned char *)0) ) { 57 return PCIBIOS_DEVICE_NOT_FOUND; 58 } 59 device_vertex = devfn_to_vertex(dev->bus->number, dev->devfn); 60 if (!device_vertex) { 61 DBG("%s : nonexistent device: bus= 0x%x slot= 0x%x func= 0x%x\n", 62 __FUNCTION__, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); 63 return(-1); 64 } 65 res = pciio_config_get(device_vertex, (unsigned) where, size); 66 *val = (unsigned char) res; 67 return PCIBIOS_SUCCESSFUL; 68} 69 70/* 71 * snia64_read_config_word - Read 2 bytes from the config area of the device. 72 */ 73static int snia64_read_config_word (struct pci_dev *dev, 74 int where, unsigned short *val) 75{ 76 unsigned long res = 0; 77 unsigned size = 2; /* 2 bytes */ 78 devfs_handle_t device_vertex; 79 80 if ( (dev == (struct pci_dev *)0) || (val == (unsigned short *)0) ) { 81 return PCIBIOS_DEVICE_NOT_FOUND; 82 } 83 device_vertex = devfn_to_vertex(dev->bus->number, dev->devfn); 84 if (!device_vertex) { 85 DBG("%s : nonexistent device: bus= 0x%x slot= 0x%x func= 0x%x\n", 86 __FUNCTION__, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); 87 return(-1); 88 } 89 res = pciio_config_get(device_vertex, (unsigned) where, size); 90 *val = (unsigned short) res; 91 return PCIBIOS_SUCCESSFUL; 92} 93 94/* 95 * snia64_read_config_dword - Read 4 bytes from the config area of the device. 96 */ 97static int snia64_read_config_dword (struct pci_dev *dev, 98 int where, unsigned int *val) 99{ 100 unsigned long res = 0; 101 unsigned size = 4; /* 4 bytes */ 102 devfs_handle_t device_vertex; 103 104 if (where & 3) { 105 return PCIBIOS_BAD_REGISTER_NUMBER; 106 } 107 if ( (dev == (struct pci_dev *)0) || (val == (unsigned int *)0) ) { 108 return PCIBIOS_DEVICE_NOT_FOUND; 109 } 110 111 device_vertex = devfn_to_vertex(dev->bus->number, dev->devfn); 112 if (!device_vertex) { 113 DBG("%s : nonexistent device: bus= 0x%x slot= 0x%x func= 0x%x\n", 114 __FUNCTION__, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); 115 return(-1); 116 } 117 res = pciio_config_get(device_vertex, (unsigned) where, size); 118 *val = (unsigned int) res; 119 return PCIBIOS_SUCCESSFUL; 120} 121 122/* 123 * snia64_write_config_byte - Writes 1 byte to the config area of the device. 124 */ 125static int snia64_write_config_byte (struct pci_dev *dev, 126 int where, unsigned char val) 127{ 128 devfs_handle_t device_vertex; 129 130 if ( dev == (struct pci_dev *)0 ) { 131 return PCIBIOS_DEVICE_NOT_FOUND; 132 } 133 /* 134 * if it's an IOC3 then we bail out, we special 135 * case them with pci_fixup_ioc3 136 */ 137 if (dev->vendor == PCI_VENDOR_ID_SGI && 138 dev->device == PCI_DEVICE_ID_SGI_IOC3 ) 139 return PCIBIOS_SUCCESSFUL; 140 141 device_vertex = devfn_to_vertex(dev->bus->number, dev->devfn); 142 if (!device_vertex) { 143 DBG("%s : nonexistent device: bus= 0x%x slot= 0x%x func= 0x%x\n", 144 __FUNCTION__, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); 145 return(-1); 146 } 147 pciio_config_set( device_vertex, (unsigned)where, 1, (uint64_t) val); 148 149 return PCIBIOS_SUCCESSFUL; 150} 151 152/* 153 * snia64_write_config_word - Writes 2 bytes to the config area of the device. 154 */ 155static int snia64_write_config_word (struct pci_dev *dev, 156 int where, unsigned short val) 157{ 158 devfs_handle_t device_vertex = NULL; 159 160 if (where & 1) { 161 return PCIBIOS_BAD_REGISTER_NUMBER; 162 } 163 if ( dev == (struct pci_dev *)0 ) { 164 return PCIBIOS_DEVICE_NOT_FOUND; 165 } 166 /* 167 * if it's an IOC3 then we bail out, we special 168 * case them with pci_fixup_ioc3 169 */ 170 if (dev->vendor == PCI_VENDOR_ID_SGI && 171 dev->device == PCI_DEVICE_ID_SGI_IOC3) 172 return PCIBIOS_SUCCESSFUL; 173 174 device_vertex = devfn_to_vertex(dev->bus->number, dev->devfn); 175 if (!device_vertex) { 176 DBG("%s : nonexistent device: bus= 0x%x slot= 0x%x func= 0x%x\n", 177 __FUNCTION__, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); 178 return(-1); 179 } 180 pciio_config_set( device_vertex, (unsigned)where, 2, (uint64_t) val); 181 182 return PCIBIOS_SUCCESSFUL; 183} 184 185/* 186 * snia64_write_config_dword - Writes 4 bytes to the config area of the device. 187 */ 188static int snia64_write_config_dword (struct pci_dev *dev, 189 int where, unsigned int val) 190{ 191 devfs_handle_t device_vertex; 192 193 if (where & 3) { 194 return PCIBIOS_BAD_REGISTER_NUMBER; 195 } 196 if ( dev == (struct pci_dev *)0 ) { 197 return PCIBIOS_DEVICE_NOT_FOUND; 198 } 199 /* 200 * if it's an IOC3 then we bail out, we special 201 * case them with pci_fixup_ioc3 202 */ 203 if (dev->vendor == PCI_VENDOR_ID_SGI && 204 dev->device == PCI_DEVICE_ID_SGI_IOC3) 205 return PCIBIOS_SUCCESSFUL; 206 207 device_vertex = devfn_to_vertex(dev->bus->number, dev->devfn); 208 if (!device_vertex) { 209 DBG("%s : nonexistent device: bus= 0x%x slot= 0x%x func= 0x%x\n", 210 __FUNCTION__, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); 211 return(-1); 212 } 213 pciio_config_set( device_vertex, (unsigned)where, 4, (uint64_t) val); 214 215 return PCIBIOS_SUCCESSFUL; 216} 217 218static struct pci_ops snia64_pci_ops = { 219 snia64_read_config_byte, 220 snia64_read_config_word, 221 snia64_read_config_dword, 222 snia64_write_config_byte, 223 snia64_write_config_word, 224 snia64_write_config_dword 225}; 226 227/* 228 * snia64_pci_find_bios - SNIA64 pci_find_bios() platform specific code. 229 */ 230void __init 231sn_pci_find_bios(void) 232{ 233 extern struct pci_ops pci_conf; 234 /* 235 * Go initialize our IO Infrastructure .. 236 */ 237 extern void sgi_master_io_infr_init(void); 238 239 sgi_master_io_infr_init(); 240 241 /* sn_io_infrastructure_init(); */ 242 pci_conf = snia64_pci_ops; 243} 244 245void 246pci_fixup_ioc3(struct pci_dev *d) 247{ 248 int i; 249 unsigned int size; 250 251 /* IOC3 only decodes 0x20 bytes of the config space, reading 252 * beyond that is relatively benign but writing beyond that 253 * (especially the base address registers) will shut down the 254 * pci bus...so avoid doing so. 255 * NOTE: this means we can't program the intr_pin into the device, 256 * currently we hack this with special code in 257 * sgi_pci_intr_support() 258 */ 259 DBG("pci_fixup_ioc3: Fixing base addresses for ioc3 device %s\n", d->slot_name); 260 261 /* I happen to know from the spec that the ioc3 needs only 0xfffff 262 * The standard pci trick of writing ~0 to the baddr and seeing 263 * what comes back doesn't work with the ioc3 264 */ 265 size = 0xfffff; 266 d->resource[0].end = (unsigned long) d->resource[0].start + (unsigned long) size; 267 268 /* 269 * Zero out the resource structure .. because we did not go through 270 * the normal PCI Infrastructure Init, garbbage are left in these 271 * fileds. 272 */ 273 for (i = 1; i <= PCI_ROM_RESOURCE; i++) { 274 d->resource[i].start = 0UL; 275 d->resource[i].end = 0UL; 276 d->resource[i].flags = 0UL; 277 } 278 279 /* 280 * Hardcode Device 4 register(IOC3 is in Slot 4) to set the 281 * DEV_DIRECT bit. This will not work if IOC3 is not on Slot 282 * 4. 283 */ 284 DBG("pci_fixup_ioc3: FIXME .. need to take NASID into account when setting IOC3 devreg 0x%x\n", *(volatile u32 *)0xc0000a000f000220); 285 286 *(volatile u32 *)0xc0000a000f000220 |= 0x90000; 287 288 d->subsystem_vendor = 0; 289 d->subsystem_device = 0; 290 291} 292 293#else 294void sn_pci_find_bios(void) {} 295void pci_fixup_ioc3(struct pci_dev *d) {} 296struct list_head pci_root_buses; 297struct list_head pci_root_buses; 298struct list_head pci_devices; 299 300#endif /* CONFIG_PCI */ 301