1/* 2 * Intel IO-APIC support for multi-Pentium hosts. 3 * 4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo 5 * 6 * Many thanks to Stig Venaas for trying out countless experimental 7 * patches and reporting/debugging problems patiently! 8 * 9 * (c) 1999, Multiple IO-APIC support, developed by 10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and 11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, 12 * further tested and cleaned up by Zach Brown <zab@redhat.com> 13 * and Ingo Molnar <mingo@redhat.com> 14 * 15 * Fixes 16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 17 * thanks to Eric Gilmore 18 * and Rolf G. Tews 19 * for testing these extensively 20 */ 21 22#include <linux/mm.h> 23#include <linux/irq.h> 24#include <linux/interrupt.h> 25#include <linux/init.h> 26#include <linux/delay.h> 27#include <linux/sched.h> 28#include <linux/config.h> 29#include <linux/smp_lock.h> 30#include <linux/mc146818rtc.h> 31 32#include <asm/io.h> 33#include <asm/smp.h> 34#include <asm/desc.h> 35#include <asm/smpboot.h> 36 37#undef APIC_LOCKUP_DEBUG 38 39#define APIC_LOCKUP_DEBUG 40 41static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED; 42 43unsigned int int_dest_addr_mode = APIC_DEST_LOGICAL; 44unsigned char int_delivery_mode = dest_LowestPrio; 45 46 47/* 48 * # of IRQ routing registers 49 */ 50int nr_ioapic_registers[MAX_IO_APICS]; 51 52/* 53 * Rough estimation of how many shared IRQs there are, can 54 * be changed anytime. 55 */ 56#define MAX_PLUS_SHARED_IRQS NR_IRQS 57#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS) 58 59/* 60 * This is performance-critical, we want to do it O(1) 61 * 62 * the indexing order of this array favors 1:1 mappings 63 * between pins and IRQs. 64 */ 65 66static struct irq_pin_list { 67 int apic, pin, next; 68} irq_2_pin[PIN_MAP_SIZE]; 69 70/* 71 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are 72 * shared ISA-space IRQs, so we have to support them. We are super 73 * fast in the common case, and fast for shared ISA-space IRQs. 74 */ 75static void __init add_pin_to_irq(unsigned int irq, int apic, int pin) 76{ 77 static int first_free_entry = NR_IRQS; 78 struct irq_pin_list *entry = irq_2_pin + irq; 79 80 while (entry->next) 81 entry = irq_2_pin + entry->next; 82 83 if (entry->pin != -1) { 84 entry->next = first_free_entry; 85 entry = irq_2_pin + entry->next; 86 if (++first_free_entry >= PIN_MAP_SIZE) 87 panic("io_apic.c: whoops"); 88 } 89 entry->apic = apic; 90 entry->pin = pin; 91} 92 93/* 94 * Reroute an IRQ to a different pin. 95 */ 96static void __init replace_pin_at_irq(unsigned int irq, 97 int oldapic, int oldpin, 98 int newapic, int newpin) 99{ 100 struct irq_pin_list *entry = irq_2_pin + irq; 101 102 while (1) { 103 if (entry->apic == oldapic && entry->pin == oldpin) { 104 entry->apic = newapic; 105 entry->pin = newpin; 106 } 107 if (!entry->next) 108 break; 109 entry = irq_2_pin + entry->next; 110 } 111} 112 113#define __DO_ACTION(R, ACTION, FINAL) \ 114 \ 115{ \ 116 int pin; \ 117 struct irq_pin_list *entry = irq_2_pin + irq; \ 118 \ 119 for (;;) { \ 120 unsigned int reg; \ 121 pin = entry->pin; \ 122 if (pin == -1) \ 123 break; \ 124 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \ 125 reg ACTION; \ 126 io_apic_modify(entry->apic, reg); \ 127 if (!entry->next) \ 128 break; \ 129 entry = irq_2_pin + entry->next; \ 130 } \ 131 FINAL; \ 132} 133 134#define DO_ACTION(name,R,ACTION, FINAL) \ 135 \ 136 static void name##_IO_APIC_irq (unsigned int irq) \ 137 __DO_ACTION(R, ACTION, FINAL) 138 139DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) ) 140 /* mask = 1 */ 141DO_ACTION( __unmask, 0, &= 0xfffeffff, ) 142 /* mask = 0 */ 143DO_ACTION( __mask_and_edge, 0, = (reg & 0xffff7fff) | 0x00010000, ) 144 /* mask = 1, trigger = 0 */ 145DO_ACTION( __unmask_and_level, 0, = (reg & 0xfffeffff) | 0x00008000, ) 146 /* mask = 0, trigger = 1 */ 147 148static void mask_IO_APIC_irq (unsigned int irq) 149{ 150 unsigned long flags; 151 152 spin_lock_irqsave(&ioapic_lock, flags); 153 __mask_IO_APIC_irq(irq); 154 spin_unlock_irqrestore(&ioapic_lock, flags); 155} 156 157static void unmask_IO_APIC_irq (unsigned int irq) 158{ 159 unsigned long flags; 160 161 spin_lock_irqsave(&ioapic_lock, flags); 162 __unmask_IO_APIC_irq(irq); 163 spin_unlock_irqrestore(&ioapic_lock, flags); 164} 165 166void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) 167{ 168 struct IO_APIC_route_entry entry; 169 unsigned long flags; 170 171 /* 172 * Disable it in the IO-APIC irq-routing table: 173 */ 174 memset(&entry, 0, sizeof(entry)); 175 entry.mask = 1; 176 spin_lock_irqsave(&ioapic_lock, flags); 177 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0)); 178 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1)); 179 spin_unlock_irqrestore(&ioapic_lock, flags); 180} 181 182static void clear_IO_APIC (void) 183{ 184 int apic, pin; 185 186 for (apic = 0; apic < nr_ioapics; apic++) 187 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) 188 clear_IO_APIC_pin(apic, pin); 189} 190 191/* 192 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to 193 * specific CPU-side IRQs. 194 */ 195 196#define MAX_PIRQS 8 197int pirq_entries [MAX_PIRQS]; 198int pirqs_enabled; 199int skip_ioapic_setup; 200 201static int __init noioapic_setup(char *str) 202{ 203 skip_ioapic_setup = 1; 204 return 1; 205} 206 207__setup("noapic", noioapic_setup); 208 209static int __init ioapic_setup(char *str) 210{ 211 skip_ioapic_setup = 0; 212 return 1; 213} 214 215__setup("apic", ioapic_setup); 216 217static int __init ioapic_pirq_setup(char *str) 218{ 219 int i, max; 220 int ints[MAX_PIRQS+1]; 221 222 get_options(str, ARRAY_SIZE(ints), ints); 223 224 for (i = 0; i < MAX_PIRQS; i++) 225 pirq_entries[i] = -1; 226 227 pirqs_enabled = 1; 228 printk(KERN_INFO "PIRQ redirection, working around broken MP-BIOS.\n"); 229 max = MAX_PIRQS; 230 if (ints[0] < MAX_PIRQS) 231 max = ints[0]; 232 233 for (i = 0; i < max; i++) { 234 printk(KERN_DEBUG "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); 235 /* 236 * PIRQs are mapped upside down, usually. 237 */ 238 pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; 239 } 240 return 1; 241} 242 243__setup("pirq=", ioapic_pirq_setup); 244 245/* 246 * Find the IRQ entry number of a certain pin. 247 */ 248static int __init find_irq_entry(int apic, int pin, int type) 249{ 250 int i; 251 252 for (i = 0; i < mp_irq_entries; i++) 253 if (mp_irqs[i].mpc_irqtype == type && 254 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid || 255 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) && 256 mp_irqs[i].mpc_dstirq == pin) 257 return i; 258 259 return -1; 260} 261 262/* 263 * Find the pin to which IRQ[irq] (ISA) is connected 264 */ 265static int __init find_isa_irq_pin(int irq, int type) 266{ 267 int i; 268 269 for (i = 0; i < mp_irq_entries; i++) { 270 int lbus = mp_irqs[i].mpc_srcbus; 271 272 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA || 273 mp_bus_id_to_type[lbus] == MP_BUS_EISA || 274 mp_bus_id_to_type[lbus] == MP_BUS_MCA) && 275 (mp_irqs[i].mpc_irqtype == type) && 276 (mp_irqs[i].mpc_srcbusirq == irq)) 277 278 return mp_irqs[i].mpc_dstirq; 279 } 280 return -1; 281} 282 283/* 284 * Find a specific PCI IRQ entry. 285 * Not an __init, possibly needed by modules 286 */ 287static int pin_2_irq(int idx, int apic, int pin); 288 289int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) 290{ 291 int apic, i, best_guess = -1; 292 293 Dprintk("querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", 294 bus, slot, pin); 295 if (mp_bus_id_to_pci_bus[bus] == -1) { 296 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus); 297 return -1; 298 } 299 for (i = 0; i < mp_irq_entries; i++) { 300 int lbus = mp_irqs[i].mpc_srcbus; 301 302 for (apic = 0; apic < nr_ioapics; apic++) 303 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic || 304 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) 305 break; 306 307 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) && 308 !mp_irqs[i].mpc_irqtype && 309 (bus == lbus) && 310 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) { 311 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq); 312 313 if (!(apic || IO_APIC_IRQ(irq))) 314 continue; 315 316 if (pin == (mp_irqs[i].mpc_srcbusirq & 3)) 317 return irq; 318 /* 319 * Use the first all-but-pin matching entry as a 320 * best-guess fuzzy result for broken mptables. 321 */ 322 if (best_guess < 0) 323 best_guess = irq; 324 } 325 } 326 return best_guess; 327} 328 329/* 330 * EISA Edge/Level control register, ELCR 331 */ 332static int __init EISA_ELCR(unsigned int irq) 333{ 334 if (irq < 16) { 335 unsigned int port = 0x4d0 + (irq >> 3); 336 return (inb(port) >> (irq & 7)) & 1; 337 } 338 printk(KERN_INFO "Broken MPtable reports ISA irq %d\n", irq); 339 return 0; 340} 341 342/* EISA interrupts are always polarity zero and can be edge or level 343 * trigger depending on the ELCR value. If an interrupt is listed as 344 * EISA conforming in the MP table, that means its trigger type must 345 * be read in from the ELCR */ 346 347#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq)) 348#define default_EISA_polarity(idx) (0) 349 350/* ISA interrupts are always polarity zero edge triggered, 351 * when listed as conforming in the MP table. */ 352 353#define default_ISA_trigger(idx) (0) 354#define default_ISA_polarity(idx) (0) 355 356/* PCI interrupts are always polarity one level triggered, 357 * when listed as conforming in the MP table. */ 358 359#define default_PCI_trigger(idx) (1) 360#define default_PCI_polarity(idx) (1) 361 362/* MCA interrupts are always polarity zero level triggered, 363 * when listed as conforming in the MP table. */ 364 365#define default_MCA_trigger(idx) (1) 366#define default_MCA_polarity(idx) (0) 367 368static int __init MPBIOS_polarity(int idx) 369{ 370 int bus = mp_irqs[idx].mpc_srcbus; 371 int polarity; 372 373 /* 374 * Determine IRQ line polarity (high active or low active): 375 */ 376 switch (mp_irqs[idx].mpc_irqflag & 3) 377 { 378 case 0: /* conforms, ie. bus-type dependent polarity */ 379 { 380 switch (mp_bus_id_to_type[bus]) 381 { 382 case MP_BUS_ISA: /* ISA pin */ 383 { 384 polarity = default_ISA_polarity(idx); 385 break; 386 } 387 case MP_BUS_EISA: /* EISA pin */ 388 { 389 polarity = default_EISA_polarity(idx); 390 break; 391 } 392 case MP_BUS_PCI: /* PCI pin */ 393 { 394 polarity = default_PCI_polarity(idx); 395 break; 396 } 397 case MP_BUS_MCA: /* MCA pin */ 398 { 399 polarity = default_MCA_polarity(idx); 400 break; 401 } 402 default: 403 { 404 printk(KERN_WARNING "broken BIOS!!\n"); 405 polarity = 1; 406 break; 407 } 408 } 409 break; 410 } 411 case 1: /* high active */ 412 { 413 polarity = 0; 414 break; 415 } 416 case 2: /* reserved */ 417 { 418 printk(KERN_WARNING "broken BIOS!!\n"); 419 polarity = 1; 420 break; 421 } 422 case 3: /* low active */ 423 { 424 polarity = 1; 425 break; 426 } 427 default: /* invalid */ 428 { 429 printk(KERN_WARNING "broken BIOS!!\n"); 430 polarity = 1; 431 break; 432 } 433 } 434 return polarity; 435} 436 437static int __init MPBIOS_trigger(int idx) 438{ 439 int bus = mp_irqs[idx].mpc_srcbus; 440 int trigger; 441 442 /* 443 * Determine IRQ trigger mode (edge or level sensitive): 444 */ 445 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3) 446 { 447 case 0: /* conforms, ie. bus-type dependent */ 448 { 449 switch (mp_bus_id_to_type[bus]) 450 { 451 case MP_BUS_ISA: /* ISA pin */ 452 { 453 trigger = default_ISA_trigger(idx); 454 break; 455 } 456 case MP_BUS_EISA: /* EISA pin */ 457 { 458 trigger = default_EISA_trigger(idx); 459 break; 460 } 461 case MP_BUS_PCI: /* PCI pin */ 462 { 463 trigger = default_PCI_trigger(idx); 464 break; 465 } 466 case MP_BUS_MCA: /* MCA pin */ 467 { 468 trigger = default_MCA_trigger(idx); 469 break; 470 } 471 default: 472 { 473 printk(KERN_WARNING "broken BIOS!!\n"); 474 trigger = 1; 475 break; 476 } 477 } 478 break; 479 } 480 case 1: /* edge */ 481 { 482 trigger = 0; 483 break; 484 } 485 case 2: /* reserved */ 486 { 487 printk(KERN_WARNING "broken BIOS!!\n"); 488 trigger = 1; 489 break; 490 } 491 case 3: /* level */ 492 { 493 trigger = 1; 494 break; 495 } 496 default: /* invalid */ 497 { 498 printk(KERN_WARNING "broken BIOS!!\n"); 499 trigger = 0; 500 break; 501 } 502 } 503 return trigger; 504} 505 506static inline int irq_polarity(int idx) 507{ 508 return MPBIOS_polarity(idx); 509} 510 511static inline int irq_trigger(int idx) 512{ 513 return MPBIOS_trigger(idx); 514} 515 516static int pin_2_irq(int idx, int apic, int pin) 517{ 518 int irq, i; 519 int bus = mp_irqs[idx].mpc_srcbus; 520 521 /* 522 * Debugging check, we are in big trouble if this message pops up! 523 */ 524 if (mp_irqs[idx].mpc_dstirq != pin) 525 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); 526 527 switch (mp_bus_id_to_type[bus]) 528 { 529 case MP_BUS_ISA: /* ISA pin */ 530 case MP_BUS_EISA: 531 case MP_BUS_MCA: 532 { 533 irq = mp_irqs[idx].mpc_srcbusirq; 534 break; 535 } 536 case MP_BUS_PCI: /* PCI pin */ 537 { 538 /* 539 * PCI IRQs are mapped in order 540 */ 541 i = irq = 0; 542 while (i < apic) 543 irq += nr_ioapic_registers[i++]; 544 irq += pin; 545 break; 546 } 547 default: 548 { 549 printk(KERN_ERR "unknown bus type %d.\n",bus); 550 irq = 0; 551 break; 552 } 553 } 554 555 /* 556 * PCI IRQ command line redirection. Yes, limits are hardcoded. 557 */ 558 if ((pin >= 16) && (pin <= 23)) { 559 if (pirq_entries[pin-16] != -1) { 560 if (!pirq_entries[pin-16]) { 561 printk(KERN_DEBUG "disabling PIRQ%d\n", pin-16); 562 } else { 563 irq = pirq_entries[pin-16]; 564 printk(KERN_DEBUG "using PIRQ%d -> IRQ %d\n", 565 pin-16, irq); 566 } 567 } 568 } 569 return irq; 570} 571 572static inline int IO_APIC_irq_trigger(int irq) 573{ 574 int apic, idx, pin; 575 576 for (apic = 0; apic < nr_ioapics; apic++) { 577 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { 578 idx = find_irq_entry(apic,pin,mp_INT); 579 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin))) 580 return irq_trigger(idx); 581 } 582 } 583 /* 584 * nonexistent IRQs are edge default 585 */ 586 return 0; 587} 588 589int irq_vector[NR_IRQS] = { FIRST_DEVICE_VECTOR , 0 }; 590 591static int __init assign_irq_vector(int irq) 592{ 593 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0; 594 if (IO_APIC_VECTOR(irq) > 0) 595 return IO_APIC_VECTOR(irq); 596next: 597 current_vector += 8; 598 if (current_vector == SYSCALL_VECTOR) 599 goto next; 600 601 if (current_vector > FIRST_SYSTEM_VECTOR) { 602 offset++; 603 current_vector = FIRST_DEVICE_VECTOR + offset; 604 } 605 606 if (current_vector == FIRST_SYSTEM_VECTOR) 607 panic("ran out of interrupt sources!"); 608 609 IO_APIC_VECTOR(irq) = current_vector; 610 return current_vector; 611} 612 613extern void (*interrupt[NR_IRQS])(void); 614static struct hw_interrupt_type ioapic_level_irq_type; 615static struct hw_interrupt_type ioapic_edge_irq_type; 616 617void __init setup_IO_APIC_irqs(void) 618{ 619 struct IO_APIC_route_entry entry; 620 int apic, pin, idx, irq, first_notcon = 1, vector; 621 unsigned long flags; 622 623 printk(KERN_DEBUG "init IO_APIC IRQs\n"); 624 625 for (apic = 0; apic < nr_ioapics; apic++) { 626 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { 627 628 /* 629 * add it to the IO-APIC irq-routing table: 630 */ 631 memset(&entry,0,sizeof(entry)); 632 633 entry.delivery_mode = INT_DELIVERY_MODE; 634 entry.dest_mode = (INT_DEST_ADDR_MODE != 0); 635 entry.mask = 0; /* enable IRQ */ 636 entry.dest.logical.logical_dest = target_cpus(); 637 638 idx = find_irq_entry(apic,pin,mp_INT); 639 if (idx == -1) { 640 if (first_notcon) { 641 printk(KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin); 642 first_notcon = 0; 643 } else 644 printk(", %d-%d", mp_ioapics[apic].mpc_apicid, pin); 645 continue; 646 } 647 648 entry.trigger = irq_trigger(idx); 649 entry.polarity = irq_polarity(idx); 650 651 if (irq_trigger(idx)) { 652 entry.trigger = 1; 653 entry.mask = 1; 654 } 655 656 irq = pin_2_irq(idx, apic, pin); 657 /* 658 * skip adding the timer int on secondary nodes, which causes 659 * a small but painful rift in the time-space continuum 660 */ 661 if ((clustered_apic_mode == CLUSTERED_APIC_NUMAQ) 662 && (apic != 0) && (irq == 0)) 663 continue; 664 else 665 add_pin_to_irq(irq, apic, pin); 666 667 if (!apic && !IO_APIC_IRQ(irq)) 668 continue; 669 670 if (IO_APIC_IRQ(irq)) { 671 vector = assign_irq_vector(irq); 672 entry.vector = vector; 673 674 if (IO_APIC_irq_trigger(irq)) 675 irq_desc[irq].handler = &ioapic_level_irq_type; 676 else 677 irq_desc[irq].handler = &ioapic_edge_irq_type; 678 679 set_intr_gate(vector, interrupt[irq]); 680 681 if (!apic && (irq < 16)) 682 disable_8259A_irq(irq); 683 } 684 spin_lock_irqsave(&ioapic_lock, flags); 685 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1)); 686 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0)); 687 spin_unlock_irqrestore(&ioapic_lock, flags); 688 } 689 } 690 691 if (!first_notcon) 692 printk(" not connected.\n"); 693} 694 695/* 696 * Set up the 8259A-master output pin as broadcast to all 697 * CPUs. 698 */ 699void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector) 700{ 701 struct IO_APIC_route_entry entry; 702 unsigned long flags; 703 704 memset(&entry,0,sizeof(entry)); 705 706 disable_8259A_irq(0); 707 708 /* mask LVT0 */ 709 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); 710 711 /* 712 * We use logical delivery to get the timer IRQ 713 * to the first CPU. 714 */ 715 entry.dest_mode = (INT_DEST_ADDR_MODE != 0); 716 entry.mask = 0; /* unmask IRQ now */ 717 entry.dest.logical.logical_dest = target_cpus(); 718 entry.delivery_mode = INT_DELIVERY_MODE; 719 entry.polarity = 0; 720 entry.trigger = 0; 721 entry.vector = vector; 722 723 /* 724 * The timer IRQ doesn't have to know that behind the 725 * scene we have a 8259A-master in AEOI mode ... 726 */ 727 irq_desc[0].handler = &ioapic_edge_irq_type; 728 729 /* 730 * Add it to the IO-APIC irq-routing table: 731 */ 732 spin_lock_irqsave(&ioapic_lock, flags); 733 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1)); 734 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0)); 735 spin_unlock_irqrestore(&ioapic_lock, flags); 736 737 enable_8259A_irq(0); 738} 739 740void __init UNEXPECTED_IO_APIC(void) 741{ 742 printk(KERN_WARNING " WARNING: unexpected IO-APIC, please mail\n"); 743 printk(KERN_WARNING " to linux-smp@vger.kernel.org\n"); 744} 745 746void __init print_IO_APIC(void) 747{ 748 int apic, i; 749 struct IO_APIC_reg_00 reg_00; 750 struct IO_APIC_reg_01 reg_01; 751 struct IO_APIC_reg_02 reg_02; 752 unsigned long flags; 753 754 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); 755 for (i = 0; i < nr_ioapics; i++) 756 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", 757 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]); 758 759 /* 760 * We are a bit conservative about what we expect. We have to 761 * know about every hardware change ASAP. 762 */ 763 printk(KERN_INFO "testing the IO APIC.......................\n"); 764 765 for (apic = 0; apic < nr_ioapics; apic++) { 766 767 spin_lock_irqsave(&ioapic_lock, flags); 768 *(int *)®_00 = io_apic_read(apic, 0); 769 *(int *)®_01 = io_apic_read(apic, 1); 770 if (reg_01.version >= 0x10) 771 *(int *)®_02 = io_apic_read(apic, 2); 772 spin_unlock_irqrestore(&ioapic_lock, flags); 773 774 printk("\n"); 775 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid); 776 printk(KERN_DEBUG ".... register #00: %08X\n", *(int *)®_00); 777 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.ID); 778 if (reg_00.__reserved_1 || reg_00.__reserved_2) 779 UNEXPECTED_IO_APIC(); 780 781 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); 782 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.entries); 783 if ( (reg_01.entries != 0x0f) && /* older (Neptune) boards */ 784 (reg_01.entries != 0x17) && /* typical ISA+PCI boards */ 785 (reg_01.entries != 0x1b) && /* Compaq Proliant boards */ 786 (reg_01.entries != 0x1f) && /* dual Xeon boards */ 787 (reg_01.entries != 0x22) && /* bigger Xeon boards */ 788 (reg_01.entries != 0x2E) && 789 (reg_01.entries != 0x3F) 790 ) 791 UNEXPECTED_IO_APIC(); 792 793 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.PRQ); 794 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.version); 795 if ( (reg_01.version != 0x01) && /* 82489DX IO-APICs */ 796 (reg_01.version != 0x10) && /* oldest IO-APICs */ 797 (reg_01.version != 0x11) && /* Pentium/Pro IO-APICs */ 798 (reg_01.version != 0x13) && /* Xeon IO-APICs */ 799 (reg_01.version != 0x20) /* Intel P64H (82806 AA) */ 800 ) 801 UNEXPECTED_IO_APIC(); 802 if (reg_01.__reserved_1 || reg_01.__reserved_2) 803 UNEXPECTED_IO_APIC(); 804 805 if (reg_01.version >= 0x10) { 806 printk(KERN_DEBUG ".... register #02: %08X\n", *(int *)®_02); 807 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.arbitration); 808 if (reg_02.__reserved_1 || reg_02.__reserved_2) 809 UNEXPECTED_IO_APIC(); 810 } 811 812 printk(KERN_DEBUG ".... IRQ redirection table:\n"); 813 814 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol" 815 " Stat Dest Deli Vect: \n"); 816 817 for (i = 0; i <= reg_01.entries; i++) { 818 struct IO_APIC_route_entry entry; 819 820 spin_lock_irqsave(&ioapic_lock, flags); 821 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2); 822 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2); 823 spin_unlock_irqrestore(&ioapic_lock, flags); 824 825 printk(KERN_DEBUG " %02x %03X %02X ", 826 i, 827 entry.dest.logical.logical_dest, 828 entry.dest.physical.physical_dest 829 ); 830 831 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", 832 entry.mask, 833 entry.trigger, 834 entry.irr, 835 entry.polarity, 836 entry.delivery_status, 837 entry.dest_mode, 838 entry.delivery_mode, 839 entry.vector 840 ); 841 } 842 } 843 printk(KERN_DEBUG "IRQ to pin mappings:\n"); 844 for (i = 0; i < NR_IRQS; i++) { 845 struct irq_pin_list *entry = irq_2_pin + i; 846 if (entry->pin < 0) 847 continue; 848 printk(KERN_DEBUG "IRQ%d ", i); 849 for (;;) { 850 printk("-> %d:%d", entry->apic, entry->pin); 851 if (!entry->next) 852 break; 853 entry = irq_2_pin + entry->next; 854 } 855 printk("\n"); 856 } 857 858 printk(KERN_INFO ".................................... done.\n"); 859 860 return; 861} 862 863static void print_APIC_bitfield (int base) 864{ 865 unsigned int v; 866 int i, j; 867 868 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); 869 for (i = 0; i < 8; i++) { 870 v = apic_read(base + i*0x10); 871 for (j = 0; j < 32; j++) { 872 if (v & (1<<j)) 873 printk("1"); 874 else 875 printk("0"); 876 } 877 printk("\n"); 878 } 879} 880 881void /*__init*/ print_local_APIC(void * dummy) 882{ 883 unsigned int v, ver, maxlvt; 884 885 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", 886 smp_processor_id(), hard_smp_processor_id()); 887 v = apic_read(APIC_ID); 888 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v)); 889 v = apic_read(APIC_LVR); 890 printk(KERN_INFO "... APIC VERSION: %08x\n", v); 891 ver = GET_APIC_VERSION(v); 892 maxlvt = get_maxlvt(); 893 894 v = apic_read(APIC_TASKPRI); 895 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); 896 897 if (APIC_INTEGRATED(ver)) { /* !82489DX */ 898 v = apic_read(APIC_ARBPRI); 899 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, 900 v & APIC_ARBPRI_MASK); 901 v = apic_read(APIC_PROCPRI); 902 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); 903 } 904 905 v = apic_read(APIC_EOI); 906 printk(KERN_DEBUG "... APIC EOI: %08x\n", v); 907 v = apic_read(APIC_RRR); 908 printk(KERN_DEBUG "... APIC RRR: %08x\n", v); 909 v = apic_read(APIC_LDR); 910 printk(KERN_DEBUG "... APIC LDR: %08x\n", v); 911 v = apic_read(APIC_DFR); 912 printk(KERN_DEBUG "... APIC DFR: %08x\n", v); 913 v = apic_read(APIC_SPIV); 914 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); 915 916 printk(KERN_DEBUG "... APIC ISR field:\n"); 917 print_APIC_bitfield(APIC_ISR); 918 printk(KERN_DEBUG "... APIC TMR field:\n"); 919 print_APIC_bitfield(APIC_TMR); 920 printk(KERN_DEBUG "... APIC IRR field:\n"); 921 print_APIC_bitfield(APIC_IRR); 922 923 if (APIC_INTEGRATED(ver)) { /* !82489DX */ 924 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 925 apic_write(APIC_ESR, 0); 926 v = apic_read(APIC_ESR); 927 printk(KERN_DEBUG "... APIC ESR: %08x\n", v); 928 } 929 930 v = apic_read(APIC_ICR); 931 printk(KERN_DEBUG "... APIC ICR: %08x\n", v); 932 v = apic_read(APIC_ICR2); 933 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v); 934 935 v = apic_read(APIC_LVTT); 936 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); 937 938 if (maxlvt > 3) { /* PC is LVT#4. */ 939 v = apic_read(APIC_LVTPC); 940 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); 941 } 942 v = apic_read(APIC_LVT0); 943 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); 944 v = apic_read(APIC_LVT1); 945 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); 946 947 if (maxlvt > 2) { /* ERR is LVT#3. */ 948 v = apic_read(APIC_LVTERR); 949 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); 950 } 951 952 v = apic_read(APIC_TMICT); 953 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); 954 v = apic_read(APIC_TMCCT); 955 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); 956 v = apic_read(APIC_TDCR); 957 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); 958 printk("\n"); 959} 960 961void print_all_local_APICs (void) 962{ 963 smp_call_function(print_local_APIC, NULL, 1, 1); 964 print_local_APIC(NULL); 965} 966 967void /*__init*/ print_PIC(void) 968{ 969 extern spinlock_t i8259A_lock; 970 unsigned int v, flags; 971 972 printk(KERN_DEBUG "\nprinting PIC contents\n"); 973 974 spin_lock_irqsave(&i8259A_lock, flags); 975 976 v = inb(0xa1) << 8 | inb(0x21); 977 printk(KERN_DEBUG "... PIC IMR: %04x\n", v); 978 979 v = inb(0xa0) << 8 | inb(0x20); 980 printk(KERN_DEBUG "... PIC IRR: %04x\n", v); 981 982 outb(0x0b,0xa0); 983 outb(0x0b,0x20); 984 v = inb(0xa0) << 8 | inb(0x20); 985 outb(0x0a,0xa0); 986 outb(0x0a,0x20); 987 988 spin_unlock_irqrestore(&i8259A_lock, flags); 989 990 printk(KERN_DEBUG "... PIC ISR: %04x\n", v); 991 992 v = inb(0x4d1) << 8 | inb(0x4d0); 993 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); 994} 995 996static void __init enable_IO_APIC(void) 997{ 998 struct IO_APIC_reg_01 reg_01; 999 int i; 1000 unsigned long flags; 1001 1002 for (i = 0; i < PIN_MAP_SIZE; i++) { 1003 irq_2_pin[i].pin = -1; 1004 irq_2_pin[i].next = 0; 1005 } 1006 if (!pirqs_enabled) 1007 for (i = 0; i < MAX_PIRQS; i++) 1008 pirq_entries[i] = -1; 1009 1010 /* 1011 * The number of IO-APIC IRQ registers (== #pins): 1012 */ 1013 for (i = 0; i < nr_ioapics; i++) { 1014 spin_lock_irqsave(&ioapic_lock, flags); 1015 *(int *)®_01 = io_apic_read(i, 1); 1016 spin_unlock_irqrestore(&ioapic_lock, flags); 1017 nr_ioapic_registers[i] = reg_01.entries+1; 1018 } 1019 1020 /* 1021 * Do not trust the IO-APIC being empty at bootup 1022 */ 1023 clear_IO_APIC(); 1024} 1025 1026/* 1027 * Not an __init, needed by the reboot code 1028 */ 1029void disable_IO_APIC(void) 1030{ 1031 /* 1032 * Clear the IO-APIC before rebooting: 1033 */ 1034 clear_IO_APIC(); 1035 1036 disconnect_bsp_APIC(); 1037} 1038 1039/* 1040 * function to set the IO-APIC physical IDs based on the 1041 * values stored in the MPC table. 1042 * 1043 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 1044 */ 1045 1046static void __init setup_ioapic_ids_from_mpc (void) 1047{ 1048 struct IO_APIC_reg_00 reg_00; 1049 unsigned long phys_id_present_map = phys_cpu_present_map; 1050 int apic; 1051 int i; 1052 unsigned char old_id; 1053 unsigned long flags; 1054 1055 if (clustered_apic_mode) 1056 /* We don't have a good way to do this yet - hack */ 1057 phys_id_present_map = (u_long) 0xf; 1058 /* 1059 * Set the IOAPIC ID to the value stored in the MPC table. 1060 */ 1061 for (apic = 0; apic < nr_ioapics; apic++) { 1062 1063 /* Read the register 0 value */ 1064 spin_lock_irqsave(&ioapic_lock, flags); 1065 *(int *)®_00 = io_apic_read(apic, 0); 1066 spin_unlock_irqrestore(&ioapic_lock, flags); 1067 1068 old_id = mp_ioapics[apic].mpc_apicid; 1069 1070 if (mp_ioapics[apic].mpc_apicid >= 0xf) { 1071 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", 1072 apic, mp_ioapics[apic].mpc_apicid); 1073 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", 1074 reg_00.ID); 1075 mp_ioapics[apic].mpc_apicid = reg_00.ID; 1076 } 1077 1078 /* 1079 * Sanity check, is the ID really free? Every APIC in a 1080 * system must have a unique ID or we get lots of nice 1081 * 'stuck on smp_invalidate_needed IPI wait' messages. 1082 */ 1083 if (phys_id_present_map & (1 << mp_ioapics[apic].mpc_apicid)) { 1084 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", 1085 apic, mp_ioapics[apic].mpc_apicid); 1086 for (i = 0; i < 0xf; i++) 1087 if (!(phys_id_present_map & (1 << i))) 1088 break; 1089 if (i >= 0xf) 1090 panic("Max APIC ID exceeded!\n"); 1091 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", 1092 i); 1093 phys_id_present_map |= 1 << i; 1094 mp_ioapics[apic].mpc_apicid = i; 1095 } else { 1096 printk("Setting %d in the phys_id_present_map\n", mp_ioapics[apic].mpc_apicid); 1097 phys_id_present_map |= 1 << mp_ioapics[apic].mpc_apicid; 1098 } 1099 1100 1101 /* 1102 * We need to adjust the IRQ routing table 1103 * if the ID changed. 1104 */ 1105 if (old_id != mp_ioapics[apic].mpc_apicid) 1106 for (i = 0; i < mp_irq_entries; i++) 1107 if (mp_irqs[i].mpc_dstapic == old_id) 1108 mp_irqs[i].mpc_dstapic 1109 = mp_ioapics[apic].mpc_apicid; 1110 1111 /* 1112 * Read the right value from the MPC table and 1113 * write it into the ID register. 1114 */ 1115 printk(KERN_INFO "...changing IO-APIC physical APIC ID to %d ...", 1116 mp_ioapics[apic].mpc_apicid); 1117 1118 reg_00.ID = mp_ioapics[apic].mpc_apicid; 1119 spin_lock_irqsave(&ioapic_lock, flags); 1120 io_apic_write(apic, 0, *(int *)®_00); 1121 spin_unlock_irqrestore(&ioapic_lock, flags); 1122 1123 /* 1124 * Sanity check 1125 */ 1126 spin_lock_irqsave(&ioapic_lock, flags); 1127 *(int *)®_00 = io_apic_read(apic, 0); 1128 spin_unlock_irqrestore(&ioapic_lock, flags); 1129 if (reg_00.ID != mp_ioapics[apic].mpc_apicid) 1130 panic("could not set ID!\n"); 1131 else 1132 printk(" ok.\n"); 1133 } 1134} 1135 1136/* 1137 * There is a nasty bug in some older SMP boards, their mptable lies 1138 * about the timer IRQ. We do the following to work around the situation: 1139 * 1140 * - timer IRQ defaults to IO-APIC IRQ 1141 * - if this function detects that timer IRQs are defunct, then we fall 1142 * back to ISA timer IRQs 1143 */ 1144static int __init timer_irq_works(void) 1145{ 1146 unsigned int t1 = jiffies; 1147 1148 sti(); 1149 /* Let ten ticks pass... */ 1150 mdelay((10 * 1000) / HZ); 1151 1152 /* 1153 * Expect a few ticks at least, to be sure some possible 1154 * glue logic does not lock up after one or two first 1155 * ticks in a non-ExtINT mode. Also the local APIC 1156 * might have cached one ExtINT interrupt. Finally, at 1157 * least one tick may be lost due to delays. 1158 */ 1159 if (jiffies - t1 > 4) 1160 return 1; 1161 1162 return 0; 1163} 1164 1165/* 1166 * In the SMP+IOAPIC case it might happen that there are an unspecified 1167 * number of pending IRQ events unhandled. These cases are very rare, 1168 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much 1169 * better to do it this way as thus we do not have to be aware of 1170 * 'pending' interrupts in the IRQ path, except at this point. 1171 */ 1172/* 1173 * Edge triggered needs to resend any interrupt 1174 * that was delayed but this is now handled in the device 1175 * independent code. 1176 */ 1177#define enable_edge_ioapic_irq unmask_IO_APIC_irq 1178 1179static void disable_edge_ioapic_irq (unsigned int irq) { /* nothing */ } 1180 1181/* 1182 * Starting up a edge-triggered IO-APIC interrupt is 1183 * nasty - we need to make sure that we get the edge. 1184 * If it is already asserted for some reason, we need 1185 * return 1 to indicate that is was pending. 1186 * 1187 * This is not complete - we should be able to fake 1188 * an edge even if it isn't on the 8259A... 1189 */ 1190 1191static unsigned int startup_edge_ioapic_irq(unsigned int irq) 1192{ 1193 int was_pending = 0; 1194 unsigned long flags; 1195 1196 spin_lock_irqsave(&ioapic_lock, flags); 1197 if (irq < 16) { 1198 disable_8259A_irq(irq); 1199 if (i8259A_irq_pending(irq)) 1200 was_pending = 1; 1201 } 1202 __unmask_IO_APIC_irq(irq); 1203 spin_unlock_irqrestore(&ioapic_lock, flags); 1204 1205 return was_pending; 1206} 1207 1208#define shutdown_edge_ioapic_irq disable_edge_ioapic_irq 1209 1210/* 1211 * Once we have recorded IRQ_PENDING already, we can mask the 1212 * interrupt for real. This prevents IRQ storms from unhandled 1213 * devices. 1214 */ 1215static void ack_edge_ioapic_irq(unsigned int irq) 1216{ 1217 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED)) 1218 == (IRQ_PENDING | IRQ_DISABLED)) 1219 mask_IO_APIC_irq(irq); 1220 ack_APIC_irq(); 1221} 1222 1223static void end_edge_ioapic_irq (unsigned int i) { /* nothing */ } 1224 1225 1226/* 1227 * Level triggered interrupts can just be masked, 1228 * and shutting down and starting up the interrupt 1229 * is the same as enabling and disabling them -- except 1230 * with a startup need to return a "was pending" value. 1231 * 1232 * Level triggered interrupts are special because we 1233 * do not touch any IO-APIC register while handling 1234 * them. We ack the APIC in the end-IRQ handler, not 1235 * in the start-IRQ-handler. Protection against reentrance 1236 * from the same interrupt is still provided, both by the 1237 * generic IRQ layer and by the fact that an unacked local 1238 * APIC does not accept IRQs. 1239 */ 1240static unsigned int startup_level_ioapic_irq (unsigned int irq) 1241{ 1242 unmask_IO_APIC_irq(irq); 1243 1244 return 0; /* don't check for pending */ 1245} 1246 1247#define shutdown_level_ioapic_irq mask_IO_APIC_irq 1248#define enable_level_ioapic_irq unmask_IO_APIC_irq 1249#define disable_level_ioapic_irq mask_IO_APIC_irq 1250 1251static void end_level_ioapic_irq (unsigned int irq) 1252{ 1253 unsigned long v; 1254 int i; 1255 1256 i = IO_APIC_VECTOR(irq); 1257 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); 1258 1259 ack_APIC_irq(); 1260 1261 if (!(v & (1 << (i & 0x1f)))) { 1262#ifdef APIC_LOCKUP_DEBUG 1263 struct irq_pin_list *entry; 1264#endif 1265 1266#ifdef APIC_MISMATCH_DEBUG 1267 atomic_inc(&irq_mis_count); 1268#endif 1269 spin_lock(&ioapic_lock); 1270 __mask_and_edge_IO_APIC_irq(irq); 1271#ifdef APIC_LOCKUP_DEBUG 1272 for (entry = irq_2_pin + irq;;) { 1273 unsigned int reg; 1274 1275 if (entry->pin == -1) 1276 break; 1277 reg = io_apic_read(entry->apic, 0x10 + entry->pin * 2); 1278 if (reg & 0x00004000) 1279 printk(KERN_CRIT "Aieee!!! Remote IRR" 1280 " still set after unlock!\n"); 1281 if (!entry->next) 1282 break; 1283 entry = irq_2_pin + entry->next; 1284 } 1285#endif 1286 __unmask_and_level_IO_APIC_irq(irq); 1287 spin_unlock(&ioapic_lock); 1288 } 1289} 1290 1291static void mask_and_ack_level_ioapic_irq (unsigned int irq) { /* nothing */ } 1292 1293static void set_ioapic_affinity (unsigned int irq, unsigned long mask) 1294{ 1295 unsigned long flags; 1296 /* 1297 * Only the first 8 bits are valid. 1298 */ 1299 mask = mask << 24; 1300 1301 spin_lock_irqsave(&ioapic_lock, flags); 1302 __DO_ACTION(1, = mask, ) 1303 spin_unlock_irqrestore(&ioapic_lock, flags); 1304} 1305 1306/* 1307 * Level and edge triggered IO-APIC interrupts need different handling, 1308 * so we use two separate IRQ descriptors. Edge triggered IRQs can be 1309 * handled with the level-triggered descriptor, but that one has slightly 1310 * more overhead. Level-triggered interrupts cannot be handled with the 1311 * edge-triggered handler, without risking IRQ storms and other ugly 1312 * races. 1313 */ 1314 1315static struct hw_interrupt_type ioapic_edge_irq_type = { 1316 "IO-APIC-edge", 1317 startup_edge_ioapic_irq, 1318 shutdown_edge_ioapic_irq, 1319 enable_edge_ioapic_irq, 1320 disable_edge_ioapic_irq, 1321 ack_edge_ioapic_irq, 1322 end_edge_ioapic_irq, 1323 set_ioapic_affinity, 1324}; 1325 1326static struct hw_interrupt_type ioapic_level_irq_type = { 1327 "IO-APIC-level", 1328 startup_level_ioapic_irq, 1329 shutdown_level_ioapic_irq, 1330 enable_level_ioapic_irq, 1331 disable_level_ioapic_irq, 1332 mask_and_ack_level_ioapic_irq, 1333 end_level_ioapic_irq, 1334 set_ioapic_affinity, 1335}; 1336 1337static inline void init_IO_APIC_traps(void) 1338{ 1339 int irq; 1340 1341 /* 1342 * NOTE! The local APIC isn't very good at handling 1343 * multiple interrupts at the same interrupt level. 1344 * As the interrupt level is determined by taking the 1345 * vector number and shifting that right by 4, we 1346 * want to spread these out a bit so that they don't 1347 * all fall in the same interrupt level. 1348 * 1349 * Also, we've got to be careful not to trash gate 1350 * 0x80, because int 0x80 is hm, kind of importantish. ;) 1351 */ 1352 for (irq = 0; irq < NR_IRQS ; irq++) { 1353 if (IO_APIC_IRQ(irq) && !IO_APIC_VECTOR(irq)) { 1354 /* 1355 * Hmm.. We don't have an entry for this, 1356 * so default to an old-fashioned 8259 1357 * interrupt if we can.. 1358 */ 1359 if (irq < 16) 1360 make_8259A_irq(irq); 1361 else 1362 /* Strange. Oh, well.. */ 1363 irq_desc[irq].handler = &no_irq_type; 1364 } 1365 } 1366} 1367 1368static void enable_lapic_irq (unsigned int irq) 1369{ 1370 unsigned long v; 1371 1372 v = apic_read(APIC_LVT0); 1373 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED); 1374} 1375 1376static void disable_lapic_irq (unsigned int irq) 1377{ 1378 unsigned long v; 1379 1380 v = apic_read(APIC_LVT0); 1381 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); 1382} 1383 1384static void ack_lapic_irq (unsigned int irq) 1385{ 1386 ack_APIC_irq(); 1387} 1388 1389static void end_lapic_irq (unsigned int i) { /* nothing */ } 1390 1391static struct hw_interrupt_type lapic_irq_type = { 1392 "local-APIC-edge", 1393 NULL, /* startup_irq() not used for IRQ0 */ 1394 NULL, /* shutdown_irq() not used for IRQ0 */ 1395 enable_lapic_irq, 1396 disable_lapic_irq, 1397 ack_lapic_irq, 1398 end_lapic_irq 1399}; 1400 1401static void enable_NMI_through_LVT0 (void * dummy) 1402{ 1403 unsigned int v, ver; 1404 1405 ver = apic_read(APIC_LVR); 1406 ver = GET_APIC_VERSION(ver); 1407 v = APIC_DM_NMI; /* unmask and set to NMI */ 1408 if (!APIC_INTEGRATED(ver)) /* 82489DX */ 1409 v |= APIC_LVT_LEVEL_TRIGGER; 1410 apic_write_around(APIC_LVT0, v); 1411} 1412 1413static void setup_nmi (void) 1414{ 1415 /* 1416 * Dirty trick to enable the NMI watchdog ... 1417 * We put the 8259A master into AEOI mode and 1418 * unmask on all local APICs LVT0 as NMI. 1419 * 1420 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') 1421 * is from Maciej W. Rozycki - so we do not have to EOI from 1422 * the NMI handler or the timer interrupt. 1423 */ 1424 printk(KERN_INFO "activating NMI Watchdog ..."); 1425 1426 smp_call_function(enable_NMI_through_LVT0, NULL, 1, 1); 1427 enable_NMI_through_LVT0(NULL); 1428 1429 printk(" done.\n"); 1430} 1431 1432/* 1433 * This looks a bit hackish but it's about the only one way of sending 1434 * a few INTA cycles to 8259As and any associated glue logic. ICR does 1435 * not support the ExtINT mode, unfortunately. We need to send these 1436 * cycles as some i82489DX-based boards have glue logic that keeps the 1437 * 8259A interrupt line asserted until INTA. --macro 1438 */ 1439static inline void unlock_ExtINT_logic(void) 1440{ 1441 int pin, i; 1442 struct IO_APIC_route_entry entry0, entry1; 1443 unsigned char save_control, save_freq_select; 1444 unsigned long flags; 1445 1446 pin = find_isa_irq_pin(8, mp_INT); 1447 if (pin == -1) 1448 return; 1449 1450 spin_lock_irqsave(&ioapic_lock, flags); 1451 *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin); 1452 *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin); 1453 spin_unlock_irqrestore(&ioapic_lock, flags); 1454 clear_IO_APIC_pin(0, pin); 1455 1456 memset(&entry1, 0, sizeof(entry1)); 1457 1458 entry1.dest_mode = 0; /* physical delivery */ 1459 entry1.mask = 0; /* unmask IRQ now */ 1460 entry1.dest.physical.physical_dest = hard_smp_processor_id(); 1461 entry1.delivery_mode = dest_ExtINT; 1462 entry1.polarity = entry0.polarity; 1463 entry1.trigger = 0; 1464 entry1.vector = 0; 1465 1466 spin_lock_irqsave(&ioapic_lock, flags); 1467 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1)); 1468 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0)); 1469 spin_unlock_irqrestore(&ioapic_lock, flags); 1470 1471 save_control = CMOS_READ(RTC_CONTROL); 1472 save_freq_select = CMOS_READ(RTC_FREQ_SELECT); 1473 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, 1474 RTC_FREQ_SELECT); 1475 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); 1476 1477 i = 100; 1478 while (i-- > 0) { 1479 mdelay(10); 1480 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) 1481 i -= 10; 1482 } 1483 1484 CMOS_WRITE(save_control, RTC_CONTROL); 1485 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); 1486 clear_IO_APIC_pin(0, pin); 1487 1488 spin_lock_irqsave(&ioapic_lock, flags); 1489 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1)); 1490 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0)); 1491 spin_unlock_irqrestore(&ioapic_lock, flags); 1492} 1493 1494/* 1495 * This code may look a bit paranoid, but it's supposed to cooperate with 1496 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ 1497 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast 1498 * fanatically on his truly buggy board. 1499 */ 1500static inline void check_timer(void) 1501{ 1502 extern int timer_ack; 1503 int pin1, pin2; 1504 int vector; 1505 1506 /* 1507 * get/set the timer IRQ vector: 1508 */ 1509 disable_8259A_irq(0); 1510 vector = assign_irq_vector(0); 1511 set_intr_gate(vector, interrupt[0]); 1512 1513 /* 1514 * Subtle, code in do_timer_interrupt() expects an AEOI 1515 * mode for the 8259A whenever interrupts are routed 1516 * through I/O APICs. Also IRQ0 has to be enabled in 1517 * the 8259A which implies the virtual wire has to be 1518 * disabled in the local APIC. 1519 */ 1520 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); 1521 init_8259A(1); 1522 timer_ack = 1; 1523 enable_8259A_irq(0); 1524 1525 pin1 = find_isa_irq_pin(0, mp_INT); 1526 pin2 = find_isa_irq_pin(0, mp_ExtINT); 1527 1528 printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2); 1529 1530 if (pin1 != -1) { 1531 /* 1532 * Ok, does IRQ0 through the IOAPIC work? 1533 */ 1534 unmask_IO_APIC_irq(0); 1535 if (timer_irq_works()) { 1536 if (nmi_watchdog == NMI_IO_APIC) { 1537 disable_8259A_irq(0); 1538 setup_nmi(); 1539 enable_8259A_irq(0); 1540 check_nmi_watchdog(); 1541 } 1542 return; 1543 } 1544 clear_IO_APIC_pin(0, pin1); 1545 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n"); 1546 } 1547 1548 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... "); 1549 if (pin2 != -1) { 1550 printk("\n..... (found pin %d) ...", pin2); 1551 /* 1552 * legacy devices should be connected to IO APIC #0 1553 */ 1554 setup_ExtINT_IRQ0_pin(pin2, vector); 1555 if (timer_irq_works()) { 1556 printk("works.\n"); 1557 if (pin1 != -1) 1558 replace_pin_at_irq(0, 0, pin1, 0, pin2); 1559 else 1560 add_pin_to_irq(0, 0, pin2); 1561 if (nmi_watchdog == NMI_IO_APIC) { 1562 setup_nmi(); 1563 check_nmi_watchdog(); 1564 } 1565 return; 1566 } 1567 /* 1568 * Cleanup, just in case ... 1569 */ 1570 clear_IO_APIC_pin(0, pin2); 1571 } 1572 printk(" failed.\n"); 1573 1574 if (nmi_watchdog) { 1575 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n"); 1576 nmi_watchdog = 0; 1577 } 1578 1579 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); 1580 1581 disable_8259A_irq(0); 1582 irq_desc[0].handler = &lapic_irq_type; 1583 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ 1584 enable_8259A_irq(0); 1585 1586 if (timer_irq_works()) { 1587 printk(" works.\n"); 1588 return; 1589 } 1590 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector); 1591 printk(" failed.\n"); 1592 1593 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ..."); 1594 1595 init_8259A(0); 1596 make_8259A_irq(0); 1597 apic_write_around(APIC_LVT0, APIC_DM_EXTINT); 1598 1599 unlock_ExtINT_logic(); 1600 1601 if (timer_irq_works()) { 1602 printk(" works.\n"); 1603 return; 1604 } 1605 printk(" failed :(.\n"); 1606 panic("IO-APIC + timer doesn't work! pester mingo@redhat.com"); 1607} 1608 1609/* 1610 * 1611 * IRQ's that are handled by the old PIC in all cases: 1612 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ. 1613 * Linux doesn't really care, as it's not actually used 1614 * for any interrupt handling anyway. 1615 * - There used to be IRQ13 here as well, but all 1616 * MPS-compliant must not use it for FPU coupling and we 1617 * want to use exception 16 anyway. And there are 1618 * systems who connect it to an I/O APIC for other uses. 1619 * Thus we don't mark it special any longer. 1620 * 1621 * Additionally, something is definitely wrong with irq9 1622 * on PIIX4 boards. 1623 */ 1624#define PIC_IRQS (1<<2) 1625 1626void __init setup_IO_APIC(void) 1627{ 1628 enable_IO_APIC(); 1629 1630 io_apic_irqs = ~PIC_IRQS; 1631 printk("ENABLING IO-APIC IRQs\n"); 1632 1633 /* 1634 * Set up the IO-APIC IRQ routing table by parsing the MP-BIOS 1635 * mptable: 1636 */ 1637 setup_ioapic_ids_from_mpc(); 1638 sync_Arb_IDs(); 1639 setup_IO_APIC_irqs(); 1640 init_IO_APIC_traps(); 1641 check_timer(); 1642 print_IO_APIC(); 1643} 1644