1/* ********************************************************************* 2 * BCM947XX Board Support Package 3 * 4 * Board-specific initialization File: BCM947XX_INIT.S 5 * 6 * This module contains the assembly-language part of the init 7 * code for this board support package. The routine 8 * "board_earlyinit" lives here. 9 * 10 * Author: Mitch Lichtenberg (mpl@broadcom.com) 11 * 12 ********************************************************************* 13 * 14 * Copyright 2000,2001,2002,2003 15 * Broadcom Corporation. All rights reserved. 16 * 17 * This software is furnished under license and may be used and 18 * copied only in accordance with the following terms and 19 * conditions. Subject to these conditions, you may download, 20 * copy, install, use, modify and distribute modified or unmodified 21 * copies of this software in source and/or binary form. No title 22 * or ownership is transferred hereby. 23 * 24 * 1) Any source code used, modified or distributed must reproduce 25 * and retain this copyright notice and list of conditions 26 * as they appear in the source file. 27 * 28 * 2) No right is granted to use any trade name, trademark, or 29 * logo of Broadcom Corporation. The "Broadcom Corporation" 30 * name may not be used to endorse or promote products derived 31 * from this software without the prior written permission of 32 * Broadcom Corporation. 33 * 34 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 35 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 36 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 37 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 38 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 39 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 40 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 41 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 42 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 43 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 44 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 45 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 46 * THE POSSIBILITY OF SUCH DAMAGE. 47 ********************************************************************* */ 48 49#include "sbconfig.h" 50#include "bcmdevs.h" 51#include "sbchipc.h" 52#include "sbmips.h" 53#include "bsp_config.h" 54#include "mipsmacros.h" 55 56 .text 57 58 59/* ********************************************************************* 60 * BOARD_EARLYINIT() 61 * 62 * Initialize board registers. This is the earliest 63 * time the BSP gets control. This routine cannot assume that 64 * memory is operational, and therefore all code in this routine 65 * must run from registers only. The $ra register must not 66 * be modified, as it contains the return address. 67 * 68 * This routine will be called from uncached space, before 69 * the caches are initialized. If you want to make 70 * subroutine calls from here, you must use the CALLKSEG1 macro. 71 * 72 * Among other things, this is where the GPIO registers get 73 * programmed to make on-board LEDs function, or other startup 74 * that has to be done before anything will work. 75 * 76 * Input parameters: 77 * nothing 78 * 79 * Return value: 80 * nothing 81 ********************************************************************* */ 82 83/* 84 * Define TRADDR to be an (uncached) addres to store the "leds" for tracing 85 * This for example would use chipcommon's flash address register: 86 * #define TRADDR 0xb8000044 87 */ 88 89 90LEAF(board_earlyinit) 91 92 # XXX:the following code snipet sets clk frequency to 200M 93 # correct pll clk freq to real speed in the 5350 case. 94 # It is Ugly...but 95 96 li a2,PHYS_TO_K1(SB_ENUM_BASE) # Is there a chipcommon core? 97 lw t1,(SBCONFIGOFF + SBIDHIGH)(a2) 98 and t1,t1,SBIDH_CC_MASK 99 srl t1,t1,SBIDH_CC_SHIFT 100 bne t1,SB_CC,_move_ahead 101 nop 102 103 li a3,BCM5350_CHIP_ID # 5350 ChipID 104 lw t1,CC_CHIPID(a2) # ChipID register 105 li t2,CID_ID_MASK # chip id is bit 0-15 106 and t2,t1,t2 107 bne t2,a3,_move_ahead # if not 5350 then skip 108 nop 109 110 li t2,CID_PKG_MASK # if it is a vsim 5350, also skip 111 and t2,t1,t2 112 li a3,(HDLSIM5350_PKG_ID << CID_PKG_SHIFT) 113 beq t2,a3,_move_ahead # if pkg opt 1 then skip 114 nop 115 116 li a3,CLKC_5350_N 117 lw t1,CC_CLKC_N(a2) 118 beq a3,t1,_move_ahead # move ahead if clk freq set correctly 119 nop 120 sw a3,CC_CLKC_N(a2) # set control N1 to select 6 121 li t1,1 122 sw t1,CC_WATCHDOG(a2) # set WatchDog Reset 1231: b 1b 124 nop 125 126_move_ahead: 127 li a3,BCM5354_CHIP_ID # 5354 ChipID 128 and t2,t1,t2 129 bne t2,a3,_move_ahead2 # if not 5354 then skip 130 nop 131 132 li t1,PHYS_TO_K1(SB_ENUM_BASE) # CC base 133 134 li t2, 0x1 135 SR t2, PMU_REG_CONTROL_ADDR(t1) 136 LR t2, PMU_REG_CONTROL_DATA(t1) 137 li t3, 0x6800000 138 beq t3, t2,_move_ahead1 # move ahead if switcher freq set correctly 139 SR t3, PMU_REG_CONTROL_DATA(t1) 140 141 /* 142 * Trim the output voltage of the 1.2V BB switcher and 2.5V 143 * regulator to the correct value. 144 */ 145 li t2,0x0 146 sw t2,PMU_REG_CONTROL_ADDR(a2) 147 li t3,0x2000 # Reduce the output voltage of 148 sw t3,PMU_REG_CONTROL_DATA(a2) # BB switcher to get 1.2V 149 li t2,0x3 150 sw t2,PMU_REG_CONTROL_ADDR(a2) 151 li t3,0x02000000 # Increase the output voltage 152 sw t3,PMU_REG_CONTROL_DATA(a2) # of VDDP LDO to get 2.5V 153 154 li t2, 0x1 155 SR t2, PMU_PLL_CONTROL_ADDR(t1) 156 LR t2, PMU_REG_CONTROL_DATA(t1) 157 li t3, 0x66666602 158 beq t3, t2,_move_ahead1 # move ahead if PLL is set correctly 159 160 li t2, 0x7ffff 161 SR t2, PMU_MIN_RES_MASK(t1) # Disable base band PLL 162 SR t2, PMU_MAX_RES_MASK(t1) 163 nop 164 165 li t2, 0x1 # Set the PLL mode properly 166 SR t2, PMU_PLL_CONTROL_ADDR(t1) 167 li t2, 0x66666602 168 SR t2, PMU_PLL_CONTROL_DATA(t1) 169 170 171 li t1,1 172 sw t1,CC_WATCHDOG(a2) # set WatchDog Reset 1731: b 1b 174 nop 175 176_move_ahead1: 177 li t1,PHYS_TO_K1(SB_ENUM_BASE) # CC base 178 li t2, 0xfffff 179 SR t2, PMU_MIN_RES_MASK(t1) # Enable Base band PLL 180 SR t2, PMU_MAX_RES_MASK(t1) 181 182 #Init code for FF4 space without TLB, enabling RAC 183 li t0, 0x1FA0000C # Set up CBR to 0x1FAx_xxxx 184 mtc0 t0, $22,6 185 li t1, 0x1FA00000 186 lw t2, 0x14(t1) 187 or t3, t2,0xC0000000 # enable ffxx_xxxx space # without programming TLB 188 sw t3, 0x14(t1) 189 li t0, 0xFF40000C # change CBR to FF4x_xxxx 190 mtc0 t0, $22,6 191 192_move_ahead2: 193#ifdef TRADDR 194 li t0,TRADDR 195 li t1,0xaa55aa55 196 sw t1,0(t0) 197#endif 198 j ra 199 200END(board_earlyinit) 201 202/* ********************************************************************* 203 * BOARD_DRAMINFO 204 * 205 * Return the address of the DRAM information table 206 * 207 * Input parameters: 208 * nothing 209 * 210 * Return value: 211 * v0 - DRAM info table, return 0 to use default table 212 ********************************************************************* */ 213 214LEAF(board_draminfo) 215 216 move v0,zero # auto configure 217 j ra 218 219END(board_draminfo) 220 221/* ********************************************************************* 222 * BOARD_SETLEDS(x) 223 * 224 * Set LEDs for boot-time progress indication. Not used if 225 * the board does not have progress LEDs. This routine 226 * must not call any other routines, since it may be invoked 227 * either from KSEG0 or KSEG1 and it may be invoked 228 * whether or not the icache is operational. 229 * 230 * Input parameters: 231 * a0 - LED value (8 bits per character, 4 characters) 232 * 233 * Return value: 234 * nothing 235 ********************************************************************* */ 236 237LEAF(board_setleds) 238 239#ifdef TRADDR 240 li t0,TRADDR 241 sw a0,0(t0) 242#endif 243 j ra 244 245END(board_setleds) 246