/u-boot/arch/m68k/cpu/mcf5445x/ |
H A D | interrupts.c | 21 setbits_be32(&intp->imrh0, 0xffffffff); 22 setbits_be32(&intp->imrl0, 0xffffffff);
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/u-boot/arch/m68k/cpu/mcf532x/ |
H A D | interrupts.c | 18 setbits_be32(&intp->imrh0, 0xffffffff); 19 setbits_be32(&intp->imrl0, 0xffffffff);
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/u-boot/board/netgear/dgnd3700v2/ |
H A D | dgnd3700v2.c | 23 setbits_be32(gpio_regs + GPIO_MODE_6362_REG,
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/u-boot/board/freescale/m5275evb/ |
H A D | m5275evb.c | 49 setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); 55 setbits_be32(&sdp->sdmr, 68 setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); 73 setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
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/u-boot/arch/m68k/cpu/mcf523x/ |
H A D | interrupts.c | 18 setbits_be32(&intp->imrl0, 0x1);
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/u-boot/board/freescale/m5235evb/ |
H A D | m5235evb.c | 75 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP); 86 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE); 94 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS);
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/u-boot/board/freescale/p1_p2_rdb_pc/ |
H A D | p1_p2_rdb_pc.c | 156 setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA); 159 setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA); 172 setbits_be32(&pgpio->gpdir, 0x02130000); 175 setbits_be32(&pgpio->gpdir, 0x00200000); 176 setbits_be32(&pgpio->gpodr, 0x00200000); 179 setbits_be32(&pgpio->gpdat, 0x00200000); 186 setbits_be32(&pgpio->gpdir, 0x00080000); 187 setbits_be32(&pgpio->gpdat, 0x00080000); 192 setbits_be32(&pgpio->gpdir, 0x00040000); 193 setbits_be32( [all...] |
H A D | spl.c | 43 setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); 44 setbits_be32(&gur->pmuxcr,
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/u-boot/board/cssi/cmpc885/ |
H A D | cmpc885.c | 82 setbits_be32(&cp->cp_pedat, 0x00002000); 156 setbits_be32(&cp->cp_pbdat, 0x00029510); 157 setbits_be32(&cp->cp_pedat, 0x00000002); 183 setbits_be32(&cp->cp_pbdir, 0x0003A130); 275 setbits_be32(&cp->cp_peodr, 0x00002002); 303 setbits_be32(&cp->cp_pedat, 0x00002000); 465 setbits_be32(&cp->cp_pbdat, 0x00021510); 466 setbits_be32(&cp->cp_pedat, 0x00000002); 499 setbits_be32(&cp->cp_pbpar, 0x0000C800); 532 setbits_be32( [all...] |
/u-boot/arch/arm/cpu/armv7/ls102xa/ |
H A D | ls102xa_psci.c | 127 setbits_be32(&scfg->hrstcr, 0x80000000); 130 setbits_be32(&ddr->sdram_cfg_2, 0x80000000); 143 setbits_be32(dcsr_epu_base + EPGCR, 0x80000000); 146 setbits_be32(dcsr_epu_base + EPECR15, 0x90000004); 176 setbits_be32(&rcpm->clpcl10setr, RCPM_CLPCL10SETR_C0); 200 setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN); 201 setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR); 204 setbits_be32(&gur->devdisr, CCSR_DEVDISR1_QE); 233 setbits_be32(&rcpm->powmgtcsr, RCPM_POWMGTCSR_LPM20_REQ);
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/u-boot/drivers/misc/ |
H A D | fsl_devdis.c | 24 setbits_be32(&gur->devdisr + tbl[i].offset,
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/u-boot/arch/powerpc/cpu/mpc85xx/ |
H A D | cpu_init.c | 76 setbits_be32(&usb_phy->pllprg[1], 117 setbits_be32(&usb_phy->config1, 119 setbits_be32(&usb_phy->config2, 245 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 248 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 251 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); 255 setbits_be32(&cpc->cpchdbcr0, 350 setbits_be32(plldadcr1, 0x02000001); 352 setbits_be32(plldadcr2, 0x02000001); 354 setbits_be32(plldadcr [all...] |
/u-boot/arch/m68k/cpu/mcf52x2/ |
H A D | interrupts.c | 42 setbits_be32(&intp->int_icr1, CFG_SYS_TMRINTR_PRI); 58 setbits_be32(&intp->imrl0, 0x1);
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/u-boot/arch/powerpc/cpu/mpc8xx/ |
H A D | interrupts.c | 132 setbits_be32(&immr->im_cpic.cpic_cisr, 1 << vec); 161 setbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec); 169 setbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec)); 213 setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN); 249 setbits_be32(&immr->im_clkrst.car_plprcr, 0);
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/u-boot/drivers/net/ |
H A D | mpc8xx_fec.c | 281 setbits_be32(&immr->im_cpm.cp_cptr, mask); 306 setbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */ 315 setbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT); 356 setbits_be32(&immr->im_cpm.cp_pbpar, 0x00001001); 362 setbits_be32(&immr->im_cpm.cp_pepar, 0x00000003); 363 setbits_be32(&immr->im_cpm.cp_pedir, 0x00000003); 378 setbits_be32(&immr->im_cpm.cp_pbpar, 0x00000001); 381 setbits_be32(&immr->im_cpm.cp_cptr, 0x00000100); 410 setbits_be32(&immr->im_ioport.utmode, 0x80); 421 setbits_be32( [all...] |
/u-boot/drivers/phy/ |
H A D | bcm6318-usbh-phy.c | 52 setbits_be32(priv->regs + USBH_PLL_REG, USBH_PLL_SUSP_EN); 60 setbits_be32(priv->regs + USBH_SETUP_REG, USBH_SETUP_IOC); 66 setbits_be32(priv->regs + USBH_SIM_REG, USBH_SIM_LADDR);
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/u-boot/board/freescale/ls1012afrdm/ |
H A D | eth.c | 35 setbits_be32(&pgpio->gpdir, MASK_ETH_PHY_RST); 38 setbits_be32(&pgpio->gpdat, val & ~MASK_ETH_PHY_RST); 42 setbits_be32(&pgpio->gpdat, val | MASK_ETH_PHY_RST);
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/u-boot/board/cssi/mcr3000/ |
H A D | mcr3000.c | 136 setbits_be32(&immr->im_cpm.cp_pbdat, 0x20000); 167 setbits_be32(&immr->im_cpm.cp_pbdir, 0xf); 192 setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */ 194 setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */
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/u-boot/arch/powerpc/cpu/mpc8xxx/ |
H A D | srio.c | 122 setbits_be32((void *)&srio_regs->lp_serial 129 setbits_be32((void *)&srio_regs->impl.port[port].pcr, 168 setbits_be32(&srds_regs->lane[idx].gcr0, 278 setbits_be32(devdisr, _DEVDISR_SRIO1); 280 setbits_be32(devdisr, _DEVDISR_SRIO2); 285 setbits_be32(devdisr, _DEVDISR_SRIO1); 286 setbits_be32(devdisr, _DEVDISR_SRIO2); 287 setbits_be32(devdisr, _DEVDISR_RMU);
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/u-boot/board/freescale/p1010rdb/ |
H A D | spl.c | 37 setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); 40 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
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/u-boot/drivers/spi/ |
H A D | mpc8xxx_spi.c | 95 setbits_be32(&priv->spi->mode, SPI_MODE_OP); 98 setbits_be32(&spi->mode, (8 - 1) << SPI_MODE_LEN_SHIFT); 100 setbits_be32(&spi->mode, SPI_MODE_EN); 103 setbits_be32(&priv->spi->event, 0xffffffff); 156 setbits_be32(&spi->event, 0xffffffff); 189 setbits_be32(&spi->event, SPI_EV_NE);
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/u-boot/arch/mips/mach-ath79/ |
H A D | reset.c | 81 setbits_be32(base + reg, AR71XX_RESET_FULL_CHIP); 135 setbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask); 168 setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask); 187 setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask); 256 setbits_be32(rregs + QCA956X_RESET_REG_RESET_MODULE, mask); 331 setbits_be32(rregs + QCA956X_RESET_REG_RESET_MODULE, mask); 360 setbits_be32(rregs + QCA956X_RESET_REG_RESET_MODULE, mask); 446 setbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE, 462 setbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE, 488 setbits_be32(reset_reg [all...] |
/u-boot/board/keymile/pg-wcom-ls102xa/ |
H A D | pg-wcom-ls102xa.c | 58 setbits_be32(&gur->ddrclkdr, 2); 61 setbits_be32(&ifc.gregs->ifc_gcr, 12 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); 62 setbits_be32(&ifc.gregs->ifc_ccr, IFC_CCR_CLK_DIV(3) |
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/u-boot/drivers/ddr/fsl/ |
H A D | mpc85xx_ddr_gen3.c | 403 setbits_be32(&ddr->debug[0], 1); 414 setbits_be32(&ecm->eebacr, 0x10000000); 418 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT); 423 setbits_be32(&ddr->debug[2], 0x400); 440 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); 509 setbits_be32(&ddr->debug[0], 0x10000); 513 setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK); 526 setbits_be32(&ddr->debug[1], 0x800); 538 setbits_be32(&ddr->sdram_cfg_2, 544 setbits_be32( [all...] |
/u-boot/drivers/net/fm/ |
H A D | dtsec.c | 70 setbits_be32(®s->maccfg1, MACCFG1_RXTX_EN); 84 setbits_be32(®s->rctrl, RCTRL_GRS); 87 setbits_be32(®s->tctrl, TCTRL_GTS);
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