/u-boot/arch/arm/include/asm/arch-tegra/ |
H A D | pwm.h | 13 uint control; /* Control register */ member in struct:pwm_ctlr
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/u-boot/arch/arm/cpu/arm11/ |
H A D | sctlr.S | 3 * Routines to access the system control register 14 * aligned flag in the system control register. 20 mrc p15, 0, r0, c1, c0, 0 @ load system control register 23 mcr p15, 0, r0, c1, c0, 0 @ write system control register
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/u-boot/arch/arm/cpu/armv7/ |
H A D | sctlr.S | 3 * Routines to access the system control register 13 * This routine clears the aligned flag in the system control register. 18 mrc p15, 0, r0, c1, c0, 0 @ load system control register 20 mcr p15, 0, r0, c1, c0, 0 @ write system control register
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/u-boot/drivers/spi/ |
H A D | microchip_coreqspi.c | 121 u32 control; local 123 control = CONTROL_CLKIDLE | CONTROL_ENABLE; 125 writel(control, qspi->regs + REG_CONTROL); 131 u32 control, data; local 136 control = readl(qspi->regs + REG_CONTROL); 142 control |= CONTROL_FLAGSX4; 143 writel(control, qspi->regs + REG_CONTROL); 154 control &= ~CONTROL_FLAGSX4; 155 writel(control, qspi->regs + REG_CONTROL); 167 u32 control, dat local 269 u32 control = readl(qspi->regs + REG_CONTROL); local 404 u32 control, baud_rate_val = 0; local 424 u32 control; local [all...] |
/u-boot/drivers/misc/ |
H A D | qfw_sandbox.c | 50 u32 control = be32_to_cpu(dma->control); local 58 if (!(control & FW_CFG_DMA_READ)) 61 if (control & FW_CFG_DMA_SELECT) { 63 entry = control >> 16; 104 dma->control = 0;
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H A D | ihs_fpga.h | 17 * @control: FPGA control register 18 * @extended_control: FPGA extended control register 29 u16 control; member in struct:ihs_fpga_regs
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/u-boot/board/gdsys/a38x/ |
H A D | hydra.h | 7 u32 control; /* 0x0020 */ member in struct:ihs_fpga
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/u-boot/include/ |
H A D | tegra-kbc.h | 14 u32 control; member in struct:kbc_tegra
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H A D | gdsys_fpga.h | 57 u16 control; member in struct:ihs_osd 65 u16 control; member in struct:ihs_mdio
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/u-boot/arch/arm/mach-omap2/ |
H A D | abb.c | 59 void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, argument 65 if (!setup || !control || !txdone) 101 writel(0, control); 113 setbits_le32(control, opp_sel_mask | OMAP_ABB_CONTROL_OPP_CHANGE_MASK);
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/u-boot/arch/arm/mach-imx/ |
H A D | timer.c | 21 unsigned int control; member in struct:mxc_gpt 72 __raw_writel(GPTCR_SWR, &cur_gpt->control); 76 __raw_writel(0, &cur_gpt->control); 78 i = __raw_readl(&cur_gpt->control); 104 __raw_writel(i, &cur_gpt->control);
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/u-boot/drivers/i2c/ |
H A D | tegra_i2c.c | 39 struct i2c_control *control; member in struct:i2c_bus 157 writel(data, &i2c_bus->control->tx_fifo); 162 writel(data, &i2c_bus->control->tx_fifo); 175 writel(data, &i2c_bus->control->tx_fifo); 179 static int wait_for_tx_fifo_empty(struct i2c_control *control) argument 185 count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK) 196 static int wait_for_rx_fifo_notempty(struct i2c_control *control) argument 202 count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK) 213 static int wait_for_transfer_complete(struct i2c_control *control) argument 219 int_status = readl(&control 237 struct i2c_control *control = i2c_bus->control; local [all...] |
H A D | mvtwsi.c | 62 u32 control; member in struct:mvtwsi_registers 74 u32 control; member in struct:mvtwsi_registers 104 * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control 254 * @lc: The last value of the control register. 276 int control, status; local 280 control = readl(&twsi->control); 281 if (control & MVTWSI_CONTROL_IFLG) { 285 * control register and only after that it changed the 299 control, statu 372 int expected_status, status, control; local 402 int control, stop_status; local [all...] |
/u-boot/tools/kermit/ |
H A D | send_cmd | 7 set flow-control none
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H A D | send_image | 9 set flow-control none
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/u-boot/drivers/timer/ |
H A D | altera_timer.c | 17 /* control register */ 24 u32 control; /* Timer control reg */ member in struct:altera_timer_regs 56 writel(0, ®s->control); 57 writel(ALTERA_TIMER_STOP, ®s->control); 61 writel(ALTERA_TIMER_CONT | ALTERA_TIMER_START, ®s->control);
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/u-boot/drivers/ram/ |
H A D | stm32_sdram.c | 28 u32 bcr1; /* NOR/PSRAM Chip select control register 1 */ 39 u32 pcr; /* NAND Flash control register */ 168 struct stm32_sdram_control *control; local 181 control = params->bank_params[i].sdram_control; 186 writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT 187 | control->cas_latency << FMC_SDCR_CAS_SHIFT 188 | control->no_banks << FMC_SDCR_NB_SHIFT 189 | control->memory_width << FMC_SDCR_MWID_SHIFT 190 | control->no_rows << FMC_SDCR_NR_SHIFT 191 | control [all...] |
/u-boot/arch/arm/mach-lpc32xx/ |
H A D | dram.c | 56 writel(0x00000193, &emc->control); 59 writel(0x00000113, &emc->control); 67 writel(0x00000093, &emc->control); 70 writel(0x00000093, &emc->control); 73 writel(0x00000010, &emc->control);
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/u-boot/drivers/net/ |
H A D | xilinx_axi_mrmac.c | 127 writel(XMCDMA_CR_RESET, &priv->mm2s_cmn->control); 128 writel(XMCDMA_CR_RESET, &priv->s2mm_cmn->control); 131 ret = wait_for_bit_le32(&priv->mm2s_cmn->control, XMCDMA_CR_RESET, 138 ret = wait_for_bit_le32(&priv->s2mm_cmn->control, XMCDMA_CR_RESET, 180 clrbits_le32(&priv->mcdma_rx->control, XMCDMA_IRQ_ALL_MASK); 214 setbits_le32(&priv->s2mm_cmn->control, XMCDMA_CR_RUNSTOP_MASK); 215 setbits_le32(&priv->mm2s_cmn->control, XMCDMA_CR_RUNSTOP_MASK); 216 setbits_le32(&priv->mcdma_rx->control, XMCDMA_IRQ_ALL_MASK); 219 setbits_le32(&priv->mcdma_rx->control, XMCDMA_CR_RUNSTOP_MASK); 265 clrbits_le32(&priv->mcdma_tx->control, XMCDMA_CR_RUNSTOP_MAS [all...] |
/u-boot/drivers/serial/ |
H A D | altera_jtag_uart.c | 17 /* control register */ 26 u32 control; /* Control register */ member in struct:altera_jtaguart_regs 42 u32 st = readl(®s->control); 61 u32 st = readl(®s->control); 89 writel(ALTERA_JTAG_AC, ®s->control); /* clear AC flag */ 140 u32 st = readl(®s->control);
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H A D | serial_xuartlite.c | 32 unsigned int control; member in struct:uartlite 96 uart_out32(®s->control, 0); 97 uart_out32(®s->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX); 102 uart_out32(®s->control, ULITE_CONTROL_RST_RX | 149 uart_out32(®s->control, 0); 150 uart_out32(®s->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX); 155 uart_out32(®s->control, ULITE_CONTROL_RST_RX |
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/u-boot/tools/binman/ |
H A D | main.py | 46 from binman import control namespace 90 glob_list = control.GetEntryModules(False) 127 control.write_bintool_docs(bintool.Bintool.get_tool_list()) 130 control.WriteEntryDocs(control.GetEntryModules()) 134 ret_code = control.Binman(args)
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H A D | binman | 46 from binman import control 90 glob_list = control.GetEntryModules(False) 127 control.write_bintool_docs(bintool.Bintool.get_tool_list()) 130 control.WriteEntryDocs(control.GetEntryModules()) 134 ret_code = control.Binman(args)
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/u-boot/tools/patman/ |
H A D | __main__.py | 26 from patman import control namespace 36 the control module. 78 control.send(args) 84 control.patchwork_status(args.branch, args.count, args.start, args.end,
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/u-boot/tools/buildman/ |
H A D | main.py | 25 from buildman import control namespace 71 the control module. 97 ret_code = control.do_buildman(args)
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