Searched refs:clrsetbits_le32 (Results 1 - 25 of 304) sorted by relevance

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/u-boot/arch/arm/mach-omap2/omap3/
H A Dclock.c134 clrsetbits_le32(&prcm_base->clken_pll,
145 clrsetbits_le32(&prcm_base->clksel1_emu,
147 clrsetbits_le32(&prcm_base->clksel1_emu,
151 clrsetbits_le32(&prcm_base->clksel1_pll,
155 clrsetbits_le32(&prcm_base->clksel1_pll,
159 clrsetbits_le32(&prcm_base->clksel1_pll,
166 clrsetbits_le32(&prcm_base->clksel_core,
169 clrsetbits_le32(&prcm_base->clksel_core,
172 clrsetbits_le32(&prcm_base->clksel_core,
175 clrsetbits_le32(
[all...]
H A Dam35x_musb.c20 clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
22 clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
34 clrsetbits_le32(&am35x_scm_general_regs->devconf2,
51 clrsetbits_le32(&am35x_scm_general_regs->devconf2,
59 clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr,
/u-boot/board/mscc/common/
H A Dspi.c23 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
28 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
/u-boot/board/toradex/colibri_vf/
H A Dcolibri_vf.c224 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
229 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
231 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
235 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
237 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
240 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
242 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
244 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
246 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
253 clrsetbits_le32(
[all...]
/u-boot/board/phytec/pcm052/
H A Dpcm052.c222 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
224 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
226 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
231 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
233 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
236 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
238 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
240 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
242 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
245 clrsetbits_le32(
[all...]
/u-boot/arch/riscv/include/asm/arch-jh7110/
H A Dgpio.h52 clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_OFFSET(gpio), \
57 clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DOUT + GPIO_OFFSET(gpio), \
62 clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DIN + GPIO_OFFSET(gpi), \
67 clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
71 clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
75 clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
/u-boot/drivers/ram/rockchip/
H A Dsdram_phy_px30.c73 clrsetbits_le32(PHY_REG(phy_base, 0x12), 0x1f << 3, cmd_drv << 3);
100 clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 0xf << 4);
104 clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 3 << 4);
108 clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 1 << 4);
132 clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0);
133 clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0);
134 clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0);
135 clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0);
138 clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs));
140 clrsetbits_le32(PHY_RE
[all...]
H A Dsdram_rk3399.c311 clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col));
312 clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
316 clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
320 clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col));
323 clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
337 clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
448 clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
450 clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
452 clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
454 clrsetbits_le32(
[all...]
/u-boot/drivers/mtd/nand/raw/
H A Dcortina_nand.c98 clrsetbits_le32(&info->reg->flash_flash_access_start, GENMASK(31, 0),
128 clrsetbits_le32(&info->reg->flash_flash_access_start,
204 clrsetbits_le32(&info->dma_nand->dma_q_rxq_base_depth,
206 clrsetbits_le32(&info->dma_nand->dma_q_rxq_base_depth,
210 clrsetbits_le32(&info->dma_nand->dma_q_txq_base_depth,
212 clrsetbits_le32(&info->dma_nand->dma_q_txq_base_depth,
263 clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0),
270 clrsetbits_le32(&info->reg->flash_nf_ecc_reset, GENMASK(31, 0),
280 clrsetbits_le32(&info->reg->flash_nf_access, GENMASK(11, 10),
290 clrsetbits_le32(
[all...]
/u-boot/board/freescale/vf610twr/
H A Dvf610twr.c275 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
277 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
279 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
284 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
286 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
289 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
291 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
293 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
295 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
298 clrsetbits_le32(
[all...]
/u-boot/drivers/phy/
H A Dphy-da8xx-usb.c23 clrsetbits_le32(&davinci_syscfg_regs->cfgchip2,
43 clrsetbits_le32(&davinci_syscfg_regs->cfgchip2,
H A Dphy-mtk-tphy.c284 clrsetbits_le32(u2_banks->com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV,
287 clrsetbits_le32(u2_banks->com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW,
302 clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM0,
316 clrsetbits_le32(u2_banks->com + U3P_USBPHYACR6,
321 clrsetbits_le32(u2_banks->com + U3P_USBPHYACR5,
342 clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
360 clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
376 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
380 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG9,
383 clrsetbits_le32(u3_bank
[all...]
/u-boot/board/phytec/phycore_imx8mp/
H A Dphycore-imx8mp.c23 clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
/u-boot/board/phytec/phycore_imx8mm/
H A Dphycore-imx8mm.c23 clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
/u-boot/board/freescale/imx8mn_evk/
H A Dimx8mn_evk.c27 clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
/u-boot/board/cloos/imx8mm_phg/
H A Dimx8mm_phg.c25 clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
/u-boot/drivers/video/rockchip/
H A Drk3399_vop.c32 clrsetbits_le32(&regs->dsp_ctrl1,
38 clrsetbits_le32(&regs->dsp_ctrl1,
44 clrsetbits_le32(&regs->dsp_ctrl1,
/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Dspl_lradc_init.c27 clrsetbits_le32(&regs->hw_lradc_ctrl3,
31 clrsetbits_le32(&regs->hw_lradc_ctrl4,
55 clrsetbits_le32(&regs->hw_lradc_conversion,
/u-boot/board/samsung/odroid/
H A Dodroid.c124 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
134 clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
143 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
167 clrsetbits_le32(&clk->div_cpu0, clr, set);
182 clrsetbits_le32(&clk->div_cpu1, clr, set);
208 clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
217 clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
228 clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
252 clrsetbits_le32(&clk->div_dmc0, clr, set);
275 clrsetbits_le32(
[all...]
/u-boot/arch/arm/mach-imx/
H A Dsata.c25 clrsetbits_le32(&iomuxc_regs->gpr[13],
/u-boot/board/renesas/rcar-common/
H A Dv3-common.c31 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
/u-boot/arch/arm/mach-omap2/omap5/
H A Dabb.c54 clrsetbits_le32(ldovbb, OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK, vset);
/u-boot/drivers/ata/
H A Dahci_sunxi.c29 clrsetbits_le32(reg_base + AHCI_PHYCS0R,
32 clrsetbits_le32(reg_base + AHCI_PHYCS1R,
37 clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20));
38 clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5));
/u-boot/drivers/ram/sunxi/
H A Ddram_sun20i_d1.c54 clrsetbits_le32(0x3000150, 0xff00, reg << 8);
73 clrsetbits_le32(0x3000150, 0x20ff00, vol << 8);
467 clrsetbits_le32(0x3103078, 0xf000ffff,
529 clrsetbits_le32(SUNXI_CCM_BASE + 0x800, BIT(31) | BIT(30), BIT(27));
569 clrsetbits_le32(0x3102008, 0x3f00, 0x2000);
721 clrsetbits_le32(0x310200c, 0xfff, (para->dram_clk / 2) - 1);
724 clrsetbits_le32(0x3103108, 0xf00, 0x300);
733 clrsetbits_le32(0x3103344, 0xf63e, val);
735 clrsetbits_le32(0x3103344, 0xf03e, val);
740 clrsetbits_le32(
[all...]
/u-boot/board/kontron/sl-mx6ul/
H A Dsl-mx6ul.c41 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
48 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,

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