Searched refs:base (Results 1 - 25 of 34) sorted by relevance

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/seL4-mcs-10.1.1/include/
H A Dcompound_types.h20 pde_t *base; member in struct:pde_range
26 pte_t *base; member in struct:pte_range
/seL4-mcs-10.1.1/include/object/
H A Duntyped.h30 #define GET_FREE_REF(base,freeIndex) ((word_t)(((word_t)(base)) + FREE_INDEX_TO_OFFSET(freeIndex)))
31 #define GET_FREE_INDEX(base,free) (((word_t)(free) - (word_t)(base))>>seL4_MinUntypedBits)
32 #define GET_OFFSET_FREE_PTR(base, offset) ((void *)(((word_t)(base)) + (offset)))
/seL4-mcs-10.1.1/include/arch/x86/arch/32/mode/
H A Dmachine.h123 static inline void FORCE_INLINE x86_write_fs_base_impl(word_t base) argument
125 gdt_entry_gdt_data_ptr_set_base_low(x86KSGlobalState[CURRENT_CPU_INDEX()].x86KSgdt + GDT_IPCBUF, base);
126 gdt_entry_gdt_data_ptr_set_base_mid(x86KSGlobalState[CURRENT_CPU_INDEX()].x86KSgdt + GDT_IPCBUF, (base >> 16) & 0xFF);
127 gdt_entry_gdt_data_ptr_set_base_high(x86KSGlobalState[CURRENT_CPU_INDEX()].x86KSgdt + GDT_IPCBUF, (base >> 24) & 0xFF);
130 static inline void FORCE_INLINE x86_write_gs_base_impl(word_t base) argument
132 gdt_entry_gdt_data_ptr_set_base_low(x86KSGlobalState[CURRENT_CPU_INDEX()].x86KSgdt + GDT_TLS, base);
133 gdt_entry_gdt_data_ptr_set_base_mid(x86KSGlobalState[CURRENT_CPU_INDEX()].x86KSgdt + GDT_TLS, (base >> 16) & 0xFF);
134 gdt_entry_gdt_data_ptr_set_base_high(x86KSGlobalState[CURRENT_CPU_INDEX()].x86KSgdt + GDT_TLS, (base >> 24) & 0xFF);
/seL4-mcs-10.1.1/include/arch/x86/arch/64/mode/
H A Dmachine.h254 static inline void x86_write_fs_base_impl(word_t base) argument
256 asm volatile ("wrfsbase %0"::"r"(base));
259 static inline void x86_write_gs_base_impl(word_t base) argument
261 asm volatile ("wrgsbase %0"::"r"(base));
266 word_t base = 0; local
267 asm volatile ("rdfsbase %0":"=r"(base));
268 return base;
273 word_t base = 0; local
274 asm volatile ("rdgsbase %0":"=r"(base));
275 return base;
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/seL4-mcs-10.1.1/src/
H A Dutil.c114 unsigned int base; local
121 base = 16;
124 base = 10;
134 if (res == -1 || res >= base) {
137 val = val * base + res;
/seL4-mcs-10.1.1/libsel4/tools/
H A Dbitfield_gen.py45 def return_name(base):
47 return 'ret__unsigned' + ret_name_suffix_map[base]
133 """entity_list : entity_list base"""
152 """base : BASE INTLIT"""
156 """base : BASE INTLIT LPAREN INTLIT COMMA INTLIT RPAREN"""
282 %(block)s_set_%(field)s(%(block)s_t %(block)s, %(type)s v%(base)d) {
284 %(assert)s((((~0x%(mask)x %(r_shift_op)s %(shift)d ) | 0x%(high_bits)x) & v%(base)d) == ((%(sign_extend)d && (v%(base)d & (1%(suf)s << (%(extend_bit)d)))) ? 0x%(high_bits)x : 0));
286 %(block)s.words[%(index)d] |= (v%(base)d %(w_shift_op)s %(shift)d) & 0x%(mask)x%(suf)s;
292 %(block)s_ptr_set_%(field)s(%(block)s_t *%(block)s_ptr, %(type)s v%(base)
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/seL4-mcs-10.1.1/manual/tools/libsel4_tools/
H A Dbitfield_gen.py45 def return_name(base):
47 return 'ret__unsigned' + ret_name_suffix_map[base]
133 """entity_list : entity_list base"""
152 """base : BASE INTLIT"""
156 """base : BASE INTLIT LPAREN INTLIT COMMA INTLIT RPAREN"""
282 %(block)s_set_%(field)s(%(block)s_t %(block)s, %(type)s v%(base)d) {
284 %(assert)s((((~0x%(mask)x %(r_shift_op)s %(shift)d ) | 0x%(high_bits)x) & v%(base)d) == ((%(sign_extend)d && (v%(base)d & (1%(suf)s << (%(extend_bit)d)))) ? 0x%(high_bits)x : 0));
286 %(block)s.words[%(index)d] |= (v%(base)d %(w_shift_op)s %(shift)d) & 0x%(mask)x%(suf)s;
292 %(block)s_ptr_set_%(field)s(%(block)s_t *%(block)s_ptr, %(type)s v%(base)
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/seL4-mcs-10.1.1/tools/
H A Dbitfield_gen.py45 def return_name(base):
47 return 'ret__unsigned' + ret_name_suffix_map[base]
133 """entity_list : entity_list base"""
152 """base : BASE INTLIT"""
156 """base : BASE INTLIT LPAREN INTLIT COMMA INTLIT RPAREN"""
282 %(block)s_set_%(field)s(%(block)s_t %(block)s, %(type)s v%(base)d) {
284 %(assert)s((((~0x%(mask)x %(r_shift_op)s %(shift)d ) | 0x%(high_bits)x) & v%(base)d) == ((%(sign_extend)d && (v%(base)d & (1%(suf)s << (%(extend_bit)d)))) ? 0x%(high_bits)x : 0));
286 %(block)s.words[%(index)d] |= (v%(base)d %(w_shift_op)s %(shift)d) & 0x%(mask)x%(suf)s;
292 %(block)s_ptr_set_%(field)s(%(block)s_t *%(block)s_ptr, %(type)s v%(base)
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/seL4-mcs-10.1.1/include/arch/x86/arch/32/mode/fastpath/
H A Dfastpath.h109 word_t base = getRegister(cur_thread, TLS_BASE); local
110 x86_write_gs_base(base, SMP_TERNARY(getCurrentCPUIndex(), 0));
112 base = cur_thread->tcbIPCBuffer;
113 x86_write_fs_base(base, SMP_TERNARY(getCurrentCPUIndex(), 0));
/seL4-mcs-10.1.1/src/arch/x86/32/
H A Dc_traps.c147 word_t base = getRegister(NODE_STATE(ksCurThread), TLS_BASE); local
148 x86_write_gs_base(base, SMP_TERNARY(getCurrentCPUIndex(), 0));
150 base = NODE_STATE(ksCurThread)->tcbIPCBuffer;
151 x86_write_fs_base(base, SMP_TERNARY(getCurrentCPUIndex(), 0));
/seL4-mcs-10.1.1/include/arch/x86/arch/
H A Dmachine.h244 static inline void x86_write_fs_base_impl(word_t base) argument
246 x86_wrmsr(IA32_FS_BASE_MSR, base);
249 static inline void x86_write_gs_base_impl(word_t base) argument
251 x86_wrmsr(IA32_GS_BASE_MSR, base);
269 static inline void x86_write_fs_base(word_t base, cpu_id_t cpu) argument
271 if (base != ARCH_NODE_STATE_ON_CORE(x86KSCurrentFSBase, cpu)) {
272 ARCH_NODE_STATE_ON_CORE(x86KSCurrentFSBase, cpu) = base;
273 x86_write_fs_base_impl(base);
277 static inline void x86_write_gs_base(word_t base, cpu_id_t cpu) argument
279 if (likely(base !
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/seL4-mcs-10.1.1/include/arch/x86/arch/64/mode/fastpath/
H A Dfastpath.h153 * update the GS base. We must *not* use any kernel functions
156 word_t base = getRegister(cur_thread, TLS_BASE); local
157 x86_write_fs_base(base, SMP_TERNARY(cpu, 0));
159 base = cur_thread->tcbIPCBuffer;
160 x86_write_gs_base(base, SMP_TERNARY(cpu, 0));
/seL4-mcs-10.1.1/src/arch/x86/64/
H A Dc_traps.c180 * update the GS base. We must *not* use any kernel functions
183 word_t base = getRegister(cur_thread, TLS_BASE); local
184 x86_write_fs_base(base, SMP_TERNARY(cpu, 0));
186 base = cur_thread->tcbIPCBuffer;
187 x86_write_gs_base(base, SMP_TERNARY(cpu, 0));
364 // set the user gs base previously
/seL4-mcs-10.1.1/include/plat/am335x/plat/machine/
H A Dinterrupt.h23 #define CMPER_REG(base, off) ((volatile uint32_t *)((base) + (off)))
/seL4-mcs-10.1.1/src/plat/am335x/machine/
H A Dhardware.c35 #define WDT_REG(base, off) ((volatile uint32_t *)((base) + (off)))
/seL4-mcs-10.1.1/src/plat/spike/machine/
H A Dfdt.c172 uint64_t base, size; local
173 value = fdt_get_address(node->parent, value, &base);
176 base, base + size
178 printf("Failed to add physical memory region %llu-%llu\n", (unsigned long long)base, (unsigned long long)(base + size));
/seL4-mcs-10.1.1/include/arch/riscv/arch/kernel/
H A Dvspace.h73 pte_t pte, pte_t *base);
74 exception_t performPageInvocationRemapPTE(pte_t pte, pte_t *base);
/seL4-mcs-10.1.1/src/arch/arm/32/kernel/
H A Dvspace.c834 to get the super section frame base */
852 to get the large frame base */
1396 /* Haskell error: "ASID pool's base must be aligned" */
1684 (paddr_t base, word_t vaddr, vm_page_size_t frameSize,
1696 ret.pte_entries.base = NULL; /* to avoid uninitialised warning */
1699 ret.pte = makeUserPTE(ARMSmallPage, base,
1716 ret.pte_entries.base = lu_ret.ptSlot;
1718 if (unlikely(pte_ptr_get_pteType(ret.pte_entries.base) ==
1721 if (unlikely(pte_ptr_get_pteType(ret.pte_entries.base) == pte_pte_small
1722 && pte_pte_small_ptr_get_contiguous_hint(ret.pte_entries.base))) {
1683 createSafeMappingEntries_PTE(paddr_t base, word_t vaddr, vm_page_size_t frameSize, vm_rights_t vmRights, vm_attributes_t attr, pde_t *pd) argument
1783 createSafeMappingEntries_PDE(paddr_t base, word_t vaddr, vm_page_size_t frameSize, vm_rights_t vmRights, vm_attributes_t attr, pde_t *pd) argument
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/seL4-mcs-10.1.1/include/arch/arm/arch/64/mode/kernel/
H A Dvspace.h36 void deleteASIDPool(asid_t base, asid_pool_t* pool);
/seL4-mcs-10.1.1/include/plat/pc99/plat/machine/
H A Dacpi.h72 uint32_t base; member in struct:acpi_rmrr_entry
/seL4-mcs-10.1.1/include/arch/arm/arch/32/mode/kernel/
H A Dvspace.h56 void deleteASIDPool(asid_t base, asid_pool_t* pool);
/seL4-mcs-10.1.1/src/arch/riscv/kernel/
H A Dvspace.c122 /* now we should be mapping the 1GiB kernel base, starting again from PADDR_LOAD */
443 /* Haskell error: "ASID pool's base must be aligned" */
466 /* Haskell error: "ASID pool's base must be aligned" */
1184 static exception_t updatePTE(pte_t pte, pte_t *base) argument
1186 *base = pte;
1192 pte_t pte, pte_t *base)
1195 return updatePTE(pte, base);
1199 performPageInvocationRemapPTE(pte_t pte, pte_t *base) argument
1201 return updatePTE(pte, base);
1191 performPageInvocationMapPTE(cap_t cap, cte_t *ctSlot, pte_t pte, pte_t *base) argument
/seL4-mcs-10.1.1/src/arch/x86/64/kernel/
H A Dvspace.c317 word_t base = (word_t)&x64KSIRQStack[CURRENT_CPU_INDEX()][IRQ_STACK_SIZE]; local
319 sizeof(*tss), /* io map base */
327 base >> 32, base & 0xffffffff, /* ist 1 */
357 0, /* base high */
366 0, /* base middle */
367 0, /* base low */
372 0, /* base high */
380 0, /* base mid */
381 0, /* base lo
1544 createSafeMappingEntries_PDPTE(paddr_t base, word_t vaddr, vm_rights_t vmRights, vm_attributes_t attr, vspace_root_t *vspace) argument
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/seL4-mcs-10.1.1/src/arch/arm/64/kernel/
H A Dvspace.c1687 paddr_t base = pptr_to_paddr((void *)base_ptr); local
1689 setRegister(NODE_STATE(ksCurThread), msgRegisters[0], base); local
2113 paddr_t base; local
2177 base = pptr_to_paddr((void *)cap_frame_cap_get_capFBasePtr(cap));
2195 makeUser3rdLevel(base, vmRights, attributes), lu_ret.ptSlot);
2214 makeUser2ndLevel(base, vmRights, attributes), lu_ret.pdSlot);
2233 makeUser1stLevel(base, vmRights, attributes), lu_ret.pudSlot);
2239 paddr_t base; local
2288 base = pptr_to_paddr((void *)cap_frame_cap_get_capFBasePtr(cap));
2296 makeUser3rdLevel(base, vmRight
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/seL4-mcs-10.1.1/src/arch/x86/32/kernel/
H A Dvspace.c387 gdt_idt_ptr.base = (uint32_t)x86KSGlobalState[CURRENT_CPU_INDEX()].x86KSgdt;
392 gdt_idt_ptr.base = (uint32_t)x86KSGlobalState[CURRENT_CPU_INDEX()].x86KSidt;

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