Searched refs:MASK (Results 1 - 25 of 55) sorted by relevance

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/seL4-mcs-10.1.1/include/arch/arm/arch/machine/
H A Dhardware.h24 #define PAGE_BASE(_p, _s) ((_p) & ~MASK(pageBitsForSize((_s))))
25 #define PAGE_OFFSET(_p, _s) ((_p) & MASK(pageBitsForSize((_s))))
26 #define IS_PAGE_ALIGNED(_p, _s) (((_p) & MASK(pageBitsForSize((_s)))) == 0)
H A Dtlb.h48 SMP_COND_STATEMENT(doRemoteInvalidateTranslationSingle(vptr, MASK(CONFIG_MAX_NUM_NODES)));
54 SMP_COND_STATEMENT(doRemoteInvalidateTranslationASID(hw_asid, MASK(CONFIG_MAX_NUM_NODES)));
60 SMP_COND_STATEMENT(doRemoteInvalidateTranslationAll(MASK(CONFIG_MAX_NUM_NODES)));
/seL4-mcs-10.1.1/src/arch/arm/64/machine/
H A Dfpu.c41 if ((id_aa64pfr0 >> ID_AA64PFR0_EL1_FP) & MASK(4) ||
42 (id_aa64pfr0 >> ID_AA64PFR0_EL1_ASIMD) & MASK(4)) {
/seL4-mcs-10.1.1/src/arch/arm/machine/
H A Derrata.c58 uint32_t variant = (proc_id >> 20) & MASK(4);
59 uint32_t revision = proc_id & MASK(4);
60 uint32_t part = (proc_id >> 4) & MASK(12);
/seL4-mcs-10.1.1/src/arch/arm/armv/armv7-a/
H A Dcache.c36 #define LOUU(x) (((x) >> 27) & MASK(3))
37 #define LOC(x) (((x) >> 24) & MASK(3))
38 #define LOUIS(x) (((x) >> 21) & MASK(3))
39 #define CTYPE(x,n) (((x) >> (n*3)) & MASK(3))
66 #define LINEBITS(s) (( (s) & MASK(3)) + 4)
68 #define ASSOC(s) ((((s) >> 3) & MASK(10)) + 1)
70 #define NSETS(s) ((((s) >> 13) & MASK(15)) + 1)
/seL4-mcs-10.1.1/src/arch/arm/armv/armv8-a/32/
H A Dcache.c36 #define LOUU(x) (((x) >> 27) & MASK(3))
37 #define LOC(x) (((x) >> 24) & MASK(3))
38 #define LOUIS(x) (((x) >> 21) & MASK(3))
39 #define CTYPE(x,n) (((x) >> (n*3)) & MASK(3))
66 #define LINEBITS(s) (( (s) & MASK(3)) + 4)
68 #define ASSOC(s) ((((s) >> 3) & MASK(10)) + 1)
70 #define NSETS(s) ((((s) >> 13) & MASK(15)) + 1)
/seL4-mcs-10.1.1/src/arch/arm/armv/armv8-a/64/
H A Dcache.c37 #define LOUU(x) (((x) >> 27) & MASK(3))
38 #define LOC(x) (((x) >> 24) & MASK(3))
39 #define LOUIS(x) (((x) >> 21) & MASK(3))
40 #define CTYPE(x,n) (((x) >> (n*3)) & MASK(3))
62 #define LINEBITS(s) (((s) & MASK(3)) + 4)
63 #define ASSOC(s) ((((s) >> 3) & MASK(10)) + 1)
64 #define NSETS(s) ((((s) >> 13) & MASK(15)) + 1)
/seL4-mcs-10.1.1/include/arch/x86/arch/64/mode/object/
H A Dstructures.h68 #define GET_PML4_INDEX(x) ( ((x) >> (PML4_INDEX_OFFSET)) & MASK(PML4_INDEX_BITS))
70 #define GET_PDPT_INDEX(x) ( ((x) >> (PDPT_INDEX_OFFSET)) & MASK(PDPT_INDEX_BITS))
71 #define GET_PD_INDEX(x) ( ((x) >> (PD_INDEX_OFFSET)) & MASK(PD_INDEX_BITS))
72 #define GET_PT_INDEX(x) ( ((x) >> (PT_INDEX_OFFSET)) & MASK(PT_INDEX_BITS))
123 #define ASID_LOW(a) (a & MASK(asidLowBits))
124 #define ASID_HIGH(a) ((a >> asidLowBits) & MASK(asidHighBits))
/seL4-mcs-10.1.1/src/arch/arm/api/
H A Dfaults.c46 ipa = (addressTranslateS1CPR(va) & ~MASK(PAGE_BITS)) | (va & MASK(PAGE_BITS));
/seL4-mcs-10.1.1/include/arch/arm/arch/32/mode/fastpath/
H A Dfastpath.h74 return (pd_cap.words[0] & MASK(5)) ==
82 really checking that n + 3 <= MASK(3), i.e. n + 3 <= 7 or n <= 4. */
87 return ((msgInfo & MASK(seL4_MsgLengthBits + seL4_MsgExtraCapBits))
88 + 3) & ~MASK(3);
/seL4-mcs-10.1.1/include/arch/x86/arch/machine/
H A Dcpu_registers.h31 #define FLAGS_MASK MASK(12)/* Only the first 12 bits of the FLAGS are used, rest should be zero */
/seL4-mcs-10.1.1/include/plat/pc99/plat/32/plat_mode/machine/
H A Dhardware.h22 #define PPTR_USER_TOP (PPTR_BASE & (~MASK(seL4_LargePageBits)))
/seL4-mcs-10.1.1/src/plat/pc99/machine/
H A Dioapic.c67 ioapic_write(ioapic, IOAPIC_WINDOW, (ioapic_read(ioapic, IOAPIC_WINDOW) & MASK(IOREDTBL_HIGH_RESERVED_BITS)) | (delivery_cpu << IOREDTBL_HIGH_RESERVED_BITS));
72 ioredtbl_state[i] |= ioapic_read(ioapic, IOAPIC_WINDOW) & ~MASK(16);
157 ioredtbl_high = ioapic_read(ioapic, IOAPIC_WINDOW) & MASK(IOREDTBL_HIGH_RESERVED_BITS);
169 ioredtbl_state[index] |= ioapic_read(ioapic, IOAPIC_WINDOW) & ~MASK(16);
/seL4-mcs-10.1.1/include/object/
H A Dstructures.h84 (((cte_t *)((word_t)(p)&~MASK(seL4_TCBBits)))+(i))
96 #define ZombieType_ZombieCNode(n) ((n) & MASK(wordRadix))
104 mask = MASK(TCB_CNODE_RADIX + 1);
106 mask = MASK(type + 1);
126 return cap_zombie_cap_get_capZombieID(cap) & MASK(radix + 1);
133 return cap_zombie_cap_get_capZombieID(cap) & ~MASK(radix + 1);
140 word_t ptr = cap_zombie_cap_get_capZombieID(cap) & ~MASK(radix + 1);
141 return cap_zombie_cap_set_capZombieID(cap, ptr | (n & MASK(radix + 1)));
/seL4-mcs-10.1.1/include/arch/arm/arch/64/mode/object/
H A Dstructures.h59 #define GET_PGD_INDEX(x) (((x) >> (PGD_INDEX_OFFSET)) & MASK(PGD_INDEX_BITS))
60 #define GET_PUD_INDEX(x) (((x) >> (PUD_INDEX_OFFSET)) & MASK(PUD_INDEX_BITS))
61 #define GET_PD_INDEX(x) (((x) >> (PD_INDEX_OFFSET)) & MASK(PD_INDEX_BITS))
62 #define GET_PT_INDEX(x) (((x) >> (PT_INDEX_OFFSET)) & MASK(PT_INDEX_BITS))
114 #define ASID_LOW(a) (a & MASK(asidLowBits))
115 #define ASID_HIGH(a) ((a >> asidLowBits) & MASK(asidHighBits))
/seL4-mcs-10.1.1/include/arch/arm/arch/32/mode/object/
H A Dstructures.h129 #define ASID_LOW(a) (a & MASK(asidLowBits))
130 #define ASID_HIGH(a) ((a >> asidLowBits) & MASK(asidHighBits))
136 asid & MASK(asidLowBits));
138 (asid >> asidLowBits) & MASK(asidHighBits));
152 asid & MASK(asidLowBits));
154 (asid >> asidLowBits) & MASK(asidHighBits));
/seL4-mcs-10.1.1/include/arch/riscv/arch/object/
H A Dstructures.h45 #define ASID_LOW(a) (a & MASK(asidLowBits))
46 #define ASID_HIGH(a) ((a >> asidLowBits) & MASK(asidHighBits))
/seL4-mcs-10.1.1/include/arch/x86/arch/32/mode/object/
H A Dstructures.h69 #define ASID_LOW(a) (a & MASK(asidLowBits))
70 #define ASID_HIGH(a) ((a >> asidLowBits) & MASK(asidHighBits))
/seL4-mcs-10.1.1/include/arch/riscv/arch/machine/
H A Dhardware.h42 #define RISCV_GET_PT_INDEX(addr, n) (((addr) >> (((PT_INDEX_BITS) * ((CONFIG_PT_LEVELS) - (n))) + seL4_PageBits)) & MASK(PT_INDEX_BITS))
/seL4-mcs-10.1.1/include/arch/x86/arch/object/
H A Dstructures.h96 #define GET_EPT_PML4_INDEX(x) ( (((uint64_t)(x)) >> (EPT_PML4_INDEX_OFFSET)) & MASK(EPT_PML4_INDEX_BITS))
97 #define GET_EPT_PDPT_INDEX(x) ( ((x) >> (EPT_PDPT_INDEX_OFFSET)) & MASK(EPT_PDPT_INDEX_BITS))
98 #define GET_EPT_PD_INDEX(x) ( ((x) >> (EPT_PD_INDEX_OFFSET)) & MASK(EPT_PD_INDEX_BITS))
99 #define GET_EPT_PT_INDEX(x) ( ((x) >> (EPT_PT_INDEX_OFFSET)) & MASK(EPT_PT_INDEX_BITS))
/seL4-mcs-10.1.1/src/arch/arm/32/kernel/
H A Dvspace.c167 word_t idx = (vaddr & MASK(pageBitsForSize(ARMSection))) >> pageBitsForSize(ARMSmallPage);
431 idx = (seL4_GlobalsFrame >> PAGE_BITS) & (MASK(PT_INDEX_BITS));
453 targetSlot = pt + ((vptr & MASK(pageBitsForSize(ARMSection)))
695 pd = poolPtr->array[asid & MASK(asidLowBits)];
735 return (word_t *)(basePtr + (w_bufferPtr & MASK(pageBits)));
756 if (unlikely(vptr & MASK(seL4_IPCBufferSizeBits))) {
794 ptIndex = (vptr >> PAGE_BITS) & MASK(PT_INDEX_BITS);
808 ptIndex = (vptr >> PAGE_BITS) & MASK(PT_INDEX_BITS);
835 ret.frameBase &= ~MASK(pageBitsForSize(ARMSuperSection));
853 ret.frameBase &= ~MASK(pageBitsForSiz
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/seL4-mcs-10.1.1/include/arch/x86/arch/64/mode/fastpath/
H A Dfastpath.h107 really checking that n + 3 <= MASK(3), i.e. n + 3 <= 7 or n <= 4. */
112 return ((msgInfo & MASK(seL4_MsgLengthBits + seL4_MsgExtraCapBits))
113 + 3) & ~MASK(3);
/seL4-mcs-10.1.1/include/plat/bcm2837/plat/
H A Dmachine.h133 #define LOCAL_TIMER_CTRL_RL_MASK MASK(28)
163 pending &= MASK(12);
/seL4-mcs-10.1.1/include/
H A Dutil.h14 #define MASK(n) (BIT(n)-1ul) macro
15 #define IS_ALIGNED(n, b) (!((n) & MASK(b)))
/seL4-mcs-10.1.1/src/arch/x86/32/kernel/
H A Dvspace_32paging.c147 *(pt + ((vptr & MASK(seL4_LargePageBits)) >> seL4_PageBits)) = pte_new(
222 poolPtr->array[asid & MASK(asidLowBits)] = asid_map;
342 offset = vaddr & MASK(seL4_LargePageBits);
347 offset = vaddr & MASK(seL4_PageBits);

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