Searched refs:x86_write_msr (Results 1 - 16 of 16) sorted by relevance
/haiku/src/system/kernel/arch/x86/64/ |
H A D | syscalls.cpp | 54 x86_write_msr(IA32_MSR_EFER, x86_read_msr(IA32_MSR_EFER) 59 x86_write_msr(IA32_MSR_FMASK, X86_EFLAGS_INTERRUPT | X86_EFLAGS_DIRECTION 64 x86_write_msr(IA32_MSR_LSTAR, (addr_t)x86_64_syscall_entry); 68 x86_write_msr(IA32_MSR_CSTAR, (addr_t)x86_64_syscall32_entry); 83 x86_write_msr(IA32_MSR_STAR, ((uint64)(USER32_CODE_SELECTOR) << 48) 105 x86_write_msr(IA32_MSR_SYSENTER_ESP, stackTop); 112 x86_write_msr(IA32_MSR_SYSENTER_CS, KERNEL_CODE_SELECTOR); 113 x86_write_msr(IA32_MSR_SYSENTER_ESP, 0); 114 x86_write_msr(IA32_MSR_SYSENTER_EIP, (addr_t)x86_64_sysenter32_entry);
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H A D | errata.cpp | 59 x86_write_msr(0xc0011029, x86_read_msr(0xc0011029) | 1); 72 x86_write_msr(0xc0011020, x86_read_msr(0xc0011020) | ((uint64)1 << 15)); 83 x86_write_msr(0xc0011029, x86_read_msr(0xc0011029) | (1 << 13)); 89 x86_write_msr(0xc0011020, x86_read_msr(0xc0011020) | (1 << 4)); 99 x86_write_msr(0xc0011028, x86_read_msr(0xc0011028) | (1 << 4)); 114 x86_write_msr(0xc0011020, x86_read_msr(0xc0011020) | ((uint64)1 << 57)); 121 x86_write_msr(MSR_F10H_DE_CFG, x86_read_msr(MSR_F10H_DE_CFG) | (1 << 9));
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H A D | thread.cpp | 102 x86_write_msr(IA32_MSR_FS_BASE, thread->user_local_storage); 103 x86_write_msr(IA32_MSR_KERNEL_GS_BASE, thread->arch_info.user_gs_base); 161 x86_write_msr(IA32_MSR_KERNEL_GS_BASE, base);
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/haiku/src/system/kernel/arch/x86/32/ |
H A D | syscalls.cpp | 55 x86_write_msr(IA32_MSR_SYSENTER_ESP, stackTop); 62 x86_write_msr(IA32_MSR_SYSENTER_CS, KERNEL_CODE_SELECTOR); 63 x86_write_msr(IA32_MSR_SYSENTER_ESP, 0); 64 x86_write_msr(IA32_MSR_SYSENTER_EIP, (addr_t)x86_sysenter);
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H A D | arch.S | 87 /* void x86_write_msr(uint32 register, uint64 value); */ 88 FUNCTION(x86_write_msr): 94 FUNCTION_END(x86_write_msr)
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/haiku/src/system/kernel/arch/x86/ |
H A D | apic.cpp | 90 x86_write_msr(IA32_MSR_APIC_TASK_PRIORITY, config); 100 x86_write_msr(IA32_MSR_APIC_EOI, 0); 121 x86_write_msr(IA32_MSR_APIC_LVT_LINT0, APIC_LVT_MASKED); 122 x86_write_msr(IA32_MSR_APIC_LVT_LINT1, APIC_LVT_MASKED); 144 x86_write_msr(IA32_MSR_APIC_SPURIOUS_INTR_VECTOR, config); 158 x86_write_msr(IA32_MSR_APIC_INTR_COMMAND, command); 197 x86_write_msr(IA32_MSR_APIC_LVT_TIMER, config); 217 x86_write_msr(IA32_MSR_APIC_LVT_ERROR, config); 237 x86_write_msr(IA32_MSR_APIC_INITIAL_TIMER_COUNT, config); 257 x86_write_msr(IA32_MSR_APIC_TIMER_DIVIDE_CONFI [all...] |
H A D | arch_cpu.cpp | 981 x86_write_msr(IA32_MSR_UCODE_REV, 0); 1103 x86_write_msr(IA32_MSR_UCODE_WRITE, data); 1222 x86_write_msr(MSR_K8_UCODE_UPDATE, data); 1529 x86_write_msr(IA32_MSR_TSC, 0); 1550 x86_write_msr(K8_MSR_IPM, msr & ~K8_CMPHALT); 1707 x86_write_msr(IA32_MSR_TSC_AUX, cpu); 1717 x86_write_msr(MSR_F10H_DE_CFG, value | DE_CFG_SERIALIZE_LFENCE);
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H A D | arch_debug.cpp | 1216 x86_write_msr(IA32_MSR_GS_BASE, (addr_t)&unsetThread);
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/haiku/headers/private/kernel/arch/x86/64/ |
H A D | cpu.h | 26 x86_write_msr(uint32_t msr, uint64_t value) function
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/haiku/src/add-ons/kernel/cpu/x86/ |
H A D | generic_x86.cpp | 87 x86_write_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + index, 0); 92 x86_write_msr(IA32_MSR_MTRR_PHYSICAL_BASE_0 + index, 94 x86_write_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + index, 98 x86_write_msr(IA32_MSR_MTRR_PHYSICAL_BASE_0 + index, 0); 144 x86_write_msr(IA32_MSR_MTRR_DEFAULT_TYPE, 189 x86_write_msr(IA32_MSR_MTRR_DEFAULT_TYPE, defaultType); 201 x86_write_msr(IA32_MSR_MTRR_DEFAULT_TYPE, defaultType | IA32_MTRR_ENABLE);
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/haiku/src/add-ons/kernel/power/cpufreq/intel_pstates/ |
H A D | intel_pstates.cpp | 106 x86_write_msr(IA32_MSR_PERF_CTL, pstate << 8); 190 x86_write_msr(IA32_MSR_HWP_INTERRUPT, 0); 191 x86_write_msr(IA32_MSR_PM_ENABLE, 1); 215 x86_write_msr(IA32_MSR_ENERGY_PERF_BIAS, perfBias); 219 x86_write_msr(IA32_MSR_HWP_REQUEST, hwpRequest 221 x86_write_msr(IA32_MSR_HWP_REQUEST_PKG, hwpRequest); 223 x86_write_msr(IA32_MSR_HWP_REQUEST, hwpRequest);
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/haiku/headers/private/kernel/arch/x86/ |
H A D | arch_thread.h | 50 x86_write_msr(IA32_MSR_GS_BASE, (addr_t)&t->arch_info);
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H A D | arch_cpu.h | 685 void x86_write_msr(uint32 registerNumber, uint64 value);
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/haiku/src/add-ons/kernel/power/cpufreq/amd_pstates/ |
H A D | amd_pstates.cpp | 69 x86_write_msr(MSR_AMD_CPPC_ENABLE, 1); 81 x86_write_msr(MSR_AMD_CPPC_REQ, request & 0xffffffff);
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/haiku/src/system/kernel/arch/x86/paging/64bit/ |
H A D | X86PagingMethod64Bit.cpp | 435 x86_write_msr(IA32_MSR_EFER, x86_read_msr(IA32_MSR_EFER)
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/haiku/src/system/kernel/arch/x86/paging/pae/ |
H A D | X86PagingMethodPAE.cpp | 183 x86_write_msr(IA32_MSR_EFER, x86_read_msr(IA32_MSR_EFER)
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