Searched refs:x86_read_msr (Results 1 - 13 of 13) sorted by relevance

/haiku/src/system/kernel/arch/x86/64/
H A Derrata.cpp45 const uint64 microcode = x86_read_msr(IA32_MSR_UCODE_REV);
59 x86_write_msr(0xc0011029, x86_read_msr(0xc0011029) | 1);
72 x86_write_msr(0xc0011020, x86_read_msr(0xc0011020) | ((uint64)1 << 15));
83 x86_write_msr(0xc0011029, x86_read_msr(0xc0011029) | (1 << 13));
89 x86_write_msr(0xc0011020, x86_read_msr(0xc0011020) | (1 << 4));
99 x86_write_msr(0xc0011028, x86_read_msr(0xc0011028) | (1 << 4));
114 x86_write_msr(0xc0011020, x86_read_msr(0xc0011020) | ((uint64)1 << 57));
121 x86_write_msr(MSR_F10H_DE_CFG, x86_read_msr(MSR_F10H_DE_CFG) | (1 << 9));
H A Dsyscalls.cpp54 x86_write_msr(IA32_MSR_EFER, x86_read_msr(IA32_MSR_EFER)
/haiku/src/system/kernel/arch/x86/
H A Dapic.cpp60 return x86_read_msr(IA32_MSR_APIC_ID);
70 return x86_read_msr(IA32_MSR_APIC_VERSION);
80 return x86_read_msr(IA32_MSR_APIC_TASK_PRIORITY);
110 return x86_read_msr(IA32_MSR_APIC_LOGICAL_DEST);
134 return x86_read_msr(IA32_MSR_APIC_SPURIOUS_INTR_VECTOR);
154 uint64 command = x86_read_msr(IA32_MSR_APIC_INTR_COMMAND);
187 return x86_read_msr(IA32_MSR_APIC_LVT_TIMER);
207 return x86_read_msr(IA32_MSR_APIC_LVT_ERROR);
227 return x86_read_msr(IA32_MSR_APIC_INITIAL_TIMER_COUNT);
247 return x86_read_msr(IA32_MSR_APIC_TIMER_DIVIDE_CONFI
[all...]
H A Darch_system_info.cpp163 uint64 mperf2 = x86_read_msr(IA32_MSR_MPERF);
164 uint64 aperf2 = x86_read_msr(IA32_MSR_APERF);
H A Darch_cpu.cpp985 uint64 value = x86_read_msr(IA32_MSR_UCODE_REV);
998 uint64 value = x86_read_msr(IA32_MSR_UCODE_REV);
1011 uint64 platformBits = (x86_read_msr(IA32_MSR_PLATFORM_ID) >> 50) & 0x7;
1548 uint64 msr = x86_read_msr(K8_MSR_IPM);
1621 uint64 value = x86_read_msr(MSR_F10H_HWCR);
1625 value = x86_read_msr(MSR_F10H_PSTATEDEF(0));
1715 uint64 value = x86_read_msr(MSR_F10H_DE_CFG);
1723 gCPU[cpu].arch.mperf_prev = x86_read_msr(IA32_MSR_MPERF);
1724 gCPU[cpu].arch.aperf_prev = x86_read_msr(IA32_MSR_APERF);
/haiku/headers/private/kernel/arch/x86/64/
H A Dcpu.h17 x86_read_msr(uint32_t msr) function
/haiku/src/add-ons/kernel/power/cpufreq/intel_pstates/
H A Dintel_pstates.cpp78 uint64 mperf = x86_read_msr(IA32_MSR_MPERF);
79 uint64 aperf = x86_read_msr(IA32_MSR_APERF);
192 uint64 hwpRequest = x86_read_msr(IA32_MSR_HWP_REQUEST);
193 uint64 caps = x86_read_msr(IA32_MSR_HWP_CAPABILITIES);
212 uint64 perfBias = x86_read_msr(IA32_MSR_ENERGY_PERF_BIAS);
246 uint64 platformInfo = x86_read_msr(IA32_MSR_PLATFORM_INFO);
253 = max_c(x86_read_msr(IA32_MSR_TURBO_RATIO_LIMIT) & 0xff, sMaxPState);
/haiku/src/add-ons/kernel/power/cpufreq/amd_pstates/
H A Damd_pstates.cpp71 uint64 cap1 = x86_read_msr(MSR_AMD_CPPC_CAP1);
98 x86_read_msr(MSR_AMD_CPPC_CAP1));
/haiku/src/add-ons/kernel/cpu/x86/
H A Dgeneric_x86.cpp113 mtrr_capabilities capabilities(x86_read_msr(IA32_MSR_MTRR_CAPABILITIES));
134 uint64 defaultType = x86_read_msr(IA32_MSR_MTRR_DEFAULT_TYPE);
161 uint64 mask = x86_read_msr(IA32_MSR_MTRR_PHYSICAL_MASK_0 + index * 2);
165 uint64 base = x86_read_msr(IA32_MSR_MTRR_PHYSICAL_BASE_0 + index * 2);
187 uint64 defaultType = x86_read_msr(IA32_MSR_MTRR_DEFAULT_TYPE)
238 uint64 defaultType = x86_read_msr(IA32_MSR_MTRR_DEFAULT_TYPE);
/haiku/src/system/kernel/arch/x86/32/
H A Darch.S80 /* uint64 x86_read_msr(uint32 register); */
81 FUNCTION(x86_read_msr):
85 FUNCTION_END(x86_read_msr)
/haiku/src/system/kernel/arch/x86/paging/64bit/
H A DX86PagingMethod64Bit.cpp435 x86_write_msr(IA32_MSR_EFER, x86_read_msr(IA32_MSR_EFER)
/haiku/headers/private/kernel/arch/x86/
H A Darch_cpu.h684 uint64 x86_read_msr(uint32 registerNumber);
/haiku/src/system/kernel/arch/x86/paging/pae/
H A DX86PagingMethodPAE.cpp183 x86_write_msr(IA32_MSR_EFER, x86_read_msr(IA32_MSR_EFER)

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