Searched refs:reg_read32 (Results 1 - 3 of 3) sorted by relevance

/haiku/src/add-ons/kernel/drivers/dvb/cx23882/
H A Dcx23882_i2c.c38 reg_read32(REG_I2C_CONTROL); // PCI bridge flush
51 reg_read32(REG_I2C_CONTROL); // PCI bridge flush
59 return (reg_read32(REG_I2C_CONTROL) & I2C_SCL) >> 1; // I2C_SCL is 0x02
67 return reg_read32(REG_I2C_CONTROL) & I2C_SDA; // I2C_SDA is 0x01
75 device->i2c_reg = reg_read32(REG_I2C_CONTROL);
79 reg_read32(REG_I2C_CONTROL); // PCI bridge flush
H A Dcx23882.c141 reg_write32(REG_TS_GEN_CONTROL, reg_read32(REG_TS_GEN_CONTROL) | TS_GEN_CONTROL_IPB_SMODE);
147 reg_write32(REG_TS_SOP_STATUS, reg_read32(REG_TS_SOP_STATUS) | 0x18000);
148 reg_write32(REG_TS_SOP_STATUS, reg_read32(REG_TS_SOP_STATUS) & ~0x06000);
151 reg_write32(REG_PCI_INT_MSK, reg_read32(REG_PCI_INT_MSK) | PCI_INT_STAT_TS_INT | 0x00fc00);
152 reg_write32(REG_TS_INT_MSK, reg_read32(REG_TS_INT_MSK) | TS_INT_STAT_TS_RISC1 | TS_INT_STAT_TS_RISC2 | 0x1f1100);
175 reg_write32(REG_DEV_CNTRL2, reg_read32(REG_DEV_CNTRL2) | DEV_CNTRL2_RUN_RISC);
176 reg_write32(REG_TS_DMA_CNTRL, reg_read32(REG_TS_DMA_CNTRL) | TS_DMA_CNTRL_TS_FIFO_EN | TS_DMA_CNTRL_TS_RISC_EN);
187 reg_write32(REG_TS_DMA_CNTRL, reg_read32(REG_TS_DMA_CNTRL) & ~(TS_DMA_CNTRL_TS_FIFO_EN | TS_DMA_CNTRL_TS_RISC_EN));
188 reg_write32(REG_DEV_CNTRL2, reg_read32(REG_DEV_CNTRL2) & ~DEV_CNTRL2_RUN_RISC);
196 uint32 mstat = reg_read32(REG_TS_INT_MSTA
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H A Dcx23882.h57 #define reg_read32(offset) (*(volatile uint32 *)((char *)(device->regs) + (offset))) macro

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