Searched refs:read32 (Results 1 - 25 of 36) sorted by relevance

12

/haiku/src/add-ons/accelerants/intel_extreme/
H A DFlexibleDisplayInterface.cpp62 uint32 value = read32(targetRegister);
65 read32(targetRegister);
75 uint32 value = read32(targetRegister);
78 read32(targetRegister);
87 return (read32(FDI_TX_CTL(fPipeIndex)) & FDI_TX_PLL_ENABLED) != 0;
96 uint32 value = read32(targetRegister);
108 read32(targetRegister);
111 read32(targetRegister);
126 write32(targetRegister, read32(targetRegister) & ~FDI_TX_PLL_ENABLED);
127 read32(targetRegiste
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H A Ddpms.cpp41 read32(INTEL_DISPLAY_A_BASE);
56 uint32 control = read32(controlRegister);
67 panelStatus = read32(statusRegister);
79 panelStatus = read32(statusRegister);
92 uint32 pll = read32(INTEL_DISPLAY_A_PLL);
96 read32(INTEL_DISPLAY_A_PLL);
99 read32(INTEL_DISPLAY_A_PLL);
102 read32(INTEL_DISPLAY_A_PLL);
106 pll = read32(INTEL_DISPLAY_B_PLL);
110 read32(INTEL_DISPLAY_B_PL
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H A DPanelFitter.cpp51 uint32 fitCtl = read32(fRegisterBase + PCH_PANEL_FITTER_CONTROL);
75 return (read32(fRegisterBase + PCH_PANEL_FITTER_CONTROL)
87 TRACE("%s: PCH_PANEL_FITTER_CONTROL, 0x%" B_PRIx32 "\n", __func__, read32(fRegisterBase + PCH_PANEL_FITTER_CONTROL));
88 TRACE("%s: PCH_PANEL_FITTER_WINDOW_POS, 0x%" B_PRIx32 "\n", __func__, read32(fRegisterBase + PCH_PANEL_FITTER_WINDOW_POS));
109 write32(targetRegister, (read32(targetRegister) & ~PANEL_FITTER_ENABLED)
111 read32(targetRegister);
H A DPipes.cpp42 write32(INTEL_DISPLAY_A_CONTROL, (read32(INTEL_DISPLAY_A_CONTROL)
45 write32(INTEL_DISPLAY_B_CONTROL, (read32(INTEL_DISPLAY_B_CONTROL)
49 write32(INTEL_DISPLAY_A_CONTROL, (read32(INTEL_DISPLAY_A_CONTROL)
52 write32(INTEL_DISPLAY_B_CONTROL, (read32(INTEL_DISPLAY_B_CONTROL)
124 return (read32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset)
132 uint32 pipeControl = read32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset);
148 read32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset);
154 write32(pipeReg, read32(pipeReg) | INTEL_PIPE_ENABLED);
199 read32(DDI_SKL_TRANS_CONF_A + fPipeOffset));
201 read32(PIPE_DDI_FUNC_CTL_
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H A DPorts.cpp50 if ((read32(address) & mask) != 0)
64 if ((read32(address) & mask) == 0)
79 status = read32(address);
166 uint32 portState = read32(portRegister);
200 read32(portRegister);
310 uint32 portState = read32(_PortRegister());
331 pipeState = read32(PIPE_DDI_FUNC_CTL_A);
334 pipeState = read32(PIPE_DDI_FUNC_CTL_B);
337 pipeState = read32(PIPE_DDI_FUNC_CTL_C);
340 pipeState = read32(PIPE_DDI_FUNC_CTL_ED
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H A Daccelerant.cpp68 // i, read32(i), read32(i + 4), read32(i + 8), read32(i + 12));
69 data = read32(i);
254 TRACE("adpa: %08" B_PRIx32 "\n", read32(INTEL_ANALOG_PORT));
256 ", dovc: %08" B_PRIx32 "\n", read32(INTEL_DIGITAL_PORT_A),
257 read32(INTEL_DIGITAL_PORT_B), read32(INTEL_DIGITAL_PORT_C));
258 TRACE("lvds: %08" B_PRIx32 "\n", read32(INTEL_DIGITAL_LVDS_POR
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H A Doverlay.cpp251 __func__, read32(INTEL_OVERLAY_UPDATE),
252 read32(INTEL_OVERLAY_TEST), read32(INTEL_OVERLAY_STATUS),
253 *(((uint32*)gInfo->overlay_registers) + 0x68/4), read32(0x30168),
254 read32(0x2024));
273 __func__, read32(INTEL_OVERLAY_UPDATE),
274 read32(INTEL_OVERLAY_TEST), read32(INTEL_OVERLAY_STATUS),
276 read32(0x30168), read32(
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H A Daccelerant.h85 read32(uint32 encodedRegister) function
/haiku/src/add-ons/kernel/drivers/graphics/radeon_hd/
H A Dsensors.cpp30 rawTemp = (read32(info.registers + SI_CG_MULT_THERMAL_STATUS)
40 uint32 offset = (read32(info.registers + EVERGREEN_CG_THERMAL_CTRL)
42 rawTemp = (read32(info.registers + EVERGREEN_CG_TS0_STATUS)
53 uint32 rawTemp = read32(info.registers + EVERGREEN_CG_THERMAL_STATUS)
59 rawTemp = (read32(info.registers + EVERGREEN_CG_MULT_THERMAL_STATUS)
74 rawTemp = (read32(info.registers + R700_CG_MULT_THERMAL_STATUS)
88 rawTemp = (read32(info.registers + R600_CG_THERMAL_STATUS)
H A Dradeon_hd.cpp328 uint32 bus_cntl = read32(info.registers + R600_BUS_CNTL);
329 uint32 d1vga_control = read32(info.registers + AVIVO_D1VGA_CONTROL);
330 uint32 d2vga_control = read32(info.registers + AVIVO_D2VGA_CONTROL);
332 = read32(info.registers + AVIVO_VGA_RENDER_CONTROL);
333 uint32 rom_cntl = read32(info.registers + R600_ROM_CNTL);
396 uint32 viph_control = read32(info.registers + RADEON_VIPH_CONTROL);
397 uint32 bus_cntl = read32(info.registers + R600_BUS_CNTL);
398 uint32 d1vga_control = read32(info.registers + AVIVO_D1VGA_CONTROL);
399 uint32 d2vga_control = read32(info.registers + AVIVO_D2VGA_CONTROL);
401 = read32(inf
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H A Ddriver.h27 #define read32(address) (*((volatile uint32*)(address))) macro
H A Ddevice.cpp84 uint32 oldValue = read32(info.registers + reg);
91 value = read32(info.registers + reg);
/haiku/src/add-ons/kernel/drivers/graphics/intel_extreme/
H A Ddevice.cpp85 uint32 oldValue = read32(info, reg);
93 value = read32(info, reg);
122 value = read32(info, INTEL_DISPLAY_A_HTOTAL + pipeOffset);
125 value = read32(info, INTEL_DISPLAY_A_HBLANK + pipeOffset);
128 value = read32(info, INTEL_DISPLAY_A_HSYNC + pipeOffset);
131 value = read32(info, INTEL_DISPLAY_A_VTOTAL + pipeOffset);
134 value = read32(info, INTEL_DISPLAY_A_VBLANK + pipeOffset);
137 value = read32(info, INTEL_DISPLAY_A_VSYNC + pipeOffset);
140 value = read32(info, INTEL_DISPLAY_A_PIPE_SIZE + pipeOffset);
147 value = read32(inf
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H A Dintel_extreme.cpp107 return enable ? 0 : read32(info, GEN11_GFX_MSTR_IRQ);
115 return enable ? 0 : read32(info, PCH_MASTER_INT_CTL_BDW);
129 uint32 identity = read32(info, regIdentity);
140 uint32 identity = read32(info, regIdentity);
151 uint32 identity = read32(info, regIdentity);
162 uint32 iir = read32(info, GEN8_DE_PORT_IIR);
171 uint32 iir = read32(info, GEN11_DE_HPD_IIR);
181 uint32 iir = read32(info, SDEIIR);
186 uint32 ddiHotplug = read32(info, SHOTPLUG_CTL_DDI);
190 uint32 tcHotplug = read32(inf
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H A Ddriver.h53 read32(intel_info &info, uint32 encodedRegister) function
H A Dpower.cpp99 uint32 rpStateCapacity = read32(info, INTEL6_RP_STATE_CAP);
100 uint32 gtPerfStatus = read32(info, INTEL6_GT_PERF_STATUS);
148 // TODO: wait for (read32(INTEL6_PCODE_MAILBOX) & INTEL6_PCODE_READY)
152 // TODO: wait for (read32(INTEL6_PCODE_MAILBOX) & INTEL6_PCODE_READY)
/haiku/src/add-ons/kernel/file_systems/fat/
H A Dutil.h37 #define read32(buffer,off) \
45 #define read32(buffer,off) \ macro
/haiku/src/add-ons/kernel/drivers/network/ether/wb840/
H A Ddevice.h21 # define read32(address) ((*gPci->read_io_32)(address)) macro
25 # define read32(address) (*((volatile uint32*)(address))) macro
H A Dinterface.c47 read32(device->reg_base + WB_SIO) | x)
51 read32(device->reg_base + WB_SIO) & ~x)
53 #define MII_DELAY(x) read32(x->reg_base + WB_SIO)
136 ack = read32(device->reg_base + WB_SIO) & WB_SIO_MII_DATAOUT;
162 if (read32(device->reg_base + WB_SIO) & WB_SIO_MII_DATAOUT)
257 #define EEPROM_DELAY(x) read32(x->reg_base + WB_SIO)
339 if (read32(device->reg_base + WB_SIO) & WB_SIO_EE_DATAOUT)
/haiku/src/add-ons/kernel/busses/i2c/pch/
H A Dpch_i2c.cpp31 if ((read32(bus->registers + PCH_IC_ENABLE_STATUS) & 1) == status)
46 uint32 enable = read32(bus->registers + PCH_IC_ENABLE);
50 uint32 status = read32(bus->registers + PCH_IC_INTR_STAT);
118 status = read32(bus->registers + PCH_IC_STATUS);
133 read32(bus->registers + PCH_IC_CON) & ~PCH_IC_CON_10BIT_ADDR_MASTER);
137 read32(bus->registers + PCH_IC_CLR_INTR);
141 read32(bus->registers + PCH_IC_CLR_INTR);
150 - read32(bus->registers + PCH_IC_TXFLR);
170 - read32(bus->registers + PCH_IC_TXFLR);
206 uint32 rxBytes = read32(bu
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H A Dpch_i2c.h38 #define read32(address) \ macro
/haiku/src/system/boot/loader/file_systems/fat/
H A Dfatfs.h24 #define read32(buffer,off) \ macro
H A DVolume.cpp122 fSectorsPerFat = read32(buf,0x24);
123 fTotalSectors = read32(buf,0x20);
128 fRootDirCluster = read32(buf,0x2c);
235 next = read32(buf, offset);
292 uint32 value = read32(buffer, offset & blockOffsetMask);
386 int32 freeClusters = read32(buffer, 0x1e8);
/haiku/src/add-ons/kernel/busses/random/ccp/
H A Dccp.h34 #define read32(address) \ macro
H A Dccp.cpp33 uint32 lowValue = read32(bus->registers + CCP_REG_TRNG);
34 uint32 highValue = read32(bus->registers + CCP_REG_TRNG);

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