Searched refs:ps (Results 1 - 25 of 108) sorted by relevance

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/haiku/src/add-ons/accelerants/neomagic/engine/
H A Dnm_info.c13 si->ps.f_ref = 14.31818;
14 si->ps.max_system_vco = 65;
15 si->ps.min_system_vco = 11;
16 si->ps.max_pixel_vco = 65;
17 si->ps.min_pixel_vco = 11;
18 si->ps.max_dac1_clock = 65;
19 si->ps.max_dac1_clock_8 = 65;
20 si->ps.max_dac1_clock_16 = 65;
22 si->ps.max_dac1_clock_24 = 0;
23 si->ps
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/haiku/src/add-ons/accelerants/matrox/engine/
H A Dmga_info.c23 si->ps.pins_status = B_ERROR;
63 /* fill out the si->ps struct if possible */
91 /* fill out the si->ps struct */
107 si->ps.pins_status = B_OK;
122 si->ps.f_ref = 0;
124 si->ps.max_system_vco = 0;
125 si->ps.min_system_vco = 0;
126 si->ps.min_pixel_vco = 0;
127 si->ps.min_video_vco = 0;
128 si->ps
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/haiku/src/system/libroot/posix/wchar/
H A Dmbsinit.c10 __mbsinit(const mbstate_t* ps) argument
12 return ps == NULL || ps->count == 0;
H A Dmbrlen.c10 __mbrlen(const char* s, size_t n, mbstate_t* ps) argument
12 if (ps == NULL) {
14 ps = &internalMbState;
17 return __mbrtowc(NULL, s, n, ps);
H A Dmbsrtowcs.cpp29 mbstate_t* ps)
36 if (ps == NULL) {
38 ps = &internalMbState;
60 memset(ps, 0, sizeof(mbstate_t));
75 memset(ps, 0, sizeof(mbstate_t));
89 ps, result);
111 __mbsrtowcs(wchar_t* dst, const char** src, size_t len, mbstate_t* ps) argument
113 if (ps == NULL) {
115 ps = &internalMbState;
121 return __mbsnrtowcs(dst, src, srcLen, len, ps);
28 __mbsnrtowcs(wchar_t* dst, const char** src, size_t nmc, size_t len, mbstate_t* ps) argument
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H A Dwcsrtombs.cpp30 mbstate_t* ps)
37 if (ps == NULL) {
39 ps = &internalMbState;
61 memset(ps, 0, sizeof(mbstate_t));
76 memset(ps, 0, sizeof(mbstate_t));
90 ps, result);
112 __wcsrtombs(char* dst, const wchar_t** src, size_t len, mbstate_t* ps) argument
114 if (ps == NULL) {
116 ps = &internalMbState;
119 return __wcsnrtombs(dst, src, __wcslen(*src) + 1, len, ps);
29 __wcsnrtombs(char* dst, const wchar_t** src, size_t nwc, size_t len, mbstate_t* ps) argument
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H A Dmbrtowc.cpp28 __mbrtowc(wchar_t* pwc, const char* s, size_t n, mbstate_t* ps) argument
30 if (ps == NULL) {
32 ps = &internalMbState;
36 return __mbrtowc(NULL, "", 1, ps);
44 memset(ps, 0, sizeof(mbstate_t));
71 status_t status = backend->MultibyteToWchar(pwc, s, n, ps, lengthUsed);
/haiku/src/add-ons/accelerants/via/engine/
H A Dinfo.c31 si->ps.pins_status = B_ERROR;
54 si->ps.pins_status = B_OK;
81 switch (si->ps.card_arch)
91 switch (si->ps.card_arch)
115 si->ps.memory_size = si->settings.memory * 1024 * 1024;
119 si->ps.tvout = false;
120 si->ps.tvout_chip_type = NONE;
124 si->ps.tvout = true;
125 si->ps.tvout_chip_bus = ???;
126 si->ps
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H A Ddac2.c157 if (si->ps.tmds2_active && !si->settings.pgm_panel)
166 if (si->ps.tmds2_active)
171 target.timing.pixel_clock = si->ps.p2_timing.pixel_clock;
192 if (si->ps.ext_pll) DAC2W(PIXPLLC2, 0x80000401);
221 switch (si->ps.card_type) {
239 /* switch(si->ps.card_type)
261 max_pclk = si->ps.max_dac2_clock_8;
265 max_pclk = si->ps.max_dac2_clock_16;
268 max_pclk = si->ps.max_dac2_clock_24;
271 max_pclk = si->ps
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/haiku/src/add-ons/accelerants/nvidia/
H A DGetDeviceInfo.c21 adi->memory = si->ps.memory_size;
22 adi->dac_speed = si->ps.max_dac1_clock;
32 if (!si->ps.crtc1_screen.have_full_edid && !si->ps.crtc2_screen.have_full_edid) {
44 if (si->ps.crtc1_screen.have_full_edid && si->ps.crtc2_screen.have_full_edid) {
48 if (si->ps.crtc1_screen.aspect < (si->ps.crtc2_screen.aspect - 0.10)) {
49 memcpy(info, &si->ps.crtc1_screen.full_edid, sizeof(struct edid1_info));
51 if (si->ps
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H A DGetModeInfo.c54 switch (si->ps.card_type)
57 *low = ((si->ps.min_video_vco * 1000) / 16);
65 max_pclk = si->ps.max_dac2_clock_8;
69 max_pclk = si->ps.max_dac2_clock_16;
72 max_pclk = si->ps.max_dac2_clock_24;
76 max_pclk = si->ps.max_dac2_clock_32dh;
80 max_pclk = si->ps.max_dac2_clock_32dh;
90 switch (si->ps.card_type)
93 *low = ((si->ps.min_pixel_vco * 1000) / 16);
97 if (!si->ps
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/haiku/src/add-ons/accelerants/skeleton/
H A DGetModeInfo.c54 switch (si->ps.card_type)
57 *low = ((si->ps.min_video_vco * 1000) / 16);
65 max_pclk = si->ps.max_dac2_clock_8;
69 max_pclk = si->ps.max_dac2_clock_16;
72 max_pclk = si->ps.max_dac2_clock_24;
76 max_pclk = si->ps.max_dac2_clock_32dh;
80 max_pclk = si->ps.max_dac2_clock_32dh;
90 switch (si->ps.card_type)
93 *low = ((si->ps.min_pixel_vco * 1000) / 16);
97 if (!si->ps
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/haiku/src/add-ons/accelerants/via/
H A DGetModeInfo.c54 switch (si->ps.card_type)
57 *low = ((si->ps.min_video_vco * 1000) / 16);
65 max_pclk = si->ps.max_dac2_clock_8;
69 max_pclk = si->ps.max_dac2_clock_16;
72 max_pclk = si->ps.max_dac2_clock_24;
76 max_pclk = si->ps.max_dac2_clock_32dh;
80 max_pclk = si->ps.max_dac2_clock_32dh;
90 switch (si->ps.card_type)
93 *low = ((si->ps.min_pixel_vco * 1000) / 16);
97 if (!si->ps
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H A DGetDeviceInfo.c19 switch (si->ps.card_type)
41 adi->memory = si->ps.memory_size;
42 adi->dac_speed = si->ps.max_dac1_clock;
/haiku/src/add-ons/accelerants/matrox/
H A DGetModeInfo.c57 switch (si->ps.card_type)
61 *low = ((si->ps.min_video_vco * 1000) / 16);
64 *low = ((si->ps.min_video_vco * 1000) / 8);
71 max_pclk = si->ps.max_dac2_clock_8;
75 max_pclk = si->ps.max_dac2_clock_16;
78 max_pclk = si->ps.max_dac2_clock_24;
82 max_pclk = si->ps.max_dac2_clock_32dh;
86 max_pclk = si->ps.max_dac2_clock_32dh;
96 switch (si->ps.card_type)
100 *low = ((si->ps
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H A DGetDeviceInfo.c21 adi->memory = (si->ps.memory_size * 1024 * 1024);
22 adi->dac_speed = si->ps.max_dac1_clock;
/haiku/src/add-ons/accelerants/nvidia/engine/
H A Dnv_general.c19 #define DUMP_CFG(reg, type) if (si->ps.card_type >= type) do { \
98 if (si->ps.int_assigned)
104 si->ps.laptop = false;
114 si->ps.card_type = NV04;
115 si->ps.card_arch = NV04A;
124 si->ps.card_type = NV05;
125 si->ps.card_arch = NV04A;
131 si->ps.card_type = NV05;
132 si->ps.card_arch = NV04A;
138 si->ps
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H A Dnv_info.c59 si->ps.pins_status = B_ERROR;
106 /* update the si->ps struct as far as is possible and coldstart card */
131 si->ps.pins_status = B_OK;
199 si->ps.min_system_vco = fvco_min / 1000;
200 si->ps.max_system_vco = fvco_max / 1000;
202 //si->ps.min_pixel_vco = fvco_min / 1000;
203 //si->ps.max_pixel_vco = fvco_max / 1000;
204 //si->ps.min_video_vco = fvco_min / 1000;
205 //si->ps.max_video_vco = fvco_max / 1000;
268 if (si->ps
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H A Dnv_dac2.c20 switch(si->ps.card_type) {
165 if (si->ps.monitors & CRTC2_TMDS)
170 target.timing.pixel_clock = si->ps.p2_timing.pixel_clock;
192 if (si->ps.card_arch >= NV30A)
200 if ((si->ps.monitors & CRTC2_TMDS) && !si->settings.pgm_panel) {
209 if (si->ps.ext_pll) DAC2W(PIXPLLC2, 0x80000401);
221 if (si->ps.card_arch < NV40A) {
246 if (si->ps.ext_pll) {
259 f_phase = si->ps.f_ref / (m1 * m2);
277 switch (si->ps
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H A Dnv_dac.c27 if (si->ps.secondary_head)
110 if ((si->ps.card_type != NV11) && !si->ps.secondary_head) return B_ERROR;
115 if (si->ps.card_type == NV11) {
135 if (si->ps.card_type == NV11) {
200 if (si->ps.monitors & CRTC1_TMDS)
205 target.timing.pixel_clock = si->ps.p1_timing.pixel_clock;
227 if (si->ps.card_arch >= NV30A)
235 if ((si->ps.monitors & CRTC1_TMDS) && !si->settings.pgm_panel) {
244 if (si->ps
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/haiku/src/add-ons/accelerants/skeleton/engine/
H A Dinfo.c59 si->ps.pins_status = B_ERROR;
106 /* update the si->ps struct as far as is possible and coldstart card */
131 si->ps.pins_status = B_OK;
187 si->ps.min_system_vco = fvco_min / 1000;
188 si->ps.max_system_vco = fvco_max / 1000;
190 //si->ps.min_pixel_vco = fvco_min / 1000;
191 //si->ps.max_pixel_vco = fvco_max / 1000;
192 //si->ps.min_video_vco = fvco_min / 1000;
193 //si->ps.max_video_vco = fvco_max / 1000;
256 if (si->ps
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H A Ddac2.c157 if (si->ps.tmds2_active && !si->settings.pgm_panel)
166 if (si->ps.tmds2_active)
171 target.timing.pixel_clock = si->ps.p2_timing.pixel_clock;
192 if (si->ps.ext_pll) DAC2W(PIXPLLC2, 0x80000401);
221 switch (si->ps.card_type) {
239 /* switch(si->ps.card_type)
261 max_pclk = si->ps.max_dac2_clock_8;
265 max_pclk = si->ps.max_dac2_clock_16;
268 max_pclk = si->ps.max_dac2_clock_24;
271 max_pclk = si->ps
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H A Ddac.c149 if (si->ps.tmds1_active && !si->settings.pgm_panel)
158 if (si->ps.tmds1_active)
163 target.timing.pixel_clock = si->ps.p1_timing.pixel_clock;
184 if (si->ps.ext_pll) DACW(PIXPLLC2, 0x80000401);
213 switch (si->ps.card_type) {
231 /* switch(si->ps.card_type)
253 max_pclk = si->ps.max_dac1_clock_8;
257 max_pclk = si->ps.max_dac1_clock_16;
260 max_pclk = si->ps.max_dac1_clock_24;
263 max_pclk = si->ps
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/haiku/src/add-ons/accelerants/neomagic/
H A DGetModeInfo.c49 switch (si->ps.card_type)
52 *low = (si->ps.min_pixel_vco * 1000);
59 max_pclk = si->ps.max_dac1_clock_8;
63 max_pclk = si->ps.max_dac1_clock_16;
66 max_pclk = si->ps.max_dac1_clock_24;
70 max_pclk = si->ps.max_dac1_clock_24;
89 if (si->ps.int_assigned)
H A DGetDeviceInfo.c21 adi->memory = (si->ps.memory_size * 1024);
22 adi->dac_speed = si->ps.max_dac1_clock;

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