Searched refs:fRegBase (Results 1 - 6 of 6) sorted by relevance

/haiku/src/system/kernel/arch/arm/
H A Dsoc_pxa.cpp15 fRegBase[PXA_ICMR] |= 1 << irq;
19 fRegBase[PXA_ICMR2] |= 1 << (irq - 32);
27 fRegBase[PXA_ICMR] &= ~(1 << irq);
31 fRegBase[PXA_ICMR2] &= ~(1 << (irq - 32));
39 if (fRegBase[PXA_ICIP] & (1 << i))
47 fRegArea = vm_map_physical_memory(B_SYSTEM_TEAM, "intc-pxa", (void**)&fRegBase,
53 fRegBase[PXA_ICMR] = 0;
54 fRegBase[PXA_ICMR2] = 0;
96 fRegBase[PXA_OIER] |= (1 << 4);
97 fRegBase[PXA_OMCR
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H A Dsoc_sun4i.cpp23 fRegBase[SUN4I_INTC_MASK_REG0] |= 1 << irq;
28 fRegBase[SUN4I_INTC_MASK_REG1] |= 1 << (irq - 32);
32 fRegBase[SUN4I_INTC_MASK_REG2] |= 1 << (irq - 64);
40 fRegBase[SUN4I_INTC_MASK_REG0] &= ~(1 << irq);
45 fRegBase[SUN4I_INTC_MASK_REG1] &= ~(1 << (irq - 32));
49 fRegBase[SUN4I_INTC_MASK_REG1] &= ~(1 << (irq - 64));
58 if (fRegBase[SUN4I_INTC_PEND_REG0] & (1 << i))
63 if (fRegBase[SUN4I_INTC_PEND_REG1] & (1 << i))
68 if (fRegBase[SUN4I_INTC_PEND_REG2] & (1 << i))
76 fRegArea = vm_map_physical_memory(B_SYSTEM_TEAM, "intc-sun4i", (void**)&fRegBase,
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H A Dsoc_omap3.cpp33 fRegBase[INTCPS_MIR_CLEARn + (8 * bank)] = 1 << bit;
41 fRegBase[INTCPS_MIR_SETn + (8 * bank)] = 1 << bit;
53 irqnr = fRegBase[INTCPS_PENDING_IRQn + (8 * i)];
61 irqnr = fRegBase[INTCPS_SIR_IRQ];
73 fRegBase[INTCPS_CONTROL] = 1;
80 uint32 tmp = fRegBase[INTCPS_REVISION] & 0xff;
83 fRegBase, tmp >> 4, tmp & 0xf);
85 tmp = fRegBase[INTCPS_SYSCONFIG];
87 fRegBase[INTCPS_SYSCONFIG] = tmp;
89 while (!(fRegBase[INTCPS_SYSSTATU
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H A Dsoc_sun4i.h22 uint32 *fRegBase; member in class:Sun4iInterruptController
H A Dsoc_pxa.h20 uint32 *fRegBase; member in class:PXAInterruptController
40 uint32 *fRegBase; member in class:PXATimer
H A Dsoc_omap3.h22 uint32 *fRegBase; member in class:OMAP3InterruptController
52 uint32 *fRegBase; member in class:OMAP3Timer

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