Searched refs:dwControlReg (Results 1 - 11 of 11) sorted by relevance
/haiku/src/add-ons/kernel/drivers/audio/echo/generic/ |
H A D | CGMLDspCommObject.cpp | 44 DWORD dwControlReg; local 46 dwControlReg = GetControlRegister(); 51 dwControlReg &= GML_SPDIF_FORMAT_CLEAR_MASK; 56 dwControlReg |= GML_SPDIF_TWO_CHANNEL | 64 dwControlReg |= GML_SPDIF_PRO_MODE; 69 dwControlReg |= GML_SPDIF_SAMPLE_RATE0 | 74 dwControlReg |= GML_SPDIF_SAMPLE_RATE0; 78 dwControlReg |= GML_SPDIF_SAMPLE_RATE1; 90 dwControlReg |= GML_SPDIF_SAMPLE_RATE0 | 95 dwControlReg | 131 DWORD dwControlReg; local 160 WriteControlReg( DWORD dwControlReg, BOOL fForceWrite ) argument 255 DWORD dwControlReg; local [all...] |
H A D | CGina24DspCommObject.cpp | 119 DWORD dwControlReg, dwSize; local 167 dwControlReg = GML_CONVERTER_ENABLE | GML_48KHZ; 168 WriteControlReg( dwControlReg, TRUE ); 186 DWORD dwControlReg; local 190 dwControlReg = GetControlRegister(); 195 dwControlReg &= GML_CLOCK_CLEAR_MASK; 219 dwControlReg |= GML_SPDIF_CLOCK; 223 dwControlReg |= GML_DOUBLE_SPEED_MODE; 227 dwControlReg &= ~GML_DOUBLE_SPEED_MODE; 241 dwControlReg | 304 DWORD dwControlReg, dwNewClock; local [all...] |
H A D | CIndigoDspCommObject.cpp | 110 DWORD dwControlReg = MIA_48000; local 115 dwControlReg = MIA_96000; 119 dwControlReg = MIA_88200; 123 dwControlReg = MIA_44100; 127 dwControlReg = MIA_32000; 134 if (dwControlReg != GetControlRegister()) 145 SetControlRegister( dwControlReg );
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H A D | C3gDco.cpp | 127 DWORD dwControlReg; local 164 dwControlReg = E3G_48KHZ; 165 WriteControlReg( dwControlReg, E3G_FREQ_REG_DEFAULT, TRUE); // TRUE == force write 184 DWORD dwControlReg,dwSampleRate; local 192 dwControlReg = GetControlRegister(); 193 dwControlReg &= E3G_CLOCK_CLEAR_MASK; 214 dwControlReg |= E3G_WORD_CLOCK; 218 dwControlReg |= E3G_DOUBLE_SPEED_MODE; 222 dwControlReg &= ~E3G_DOUBLE_SPEED_MODE; 234 dwControlReg | 289 DWORD dwControlReg,dwNewClock,dwBaseRate,dwFreqReg; local 406 DWORD dwControlReg; local 484 WriteControlReg( DWORD dwControlReg, DWORD dwFreqReg, BOOL fForceWrite ) argument 613 DWORD dwControlReg; local 634 DWORD dwControlReg; local 752 DWORD dwControlReg; local 909 DWORD dwControlReg; local [all...] |
H A D | CLayla24DspCommObject.cpp | 122 DWORD dwControlReg; local 174 dwControlReg = GML_CONVERTER_ENABLE | GML_48KHZ; 175 WriteControlReg( dwControlReg, TRUE ); 200 DWORD dwControlReg, dwNewClock, dwBaseRate; local 229 dwControlReg = GetControlRegister(); 230 dwControlReg &= GML_CLOCK_CLEAR_MASK; 231 dwControlReg &= GML_SPDIF_RATE_CLEAR_MASK; 258 if ( dwControlReg & GML_SPDIF_PRO_MODE ) 298 dwControlReg |= dwNewClock; 309 dwControlReg | 453 DWORD dwControlReg, dwSampleRate; local [all...] |
H A D | CMiaDspCommObject.cpp | 170 DWORD dwControlReg = MIA_48000; local 175 dwControlReg = MIA_96000; 179 dwControlReg = MIA_88200; 183 dwControlReg = MIA_44100; 187 dwControlReg = MIA_32000; 195 dwControlReg |= MIA_SPDIF; 200 if (dwControlReg != GetControlRegister()) 211 SetControlRegister( dwControlReg );
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H A D | CMonaDspCommObject.cpp | 118 DWORD dwControlReg; local 163 dwControlReg = GML_CONVERTER_ENABLE | GML_48KHZ; 165 dwControlReg)); 166 WriteControlReg( dwControlReg, TRUE ); 243 DWORD dwControlReg; local 247 dwControlReg = GetControlRegister(); 252 dwControlReg &= GML_CLOCK_CLEAR_MASK; 282 dwControlReg |= GML_SPDIF_CLOCK; 286 dwControlReg |= GML_DOUBLE_SPEED_MODE; 290 dwControlReg 374 DWORD dwAsicSize, dwControlReg, dwNewClock; local [all...] |
H A D | CGMLDspCommObject.h | 82 virtual ECHOSTATUS WriteControlReg( DWORD dwControlReg, BOOL fForceWrite = FALSE );
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H A D | C3gDco.h | 144 DWORD dwControlReg,
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H A D | CDspCommObject.h | 612 DWORD dwControlReg; // Mona, Gina24, Layla24 and 3G control 0xb80 4 member in struct:__anon1518 765 m_pDspCommPage->dwControlReg = SWAP( dwControlRegister ); } 920 return SWAP( m_pDspCommPage->dwControlReg ); }
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H A D | CDspCommObject.cpp | 848 ECHO_DEBUGPRINTF(("\tControl reg is 0x%lx\n",SWAP(m_pDspCommPage->dwControlReg) )); 2082 m_pDspCommPage->dwControlReg = 0;
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