Searched refs:bpp (Results 1 - 25 of 46) sorted by relevance

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/haiku/src/add-ons/accelerants/et6x00/
H A DSetDisplayMode.c32 uint8 bpp; local
45 bpp = 3;
51 bpp = 2;
56 si->fbc.bytes_per_row = target.virtual_width * bpp;
58 si->bytesPerPixel = bpp;
59 et6000aclInit(bpp);
H A DAcceleration.c43 * bpp must be bytes per pixel, not bits!
45 void et6000aclInit(uint8 bpp) { argument
51 set8(mmRegs+0x8e, 0xcf, (bpp - 1) << 4); /* set pixel color depth */
80 uint8 bpp = si->bytesPerPixel; local
92 *((vuint16 *)(mmRegs+0x8a)) = screenWidth * bpp - 1;
95 *((vuint16 *)(mmRegs+0x8c)) = screenWidth * bpp - 1;
114 *((vuint16 *)(mmRegs+0x98)) = (width + 1) * bpp - 1;
121 srcAddr = (src_top * screenWidth + src_left) * bpp;
122 destAddr = (dest_top * screenWidth + dest_left) * bpp;
126 srcAddr = (src_top * screenWidth + src_left + width) * bpp
170 uint8 bpp = si->bytesPerPixel; local
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H A Dgeneric.h40 void et6000aclInit(uint8 bpp);
/haiku/src/add-ons/accelerants/common/
H A Ddp.cpp63 dp_get_pixel_clock_max(int linkRate, int laneCount, int bpp) argument
65 return (linkRate * laneCount * 8) / bpp;
/haiku/headers/private/graphics/common/
H A Ddp.h47 uint32 dp_get_pixel_clock_max(int linkRate, int laneCount, int bpp);
/haiku/src/tests/kits/interface/flatten_picture/
H A DPictureTest.cpp263 int32 bpp, BString &reason)
269 memcpy(&color1, pixel1, bpp);
270 memcpy(&color2, pixel2, bpp);
304 int32 bpp = (int32)pixelChunk; local
313 for (int x = 0; x < width; x ++, pixel1 += bpp, pixel2 += bpp) {
314 if (memcmp(pixel1, pixel2, bpp) != 0) {
315 setMismatchReason(x, y, pixel1, pixel2, bpp, reason);
262 setMismatchReason(int32 x, int32 y, uint8 *pixel1, uint8 *pixel2, int32 bpp, BString &reason) argument
/haiku/src/add-ons/accelerants/radeon/
H A DSetDisplayMode.c44 int virtual_width, int bpp )
61 if( bpp != 3 )
62 return (virtual_width + 64/bpp - 1) & ~(64/bpp - 1);
113 int bpp; local
195 Radeon_GetFormat( mode->space, &format, &bpp );
197 vc->bpp = bpp;
431 int format, bpp; local
453 Radeon_GetFormat( mode.space, &format, &bpp );
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H A Doverlay_management.c77 uint ati_space, test_reg, bpp; local
84 bpp = 2;
90 bpp = 2;
96 bpp = 4;
102 bpp = 2;
113 bpp = 2;
138 buffer->bytes_per_row = (width * bpp + 0xf) & ~0xf;
H A Dradeon_accelerant.h79 uint32 Radeon_RoundVWidth( int virtual_width, int bpp );
95 bool Radeon_GetFormat( int space, int *format, int *bpp );
H A DProposeDisplayMode.c101 // bpp - (out) bytes per pixel
102 bool Radeon_GetFormat( int space, int *format, int *bpp )
106 case B_CMAP8: *format = 2; *bpp = 1; break;
107 case B_RGB15_LITTLE: *format = 3; *bpp = 2; break; /* 555 */
108 case B_RGB16_LITTLE: *format = 4; *bpp = 2; break; /* 565 */
109 case B_RGB24_LITTLE: *format = 5; *bpp = 3; break; /* RGB */
110 case B_RGB32_LITTLE: *format = 6; *bpp = 4; break; /* xRGB */
152 int format, bpp; local
173 if( !Radeon_GetFormat( target->space, &format, &bpp ))
380 eff_virtual_width = Radeon_RoundVWidth( target->virtual_height, bpp );
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/haiku/src/add-ons/accelerants/s3/
H A Dvirge_mode.cpp45 switch (mode.bpp) {
439 } else if (mode.bpp == 8) {
441 } else if (mode.bpp == 16) {
532 switch (mode.bpp) {
547 if (mode.bpp == 8) {
549 regRec.CR67 = 0x00; // 8bpp, 135MHz
551 regRec.CR67 = 0x10; // 8bpp, 220MHz
552 } else if (mode.bpp == 16) {
554 regRec.CR67 = 0x40; // 16bpp, 135MHz
556 regRec.CR67 = 0x50; // 16bpp, 22
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H A Dtrio64_mode.cpp114 switch (mode.bpp) {
176 InitCrtcTimingValues(mode, (mode.bpp > 8) ? 2 : 1, crtc, cr3b, cr3c, cr5d, cr5e);
218 int clock2 = mode.timing.pixel_clock * (mode.bpp / 8);
293 * (mode.bpp / 8)) >> 2) & ~1;
H A Dmode.cpp27 // is 16 bpp. The horizontal scale factor is used for this purpose.
334 if ( ! gInfo.GetColorSpaceParams(mode.space, mode.bpp, maxPixelClock))
354 int bytesPerPixel = (mode.bpp + 7) / 8;
359 if ( ! IsThereEnoughFBMemory(&mode, mode.bpp))
362 TRACE("Set display mode: %dx%d virtual size: %dx%d color depth: %d bpp\n",
364 mode.virtual_width, mode.virtual_height, mode.bpp);
449 uint32 bytesPerPixel = (si.displayMode.bpp + 7) / 8;
H A Dsavage_mode.cpp317 si.globalBitmapDesc = mode.timing.h_display | (mode.bpp << 16)
667 if (mode.bpp == 16 && si.chipType == S3_SAVAGE_3D)
677 switch (mode.bpp) {
680 regRec.CR67 = 0x10; // 8bpp, 2 pixels/clock
682 regRec.CR67 = 0x00; // 8bpp, 1 pixel/clock
688 regRec.CR67 = 0x30; // 15bpp, 2 pixel/clock
690 regRec.CR67 = 0x20; // 15bpp, 1 pixels/clock
696 regRec.CR67 = 0x50; // 16bpp, 2 pixel/clock
698 regRec.CR67 = 0x40; // 16bpp, 1 pixels/clock
733 if (mode.bpp <
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/haiku/src/add-ons/accelerants/matrox/engine/
H A Dtvp3026.c42 status_t mil2_dac_set_pix_pll (float f_need, int bpp) argument
52 LOG(4,("mil2_dac_set_pix_pll need %fMHz, %dbpp\n", f_need, bpp));
58 switch (bpp) {
79 // now compute parameters for the loop PLL (24bpp not available) see 2.4.3.1
82 // n = (65 - (4 * (PIXEL_BUS_WIDTH64? 64: 32)) / bpp);
83 n = (65 - (4 * 64) / bpp);
H A Dmga_proto.h61 status_t mil2_dac_set_pix_pll(float f_vco,int bpp);
89 status_t gx00_crtc_set_display_start(uint32 startadd,uint8 bpp);
104 status_t g400_crtc2_set_display_start(uint32 startadd,uint8 bpp);
/haiku/src/add-ons/translators/icns/
H A DICNSLoader.cpp193 int bpp = 32; local
224 iconInfo.iconBitDepth = bpp;
225 iconInfo.iconChannels = (bpp == 32 ? 4 : 1);
226 iconInfo.iconPixelDepth = bpp / iconInfo.iconChannels;
/haiku/src/add-ons/accelerants/matrox/
H A DProposeDisplayMode.c123 uint8 m,n,p, bpp; local
300 bpp = 1;
305 bpp = 2;
309 bpp = 3;
313 bpp = 4;
318 bpp = 4;
338 ((uint16)(row_bytes / bpp) >= (target->timing.h_display * 2)))
/haiku/src/add-ons/accelerants/skeleton/
H A DProposeDisplayMode.c115 uint8 m,n,p, bpp; local
417 bpp = 1;
422 bpp = 2;
426 bpp = 3;
430 bpp = 4;
435 bpp = 4;
449 ((uint16)(row_bytes / bpp) >= (target->timing.h_display * 2)))
/haiku/src/add-ons/accelerants/via/
H A DProposeDisplayMode.c117 uint8 m,n,p, bpp; local
419 bpp = 1;
424 bpp = 2;
428 bpp = 3;
432 bpp = 4;
437 bpp = 4;
451 ((uint16)(row_bytes / bpp) >= (target->timing.h_display * 2)))
/haiku/src/add-ons/accelerants/intel_810/
H A Daccelerant.h105 bool I810_GetColorSpaceParams(int colorSpace, uint8& bpp,
/haiku/src/add-ons/accelerants/nvidia/
H A DProposeDisplayMode.c231 uint8 m,n,p, bpp; local
467 bpp = 1;
472 bpp = 2;
476 bpp = 3;
480 bpp = 4;
485 bpp = 4;
497 && (uint16)(row_bytes / bpp) >= target->timing.h_display * 2)
/haiku/src/add-ons/kernel/drivers/graphics/et6x00/
H A Dsetmode.c32 uint16 width, height, bpp, refreshRate; member in struct:__anon1640
211 ioSet8(pciConfigSpace+0x58, 0xfd, 0x00); /* 16bpp is 5:5:5 */
213 ioSet8(pciConfigSpace+0x58, 0xfd, 0x02); /* 16bpp is 5:6:5 */
233 static void setATC(uint8 bpp) { argument
248 switch (bpp) {
332 (clock0MN[m].bpp == mi->BitsPerPlane) &&
389 uint8 m, bpp; local
401 bpp = 24;
407 bpp = 16;
419 (clock0MN[m].bpp
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/haiku/src/add-ons/screen_savers/ifs/
H A DIFS.cpp514 int32 bpp = info->bits_per_pixel; local
515 screenBits += left * bpp + top * bpr;
538 if (bpp == 32) {
542 } else if (bpp == 16) {
550 } else if (bpp == 15) {
558 } else if (bpp == 8) {
582 if (bpp == 32) {
586 } else if (bpp == 16) {
594 } else if (bpp == 15) {
602 } else if (bpp
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/haiku/src/add-ons/accelerants/neomagic/engine/
H A Dnm_proto.h42 status_t nm_crtc_set_display_start(uint32 startadd,uint8 bpp);

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