Searched refs:i8 (Results 1 - 25 of 57) sorted by relevance

123

/freebsd-10.1-release/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/aggs/
H A Dtst.signedkeyspos.d50 @i8["cat", (char)-2] = sum(-2);
51 @i8["dog", (char)-2] = sum(-22);
52 @i8["mouse", (char)-2] = sum(-222);
53 @i8["cat", (char)-1] = sum(-1);
54 @i8["dog", (char)-1] = sum(-11);
55 @i8["mouse", (char)-1] = sum(-111);
56 @i8["cat", (char)0] = sum(0);
57 @i8["dog", (char)0] = sum(10);
58 @i8["mouse", (char)0] = sum(100);
59 @i8["ca
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H A Dtst.signedkeys.d95 @i8[(char)-2] = sum(-2);
96 @i8[(char)-1] = sum(-1);
97 @i8[(char)0] = sum(0);
98 @i8[(char)1] = sum(1);
99 @i8[(char)2] = sum(2);
/freebsd-10.1-release/contrib/ofed/management/opensm/opensm/
H A Dosm_indent46 indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs "$@"
/freebsd-10.1-release/sys/i386/i386/
H A Dbpf_jit_machdep.h201 /* addl i8,r32 */
202 #define ADDib(i8, r32) do { \
205 emitm(&stream, i8, 1); \
221 /* subl i8,r32 */
222 #define SUBib(i8, r32) do { \
225 emitm(&stream, i8, 1); \
240 /* andb i8,r8 */
241 #define ANDib(i8, r8) do { \
248 emitm(&stream, i8, 1); \
305 /* shll i8,r3
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/freebsd-10.1-release/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp258 case MVT::i8:
287 case MVT::i8:
317 case MVT::i8:
340 case MVT::i8:
369 case MVT::i8:
392 case MVT::i8:
500 case MVT::i8:
524 case MVT::i8:
554 case MVT::i8:
578 case MVT::i8
[all...]
/freebsd-10.1-release/sys/amd64/amd64/
H A Dbpf_jit_machdep.h256 /* addl i8,r32 */
257 #define ADDib(i8, r32) do { \
260 emitm(&stream, i8, 1); \
276 /* subq i8,r64 */
277 #define SUBib(i8, r64) do { \
280 emitm(&stream, i8, 1); \
295 /* andb i8,r8 */
296 #define ANDib(i8, r8) do { \
303 emitm(&stream, i8, 1); \
360 /* shll i8,r3
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/freebsd-10.1-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp67 addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
83 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
93 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
95 setOperationAction(ISD::SRA, MVT::i8, Custom);
96 setOperationAction(ISD::SHL, MVT::i8, Custom);
97 setOperationAction(ISD::SRL, MVT::i8, Custom);
101 setOperationAction(ISD::ROTL, MVT::i8, Expand);
102 setOperationAction(ISD::ROTR, MVT::i8, Expand);
109 setOperationAction(ISD::BR_CC, MVT::i8, Custo
[all...]
H A DMSP430ISelLowering.h76 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
106 /// register R15W to i8 by referencing its sub-register R15B.
/freebsd-10.1-release/contrib/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp109 AVT = MVT::i8;
115 if (AVT.bitsGT(MVT::i8)) {
125 AVT = MVT::i8;
155 SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag };
213 AVT = MVT::i8;
H A DX86ISelDAGToDAG.cpp265 /// i8.
267 return CurDAG->getTargetConstant(Imm, MVT::i8);
789 SDValue Eight = DAG.getConstant(8, MVT::i8);
793 SDValue ShlCount = DAG.getConstant(ScaleLog, MVT::i8);
943 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8);
945 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8);
1799 case MVT::i8:
1944 LdVT != MVT::i8)
2008 if (LdVT == MVT::i8) return X86::DEC8m;
2014 if (LdVT == MVT::i8) retur
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H A DX86ISelLowering.cpp225 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
227 // X86 is weird, it always uses i8 for shift amounts and setcc results.
287 addRegisterClass(MVT::i8, &X86::GR8RegClass);
298 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
300 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
301 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
316 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
331 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
334 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
356 // Promote i1/i8 FP_TO_SIN
[all...]
H A DX86FastISel.cpp190 case MVT::i8:
255 // FALLTHROUGH, handling i1 as i8.
256 case MVT::i8: Opc = X86::MOV8mr; break;
308 case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8.
309 case MVT::i8: Opc = X86::MOV8mi; break;
841 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16)
852 SrcReg = FastEmitZExtFromI1(MVT::i8, SrcReg, /*TODO: Kill=*/false);
853 SrcVT = MVT::i8;
927 case MVT::i8: return X86::CMP8rr;
945 case MVT::i8
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H A DX86AsmPrinter.cpp247 ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
385 Reg = getX86SubSuperRegister(Reg, MVT::i8);
388 Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
/freebsd-10.1-release/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/typedef/
H A Dtst.TypedefDataAssign.d84 new_int8 i8;
/freebsd-10.1-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp276 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
455 case MVT::i8:
581 case MVT::i8:
751 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
770 case MVT::i8:
929 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 &&
951 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) {
1090 if (DestVT != MVT::i16 && DestVT != MVT::i8)
1314 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1338 } else if (RetVT == MVT::i8 || RetV
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/freebsd-10.1-release/contrib/llvm/include/llvm/CodeGen/
H A DValueTypes.h44 i8 = 2, // This is an 8 bit integer value enumerator in enum:llvm::MVT::SimpleValueType
70 v1i8 = 19, // 1 x i8
71 v2i8 = 20, // 2 x i8
72 v4i8 = 21, // 4 x i8
73 v8i8 = 22, // 8 x i8
74 v16i8 = 23, // 16 x i8
75 v32i8 = 24, // 32 x i8
76 v64i8 = 25, // 64 x i8
279 case v64i8: return i8;
377 case i8
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/freebsd-10.1-release/contrib/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp302 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
303 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 },
304 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 },
305 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 },
333 { ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 },
334 { ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 },
335 { ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 },
336 { ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 },
367 { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 },
H A DARMSelectionDAGInfo.cpp101 VT = MVT::i8;
124 VT = MVT::i8;
H A DARMFastISel.cpp604 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
835 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
951 case MVT::i8:
1057 case MVT::i8:
1188 case MVT::i8:
1468 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1503 case MVT::i8:
1531 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1649 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1656 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
[all...]
/freebsd-10.1-release/sys/contrib/octeon-sdk/
H A Dcvmx-fau.h322 uint64_t i8; member in union:__anon7078
325 result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value));
/freebsd-10.1-release/sys/cddl/contrib/opensolaris/uts/common/os/
H A Dfm.c229 uint8_t i8; local
252 (void) nvpair_value_byte(nvp, &i8);
253 c = fm_printf(d + 1, c, cols, "%x", i8);
257 (void) nvpair_value_int8(nvp, (void *)&i8);
258 c = fm_printf(d + 1, c, cols, "%x", i8);
262 (void) nvpair_value_uint8(nvp, &i8);
263 c = fm_printf(d + 1, c, cols, "%x", i8);
/freebsd-10.1-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp118 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
156 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
230 LocVT == MVT::i8 ||
621 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
869 if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
1160 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
1161 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
1162 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
1163 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
1301 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Lega
[all...]
H A DHexagonVarargsCallingConvention.h50 LocVT == MVT::i8 ||
/freebsd-10.1-release/contrib/llvm/include/llvm/Support/
H A DDataTypes.h.in136 # define INT8_C(C) C##i8
/freebsd-10.1-release/contrib/tcpdump/
H A Dprint-802_11.c1886 int8_t i8; member in union:__anon4467
1917 rc = cpack_int8(s, &u.i8);
1935 rc = cpack_int8(s, &u.i8);
2065 printf("%ddB signal ", u.i8);
2068 printf("%ddB noise ", u.i8);
2086 printf("%ddBm tx power ", u.i8);

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