/freebsd-10.1-release/contrib/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1134 unsigned Rm = fieldFromInstruction(Val, 0, 4); local 1139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1171 unsigned Rm = fieldFromInstruction(Val, 0, 4); local 1176 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1471 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 1533 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1575 unsigned Rm = fieldFromInstruction(Val, 0, 4); local 1601 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1620 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 1653 if (type && Rm 1839 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 2094 unsigned Rm = fieldFromInstruction(Insn, 8, 4); local 2218 unsigned Rm = fieldFromInstruction(Val, 0, 4); local 2240 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 2565 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 2834 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 2881 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 2929 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 2964 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 3063 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 3108 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 3189 unsigned Rm = fieldFromInstruction(Val, 3, 3); local 3236 unsigned Rm = fieldFromInstruction(Val, 2, 4); local 3758 unsigned Rm = fieldFromInstruction(Insn, 3, 4); local 3783 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 3837 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 4059 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 4132 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 4199 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 4265 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 4332 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 4396 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 4466 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 4530 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 4611 unsigned Rm = fieldFromInstruction(Insn, 0, 4); local 4683 unsigned Rm = fieldFromInstruction(Insn, 5, 1); local 4709 unsigned Rm = fieldFromInstruction(Insn, 5, 1); local 4940 unsigned Rm = fieldFromInstruction(Val, 0, 4); local [all...] |
/freebsd-10.1-release/contrib/llvm/tools/lldb/source/Plugins/Instruction/ARM/ |
H A D | EmulateInstructionARM.cpp | 767 uint32_t Rm; // the source register local 773 Rm = Bits32(opcode, 6, 3); 780 Rm = Bits32(opcode, 5, 3); 787 Rm = Bits32(opcode, 3, 0); 790 if (setflags && (BadReg(Rd) || BadReg(Rm))) 793 if (!setflags && (Rd == 15 || Rm == 15 || (Rd == 13 && Rm == 13))) 798 Rm = Bits32(opcode, 3, 0); 808 uint32_t result = ReadCoreReg(Rm, &success); 812 // The context specifies that Rm i 1152 uint32_t Rm; // the source register local 1628 uint32_t Rm; // the register with the target address local 1682 uint32_t Rm; // the register with the target address local 2420 uint32_t Rm; // the index register which contains an integer pointing to a byte/halfword in the table local 2670 uint32_t Rd, Rn, Rm; local 2805 uint32_t Rm; // the second operand local 2929 uint32_t Rm; // the second operand local 3218 uint32_t Rm; // the first operand register local 3308 uint32_t Rm; // the register whose bottom byte contains the amount to shift by local 5184 uint32_t Rm = ReadCoreReg (m, &success); local 5353 uint32_t Rd, Rn, Rm; local 5578 uint32_t Rd, Rn, Rm; local 5741 uint32_t Rd, Rn, Rm; local 6061 uint32_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); local 6476 uint32_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); local 6892 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); local 7298 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); local 7727 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); local 7858 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); local 7942 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); local 8026 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); local 8107 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success); local 8378 uint32_t Rd, Rn, Rm; local 8544 uint32_t Rd, Rn, Rm; local 8707 uint32_t Rm; // the second operand local 8846 uint32_t Rm; // the second operand local 8983 uint32_t Rm; // the second operand local 9277 uint32_t Rn, Rm; local 9401 uint32_t Rn, Rm; local 9523 uint32_t Rm = ReadCoreReg (m, &success); local 9612 uint32_t Rm = ReadCoreReg (m, &success); local 9737 uint32_t Rm = ReadCoreReg (m, &success); local 10308 uint32_t Rm = ReadCoreReg (m, &success); local 11420 uint32_t Rm = ReadCoreReg (m, &success); local 11592 uint32_t Rm = ReadCoreReg (m, &success); local 11759 uint32_t Rm = ReadCoreReg (m, &success); local 11931 uint32_t Rm = ReadCoreReg (m, &success); local 12057 uint32_t Rm = ReadCoreReg (m, &success); local 12182 uint32_t Rm = ReadCoreReg (m, &success); local [all...] |
/freebsd-10.1-release/contrib/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 1027 // This is necessary as we need to decode Rm: if Rm == 0b11111, the last 1029 // or Rm is decoded to a GPR64noxzr register. 1035 unsigned Rm = fieldFromInstruction(Insn, 16, 5); local 1084 if (Rm == 31) // If Rm is 0x11111, add the vector list length in byte 1086 else // Decode Rm 1087 DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder); 1115 // This is necessary as we need to decode Rm: if Rm 1440 unsigned Rm = fieldFromInstruction(Insn, 16, 5); local [all...] |
/freebsd-10.1-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 2626 unsigned Rm = MI->getOperand(3).getReg(); local 2627 return (Rt == Rm) ? 4 : 3; 2633 unsigned Rm = MI->getOperand(3).getReg(); local 2634 if (Rt == Rm) 2663 unsigned Rm = MI->getOperand(3).getReg(); local 2664 if (!Rm) 2666 if (Rt == Rm) 2676 unsigned Rm = MI->getOperand(3).getReg(); local 2677 return (Rt == Rm) ? 3 : 2; 2695 unsigned Rm local 2715 unsigned Rm = MI->getOperand(3).getReg(); local 2722 unsigned Rm = MI->getOperand(3).getReg(); local 2739 unsigned Rm = MI->getOperand(4).getReg(); local 2752 unsigned Rm = MI->getOperand(4).getReg(); local [all...] |
/freebsd-10.1-release/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 740 // [Rn, Rm] 741 // {5-3} = Rm 746 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); local 747 return (Rm << 3) | Rn; 964 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); local 977 // {3-0} = Rm 981 uint32_t Binary = Rm; 994 // {13} 1 == imm12, 0 == Rm 996 // {11-0} imm12/Rm 1007 // {13} 1 == imm12, 0 == Rm [all...] |
/freebsd-10.1-release/contrib/binutils/opcodes/ |
H A D | i386-dis.c | 226 #define Rm { OP_R, m_mode } macro 945 { "movZ", { Rm, Cm } }, 946 { "movZ", { Rm, Dm } }, 947 { "movZ", { Cm, Rm } }, 948 { "movZ", { Dm, Rm } },
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H A D | arm-dis.c | 1190 %S print a possibly-shifted Rm 3457 unsigned int Rm = (i8 & 0x0f); 3459 func (stream, ", %s", arm_regnames[Rm]); 3456 unsigned int Rm = (i8 & 0x0f); local
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/freebsd-10.1-release/contrib/ncurses/include/ |
H A D | Caps.uwin | 579 release_mouse relm str Rm - - ----- Curses should release the mouse */
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/freebsd-10.1-release/contrib/binutils/gas/config/ |
H A D | tc-arm.c | 1854 first_error (_("don't use Rn-Rm syntax with non-unit stride")); 4302 <Rm> 4303 <Rm>, <shift> 4481 <Rm> 4482 <Rm>, <shift> 4537 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4538 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4546 [Rn], +/-Rm 7401 unsigned int Rm = (inst.operands[1].present local [all...] |