Searched refs:Rd (Results 1 - 6 of 6) sorted by relevance

/freebsd-10.1-release/contrib/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1838 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
1846 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2041 unsigned Rd = fieldFromInstruction(Insn, 8, 4); local
2050 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2052 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2065 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
2073 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2076 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2092 unsigned Rd = fieldFromInstruction(Insn, 16, 4); local
2101 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Addres
2235 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
2560 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
2831 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
2878 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
2926 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
2961 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3016 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3061 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3104 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4003 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4133 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4200 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4266 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4333 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4397 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4467 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4531 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
4612 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
[all...]
/freebsd-10.1-release/contrib/llvm/tools/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp646 uint32_t Rd; // the destination register
650 Rd = 7;
654 Rd = Bits32(opcode, 15, 12);
669 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, addr))
705 uint32_t Rd; // the destination register
708 Rd = 7;
711 Rd = 12;
718 if (Rd == GetFramePointerRegisterNumber())
726 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, sp))
768 uint32_t Rd; // th local
851 uint32_t Rd; // the destination register local
1091 uint32_t Rd; // the destination register local
1153 uint32_t Rd; // the destination register local
2610 uint32_t Rd, Rn; local
2670 uint32_t Rd, Rn, Rm; local
3217 uint32_t Rd; // the destination register local
3306 uint32_t Rd; // the destination register local
5283 uint32_t Rd, Rn; local
5353 uint32_t Rd, Rn, Rm; local
5434 uint32_t Rd; local
5504 uint32_t Rd, Rn; local
5578 uint32_t Rd, Rn, Rm; local
5669 uint32_t Rd, Rn; local
5741 uint32_t Rd, Rn, Rm; local
8303 uint32_t Rd, Rn; local
8378 uint32_t Rd, Rn, Rm; local
8470 uint32_t Rd, Rn; local
8544 uint32_t Rd, Rn, Rm; local
8632 uint32_t Rd; // the destination register local
8705 uint32_t Rd; // the destination register local
8784 uint32_t Rd; // the destination register local
8844 uint32_t Rd; // the destination register local
8913 uint32_t Rd; // the destination register local
8981 uint32_t Rd; // the destination register local
9062 uint32_t Rd; // the destination register local
9156 uint32_t Rd; // the destination register local
13377 WriteCoreRegOptionalFlags(Context &context, const uint32_t result, const uint32_t Rd, bool setflags, const uint32_t carry, const uint32_t overflow) argument
[all...]
H A DEmulateInstructionARM.h252 const uint32_t Rd,
260 const uint32_t Rd)
263 return WriteCoreRegOptionalFlags(context, result, Rd, false);
390 // A8.6.97 MOV (register) -- Rd == r7|ip and Rm == sp
426 // A8.6.212 SUB (immediate, ARM) -- Rd == r7 and Rm == ip
430 // A8.6.215 SUB (SP minus immediate) -- Rd == ip
258 WriteCoreReg(Context &context, const uint32_t result, const uint32_t Rd) argument
/freebsd-10.1-release/contrib/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp658 unsigned Rd = fieldFromInstruction(Insn, 0, 5); local
676 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
677 // BFM MCInsts use Rd as a source too.
678 if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
681 DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
682 // BFM MCInsts use Rd as a source too.
683 if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
752 unsigned Rd = fieldFromInstruction(Insn, 0, 5); local
757 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
760 DecodeGPR64RegisterClass(Inst, Rd, Addres
1545 unsigned Rd = fieldFromInstruction(Insn, 0, 5); local
[all...]
/freebsd-10.1-release/contrib/binutils/gas/config/
H A Dtc-arm.c5112 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5145 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5235 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5243 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6535 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
6552 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
6766 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6785 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6795 Result unpredicatable if Rd or Rn is R15. */
7037 as_tsktsk (_("Rd an
8374 int Rd, Rn; local
8390 int Rd, Rs, Rn; local
8615 int Rd, Rs, Rn; local
8698 int Rd, Rs, Rn; local
10071 int Rd, Rs; local
[all...]
/freebsd-10.1-release/contrib/binutils/opcodes/
H A Di386-dis.c225 #define Rd { OP_R, d_mode } macro
949 { "movL", { Rd, Td } },
951 { "movL", { Td, Rd } },

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