Searched refs:ctl_reg (Results 1 - 4 of 4) sorted by relevance

/freebsd-10.0-release/sys/amd64/vmm/intel/
H A Dvmx_msr.c78 vmx_set_ctlreg(int ctl_reg, int true_ctl_reg, uint32_t ones_mask, argument
94 val = rdmsr(ctl_reg);
106 "truectl 0x%0x\n", i, ctl_reg, true_ctl_reg));
130 "0x%0x and true msr 0x%0x", i, ctl_reg,
H A Dvmx_msr.h57 int vmx_set_ctlreg(int ctl_reg, int true_ctl_reg, uint32_t ones_mask,
/freebsd-10.0-release/sys/dev/drm2/i915/
H A Dintel_lvds.c73 u32 ctl_reg, lvds_reg, stat_reg; local
76 ctl_reg = PCH_PP_CONTROL;
80 ctl_reg = PP_CONTROL;
103 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
117 u32 ctl_reg, lvds_reg, stat_reg; local
120 ctl_reg = PCH_PP_CONTROL;
124 ctl_reg = PP_CONTROL;
131 I915_WRITE(ctl_reg, I915_READ(ctl_reg)
[all...]
/freebsd-10.0-release/sys/dev/cxgbe/common/
H A Dt4_hw.c247 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); local
252 v = G_MBOWNER(t4_read_reg(adap, ctl_reg));
254 v = G_MBOWNER(t4_read_reg(adap, ctl_reg));
262 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
263 t4_read_reg(adap, ctl_reg); /* flush write */
277 v = t4_read_reg(adap, ctl_reg);
282 t4_write_reg(adap, ctl_reg,
293 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));

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