Searched refs:REG_READ (Results 1 - 10 of 10) sorted by relevance
/freebsd-10.0-release/sys/mips/adm5120/ |
H A D | obio.c | 99 #define REG_READ(o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(ADM5120_BASE_ICU + (o))) macro 100 #define REG_WRITE(o,v) (REG_READ(o)) = (v) 135 reg = REG_READ(ICU_DISABLE_REG); 150 reg = REG_READ(ICU_DISABLE_REG); 372 REG_WRITE(ICU_MODE_REG, REG_READ(ICU_MODE_REG) | irqmask); 374 REG_WRITE(ICU_MODE_REG, REG_READ(ICU_MODE_REG) & ~irqmask); 403 REG_WRITE(ICU_MODE_REG, REG_READ(ICU_MODE_REG) & ~irqmask); 405 REG_WRITE(ICU_MODE_REG, REG_READ(ICU_MODE_REG) | irqmask); 408 irqmask = REG_READ(ICU_ENABLE_REG); 428 irqstat = REG_READ(ICU_FIQ_STATUS_RE [all...] |
H A D | if_admsw.c | 220 #define REG_READ(o) bus_read_4((sc)->mem_res, (o)) macro 308 REG_READ(PORT_CONF0_REG) | PORT_CONF0_DP_MASK); 310 REG_READ(CPUP_CONF_REG) | CPUP_CONF_DCPUP); 321 REG_READ(PHY_CNTL2_REG) & ~PHY_CNTL2_PHYR_MASK); 338 REG_READ(PHY_CNTL2_REG) | PHY_CNTL2_ANE_MASK | PHY_CNTL2_PHYR_MASK | 341 REG_WRITE(PHY_CNTL3_REG, REG_READ(PHY_CNTL3_REG) | PHY_CNTL3_RNT); 356 REG_READ(FC_TH_REG) & ~(FC_TH_FCS_MASK | FC_TH_D2S_MASK)); 370 while (!(REG_READ(MAC_WT0_REG) & MAC_WT0_WRITE_DONE)); 373 wdog1 = REG_READ(ADM5120_WDOG1); 864 pending = REG_READ(ADMSW_INT_S [all...] |
/freebsd-10.0-release/sys/mips/idt/ |
H A D | idtpci.c | 111 #define REG_READ(o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(IDT_BASE_PCI + (o))) macro 112 #define REG_WRITE(o,v) (REG_READ(o)) = (v) 163 pci_data = REG_READ(IDT_PCI_STATUS); 194 pci_data = REG_READ(IDT_PCI_LBA0_CNTL); 200 pci_data = REG_READ(IDT_PCI_LBA1_CNTL); 207 pci_data = REG_READ(IDT_PCI_LBA2_CNTL); 214 pci_data = REG_READ(IDT_PCI_LBA3_CNTL); 217 pci_data = REG_READ(IDT_PCI_CNTL) & ~IDT_PCI_CNTL_TNR; 219 pci_data = REG_READ(IDT_PCI_CNTL); 303 data = REG_READ(IDT_PCI_CFG_DAT [all...] |
/freebsd-10.0-release/sys/mips/alchemy/ |
H A D | obio.c | 99 #define REG_READ(o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(ADM5120_BASE_ICU + (o))) macro 100 #define REG_WRITE(o,v) (REG_READ(o)) = (v) 374 REG_WRITE(ICU_MODE_REG, REG_READ(ICU_MODE_REG) | irqmask); 376 REG_WRITE(ICU_MODE_REG, REG_READ(ICU_MODE_REG) & ~irqmask); 420 irqstat = REG_READ(ICU_FIQ_STATUS_REG); 421 irqstat |= REG_READ(ICU_STATUS_REG);
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/freebsd-10.0-release/sys/dev/ath/ath_hal/ar5312/ |
H A D | ar5312reg.h | 32 #define REG_READ(_reg) *((volatile uint32_t *)(_reg)) macro
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/freebsd-10.0-release/sys/arm/broadcom/bcm2835/ |
H A D | bcm2835_mbox.c | 57 #define REG_READ 0x00 macro 111 msg = mbox_read_4(sc, REG_READ);
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/freebsd-10.0-release/sys/contrib/dev/ath/ath_hal/ar9300/ |
H A D | ar9300_reset.c | 1663 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) macro 1667 REG_READ(AR_SOC_RST_RESET) | AR_SOC_WLAN_RST); 1669 REG_READ(AR_SOC_RST_RESET) & (~AR_SOC_WLAN_RST)); 1674 tmp_reg = REG_READ(AR_SOC_BOOT_STRAP); 1686 #undef REG_READ macro 1720 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) macro 1766 REG_WRITE(RST_RESET, (REG_READ(RST_RESET) | RTC_RESET)); 1768 REG_WRITE(RST_RESET, (REG_READ(RST_RESET) & ~RTC_RESET)); 1776 #undef REG_READ macro 1900 #define REG_READ(_re macro 1922 #undef REG_READ macro 2907 #define REG_READ macro 2922 #undef REG_READ macro 4964 #define REG_READ macro 4993 #undef REG_READ macro 5062 #define REG_READ macro 5070 #undef REG_READ macro [all...] |
H A D | ar9300_attach.c | 581 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) macro 582 if ((REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_HORNET_11_MASK) 589 #undef REG_READ macro 596 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) macro 599 REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_WASP_MASK; 600 #undef REG_READ macro 766 #define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) macro 767 if (REG_READ(AR_SOC_SEL_25M_40M) & 0x1) { 776 #undef REG_READ macro 787 #define REG_READ(_re macro 795 #undef REG_READ macro 2202 #define REG_READ macro 2209 #undef REG_READ macro [all...] |
H A D | ar9300_misc.c | 2635 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) macro 2636 wasp_mm_rev = (REG_READ(AR_SOC_RST_REVISION_ID) & 2640 #undef REG_READ macro
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/freebsd-10.0-release/sys/mips/rt305x/ |
H A D | obio.c | 94 #define REG_READ(o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(INTCTL_BASE + (o))) macro 95 #define REG_WRITE(o,v) (REG_READ(o)) = (v)
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