Searched refs:_DD_MAKEMASK1 (Results 1 - 17 of 17) sorted by relevance

/broadcom-cfe-1.4.2/cfe/arch/ppc/chipset/mpc824x/src/
H A Dtulip.h15 #define _DD_MAKEMASK1(n) (1 << (n)) macro
100 #define M_CSR0_SWRESET _DD_MAKEMASK1(0)
101 #define M_CSR0_BUSARB _DD_MAKEMASK1(1)
108 #define M_CSR0_BIGENDIAN _DD_MAKEMASK1(7)
125 #define M_CSR0_DESCBYTEORDER _DD_MAKEMASK1(20) /* not 21040 */
126 #define M_CSR0_READMULTENAB _DD_MAKEMASK1(21) /* not 2104{0,1} */
127 #define M_CSR0_READLINEENAB _DD_MAKEMASK1(23) /* not 2104{0,1} */
128 #define M_CSR0_WRITEINVALENAB _DD_MAKEMASK1(24) /* not 2104{0,1} */
155 #define M_CSR5_TXINT _DD_MAKEMASK1(0)
156 #define M_CSR5_TXSTOP _DD_MAKEMASK1(
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/broadcom-cfe-1.4.2/cfe/dev/
H A Ddp83815.h13 #define _DD_MAKEMASK1(n) (1 << (n)) macro
108 #define M_CR_TXE _DD_MAKEMASK1(0)
109 #define M_CR_TXD _DD_MAKEMASK1(1)
110 #define M_CR_RXE _DD_MAKEMASK1(2)
111 #define M_CR_RXD _DD_MAKEMASK1(3)
112 #define M_CR_TXR _DD_MAKEMASK1(4)
113 #define M_CR_RXR _DD_MAKEMASK1(5)
114 #define M_CR_SWI _DD_MAKEMASK1(7)
115 #define M_CR_RST _DD_MAKEMASK1(8)
120 #define M_CFG_BEM _DD_MAKEMASK1(
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H A Ddc21143.h15 #define _DD_MAKEMASK1(n) (1 << (n)) macro
84 #define M_CSR0_SWRESET _DD_MAKEMASK1(0)
85 #define M_CSR0_BUSARB _DD_MAKEMASK1(1)
92 #define M_CSR0_BIGENDIAN _DD_MAKEMASK1(7)
109 #define M_CSR0_DESCBYTEORDER _DD_MAKEMASK1(20) /* not 21040 */
110 #define M_CSR0_READMULTENAB _DD_MAKEMASK1(21) /* not 2104{0,1} */
111 #define M_CSR0_READLINEENAB _DD_MAKEMASK1(23) /* not 2104{0,1} */
112 #define M_CSR0_WRITEINVALENAB _DD_MAKEMASK1(24) /* not 2104{0,1} */
139 #define M_CSR5_TXINT _DD_MAKEMASK1(0)
140 #define M_CSR5_TXSTOP _DD_MAKEMASK1(
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H A Drtl8139.h12 #define _DD_MAKEMASK1(n) (1 << (n)) macro
123 #define M_TS_OWN _DD_MAKEMASK1(13)
124 #define M_TS_TUN _DD_MAKEMASK1(14)
125 #define M_TS_TOK _DD_MAKEMASK1(15)
139 #define M_TS_CDH _DD_MAKEMASK1(28)
140 #define M_TS_OWC _DD_MAKEMASK1(29)
141 #define M_TS_TABT _DD_MAKEMASK1(30)
142 #define M_TS_CRS _DD_MAKEMASK1(31)
147 #define M_ERSR_EROK _DD_MAKEMASK1(0)
148 #define M_ERSR_EROVW _DD_MAKEMASK1(
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H A Di82559.h12 #define _DD_MAKEMASK1(n) (1 << (n)) macro
82 #define M_SCB_FCP _DD_MAKEMASK1(0) /* not i82557 */
83 #define M_SCB_SWI _DD_MAKEMASK1(2)
84 #define M_SCB_MDI _DD_MAKEMASK1(3)
85 #define M_SCB_RNR _DD_MAKEMASK1(4)
86 #define M_SCB_CNA _DD_MAKEMASK1(5) /* CNA or CI */
87 #define M_SCB_FR _DD_MAKEMASK1(6) /* FR or ER */
88 #define M_SCB_CX _DD_MAKEMASK1(7) /* also TNO, i82557 */
123 #define M_SCB_M _DD_MAKEMASK1(0)
124 #define M_SCB_SI _DD_MAKEMASK1(
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H A Dbcm5700.h76 #define _DD_MAKEMASK1(n) (1 << (n)) macro
340 #define RD_DMA_MODE_FIFO_SIZE_128 _DD_MAKEMASK1(17)
418 #define M_MODE_RESET _DD_MAKEMASK1(0)
419 #define M_MODE_ENABLE _DD_MAKEMASK1(1)
420 #define M_MODE_ATTNENABLE _DD_MAKEMASK1(2)
422 #define M_STAT_ERROR _DD_MAKEMASK1(1)
426 #define M_STATS_ENABLE _DD_MAKEMASK1(0)
427 #define M_STATS_FASTUPDATE _DD_MAKEMASK1(1)
428 #define M_STATS_CLEAR _DD_MAKEMASK1(2)
429 #define M_STATS_FLUSH _DD_MAKEMASK1(
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H A Dbcm4401.h63 #define _DD_MAKEMASK1(n) (1 << (n)) macro
98 #define M_SBINT_SB _DD_MAKEMASK1(2) /* SBError */
271 #define M_SBIS_IE _DD_MAKEMASK1(17) /* InbandError */
272 #define M_SBIS_TO _DD_MAKEMASK1(18) /* TimeOut */
286 #define M_SBTS_RS _DD_MAKEMASK1(0) /* Reset */
287 #define M_SBTS_RJ _DD_MAKEMASK1(1) /* Reject */
288 #define M_SBTS_CE _DD_MAKEMASK1(16) /* ClockEnable */
289 #define M_SBTS_FC _DD_MAKEMASK1(17) /* ForceGatedClocks */
296 #define M_SBTS_PE _DD_MAKEMASK1(30) /* PMEEnable */
297 #define M_SBTS_BE _DD_MAKEMASK1(3
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H A Ddev_spi_robo.c61 #define _DD_MAKEMASK1(n) (1 << (n)) macro
72 #define M_SPISTAT_TXRDY _DD_MAKEMASK1(0)
73 #define M_SPISTAT_RXRDY _DD_MAKEMASK1(1)
74 #define M_SPISTAT_MDIO_START _DD_MAKEMASK1(2)
75 #define M_SPISTAT_RACK _DD_MAKEMASK1(5)
76 #define M_SPISTAT_WCOL _DD_MAKEMASK1(6)
77 #define M_SPISTAT_SPIF _DD_MAKEMASK1(7)
80 #define M_SPISTAT_FAST_RACK _DD_MAKEMASK1(0)
H A Daic6915.h59 #define _DD_MAKEMASK1(n) (1 << (n)) macro
/broadcom-cfe-1.4.2/cfe/arch/mips/chipset/bcmsb/include/
H A Dsb_mips.h59 #define M_CORECTL_FR _DD_MAKEMASK1(0) /* ForceReset */
60 #define M_CORECTL_DF _DD_MAKEMASK1(1) /* DisableFlashExceptions */
82 #define M_BISTCTL_BD _DD_MAKEMASK1(0) /* BISTDump */
83 #define M_BISTCTL_BG _DD_MAKEMASK1(1) /* BISTDebug */
84 #define M_BISTCTL_BH _DD_MAKEMASK1(2) /* BISTHold */
89 #define M_INT_T0 _DD_MAKEMASK1(0) /* Timer0 */
H A Dsb_mac.h130 #define M_DVCTL_PM _DD_MAKEMASK1(7) /* PatMatchEn */
131 #define M_DVCTL_IP _DD_MAKEMASK1(10) /* InternalEPHY */
132 #define M_DVCTL_ER _DD_MAKEMASK1(15) /* EPHYReset */
133 #define M_DVCTL_MP _DD_MAKEMASK1(16) /* MIIPHYModeEn */
134 #define M_DVCTL_CO _DD_MAKEMASK1(17) /* ClkOutputEn */
155 #define M_WKUP_D0 _DD_MAKEMASK1(7) /* Disable0 */
162 #define M_WKUP_D1 _DD_MAKEMASK1(15) /* Disable1 */
169 #define M_WKUP_D2 _DD_MAKEMASK1(23) /* Disable2 */
176 #define M_WKUP_D3 _DD_MAKEMASK1(31) /* Disable3 */
181 #define M_INT_PM _DD_MAKEMASK1(
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H A Dsb_bp.h46 #define _DD_MAKEMASK1(n) (1 << (n)) macro
152 #define M_SBTSF_FE _DD_MAKEMASK1(6) /* SBTPSFlag0En0 */
166 #define M_SBIS_IE _DD_MAKEMASK1(17) /* InbandError */
167 #define M_SBIS_TO _DD_MAKEMASK1(18) /* TimeOut */
180 #define M_SBTS_RS _DD_MAKEMASK1(0) /* Reset */
181 #define M_SBTS_RJ _DD_MAKEMASK1(1) /* Reject */
182 #define M_SBTS_CE _DD_MAKEMASK1(16) /* ClockEnable */
183 #define M_SBTS_FC _DD_MAKEMASK1(17) /* ForceGatedClocks */
190 #define M_SBTS_PE _DD_MAKEMASK1(30) /* PMEEnable */
191 #define M_SBTS_BE _DD_MAKEMASK1(3
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H A Dsb_extif.h97 #define M_CORECTL_UE _DD_MAKEMASK1(0) /* UartEnable */
101 #define M_EXTSTAT_EM _DD_MAKEMASK1(0) /* EndianMode */
102 #define M_EXTSTAT_EI _DD_MAKEMASK1(1) /* ExtInt */
103 #define M_EXTSTAT_GI _DD_MAKEMASK1(2) /* GPIOInt */
110 #define M_IFCFG_EN _DD_MAKEMASK1(0) /* Enable */
120 #define M_IFCFG_DS _DD_MAKEMASK1(4) /* DestSize */
121 #define M_IFCFG_BS _DD_MAKEMASK1(5) /* ByteSwap */
128 #define M_IFCFG_CE _DD_MAKEMASK1(8) /* ClockEnable */
129 #define M_IFCFG_SB _DD_MAKEMASK1(9) /* Size/ByteStrobe */
H A Dsb_pci.h128 #define M_PCICTL_OE _DD_MAKEMASK1(0) /* PCIResetOutputEn */
129 #define M_PCICTL_RO _DD_MAKEMASK1(1) /* PCIResetOutput */
130 #define M_PCICTL_CE _DD_MAKEMASK1(2) /* PCIClockOutputEn */
131 #define M_PCICTL_CO _DD_MAKEMASK1(3) /* PCIClockOutput */
135 #define M_PCIARB_IA _DD_MAKEMASK1(0) /* InternalArbiter */
136 #define M_PCIARB_EA _DD_MAKEMASK1(1) /* ExternalArbiter */
150 #define M_PCIINT_PA _DD_MAKEMASK1(0) /* PCIIntA */
151 #define M_PCIINT_PB _DD_MAKEMASK1(1) /* PCIIntB */
152 #define M_PCIINT_PS _DD_MAKEMASK1(2) /* PCISerr */
153 #define M_PCIINT_PP _DD_MAKEMASK1(
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H A Dsb_chipc.h142 #define M_CORECAP_EM _DD_MAKEMASK1(2) /* EndianMode */
151 #define M_CORECAP_UG _DD_MAKEMASK1(5) /* UARTGPIOs */
152 #define M_CORECAP_EB _DD_MAKEMASK1(6) /* ExtBusPresent */
179 #define M_CORECTL_CO _DD_MAKEMASK1(0) /* UARTClkOverride */
180 #define M_CORECTL_SE _DD_MAKEMASK1(1) /* SyncClkOutEn */
184 #define M_INTSTAT_GI _DD_MAKEMASK1(0) /* GPIOInt */
185 #define M_INTSTAT_EI _DD_MAKEMASK1(1) /* ExtInt */
186 #define M_INTSTAT_WD _DD_MAKEMASK1(2) /* WDReset */
190 #define M_INTMASK_EI _DD_MAKEMASK1(1) /* ExtInt */
204 #define M_SFLASHCTL_AB _DD_MAKEMASK1(3
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/broadcom-cfe-1.4.2/cfe/include/
H A Dcfe_crypto.h49 #define _DD_MAKEMASK1(n) (1 << (n)) macro
100 #define M_MCR_SUPPRESS_INTR _DD_MAKEMASK1(31)
104 #define M_MCR_DONE _DD_MAKEMASK1(16)
105 #define M_MCR_ERROR _DD_MAKEMASK1(17)
/broadcom-cfe-1.4.2/cfe/arch/mips/chipset/bcmsb/src/
H A Ddev_sb_mac.c75 #define M_PHYINT_IS _DD_MAKEMASK1(0) /* InterruptStatus */
76 #define M_PHYINT_LC _DD_MAKEMASK1(1) /* LinkChangeInt */
77 #define M_PHYINT_SP _DD_MAKEMASK1(2) /* SpeedChangeInt */
78 #define M_PHYINT_DC _DD_MAKEMASK1(3) /* DuplexChangeInt */
79 #define M_PHYINT_MI _DD_MAKEMASK1(8) /* MasterIntMask */
80 #define M_PHYINT_LI _DD_MAKEMASK1(9) /* LinkIntMask */
81 #define M_PHYINT_SI _DD_MAKEMASK1(10) /* SpeedIntMask */
82 #define M_PHYINT_FD _DD_MAKEMASK1(11) /* FullDuplexIntMask */
83 #define M_PHYINT_IE _DD_MAKEMASK1(14) /* InterruptEnable */

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