Searched refs:V_MC_WR_LIMIT_DEFAULT (Results 1 - 2 of 2) sorted by relevance

/broadcom-cfe-1.4.2/cfe/arch/mips/chipset/sibyte/include/
H A Dsb1250_mc.h116 #define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5) macro
144 #define V_MC_CONFIG_DEFAULT V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \
/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/sb1250/src/
H A Dsb1250_draminit.c3116 mc_cfgbits |= V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT |

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