Searched refs:V_CSR0_CACHEALIGN (Results 1 - 4 of 4) sorted by relevance

/broadcom-cfe-1.4.2/cfe/arch/ppc/chipset/mpc824x/src/
H A Ddev_tulip.c1930 V_CSR0_CACHEALIGN(K_CSR0_ALIGN32) |
2082 V_CSR0_CACHEALIGN(K_CSR0_ALIGN32) |
2201 V_CSR0_CACHEALIGN(K_CSR0_ALIGN32) |
2285 V_CSR0_CACHEALIGN(K_CSR0_ALIGN32) |
H A Dtulip.h117 #define V_CSR0_CACHEALIGN(x) _DD_MAKEVALUE(x,S_CSR0_CACHEALIGN) macro
/broadcom-cfe-1.4.2/cfe/dev/
H A Ddc21143.h101 #define V_CSR0_CACHEALIGN(x) _DD_MAKEVALUE(x,S_CSR0_CACHEALIGN) macro
H A Ddev_tulip.c1715 V_CSR0_CACHEALIGN(K_CSR0_ALIGN32) |
1866 V_CSR0_CACHEALIGN(K_CSR0_ALIGN32) |
1984 V_CSR0_CACHEALIGN(K_CSR0_ALIGN32) |
2067 V_CSR0_CACHEALIGN(K_CSR0_ALIGN32) |

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