Searched refs:base (Results 76 - 100 of 1028) sorted by relevance

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/u-boot/drivers/phy/qcom/
H A Dphy-qcom-snps-eusb2.c126 void __iomem *base; member in struct:qcom_snps_eusb2_phy_priv
131 static void qcom_snps_eusb2_hsphy_write_mask(void __iomem *base, u32 offset, argument
136 reg = readl_relaxed(base + offset);
139 writel_relaxed(reg, base + offset);
142 readl_relaxed(base + offset);
148 qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_9,
153 qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_9,
158 qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_9,
163 qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_8,
168 qcom_snps_eusb2_hsphy_write_mask(qcom_snps_eusb2->base, USB_PHY_CFG_CTRL_
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/u-boot/drivers/i2c/
H A Dfsl_i2c.c121 * @param base: the I2C device registers
129 static uint set_i2c_bus_speed(const struct fsl_i2c_base *base, argument
193 writeb(dfsr, &base->dfsrr); /* set default filter */
194 writeb(fdr, &base->fdr); /* set bus speed */
204 writeb(fdr, &base->fdr); /* set bus speed */
222 static int fsl_i2c_fixup(const struct fsl_i2c_base *base) argument
237 writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr);
240 while (!(readb(&base->sr) & I2C_SR_MBB)) {
245 if (readb(&base->sr) & I2C_SR_MAL) {
247 writeb(0, &base
270 __i2c_init(const struct fsl_i2c_base *base, int speed, int slaveadd, int i2c_clk, int busnum) argument
297 i2c_wait4bus(const struct fsl_i2c_base *base) argument
310 i2c_wait(const struct fsl_i2c_base *base, int write) argument
347 i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, u8 dir, int rsta) argument
362 __i2c_write_data(const struct fsl_i2c_base *base, u8 *data, int length) argument
377 __i2c_read_data(const struct fsl_i2c_base *base, u8 *data, int length) argument
409 __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen, u8 *data, int dlen) argument
456 __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen, u8 *data, int dlen) argument
479 __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip) argument
491 __i2c_set_bus_speed(const struct fsl_i2c_base *base, uint speed, int i2c_clk) argument
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/u-boot/arch/arm/include/asm/ti-common/
H A Dti-edma3.h102 void qedma3_start(u32 base, struct edma3_channel_config *cfg);
103 void qedma3_stop(u32 base, struct edma3_channel_config *cfg);
104 void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg);
105 int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg);
106 void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param);
107 void edma3_read_slot(u32 base, int slot, struct edma3_slot_layout *param);
109 void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode,
111 void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx);
112 void edma3_set_dest_addr(u32 base, int slot, u32 dst);
114 void edma3_set_src(u32 base, in
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/u-boot/drivers/clk/exynos/
H A Dclk.c13 static void samsung_clk_register_mux(void __iomem *base, unsigned int cmu_id, argument
26 m->num_parents, m->flags, base + m->offset, m->shift,
33 static void samsung_clk_register_div(void __iomem *base, unsigned int cmu_id, argument
46 d->flags, base + d->offset, d->shift,
53 static void samsung_clk_register_gate(void __iomem *base, unsigned int cmu_id, argument
66 g->flags, base + g->offset, g->bit_idx,
73 typedef void (*samsung_clk_register_fn)(void __iomem *base, unsigned int cmu_id,
86 * @base: Base address of CMU registers
94 static void samsung_cmu_register_clocks(void __iomem *base, unsigned int cmu_id, argument
103 samsung_clk_register_fns[g->type](base, cmu_i
121 void __iomem *base; local
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/u-boot/drivers/serial/
H A Dserial_msm.c74 phys_addr_t base; member in struct:msm_serial_data
89 if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
90 writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR);
93 sr = readl(priv->base + UARTDM_SR);
97 priv->chars_buf = readl(priv->base + UARTDM_RF);
101 priv->chars_cnt = readl(priv->base + UARTDM_RXFS);
111 priv->base + UARTDM_CR);
113 priv->chars_buf = readl(priv->base + UARTDM_RF);
115 priv->base + UARTDM_CR);
116 writel(0x7, priv->base
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H A Dserial_mxs.c38 void __iomem *base; member in struct:mxs_auart_uart_priv
46 writel(AUART_CTRL0_CLKGATE, priv->base + AUART_CTRL0 + CLR_REG);
47 writel(AUART_CTRL0_SFTRST, priv->base + AUART_CTRL0 + CLR_REG);
49 writel(AUART_CTRL2_UARTEN, priv->base + AUART_CTRL2 + SET_REG);
51 writel(0, priv->base + AUART_INTR);
59 priv->base + AUART_LINECTRL);
67 u32 stat = readl(priv->base + AUART_STAT);
78 u32 stat = readl(priv->base + AUART_STAT);
83 writel(ch, priv->base + AUART_DATA);
95 return readl(priv->base
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/u-boot/arch/arm/mach-mvebu/armada3700/
H A Defuse.c26 static void otp_read_parallel(void __iomem *base, u32 *data, u32 count) argument
31 regval = readl(base + OTP_CONTROL_OFF);
33 writel(regval, base + OTP_CONTROL_OFF);
36 regval = readl(base + OTP_CONTROL_OFF);
38 writel(regval, base + OTP_CONTROL_OFF);
41 regval = readl(base + OTP_READ_POINTER_OFF);
43 writel(regval, base + OTP_READ_POINTER_OFF);
46 regval = readl(base + OTP_CONTROL_OFF);
48 writel(regval, base + OTP_CONTROL_OFF);
50 regval = readl(base
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/u-boot/drivers/timer/
H A Datmel_tcb_timer.c45 void __iomem *base; member in struct:atmel_tcb_plat
55 cv1 = readl(plat->base + TCB_CV(1));
56 cv0 = readl(plat->base + TCB_CV(0));
57 } while (readl(plat->base + TCB_CV(1)) != cv1);
64 static void atmel_tcb_configure(void __iomem *base) argument
67 writel(TCB_WPMR_WAKEY, base + TCB_WPMR);
70 writel(0xff, base + TCB_IDR(0));
71 writel(0xff, base + TCB_IDR(1));
80 | TCB_CMR_ACPC_CLEAR, base + TCB_CMR(0));
81 writel(0x80000000, base
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/u-boot/arch/arm/mach-keystone/include/mach/
H A Dddr3.h74 void ddr3_init_ecc(u32 base, u32 ddr3_size);
75 void ddr3_disable_ecc(u32 base);
76 void ddr3_check_ecc_int(u32 base);
77 int ddr3_ecc_support_rmw(u32 base);
79 void ddr3_enable_ecc(u32 base, int test);
80 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
81 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
/u-boot/arch/arm/mach-uniphier/
H A Dbase-address.c14 #include "base-address.h"
52 u64 base; local
54 base = uniphier_base_address_get("-soc-glue");
55 if (base == OF_BAD_ADDR)
58 sg_base = ioremap(base, SZ_8K);
60 base = uniphier_base_address_get("-sysctrl");
61 if (base == OF_BAD_ADDR)
64 sc_base = ioremap(base, SZ_64K);
H A Ddebug.h24 void __iomem *base = (void __iomem *)DEBUG_UART_BASE; local
26 while (!(readl(base + UNIPHIER_UART_LSR) & UART_LSR_THRE))
29 writel(c, base + UNIPHIER_UART_TX);
/u-boot/drivers/soc/ti/
H A Dkeystone_serdes.c110 static void ks2_serdes_cfg_setup(u32 base, struct serdes_cfg *cfg, u32 size) argument
115 ks2_serdes_rmw(base + cfg[i].ofs, cfg[i].val, cfg[i].mask);
118 static void ks2_serdes_lane_config(u32 base, struct serdes_cfg *cfg_lane, argument
124 ks2_serdes_rmw(base + cfg_lane[i].ofs + SERDES_LANE_REGS(lane),
128 static int ks2_serdes_init_cfg(u32 base, struct cfg_entry *cfg, u32 num_lanes) argument
132 ks2_serdes_cfg_setup(base, cfg->cmu, SERDES_CMU_CFG_NUM);
133 ks2_serdes_cfg_setup(base, cfg->comlane, SERDES_COMLANE_CFG_NUM);
136 ks2_serdes_lane_config(base, cfg->lane, SERDES_LANE_CFG_NUM, i);
141 static void ks2_serdes_cmu_comlane_enable(u32 base, struct ks2_serdes *serdes) argument
144 ks2_serdes_rmw(base
156 ks2_serdes_pll_enable(u32 base, struct ks2_serdes *serdes) argument
162 ks2_serdes_lane_reset(u32 base, u32 reset, u32 lane) argument
172 ks2_serdes_lane_enable(u32 base, struct ks2_serdes *serdes, u32 lane) argument
188 ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes) argument
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/u-boot/drivers/pch/
H A Dpch7.c19 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
43 u32 base; local
51 * GPIO base address register bit0 is reserved (read returns 0),
55 dm_pci_read_config32(dev, GPIO_BASE, &base);
56 if (base == 0x00000000 || base == 0xffffffff) {
67 *gbasep = base & 1 ? base & ~3 : base & ~15;
/u-boot/drivers/cache/
H A Dcache-sifive-ccache.c19 void __iomem *base; member in struct:sifive_ccache
29 config = readl(priv->base + SIFIVE_CCACHE_CONFIG);
32 writel(ways - 1, priv->base + SIFIVE_CCACHE_WAY_ENABLE);
41 info->base = (uintptr_t)priv->base;
55 priv->base = dev_read_addr_ptr(dev);
56 if (!priv->base)
/u-boot/drivers/clk/owl/
H A Dclk_owl.c31 setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
36 clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
42 writel(bus_clk, priv->base + CMU_BUSCLK);
47 core_pll = readl(priv->base + CMU_COREPLL);
49 writel(core_pll, priv->base + CMU_COREPLL);
54 dev_pll = readl(priv->base + CMU_DEVPLL);
56 writel(dev_pll, priv->base + CMU_DEVPLL);
61 clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,
65 setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
80 clrbits_le32(priv->base
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/u-boot/drivers/ram/cadence/
H A Dddr_ctrl.c98 void cdns_ddr_set_mr1(void *base, int cs, u16 odt_impedance, u16 drive_strength) argument
104 reg = (u8 *)base + DDR_CS0_MR1_REG;
106 reg = (u8 *)base + DDR_CS1_MR1_REG;
122 void cdns_ddr_set_mr2(void *base, int cs, u16 dynamic_odt, u16 self_refresh_temp) argument
128 reg = (u8 *)base + DDR_CS0_MR2_REG;
130 reg = (u8 *)base + DDR_CS1_MR2_REG;
146 void cdns_ddr_set_odt_map(void *base, int cs, u16 odt_map) argument
151 reg = (u8 *)base + DDR_CS0_ODT_MAP_REG;
153 reg = (u8 *)base + DDR_CS1_ODT_MAP_REG;
158 void cdns_ddr_set_odt_times(void *base, u argument
169 cdns_ddr_set_same_cs_delays(void *base, u8 r2r, u8 r2w, u8 w2r, u8 w2w) argument
176 cdns_ddr_set_diff_cs_delays(void *base, u8 r2r, u8 r2w, u8 w2r, u8 w2w) argument
183 cdns_ddr_set_port_rw_priority(void *base, int port, u8 read_pri, u8 write_pri) argument
199 cdns_ddr_enable_port_addr_range(void *base, int port, int entry, u32 addr_start, u32 size) argument
231 cdns_ddr_enable_addr_range(void *base, int entry, u32 addr_start, u32 size) argument
241 cdns_ddr_enable_port_prot(void *base, int port, int entry, enum cdns_ddr_range_prot range_protection_bits, u16 range_RID_check_bits, u16 range_WID_check_bits, u8 range_RID_check_bits_ID_lookup, u8 range_WID_check_bits_ID_lookup) argument
272 cdns_ddr_enable_prot(void *base, int entry, enum cdns_ddr_range_prot range_protection_bits, u16 range_RID_check_bits, u16 range_WID_check_bits, u8 range_RID_check_bits_ID_lookup, u8 range_WID_check_bits_ID_lookup) argument
290 cdns_ddr_set_port_bandwidth(void *base, int port, u8 max_percent, u8 overflow_ok) argument
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/u-boot/drivers/mailbox/
H A Dapple-mbox.c25 void *base; member in struct:apple_mbox_priv
42 writeq(msg->msg0, priv->base + REG_A2I_MSG0);
43 writeq(msg->msg1, priv->base + REG_A2I_MSG1);
44 while (readl(priv->base + REG_A2I_STAT) & REG_A2I_STAT_FULL)
55 if (readl(priv->base + REG_I2A_STAT) & REG_I2A_STAT_EMPTY)
58 msg->msg0 = readq(priv->base + REG_I2A_MSG0);
59 msg->msg1 = readq(priv->base + REG_I2A_MSG1);
73 priv->base = dev_read_addr_ptr(dev);
74 if (!priv->base)
/u-boot/arch/arm/include/asm/kona-common/
H A Dclk.h25 int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
26 int clk_bsc_enable(void *base);
27 int clk_usb_otg_enable(void *base);
/u-boot/arch/riscv/lib/
H A Dandes_plicsw.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + 4 * (((hart) + 1) / 32))
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80 + 4 * (((hart) + 1) / 32))
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000)
30 #define PRIORITY_REG(base) ((ulong)(base) + PLICSW_PRIORITY_BASE)
60 long *base = syscon_get_first_range(RISCV_SYSCON_PLICSW); local
65 if (IS_ERR(base))
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/u-boot/drivers/rng/
H A Dmsm_rng.c35 phys_addr_t base; member in struct:msm_rng_priv
52 val = readl_relaxed(priv->base + PRNG_STATUS);
56 val = readl_relaxed(priv->base + PRNG_DATA_OUT);
77 val = readl_relaxed(priv->base + PRNG_CONFIG);
79 val = readl_relaxed(priv->base + PRNG_LFSR_CFG);
82 writel(val, priv->base + PRNG_LFSR_CFG);
84 val = readl_relaxed(priv->base + PRNG_CONFIG);
86 writel(val, priv->base + PRNG_CONFIG);
89 val = readl_relaxed(priv->base + PRNG_CONFIG);
91 writel(val, priv->base
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/u-boot/drivers/spi/
H A Dspi-synquacer.c106 void __iomem *base; member in struct:synquacer_spi_plat
111 void __iomem *base; member in struct:synquacer_spi_priv
121 u32 len = readl(priv->base + DMSTATUS);
129 *buf++ = readb(priv->base + RXFIFO);
137 u32 len = readl(priv->base + DMSTATUS);
145 writeb(*buf++, priv->base + TXFIFO);
155 val = readl(priv->base + DMSTART);
160 writel(val, priv->base + DMSTART);
162 val = readl(priv->base + DMSTART);
164 writel(val, priv->base
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/u-boot/drivers/rtc/
H A Dzynqmp_rtc.c27 fdt_addr_t base; member in struct:zynqmp_rtc_priv
37 status = readl(priv->base + RTC_INT_STS);
44 read_time = readl(priv->base + RTC_CUR_TM);
53 read_time = readl(priv->base + RTC_SET_TM_RD) - 1;
79 writel(priv->calibval, (priv->base + RTC_CALIB_WR));
81 writel(new_time, priv->base + RTC_SET_TM_WR);
91 writel(RTC_INT_SEC, priv->base + RTC_INT_STS);
107 rtc_ctrl = readl(priv->base + RTC_CTRL);
109 writel(rtc_ctrl, priv->base + RTC_CTRL);
118 writel(priv->calibval, (priv->base
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/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-bsc.c14 int clk_bsc_enable(void *base) argument
19 switch ((u32) base) {
36 printf("%s: base 0x%p not found\n", __func__, base);
/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-bsc.c14 int clk_bsc_enable(void *base) argument
19 switch ((u32) base) {
36 printf("%s: base 0x%p not found\n", __func__, base);
/u-boot/drivers/phy/
H A Dphy-imx8mq-usb.c82 void __iomem *base; member in struct:imx8mq_usb_phy
99 value = readl(imx_phy->base + PHY_CTRL1);
103 writel(value, imx_phy->base + PHY_CTRL1);
105 value = readl(imx_phy->base + PHY_CTRL0);
109 writel(value, imx_phy->base + PHY_CTRL0);
111 value = readl(imx_phy->base + PHY_CTRL2);
113 writel(value, imx_phy->base + PHY_CTRL2);
115 value = readl(imx_phy->base + PHY_CTRL1);
117 writel(value, imx_phy->base + PHY_CTRL1);
129 value = readl(imx_phy->base
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